MOSEL VITELIC
1
V82658B04S
64 MB 200-PIN DDR UNBUFFERED SODIMM
2.5 VOLT 8M x 64
PRELIMINARY
V82658B04S Rev. 1.2 March 2002
Features
JEDEC 200 Pin DDR Unbuffered Small-Outline,
Dual In-Line memory module (SODIMM);
8,388,608 x 64 bit organization.
Utilizes High Performance 8M x 16 DDR
SDRAM in TSOPII-66 Packages
Single +2.5V ( 0.2V) Power Supply
Programmable CAS Latency, Burst Length, and
Wrap Sequence (Sequential & Interleave)
Auto Refresh (CBR) and Self Refresh
All Inputs, Outputs are SSTL-2 Compatible
4096 Refresh Cycles every 64 ms
Serial Presence Detect (SPD)
DDR SDRAM Performance
Description
The V82658B04S memory module is organized
8,388,608 x 64 bits in a 200 pin memory module.
The 8M x 64 memory module uses 4 Mosel-Vitelic
8M x 16 DDR SDRAM. The x64 modules are ideal
for use in high performance computer systems
where increased memory density and fast access
times are required.
Component Used
-7
-75
-8
Units
t
CK
Clock Frequency
(max.)
143
(PC266A)
133
(PC266B)
125
(PC200)
MHz
t
AC
Clock Access Time
CAS Latency = 2.5
7
7.5
8
ns
Module Speed
A1
PC1600 (100MHz @ CL2)
B0
PC2100B (133MHz @ CL2.5)
B1
PC2100A (133MHz @ CL2)
2
MOSEL VITELIC
V82658B04S
V82658B04S Rev. 1.2 March 2002
Part Number Information
V 8 2 65 8 B 0 4 S X T G - XX
DDRSDRAM
2.5V
WIDTH
DEPTH
200 PIN Unbuffered
SODIMM X16 COMPONENT
REFRESH
RATE 4K
4 BANKS
STTL
COMPONENT
REV LEVEL
COMPONENT
PACKAGE, T = TSOP
LEAD FINISH
G = GOLD
SPEED
A1 (100MHZ@CL2)
MOSEL VITELIC
MANUFACTURED
B0 (133MHZ@CL2.5)
B1 (133MHZ@CL2)
MOSEL VITELIC
V82658B04S
3
V82658B04S Rev. 1.2 March 2002
Block Diagram
DQ0
DQ1
DQ2
DQ3
LDM
I/O 0
I/O 1
I/O 2
I/O 3
D0
DQ4
DQ5
DQ6
DQ7
I/O 4
I/O 5
I/O 6
I/O 7
UDM
I/O 8
I/O 9
I/O 10
I/O 11
I/O 12
I/O 13
I/O 14
I/O 15
DQ9
DQ10
DQ11
DQ12
DQ13
DQ14
DQ15
DQ8
DM0
S
LDQS
DQS0
DM1
DQS1
UDQS
A0 - A13
A0-A13: DDR SDRAMs D0 - D3
BA0 - BA1
BA0-BA1: DDR SDRAMs D0 - D3
RAS
RAS: SDRAMs D0 - D3
CAS
CAS: SDRAMs D0 - D3
CKE0
CKE: SDRAMs D0 - D3
WE
WE: SDRAMs D0 - D3
Notes:
1. DQ-to-I/O wiring is shown as recom-
mended but may be changed.
2. DQ/DQS/DM/CKE/CS relationships must
be maintained as shown.
3. DQ, DQS, DM/DQS resistors: 22 Ohms.
4. VDDID strap connections
(for memory device VDD, VDDQ):
STRAP OUT (OPEN): VDD = VDDQ
STRAP IN (VSS): VDD
VDDQ.
S0
A0
Serial PD
A1
A2
SA0
SA1
SA2
SCL
SDA
WP
V
SS
D0 - D3
D0 - D3
V
DD
/V
DDQ
D0 - D3
D0 - D3
VREF
V
DDID
Strap: see Note 4
V
DDSPD
SPD
Clock Wiring
Clock
Input
SDRAMs
CK0/CK0
CK1/CK1
CK2/CK2
2 SDRAMs
2 SDRAMs
NC
*Clock Net Wiring
Card
Edge
Dram1
Cap
Dram3
Cap
R=120
5%
CK
CK
DQ32
DQ33
DQ34
DQ35
LDM
I/O 0
I/O 1
I/O 2
I/O 3
D2
DQ36
DQ37
DQ38
DQ39
I/O 4
I/O 5
I/O 6
I/O 7
UDM
I/O 8
I/O 9
I/O 10
I/O 11
I/O 12
I/O 13
I/O 14
I/O 15
DQ41
DQ42
DQ43
DQ44
DQ45
DQ46
DQ47
DQ40
DM4
S
LDQS
DQS4
DM5
DQS5
UDQS
DQ16
DQ17
DQ18
DQ19
LDM
I/O 0
I/O 1
I/O 2
I/O 3
D1
DQ20
DQ21
DQ22
DQ23
I/O 4
I/O 5
I/O 6
I/O 7
UDM
I/O 8
I/O 9
I/O 10
I/O 11
I/O 12
I/O 13
I/O 14
I/O 15
DQ25
DQ26
DQ27
DQ28
DQ29
DQ30
DQ31
DQ24
DM2
S
LDQS
DQS2
DM3
DQS3
UDQS
DQ48
DQ49
DQ50
DQ51
LDM
I/O 0
I/O 1
I/O 2
I/O 3
D3
DQ52
DQ53
DQ54
DQ55
I/O 4
I/O 5
I/O 6
I/O 7
UDM
I/O 8
I/O 9
I/O 10
I/O 11
I/O 12
I/O 13
I/O 14
I/O 15
DQ57
DQ58
DQ58
DQ60
DQ61
DQ62
DQ63
DQ56
DM6
S
LDQS
DQS6
DM7
DQS7
UDQS
4
MOSEL VITELIC
V82658B04S
V82658B04S Rev. 1.2 March 2002
Pin Configurations (Front Side/Back Side)
Notes:
* These pins are not used in this module.
Pin
Front
Pin
Front
Pin
Front
Pin
Back
Pin
Back
Pin
Back
1
3
5
7
9
11
13
15
17
19
21
23
25
27
29
31
33
35
37
39
41
43
45
47
49
51
53
55
57
59
61
63
65
VREF
VSS
DQ0
DQ1
VDD
DQS0
DQ2
VSS
DQ3
DQ8
VDD
DQ9
DQS1
VSS
DQ10
DQ11
VDD
CK0
CK0
VSS
DQ16
DQ17
VDD
DQS2
DQ18
VSS
DQ19
DQ24
VDD
DQ25
DQS3
VSS
DQ26
67
69
71
73
75
77
79
81
83
85
87
89
91
93
95
97
99
101
103
105
107
109
111
113
115
117
119
121
123
125
127
129
131
133
DQ27
VDD
CB0
CB1
VSS
DQS8
CB2
VDD
CB3
DU
VSS
CK2
CK2
VDD
CKE1
DU(A13)
A12
A9
VSS
A7
A5
A3
A1
VDD
A10/AP
BA0
WE
S0
DU
VSS
DQ32
DQ33
VDD
DQS4
135
137
139
141
143
145
147
149
151
153
155
157
159
161
163
165
167
169
171
173
175
177
179
181
183
185
187
189
191
193
195
197
199
DQ34
VSS
DQ35
DQ40
VDD
DQ41
DQS5
VSS
DQ42
DQ43
VDD
VDD
VSS
VSS
DQ48
DQ49
VDD
DQS6
DQ50
VSS
DQ51
DQ56
VDD
DQ57
DQS7
DQ58
DQ58
DQ59
VDD
SDA
SCL
VDDSPD
VDDID
2
4
6
8
10
12
14
16
18
20
22
24
26
28
30
32
34
36
38
40
42
44
46
48
50
52
54
56
58
60
62
64
66
VREF
VSS
DQ4
DQ5
VDD
DM0
DQ6
VSS
DQ7
DQ12
VDD
DQ13
DM1
VSS
DQ14
DQ15
VDD
VDD
VSS
VSS
DQ20
DQ21
VDD
DM2
DQ22
VSS
DQ23
DQ28
VDD
DQ29
DM3
VSS
DQ30
68
70
72
74
76
78
80
82
84
86
88
90
92
94
96
98
100
102
104
106
108
110
112
114
116
118
120
122
124
126
128
130
132
134
DQ31
VDD
CB4
CB5
VSS
DM8
CB6
VDD
CB7
DU/(RESET)
VSS
VSS
VDD
VDD
CKE0
DU(BA2)
A11
A8
VSS
A6
A4
A2
A0
VDD
BA1
RAS
CAS
S1
DU
VSS
DQ36
DQ37
VDD
DM4
136
138
140
142
144
146
148
150
152
154
156
158
160
162
164
166
168
170
172
174
176
178
180
182
184
186
188
190
192
194
196
198
200
DQ38
VSS
DQ39
DQ44
VDD
DQ45
DM5
VSS
DQ46
DQ47
VDD
CK1
CK1
VSS
DQ52
DQ53
VDD
DM6
DQ54
VSS
DQ55
DQ60
VDD
DQ61
DM7
VSS
DQ62
DQ63
VDD
SA0
SA1
SA2
DU
Pin Names
Pin Pin
Description
A0~A11
Address Input (Multiplexed)
BA0~BA1
Bank Select Address
DQ0~DQ63
Data Input/Output
DQS0~DQS7
Data Strobe Input/Output
CK0~CK2, CK0~CK2,
Clock Input
CKE0
Clock Enable Input
CS0
Chip Select Input
RAS
Row Address Strobe
CAS
Column Address Strobe
WE
Write Enable
DM0~DM7
Data - In Mask
VDD
Power Supply (2.5V)
VDDQ
Power Supply for DQS(2.5V)
VSS
Ground
VREF
Power Supply for Reference
VDDSPD
Serial EEPOM Power Supply (2.3V
to 3.6V)
SDA
Serial Data I/O
SCL
Serial Clock
SA0~2
Address in EEPROM
VDDID
VDD Identification Flag
NC
No Connection
Pin Pin
Description
Key
Key
MOSEL VITELIC
V82658B04S
5
V82658B04S Rev. 1.2 March 2002
Serial Presence Detect Information
Bin Sort:
A1 (PC1600 @ CL2)
B0 (PC2100B @ CL2.5)
B1 (PC2100A @ CL2)
Byte #
Function described
Function Supported
Hex value
A1 B0
B1
A1 B0
B1
0
Defines # of Bytes written into serial memory at module manufacturer
128bytes
80h
1
Total # of Bytes of SPD memory device
256bytes
08h
2
Fundamental memory type
SDRAM DDR
07h
3
# of row address on this assembly
12
0Ch
4
# of column address on this assembly
9
09h
5
# of module Rows on this assembly
1Bank
01h
6
Data width of this assembly
64 bits
40h
7
Data width of this assembly
-
00h
8
VDDQ and interface standard of this assembly
SSTL 2.5V
04h
9
DDR SDRAM cycle time at CAS Latency =2.5
8ns
7.5ns
7ns
80h
75h
70h
10
DDR SDRAM Access time from clock at CL=2.5
0.8ns 0.75ns 0.70ns
80h
75h
70h
11
DIMM configuration type(Non-parity, Parity, ECC)
Non-parity, ECC
00
12
Refresh rate & type
15.6us & Self refresh
80h
13
Primary DDR SDRAM width
x16
10h
14
Error checking DDR SDRAM data width
x0
00h
15
Minimum clock delay for back-to-back random column
address
t
CCD
=1CLK 01h
16
DDR SDRAM device attributes : Burst lengths supported
2,4,8
0Eh
17
DDR SDRAM device attributes : # of banks on each DDR SDRAM
4 banks
04h
18
DDR SDRAM device attributes : CAS Latency supported
2,2.5
0Ch
19
DDR SDRAM device attributes : CS Latency
0CLK
01h
20
DDR SDRAM device attributes : WE Latency
1CLK
02h
21
DDR SDRAM module attributes
Unbuffered
Diff Clock
20h
22
DDR SDRAM device attributes : General
+/-0.2V voltage tolerance
00h
23
DDR SDRAM cycle time at CL =2
10ns
10ns
7.5ns
A0h
A0h
75h
24
DDR SDRAM Access time from clock at CL =2
0.8ns 0.8ns 0.75ns
80h
80h
75h
25
DDR SDRAM cycle time at CL =1.5
-
-
-
00h
26
DDR SDRAM Access time from clock at CL =1.5
-
-
-
00h
27
Minimum row precharge time (=t
RP
)
20ns 20ns 18ns 50h 50h 48h
28
Minimum row activate to row active delay(=t
RRD
) 15ns
15ns
14ns
3Ch
3Ch
38h
6
MOSEL VITELIC
V82658B04S
V82658B04S Rev. 1.2 March 2002
29
Minimum RAS to CAS delay(=t
RCD
)
20ns 20ns 18ns 50h 50h 48h
30
Minimum active to precharge time(=t
RAS
) 50ns
45ns
45ns
32h
2Dh
2Dh
31
Module ROW density
64MB
10h
32
Command and address signal input setup time
1.1ns
0.9ns
0.9ns
B0h
90h
90h
33
Command and address signal input hold time
1.1ns
0.9ns
0.9ns
B0h
90h
90h
34
Data signal input setup time
0.6ns
0.5ns
0.5ns
60h
50h
50h
35
Data signal input hold time
0.6ns
0.5ns
0.5ns
60h
50h
50h
36-40
Superset information (may be used in future)
-
00h
41
SDRAM device minimum active to active/auto-refresh time
(=t
RC
)
70ns 65ns 60ns
46h
41h 3Ch
42
SDRAM device minimum active to autorefresh to active/auto-refresh
time (=t
RFC
)
80ns 75ns 67ns
50h
4Bh 43h
43
SDRAM device maximum device cycle time (=t
CK MAX
)
12ns 12ns 12ns
30h
30h 30h
44
SDRAM device maximum skew between DQS and DQ signals
(=t
DQSQ
)
0.6ns 0.5ns 0.5ns
3Ch
32h 32h
45
SDRAM device maximum read datahold skew factor (=t
QHS
)
1ns 0.75ns
0.75ns
A0h
75h 75h
46-61
Superset information (may be used in future)
-
00h
62
SPD data revision code
Initial release
00h
63
Checksum for Bytes 0 ~ 62
-
BBh
01h
A0h
64
Manufacturer JEDEC ID code
Mosel Vitelic
40h
65 -71
....... Manufacturer JEDEC ID code
Mosel Vitelic
00h
72
Manufacturing location
01h
73-90
Module part number (ASCII)
V82658B04S
91
Manufacturer revison code (For PCB)
0
00
92
Manufacturer revison code (For component)
0
00
93
Manufacturing date (Week)
-
-
94
Manufacturing date (Year)
-
-
95~98
Assembly serial #
-
-
99~127 Manufacturer specific data (may be used in future)
Undefined
00h
128~255 Open for customer use
Undefined
00h
Byte #
Function described
Function Supported
Hex value
A1 B0
B1
A1 B0
B1
Serial Presence Detect Information (cont.)
MOSEL VITELIC
V82658B04S
7
V82658B04S Rev. 1.2 March 2002
DC Operating Conditions
(T
A
= 0 to 70C, Voltage referenced to V
SS
= 0V)
Notes: 1. V
DDQ
must not exceed the level of V
DD
.
2. V
IL
(min) is acceptable -1.5V AC pulse width with 5ns of duration.
3. The value of V
REF
is approximately equal to 0.5V
DDQ
.
AC Operating Conditions
(T
A
= 0 to 70 C, Voltage referenced to V
SS
= 0V)
Notes: 1. VID is the magnitude of the difference between the input level on CK and the input on CK.
2. The value of VIX is expected to equal 0.5*V
DDQ
of the transmitting device and must track variations in the DC level of the
same.
Parameter
Symbol
Min
Typ.
Max
Unit
Note
Power Supply Voltage
V
DD
2.3
2.5
2.7
V
Power Supply Voltage
V
DDQ
2.3
2.5
2.7
V
1
Input High Voltage
V
IH
V
REF
+ 0.15
-
V
DDQ
+ 0.3
V
Input Low Voltage
V
IL
-0.3
-
V
REF
- 0.15
V
2
I/O Termination Voltage
V
TT
V
REF
- 0.04
V
REF
V
REF
+ 0.04
V
Reference Voltage
V
REF
1.15
1.25
1.35
V
3
Input Leakage Current
I
I
-2
-
2
A
Output Leakage Current
IO
z
-5
-
5
A
Output High Current (V
OUT
= 1.95V)
IO
H
-16.8
-
-
mA
Output Low Current (V
OUT
= 0.35V)
IO
L
16.8
-
-
mA
Parameter Symbol
Min
Max
Unit
Note
Input High (Logic 1) Voltage, DQ, DQS and DM signals
V
IH(AC)
V
REF
+ 0.31
V
Input Low (Logic 0) Voltage, DQ, DQS and DM signals
V
IL(AC)
V
REF
- 0.31
V
Input Differential Voltage, CK and CK inputs
V
ID(AC)
0.7
V
DDQ
+ 0.6
V
1
Input Crossing Point Voltage, CK and CK inputs
V
IX(AC)
0.5*V
DDQ-0.2
0.5*V
DDQ+0.2
V
2
8
MOSEL VITELIC
V82658B04S
V82658B04S Rev. 1.2 March 2002
AC Operating Test Conditions
(T
A
= 0 to 70C, Voltage referenced to V
SS
= 0V)
Input/Output Capacitance
(V
DD
= 2.5V, V
DDQ
= 2.5V, T
A
= 25C, f = 1MHz)
Parameter Value
Unit
Reference Voltage
V
DDQ
x 0.5
V
Termination Voltage
V
DDQ
x 0.5
V
AC Input High Level Voltage (V
IH
, min)
V
REF
+ 0.31
V
AC Input Low Level Voltage (V
IL
, max)
V
REF
- 0.31
V
Input Timing Measurement Reference Level Voltage
V
REF
V
Output Timing Measurement Reference Level Voltage
V
TT
V
Input Signal maximum peak swing
1.5
V
Input minimum Signal Slew Rate
1
V/ns
Termination Resistor (R
T
) 50
Series Resistor (R
S
)
25
Output Load Capacitance for Access Time Measurement (C
L
) 30
pF
Parameter
Symbol Min
Max
Unit
Input capacitance (A
0
~ A
11
, BA
0
~ BA
1
, RAS, CAS, WE) CIN
1
36
45
pF
Input capacitance (CKE
0
) CIN
2
36
45
pF
Input capacitance (CS
0
) CIN
3
34
42
pF
Input capacitance (CLK
1
, CLK
2
) CIN
4
34
38
pF
Data & DQS input/output capacitance (DQ
0
~DQ
63
) C
OUT
8
9
pF
Input capacitance (DM0~DM8)
CIN
5
8
9
pF
Output Load Circuit (SSTL_2)
Output
Z0=50
C
LOAD
=30pF
V
REF
=0.5*V
DDQ
R
T
=50
V
tt
=0.5*V
DDQ
MOSEL VITELIC
V82658B04S
9
V82658B04S Rev. 1.2 March 2002
DDR SDRAM I
DD
SPEC TABLE
* Module I
DD
was calculated on the basis of component I
DD
and can be differently measured according to DQ loading cap.
Detailed test conditions for DDR SDRAM IDD1 & IDD
IDD1 : Operating current: One bank operation
1. Typical Case : Vdd = 2.5V, T=25' C
2. Worst Case : Vdd = 2.7V, T= 10' C
3. Only one bank is accessed with tRC(min), Burst Mode, Address and Control inputs on NOP edge are changing once
per clock cycle. lout = 0mA
4. Timing patterns
- DDR200(100Mhz, CL=2) : tCK = 10ns, CL2, BL=4, tRCD = 2*tCK, tRAS = 5*tCK
Read : A0 N R0 N N P0 N A0 N - repeat the same timing with random address changing
*50% of data changing at every burst
- DDR266B(133Mhz, CL=2.5) : tCK = 7.5ns, CL=2.5, BL=4, tRCD = 3*tCK, tRC = 9*tCK, tRAS = 5*tCK
Read : A0 N N R0 N P0 N N N A0 N - repeat the same timing with random address changing
*50% of data changing at every burst
- DDR266A (133Mhz, CL=2) : tCK = 7.5ns, CL=2, BL=4, tRCD = 3*tCK, tRC = 9*tCK, tRAS = 5*tCK
Read : A0 N N R0 N P0 N N N A0 N - repeat the same timing with random address changing
*50% of data changing at every burst
Legend : A=Activate, R=Read, W=Write, P=Precharge, N=NOP
Symbol
B1(DDR266@CL=2) B0(DDR266@CL=2.5)
A1(DDR200@CL=2)
Unit
Notes
Typical
Worst
Typical
Worst
Typical
Worst
IDD0
410
470
410
470
370
410
mA
IDD1
510
590
510
590
470
550
mA
IDD2P
110
130
110
130
90
110
mA
IDD2F
210
250
210
250
190
210
mA
IDD2Q
170
190
170
190
150
170
mA
IDD3P
150
170
150
170
130
150
mA
IDD3N
230
270
230
270
190
230
mA
IDD4R
730
850
730
850
610
750
mA
IDD4W
770
910
770
910
650
810
mA
IDD5
770
870
770
870
730
810
mA
IDD6
Normal
8
8
8
8
8
8
mA
Low power
4
4
4
4
4
4
mA
Optional
IDD7A
1390
1610
1390
1610
1130
1330
mA
10
MOSEL VITELIC
V82658B04S
V82658B04S Rev. 1.2 March 2002
AC Characteristics
(AC operating conditions unless otherwise noted)
Parameter Symbol
(PC1600) (PC2100B)
(PC2100A)
Unit Note
Min Max Min Max Min Max
Row Cycle Time
t
RC
60 - 65 - 70 - ns
Auto Refresh Row Cycle Time
t
RFC
67 - 75 - 80 - ns
Row Active Time
t
RAS
45 120K 48 120K 50 120K
ns
Row Address to Column Address Delay
t
RCD
18 - 20 - 20 - ns
Row Active to Row Active Delay
t
RRD
14
-
15
-
15
-
ns
Column Address to Column Address Delay
t
CCD
1 - 1 - 1 -
CLK
Row Precharge Time
t
RP
18
- 20 - 20 - ns
Write Recovery Time
t
WR
15 - 15 - 15 - ns
Last Data-In to Read Command
t
DRL
1 - 1 - 1 -
CLK
Auto Precharge Write Recovery + Precharge Time
t
DAL
35 - 35 - 35 - ns
System Clock Cycle Time
CAS Latency = 2.5
t
CK
7 12 7.5 12 8 12
ns
CAS Latency = 2
7.5
12
10
12
10
12
ns
Clock High Level Width
t
CH
0.45 0.55 0.45 0.55 0.45 0.55
CLK
Clock Low Level Width
t
CL
0.45 0.55 0.45 0.55 0.45 0.55
CLK
Data-Out edge to Clock edge Skew
t
AC
-0.75 0.75 -0.75 0.75 -0.8 0.8 ns
DQS-Out edge to Clock edge Skew
t
DQSCK
-0.75 0.75 -0.75 0.75 -0.8 0.8 ns
DQS-Out edge to Data-Out edge Skew
t
DQSQ
- 0.5 -
0.5
- 0.6
ns
Data-Out hold time from DQS
t
QH
t
HPmin
-0.75ns
- t
HPmin
-0.75ns
- t
HPmin
-0.75ns
- ns 1
Clock Half Period
t
HP
t
CH/L
min
- t
CH/L
min
- t
CH/L
min
- ns 1
Input Setup Time (fast slew rate)
t
IS
0.9 - 0.9 - 1.1 - ns
2,3,5,6
Input Hold Time (fast slew rate)
t
IH
0.9 - 0.9 - 1.1 - ns
2,3,5,6
Input Setup Time (slow slew rate)
t
IS
1.0 - 1.0 - 1.1 - ns
2,4,5,6
Input Hold Time (slow slew rate)
t
IH
1.0 - 1.0 - 1.1 - ns
2,4,5,6
Input Pulse Width
t
IPW
2.2 - 2.2 - - -
ns
6
Write DQS High Level Width
t
DQSH
0.4 0.6 0.4 0.6 0.4 0.6
CLK
Write DQS Low Level Width
t
DQSL
0.4 0.6 0.4 0.6 0.4 0.6
CLK
CLK to First Rising edge of DQS-In
t
DQSS
0.75 1.25 0.75 1.25 0.75 1.25
CLK
Data-In Setup Time to DQS-In (DQ & DM)
t
DS
0.5 - 0.5 - 0.6 - ns 7
Data-in Hold Time to DQS-In (DQ & DM)
t
DH
0.5 - 0.5 - 0.6 - ns 7
DQ & DM Input Pulse Width
t
DIPW
1.75 -
1.75
- 2 -
ns
Read DQS Preamble Time
t
RPRE
0.9 1.1 0.9 1.1 0.9 1.1
CLK
Read DQS Postamble Time
t
RPST
0.4 0.6 0.4 0.6 0.4 0.6
CLK
MOSEL VITELIC
V82658B04S
11
V82658B04S Rev. 1.2 March 2002
AC Characteristics (cont.)
Notes: 1. This calculation accounts for tDQSQ(max), the pulse width distortion of on-chip circuit and jitter.
2. Data sampled at the rising edges of the clock : A0~A11, BA0~BA1, CKE, CS, RAS, CAS, WE.
3. For command/address input slew rate >=1.0V/ns
4. For command/address input slew rate >=0.5V/ns and <1.0V/ns
5. CK, CK slew rates are >=1.0V/ns
6. These parameters guarantee device timing, but they are not necessarily tested on each device, and they may be guaranteed
by design or tester correlation.
7. Data latched at both rising and falling edges of Data Strobes(DQS) : DQ, DM
8. Minimum of 200 cycles of stable input clocks after Self Refresh Exit command, where CKE is held high, is required to complete
Self Refresh Exit and lock the internal DLL circuit of DDR SDRAM.
Absolute Maximum Ratings
Note: Operation at above absolute maximum rating can adversely affect device reliability
Write DQS Preamble Setup Time
t
WPRES
0 - 0 - 0 -
CLK
Write DQS Preamble Hold Time
t
WPREH
0.25 - 0.25 - 0.25 -
CLK
Write DQS Postamble Time
t
WPST
0.4 0.6 0.4 0.6 0.4 0.6
CLK
Mode Register Set Delay
t
MRD
2 - 2 - 2 -
CLK
Power Down Exit Time
t
PDEX
10 - 10 - 10 - ns
Exit Self Refresh to Non-Read Command
t
XSNR
75 - 75 - 80 - ns
Exit Self Refresh to Read Command
t
XSRD
200 - 200 - 200 -
CLK
8
Average Periodic Refresh Interval
t
REFI
- 15.6 - 15.6 - 15.6
us
Parameter Symbol
Rating
Unit
Ambient Temperature
T
A
0
~
70
C
Storage Temperature
T
STG
-55 ~ 125
C
Voltage on Any Pin relative to V
SS
V
IN
, V
OUT
-0.5 ~ 3.6
V
Voltage on V
DD
relative to V
SS
V
DD
-0.5 ~ 3.6
V
Voltage on V
DDQ
relative to V
SS
V
DDQ
-0.5 ~ 3.6
V
Output Short Circuit Current
I
OS
50 mA
Power Dissipation
P
D
8 W
Soldering Temperature Time
T
SOLDER
260 10
C Sec
Parameter Symbol
(PC1600) (PC2100B)
(PC2100A)
Unit Note
Min Max Min Max Min Max
12
MOSEL VITELIC
V82658B04S
V82658B04S Rev. 1.2 March 2002
Package Dimensions
T olerances : .006(.15) unles s otherwis e s pecified
2.70
2.50
Units : Inches (Millimeters )
F ull R 2x
0.17
(4.20)
0.456
11.40
1.896
(47.40)
0.
24
(6.
0
)
0.086
0.
79
(
2
0.
00)
2.15
(63.60)
(67.60)
Detail Z
0.16 0.0039
(4.00 0.10)
0.04 0.0039
(1.00 0.1)
2-
0.07
(1.80)
1.
25
(
31.
75
)
0.16 0.039
(4.00 0.10)
0.096
(2.40)
0.07
(1.8)
0.095 Max
0.04
0.0039
(1.00 0.10)
(2.40 Max)
0.
15
7 M
i
n
(
4
.
00 M
i
n
)
1
0.024 T Y P
0.018 0.001
0.01
(0.25)
(0.45
0.03)
(0.60 T Y P )
0.
10
2 M
i
n
(
2
.
55 M
i
n
)
Detail Y
2
0.098
2.45
40 42
39 41
Z
Y
199
200
MOSEL VITELIC
V82658B04S
13
V82658B04S Rev. 1.2 March 2002
Label Information
C
L
= 2.5 (CLK)
t
RCD
= 3 (CLK)
t
RP
= 3 (CLK)
2533
U
UNBUFFERED DIMM
PC2100
08
SPD Revision 0
0
V82658B04SXXX-XX 64MB CLXX
PC2100U-2533-080-A
XXXX-XXXXXXX
Assembly in Taiwan
A
Gerber file JEDEC
-
-
-
MOSEL VITELIC
Part Number
Module Density
DIMM manufacture date code
Criteria of PC2100 or PC1600
CAS Latency
14
MOSEL VITELIC
V82658B04S
V82658B04S Rev. 1.2 March 2002
WORLDWIDE OFFICES
Copyright , MOSEL VITELIC Corp.
Printed in U.S.A.
The information in this document is subject to change without
notice.
MOSEL VITELIC makes no commitment to update or keep cur-
rent the information contained in this document. No part of this
document may be copied or reproduced in any form or by any
means without the prior written consent of MOSEL-VITELIC.
MOSEL VITELIC subjects its products to normal quality control
sampling techniques which are intended to provide an assurance
of high quality products suitable for usual commercial applica-
tions. MOSEL VITELIC does not do testing appropriate to provide
100% product quality assurance and does not assume any liabil-
ity for consequential or incidental arising from any use of its prod-
ucts. If such products are to be used in applications in which
personal injury might occur from failure, purchaser must do its
own quality assurance testing appropriate to such applications.
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