MOSEL VITELIC

V826664K24S
64M x 64 HIGH PERFORMANCE
UNBUFFERED DDR SDRAM MODULE

PRELIMINARY

V826664K24S Rev. 1.3 January 2003

.Features

184 Pin Unbuffered 67,108,864 x 64 bit
Organization DDR SDRAM Modules

Utilizes High Performance 32M x 8 DDR
SDRAM in TSOPII-66 Packages

Single +2.5V (± 0.2V) Power Supply

Single +2.6V (± 0.1V) Power Supply for DDR400

Programmable CAS Latency, Burst Length, and
Wrap Sequence (Sequential & Interleave)

Auto Refresh (CBR) and Self Refresh

All Inputs, Outputs are SSTL-2 Compatible

8192 Refresh Cycles every 64 ms

Serial Presence Detect (SPD)

DDR SDRAM Performance

Description

The V826664K24S memory module is organized

67,108,864 x 64 bits in a 184 pin memory module.
The 64M x 64 memory module uses 16 Mosel-
Vitelic 32M x 8 DDR SDRAM. The x64 modules are
ideal for use in high performance computer systems
where increased memory density and fast access
times are required.

Module Speed

Units

Clock Frequency

(max.)

200

(PC400C)

200

(PC400B)

200

(PC400A)

166

(PC333)

143

(PC266A)

133

(PC266B)

125

(PC200)

MHz

Clock Cycle Time

CAS Latency = 2

7.5

Clock Cycle Time
CAS Latency = 2.5

7.5

Clock Cycle Time

CAS Latency = 3

RCD

tRP parameter

CLK

tRCD parameter

CLK

MOSEL VITELIC

V826664K24S

V826664K24S Rev. 1.3 January 2003

Functional Block Diagram

DQ4
DQ5
DQ6
DQ7

DQ0
DQ1
DQ2
DQ3

I/O 7
I/O 6
I/O 1
I/O 0

DM0

I/O 5
I/O 4
I/O 3
I/O 2

I/O 0
I/O 1
I/O 6
I/O 7
I/O 2
I/O 3
I/O 4
I/O 5

DQ12
DQ13
DQ14

DQ8
DQ9
DQ10
DQ11

I/O 7
I/O 6
I/O 1
I/O 0

I/O 5
I/O 4
I/O 3

I/O 0
I/O 1
I/O 6
I/O 7
I/O 2
I/O 3
I/O 4

DM1

DQ20
DQ21
DQ22
DQ23

DQ16
DQ17
DQ18
DQ19

I/O 7
I/O 6
I/O 1
I/O 0

D10

I/O 5
I/O 4
I/O 3
I/O 2

I/O 0
I/O 1
I/O 6
I/O 7
I/O 2
I/O 3
I/O 4
I/O 5

DM2

DQ28
DQ29
DQ30
DQ31

DQ24
DQ25
DQ26
DQ27

I/O 7
I/O 6
I/O 1
I/O 0

D11

I/O 5
I/O 4
I/O 3
I/O 2

I/O 0
I/O 1
I/O 6
I/O 7
I/O 2
I/O 3
I/O 4
I/O 5

DM3

DQ36
DQ37
DQ38
DQ39

DQ32
DQ33
DQ34
DQ35

I/O 7
I/O 6
I/O 1
I/O 0

DM4

D12

I/O 5
I/O 4
I/O 3
I/O 2

I/O 0
I/O 1
I/O 6
I/O 7
I/O 2
I/O 3
I/O 4
I/O 5

DQ44
DQ45
DQ46
DQ47

DQ40
DQ41
DQ42
DQ43

I/O 7
I/O 6
I/O 1
I/O 0

D13

I/O 5
I/O 4
I/O 3
I/O 2

I/O 0
I/O 1
I/O 6
I/O 7
I/O 2
I/O 3
I/O 4
I/O 5

DM5

DQ52
DQ53
DQ54
DQ55

DQ48
DQ49
DQ50
DQ51

I/O 7
I/O 6
I/O 1
I/O 0

D14

I/O 5
I/O 4
I/O 3
I/O 2

I/O 0
I/O 1
I/O 6
I/O 7
I/O 2
I/O 3
I/O 4
I/O 5

DQ60
DQ61
DQ62
DQ63

DQ56
DQ57
DQ58
DQ59

I/O 7
I/O 6
I/O 1
I/O 0

D15

I/O 5
I/O 4
I/O 3
I/O 2

I/O 0
I/O 1
I/O 6
I/O 7
I/O 2
I/O 3
I/O 4
I/O 5

DM7

A0 - A12

A0-A12: SDRAMs D0 - D15

Serial PD

SA0

SA1

SA2

SCL

SDA

RAS

RAS: SDRAMs D0 - D15

CAS

CAS: SDRAMs D0 - D15

CKE0

CKE: SDRAMs D0 - D7

WE: SDRAMs D0 - D15

CS0

CS1

Clock Wiring

CK0/CK0

Clock

Input

SDRAMs

CK1/CK1

4 SDRAMs
6 SDRAMs
6 SDRAMs

CKE1

CKE: SDRAMs D8 - D15

BA0 - BA1

BA0-BA1: SDRAMs D0 - D15

DQS0

DQS

DQS4

DQS1

DQS5

DQS

DQS2

DQS

DQS3

DQS

DM6

DQS6

DQS7

DQ15

I/O 2

I/O 5

DQS

CK2/CK2

Notes:
1. DQ-to-I/O wiring is shown as recom-
mended but may be changed.
2. DQ/DQS/DM/CKE/S relationships must

be maintained as shown.
3. DQ, DQS, DM resistors: 22 Ohms.
4. VDDID strap connections
(for memory device VDD, VDDQ):

STRAP OUT (OPEN): VDD = VDDQ
STRAP IN (VSS): VDD

VDDQ.

*Clock Net Wiring

Card

Edge

Dram1

Dram2

Dram4

Dram5

Dram6

R=120

Dram3

*(Cap.)

Cap will replace DRAM3,4

*If four DRAMs are loaded,

D0 - D15

DDQ

D0 - D15

VREF

DDID

Strap: see Note 4

0.1uF

MOSEL VITELIC

V826664K24S

V826664K24S Rev. 1.3 January 2003

Pin Configurations (Front Side/Back Side)

Notes:

* These pins are not used in this module.

Pin

Front

Pin

Front

Pin

Front

Pin

Back

Pin

Back

Pin

Back

6
7

12
13

18
19

24
25

30
31

VREF

DQ0

VSS

DQ1

DQS0

DQ2
VDD

DQ3

VSS

DQ8
DQ9

DQS1

VDDQ

CK1

VSS

DQ10

DQ11

CKE0

VDDQ

DQ16

DQ17

DQS2

VSS

DQ18

VDDQ

DQ19

37
38

43
44

49
50

54
55

60
61

DQ24

VSS

DQ25

DQS3

VDD

DQ26

DQ27

Vss

CB0*

CB1*

VDD

DQS8*

CB2*

VSS

CB3*

BA1

Key

DQ32

VDDQ

DQ33

DQS4

DQ34

VSS

BA0

DQ35
DQ40

67
68

73
74

79
80

85
86

91
92

VDDQ

DQ41

CAS

VSS

DQS5

DQ42

DQ43

VDD

DQ48

DQ49

VSS

CK2

VDDQ

DQS6

DQ50
DQ51

VSS

VDDID

DQ56

DQ57

VDD

DQS7

DQ58

DQ59

VSS

SDA
SCL

98
99

100

101

102

103

104
105

106

107

108

109

110
111

112

113

114

115

116
117

118

119

120

121

122
123

VSS

DQ4

DQ5

VDDQ

DM0

DQ6
DQ7

VSS

A13*

VDDQ

DQ12

DQ13

DM1

VDD

DQ14

DQ15
CKE1

VDDQ

BA2*

DQ20

A12

VSS

DQ21

A11

DM2

VDD

DQ22

DQ23

124

125

126

127

128

129
130

131

132

133

134

135
136

137

138

139

140

141
142

143

144

145

146
147

148

149

150

151

152
153

VSS

DQ28

DQ29

VDDQ

DM3

DQ30

VSS

DQ31

CB4*

CB5*

VDDQ

CK0*

VSS

DM8*

A10

CB6*

VDDQ

CB7*

key

VSS

DQ36
DQ37

VDD

DM4

DQ38

DQ39

VSS

DQ44

154

155

156

157

158

159
160

161

162

163

164

165
166

167

168

169

170

171
172

173

174

175

176

177
178

179

180

181

182

183
184

RAS

DQ45

VDDQ

CS0

CS1

DM5

VSS

DQ46

DQ47

VDDQ

DQ52
DQ53

VDD

DM6

DQ54

DQ55

VDDQ

DQ60

DQ61

VSS

DM7

DQ62

DQ63

VDDQ

SA0

SA1

SA2

VDDSPD

Pin Names

Pin Pin

Description

CK1, CK1, CK2, CK2 Differential

Clock

Inputs

CS0

Chip Select Input

CKE0

Clock Enable Input

RAS, CAS, WE Commend

Sets

Inputs

A0 ~ A12

Address

BA0, BA1

Bank Address

DQ0~DQ63 Data

Inputs/Outputs

DQS0~DQS7 Data

Strobe

Inputs/Outputs

DM0~DM7 Data-in

Mask

VDD Power

Supply

Key

VDDQ DQs

Power

Supply

VSS Ground

VREF Reference

Power

Supply

VDDSPD

Power Supply for SPD

SA0~SA2 E

PROM Address Inputs

SCL E

PROM Clock

SDA E

PROM Data I/O

VDDID VDD

Identification

Flag

Do not Use

NC No

Connection

Pin Pin

Description

MOSEL VITELIC

V826664K24S

V826664K24S Rev. 1.3 January 2003

Serial Presence Detect Information

Bin Sort:
A1 (PC1600 @ 2-2-2)
B0 (PC2100B @ 2.5-3-3)
B1 (PC2100A @ 2-2-2)

C0 (PC2700 @ 2.5-3-3)
D0 (PC3200 @ 2.5-3-3)
D3 (PC3200 @ 3-3-3 )
D4 (PC3200 @ 3-4-4)

Byte

# Function

described

Function Supported

Hex value

B0 B1 C0

B0 B1

Defines # of Bytes written into serial memory at

module manufacturer

128bytes 80h

Total # of Bytes of SPD memory device

256bytes

08h

Fundamental memory type

SDRAM DDR

07h

# of row address on this assembly

0Dh

# of column address on this assembly

0Ah

# of module Rows on this assembly

2 Bank

02h

Data width of this assembly

64 bits

40h

.........Data width of this assembly

00h

VDDQ and interface standard of this assembly

SSTL 2.5V

04h

DDR SDRAM cycle time at highest CAS Latency 8ns 7.5ns 7ns

6ns

5ns

80h 75h 70h 60h 50h

50h

DDR SDRAM Access time from clock at highest
CL

±0.8

±0.75

±0.70

±0.65

80h 75h 75h 70h 65h

65h

DIMM configuration type(Non-parity, Parity,

ECC)

Non-parity, ECC

00h

Refresh rate & type

7.8us & Self refresh

82h

Primary DDR SDRAM width

08h

Error checking DDR SDRAM data width

N/A

00h

Minimum clock delay for back-to-back random

column

address

CCD

=1CLK 01h

DDR SDRAM device attributes : Burst lengths

supported

2,4,8 0Eh

DDR SDRAM device attributes : # of banks on
each DDR SDRAM

4 banks

04h

DDR SDRAM device attributes : CAS Latency

supported

2,2.5,3

0Ch 0Ch 0Ch 0Ch 1Ch 1Ch 1Ch

DDR SDRAM device attributes : CS Latency

0CLK

01h

DDR SDRAM device attributes : WE Latency

1CLK

02h

DDR SDRAM module attributes

Differential clock /

non Registered

20h

DDR SDRAM device attributes : General

+/-0.2V voltage tolerance

00h

DDR SDRAM cycle time at second highest CL

10ns 10ns 7.5ns 7.5ns 5.0ns 6.0ns 6.0ns A0h A0h 75h 75h 50h

60h

MOSEL VITELIC

V826664K24S

V826664K24S Rev. 1.3 January 2003

DDR SDRAM Access time from clock at highest

±0.8

±0.75

±0.70

±0.65

±0.70

80h 75h 75h 70h 65h

70h

DDR SDRAM cycle time at third highest CL

7.5ns 7.5ns 7.5ns 00h 00h 00h 00h 75h

75h

DDR SDRAM Access time from clock at third

highest CL

- - - -

±0.75

00h

75h

Minimum row precharge time (=t

)

20ns 20ns 15ns 18ns 15ns 15ns 20ns 50h 50h 3Ch 48h 3Ch 3Ch 50h

Minimum row activate to row active delay(=t

RRD

) 15ns 15ns 15ns 12ns 10ns 10ns 10ns 3Ch 3Ch 3Ch 30h

28h

Minimum RAS to CAS delay(=t

RCD

)

20ns 20ns 15ns 18ns 15ns 15ns 20ns 50h 50h 3Ch 48h

3Ch 3Ch 50h

Minimum active to precharge time(=t

RAS

)

50ns 45ns 45ns 42ns 40ns 40ns 40ns 32h 2Dh 2Dh 2Ah 28h

28h

Module ROW density

256MB

40h

Command and address signal input setup time 1.1ns 0.9ns 0.9ns 0.75

0.6ns 0.6ns 0.6ns B0h 90h 90h

75h

60h

Command and address signal input hold time

1.1ns 0.9ns 0.9ns 0.75

0.6ns 0.6ns 0.6ns B0h 90h 90h

75h

60h

Data signal input setup time

0.6ns 0.5ns 0.5ns 0.45

0.4ns 0.4ns 0.4ns 60h 50h 50h

45h

40h

Data signal input hold time

0.6ns 0.5ns 0.5ns 0.45

0.4ns 0.4ns 0.4ns 60h 50h 50h

45h

40h

36-40 Superset information (may be used in future)

00h

SDRAM device minimum active to active/auto-
refresh time

(=t

)

70ns 65ns 65ns 60ns 60ns 60ns 60ns 46h 41h 41h

3Ch 3Ch 3Ch 3Ch

SDRAM device minimum active to autorefresh to

active/auto-refresh time (=t

RFC

)

80ns 75ns 75ns 72ns 70ns 70ns 70ns 50h 4Bh 4Bh 48h

46h

SDRAM device maximum device cycle time

(=t

CK MAX

)

12ns 12ns 12ns 12ns 12ns 12ns 12ns 30h 30h 30h

30h

SDRAM device maximum skew between DQS

and DQ signals (=t

DQSQ

)

0.6ns 0.5ns 0.5ns 0.45

0.4ns 0.4ns 0.4ns 3Ch 32h 32h

2Dh 28h

28h

SDRAM device maximum read datahold skew

factor (=t

QHS

)

1ns 0.75

0.75

0.60

0.55

A0h 75h 75h

60h

55h

46-61 Superset information (may be used in future)

00h

SPD data revision code

Initial release

00h

11h

Checksum for Bytes 0 ~ 62

E8h 23h CBh 4Ch A4h BFh E7h

Manufacturer JEDEC ID code

Mosel Vitelic

40h

65 -

....... Manufacturer JEDEC ID code

00h

Manufacturing location

02=Taiwan 05=China 0A=S-CH

73-90 Module part number (ASCII)

V826664K24S

Manufacturer revison code (For PCB)

Byte

# Function

described

Function Supported

Hex value

B0 B1 C0

B0 B1

Serial Presence Detect Information (cont.)

MOSEL VITELIC

V826664K24S

V826664K24S Rev. 1.3 January 2003

DC Operating Conditions

= 0 to 70°C, Voltage referenced to V

= 0V)

Notes: 1. V

DDQ

must not exceed the level of V

2. V

(min) is acceptable -1.5V AC pulse width with <= 5ns of duration.

AC Operating Conditions

= 0 to 70 °C, Voltage referenced to V

= 0V)

Notes: 1. VID is the magnitude of the difference between the input level on CK and the input on CK.

2. The value of VIX is expected to equal 0.5*V

DDQ

of the transmitting device and must track variations in the DC level of the same.

Manufacturer revison code (For component)

Manufacturing date (Week)

Manufacturing date (Year)

95~9

Assembly serial #

99~1

Manufacturer specific data (may be used in fu-

ture)

Undefined 00h

128~

255

Open for customer use

Undefined

00h

Parameter

Symbol

Min

Typ.

Max

Unit

Note

Power Supply Voltage

2.3

2.5

2.7

Power Supply Voltage for DDR400

2.5

2.6

2.7

Power Supply Voltage

DDQ

2.3

2.5

2.7

Power Supply Voltage for DDR400

DDQ

2.5

2.6

2.7

Input High Voltage

REF

+ 0.15

DDQ

+ 0.3

Input Low Voltage

-0.3

REF

- 0.15

I/O Termination Voltage

REF

- 0.04

REF

+ 0.04

Reference Voltage

REF

DDQ/2

- 0.05

DDQ/2

+ 0.05

Input Leakage Current

-2

µA

Output Leakage Current

-5

µA

Output High Current (V

OUT

= 1.95V)

-16.8

Output Low Current (V

OUT

= 0.35V)

16.8

Parameter Symbol

Min

Max

Unit

Note

Input High (Logic 1) Voltage, DQ, DQS and DM signals

IH(AC)

REF

+ 0.31

Input Low (Logic 0) Voltage, DQ, DQS and DM signals

IL(AC)

REF

- 0.31

Input Differential Voltage, CK and CK inputs

ID(AC)

0.7

DDQ

+ 0.6

Input Crossing Point Voltage, CK and CK inputs

IX(AC)

0.5*V

DDQ-0.2

0.5*V

DDQ+0.2

Byte

# Function

described

Function Supported

Hex value

B0 B1 C0

B0 B1

MOSEL VITELIC

V826664K24S

V826664K24S Rev. 1.3 January 2003

AC Operating Test Conditions

= 0 to 70°C, Voltage referenced to V

= 0V)

Input/Output Capacitance

= 2.5V, V

= 2.6V for DDR400, V

DDQ

= 2.5V, V

DDQ

= 2.6V for DDR400, T

= 25°C, f = 1MHz)

Parameter Value

Unit

Reference Voltage

DDQ

x 0.5

Termination Voltage

DDQ

x 0.5

AC Input High Level Voltage (V

, min)

REF

+ 0.31

AC Input Low Level Voltage (V

, max)

REF

- 0.31

Input Timing Measurement Reference Level Voltage

REF

Output Timing Measurement Reference Level Voltage

Input Signal maximum peak swing

1.5

Input minimum Signal Slew Rate

V/ns

Termination Resistor (R

) 50

Ohm

Series Resistor (R

)

25 Ohm

Output Load Capacitance for Access Time Measurement (C

) 30

Parameter

Symbol Min

Max

Unit

Input capacitance (A

~ A

, BA

~ BA

, RAS, CAS, WE) CIN

60 75

Input capacitance (CKE

) CIN

Input capacitance (CS

) CIN

Input capacitance (CLK

, CLK

) CIN

Data & DQS input/output capacitance (DQ

~DQ

) C

OUT

Input capacitance (DM0~DM8)

CIN

Output Load Circuit (SSTL_2)

Output

Z0=50

LOAD

=30pF

REF

=0.5*V

DDQ

=50

=0.5*V

DDQ

MOSEL VITELIC

V826664K24S

V826664K24S Rev. 1.3 January 2003

DDR SDRAM MODULE I

SPEC TABLE

* Module I

was calculated on the basis of component I

and can be differently measured according to DQ loading cap.

Detailed test conditions for DDR SDRAM IDD1 & IDD

IDD1 : Operating current: One bank operation

1. Typical Case : Vdd = 2.5V, T=25' C

2. Worst Case : Vdd = 2.7V, T= 10' C

3. Only one bank is accessed with tRC(min), Burst Mode, Address and Control inputs on NOP edge are changing once

per clock cycle. lout = 0mA

4. Timing patterns

- DDR200(100Mhz, CL=2) : tCK = 10ns, CL2, BL=4, tRCD = 2*tCK, tRAS = 5*tCK

Read : A0 N R0 N N P0 N A0 N - repeat the same timing with random address changing
*50% of data changing at every burst

- DDR266B(133Mhz, CL=2.5) : tCK = 7.5ns, CL=2.5, BL=4, tRCD = 3*tCK, tRC = 9*tCK, tRAS = 5*tCK

Read : A0 N N R0 N P0 N N N A0 N - repeat the same timing with random address changing
*50% of data changing at every burst

- DDR266A (133Mhz, CL=2) : tCK = 7.5ns, CL=2, BL=4, tRCD = 3*tCK, tRC = 9*tCK, tRAS = 5*tCK

Read : A0 N N R0 N P0 N N N A0 N - repeat the same timing with random address changing
*50% of data changing at every burst

Legend : A=Activate, R=Read, W=Write, P=Precharge, N=NOP

Symbol

PC1600@CL=2

PC2100B@CL=2.5

PC2100A@CL=2

PC2700A@CL=2.5

D0/D3/D4

PC3200A@CL=3

Unit

IDD0

720

800

880

960

IDD1

800

960

1120

1280

IDD2P

120

IDD2F

440

500

560

620

IDD2Q

280

340

380

420

IDD3P

480

500

580

660

IDD3N

720

740

900

1060

IDD4R

1200

1520

1840

2160

IDD4W

1040

1360

1680

2000

IDD5

1440

1520

1600

1680

IDD6

Normal

Low power

IDD7

2000

2400

2800

3200

MOSEL VITELIC

V826664K24S

V826664K24S Rev. 1.3 January 2003

AC Characteristics

(AC operating conditions unless otherwise noted)

Parameter

Sym-

bol

(DDR400A)

(DDR400B)

(DDR400C)

(DDR333)

(DDR266A)

(DDR266B)

(DDR200)

Unit Note

Min Max

Min Max Min

Max

Row Cycle Time

- 60

- 65

- 65 - 70 - ns

Auto Refresh Row Cycle Time

RFC

- 70

- 72

- 75 - 75 - 80 - ns

Row Active Time

RAS

120K 40

120K 42 120K 45 120K 45 120K 50 120K ns

Row Address to Column Address

Delay

RCD

- 15

- 20

- 18

- 15

- 20 - 20 - ns

Row Active to Row Active Delay

RRD

Column Address to Column Ad-

dress Delay

CCD

1 - 1 - 1 - 1 - 1 - 1 - 1 -

CLK

Row Precharge Time

- 15

- 20

- 18

- 15

- 20 - 20 - ns

Write Recovery Time

- 15

- 12

- 15 - 15 - 15 - ns

Last Data-In to Read Command

DRL

1 - 1 - 1 - 1 - 1 - 1 - 1 -

CLK

Auto Precharge Write Recovery +

Precharge Time

DAL

35 - 35 - 35 - 35 - 35 - 35 - 35 - ns

System Clock Cy-

cle Time

CAS Latency

= 3

12 5

12 -

CAS Latency

= 2.5

12 6

12 6 12 7 12

7.5 12 8 12

CAS Latency

= 2

7.5 12 7.5 12 7.5 12 7.5 12 7.5 12 10 12

10 12 ns

Clock High Level Width

0.45 0.55 0.45 0.55 0.45 0.55 0.45 0.55 0.45 0.55 0.45 0.55 0.45 0.55

CLK

Clock Low Level Width

0.45 0.55 0.45 0.55 0.45 0.55 0.45 0.55 0.45 0.55 0.45 0.55 0.45 0.55

CLK

Data-Out edge to Clock edge

Skew

-0.65 0.65 -0.65 0.65 -0.65 0.65 -0.75 0.75 -0.75 0.75 -0.75 0.75 -0.8 0.8 ns

DQS-Out edge to Clock edge

Skew

DQSCK

-0.60 0.60 -0.60 0.60

-0.60 0.60

-0.75 0.75 -0.75 0.75 -0.75 0.75 -0.8 0.8 ns

DQS-Out edge to Data-Out edge

Skew

DQSQ

- 0.40 - 0.40 - 0.40 - 0.45 - 0.5 -

0.5

- 0.6

Data-Out hold time from DQS

HPmin

0.75ns

- t

HPmin

0.75ns

- t

HPmin

0.75ns

- t

HPmin

0.75ns

- t

HPmin

0.75ns

- t

HPmin

0.75ns

- t

HPmin

0.75n

- ns 1

Clock Half Period

CH/L

min

- t

CH/L

min

- t

CH/L

min

- t

CH/L

min

- t

CH/L

min

- t

CH/L

min

- t

CH/L

min

- ns 1

Input Setup Time (fast slew rate)

0.6 - 0.6 - 0.6 - 0.75 - 0.9 - 0.9 - 1.1 - ns

2,3,5,

Input Hold Time (fast slew rate)

0.6

- 0.6

- 0.75

- 0.9 - 0.9 - 1.1 - ns

2,3,5,

Input Setup Time (slow slew rate)

0.75 - 0.75 - 0.75 - 0.8 - 1.0 - 1.0 - 1.1 - ns

2,4,5,

MOSEL VITELIC

V826664K24S

V826664K24S Rev. 1.3 January 2003

AC Characteristics (cont.)

Notes: 1. This calculation accounts for tDQSQ(max), the pulse width distortion of on-chip circuit and jitter.

2. Data sampled at the rising edges of the clock : A0~A11, BA0~BA1, CKE, CS, RAS, CAS, WE.
3. For command/address input slew rate >=1.0V/ns
4. For command/address input slew rate >=0.5V/ns and <1.0V/ns
5. CK, CK slew rates are >=1.0V/ns
6. These parameters guarantee device timing, but they are not necessarily tested on each device, and they may be guaranteed

by design or tester correlation.

7. Data latched at both rising and falling edges of Data Strobes(DQS) : DQ, DM
8. Minimum of 200 cycles of stable input clocks after Self Refresh Exit command, where CKE is held high, is required to complete

Self Refresh Exit and lock the internal DLL circuit of DDR SDRAM.

Input Hold Time (slow slew rate)

0.75

- 0.75

- 0.8

- 1.0 - 1.0 - 1.1 - ns

2,4,5,

Input Pulse Width

IPW

0.4 0.6 0.4 0.6 0.4 0.6 0.4 0.6 2.2 - 2.2 -

- - ns 6

Write DQS High Level Width

DQSH

0.35 0.35 0.35 0.35 0.35 0.35 0.35

CLK

Write DQS Low Level Width

DQSL

0.35 0.35 0.35 0.35 0.35 0.35 0.35

CLK

CLK to First Rising edge of DQS-
In

DQSS

0.72 1.25 0.72 1.25 0.72 1.25 0.75 1.25 0.75 1.25 0.75 1.25 0.75 1.25

CLK

Data-In Setup Time to DQS-In

(DQ & DM)

0.40 - 0.40 - 0.40 - 0.45 - 0.5 - 0.5 - 0.6 - ns 7

Data-in Hold Time to DQS-In (DQ

& DM)

0.40 - 0.40 - 0.40 - 0.45

- 0.5 - 0.5 - 0.6 - ns 7

DQ & DM Input Pulse Width

DIPW

1.75 - 1.75 - 1.75 - 1.75 - 1.75 - 1.75 - 2 - ns

Read DQS Preamble Time

RPRE

0.9 1.1 0.9 1.1 0.9 1.1 0.9 1.1 0.9 1.1 0.9 1.1 0.9 1.1

CLK

Read DQS Postamble Time

RPST

0.4 0.6 0.4 0.6 0.4 0.6 0.4 0.6 0.4 0.6 0.4 0.6 0.4 0.6

CLK

Write DQS Preamble Setup Time t

WPRES

0 - 0 - 0 - 0 - 0 - 0 - 0 -

CLK

Write DQS Preamble Hold Time t

WPREH

0.25 - 0.25 - 0.25 - 0.25 - 0.25 - 0.25 - 0.25 -

CLK

Write DQS Postamble Time

WPST

0.4 0.6 0.4 0.6 0.4 0.6 0.4 0.6 0.4 0.6 0.4 0.6 0.4 0.6

CLK

Mode Register Set Delay

MRD

CLK

Power Down Exit Time to any

command

XPDN

1 - 1 - 1 - 1 - 1 - 1 - 1 -

CLK

Exit Self Refresh to Non-Read

Command

XSNR

200 - 200 - 200 - 200 - 75 - 75 - 80 -

CLK

Exit Self Refresh to Read Com-

mand

XSRD

200 - 200 - 200 - 200 - 200 - 200 - 200 -

CLK

Average Periodic Refresh Interval t

REFI

- 7.8

Parameter

Sym-

bol

(DDR400A)

(DDR400B)

(DDR400C)

(DDR333)

(DDR266A)

(DDR266B)

(DDR200)

Unit Note

Min Max

Min Max Min

Max

MOSEL VITELIC

V826664K24S

V826664K24S Rev. 1.3 January 2003

Absolute Maximum Ratings

Note: Operation at above absolute maximum rating can adversely affect device reliability

Parameter Symbol

Rating

Unit

Ambient Temperature

°C

Storage Temperature

STG

-55 ~ 125

°C

Voltage on Any Pin relative to V

, V

OUT

-0.5 ~ 3.6

Voltage on V

relative to V

-0.5 ~ 3.6

Voltage on V

DDQ

relative to V

DDQ

-0.5 ~ 3.6

Output Short Circuit Current

50 mA

Power Dissipation

9.5

Soldering Temperature · Time

SOLDER

260 · 10

°C · Sec

MOSEL VITELIC

V826664K24S

V826664K24S Rev. 1.3 January 2003

5.25

0.006

5.077

Units : Inches (Millimeters)

0.050

0.0078

0.006

(0.20

0.15)

(

10.

)

(1.270)

100

.
5

)

Detail B

0.089

(2.26)

(128.950)

(133.350

0.15

)

0.250

(6.350

)

Detail A

0.157
(4.00)

0.071

(1.80)

0.039

0.002

(1.000

0.050)

(3.80)

2.175

(6.62)

(64.77)

(49.53)

(

)

2.55

1.95

0.26

0.1496

1.25

0.006

(31.75

0.15)

)

(

)

0.142 Max

0.050

0.0039

(1.270

0.10)

(3.81 Max)

Package Dimensions

MOSEL VITELIC

V826664K24S

V826664K24S Rev. 1.3 January 2003

Label Information

= 2.5 (CLK)

RCD

= 3 (CLK)

2533

UNBUFFERED DIMM

PC2100

SPD Revision

V826664K24SXXX-XX 512MB CLXX
PC2100U-2533-080-A
XXXX-XXXXXXX
Assembly in Taiwan

Gerber file

MOSEL VITELIC

Part Number

Module Density

DIMM manufacture date code

Criteria of PC2100 or PC1600

CAS Latency

= 2.5 (CLK)

RCD

= 3 (CLK)

2533

UNBUFFERED DIMM

PCXXXX

SPD Revision

V826664K24SXXX-XX 512MB CLXX
PCXXXXU-2533-0-XX
XXXX-XXXXXXX
Assembly in Taiwan

MOSEL VITELIC

Part Number

Module Density

DIMM manufacture date code

Criteria of PC2700

or PC3200

CAS Latency

Gerber file used for this design
"A" : Reference design for raw card A is used for this assembly
"B" : Reference design for raw card B is used for this assembly
"C" : Reference design for raw card C is used for this assembly
"Z" : None of the reference design were used for this assembly

Revision number of the reference design used
"1" : 1st Revision
"2" : 2nd Revision
blank : not applicable

MOSEL VITELIC

V826664K24S

V826664K24S Rev. 1.3 January 2003

WORLDWIDE OFFICES

Printed in U.S.A.

The information in this document is subject to change without
notice.

MOSEL VITELIC makes no commitment to update or keep cur-
rent the information contained in this document. No part of this
document may be copied or reproduced in any form or by any
means without the prior written consent of MOSEL-VITELIC.

MOSEL VITELIC subjects its products to normal quality control
sampling techniques which are intended to provide an assurance
of high quality products suitable for usual commercial applica-
tions. MOSEL VITELIC does not do testing appropriate to provide
100% product quality assurance and does not assume any liabil-
ity for consequential or incidental arising from any use of its prod-
ucts. If such products are to be used in applications in which
personal injury might occur from failure, purchaser must do its
own quality assurance testing appropriate to such applications.

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