MOSEL VITELIC

V827332N04S
2.5 VOLT 32M x 72 HIGH PERFORMANCE
REGISTERED ECC DDR SDRAM MODULE

PRELIMINARY

V827332N04S Rev. 1.1 May 2002

Features

184 Pin Registered 33,554,432 x 72 bit
Organization DDR SDRAM Modules

Utilizes High Performance 32M x 4 DDR
SDRAM in TSOPII-66 Packages

Single +2.5V (± 0.2V) Power Supply

Programmable CAS Latency, Burst Length, and
Wrap Sequence (Sequential & Interleave)

Auto Refresh (CBR) and Self Refresh

All Inputs, Outputs are SSTL-2 Compatible

4096 Refresh Cycles every 64 ms

Serial Presence Detect (SPD)

DDR SDRAM Performance

Description

The V827332N04S memory module is organized

33,554,432 x 72 bits in a 184 pin memory module.
The 32M x 72 memory module uses 18 Mosel-
Vitelic 32M x 4 DDR SDRAM. The x72 modules are
ideal for use in high performance computer systems
where increased memory density and fast access
times are required.

Component Used

-7

-75

-8

Units

Clock Frequency

(max.)

143

(PC266A)

133

(PC266B)

125

(PC200)

MHz

Clock Access Time
CAS Latency = 2.5

7.5

Module Speed

PC1600 (100MHz @ CL2)

PC2100B (133MHz @ CL2.5)

PC2100A (133MHz @ CL2)

Standard Module

Low Profile Module

MOSEL VITELIC

V827332N04S

V827332N04S Rev. 1.1 May 2002

Block Diagram

DQ4
DQ5
DQ6
DQ7

DQ0
DQ1
DQ2
DQ3

DQS0

DQ12
DQ13
DQ14

DQ8
DQ9
DQ10
DQ11

DQS9

DQ20
DQ21
DQ22
DQ23

DQ16
DQ17
DQ18
DQ19

DQS11

DQ28
DQ29
DQ30
DQ31

DQ24
DQ25
DQ26
DQ27

DQS12

DQ36
DQ37
DQ38
DQ39

DQ32
DQ33
DQ34
DQ35

DQS13

DQ44
DQ45
DQ46
DQ47

DQ40
DQ41
DQ42
DQ43

DQS14

DQ52
DQ53
DQ54
DQ55

DQ48
DQ49
DQ50
DQ51

DQ60
DQ61
DQ62
DQ63

DQ56
DQ57
DQ58
DQ59

DQS16

RS0

DQS4

DQS1

DQS5

DQS2

DQS3

DQS15

DQS6

DQS7

DQ15

CB4
CB5
CB6
CB7

CB0
CB1
CB2
CB3

DQS8

DQS17

RAS
CAS
CKE0

BA0-BAN
A0-A13

RS0B

RS0A

RBA0 - RBAn
RA0 - RA12
RRAS
RCAS
RCKE0A

RWE

RCKE0B

BA0 -BAn : SDRAMs DQ0 - D17
A0 -An : SDRAMs D0 - D17
RAS : SDRAMs D0 - D17

CAS : SDRAMs DQ0 - D17

CKE : SDRAMs D0 - D8
CKE : SDRAMs D9 - D17
WE: SDRAMs D0 - D17

R
E
G
I
S
T
E
R

DQS

I/O 3
I/O 2
I/O 1
I/O 0

DQS

I/O 3
I/O 2
I/O 1
I/O 0

DQS

I/O 3
I/O 2
I/O 1
I/O 0

DQS

I/O 3
I/O 2
I/O 1
I/O 0

DQS

I/O 3
I/O 2
I/O 1
I/O 0

DQS

I/O 3
I/O 2
I/O 1
I/O 0

DQS

I/O 3
I/O 2
I/O 1
I/O 0

DQS

I/O 3
I/O 2
I/O 1
I/O 0

DQS

I/O 3
I/O 2
I/O 1
I/O 0

VSS

DQS

I/O 3
I/O 2
I/O 1
I/O 0

D17

DQS

I/O 3
I/O 2
I/O 1
I/O 0

DQS

I/O 3
I/O 2
I/O 1
I/O 0

D10

DQS

I/O 3
I/O 2
I/O 1
I/O 0

D11

DQS

I/O 3
I/O 2
I/O 1
I/O 0

D12

DQS

I/O 3
I/O 2
I/O 1
I/O 0

D13

DQS

I/O 3
I/O 2
I/O 1
I/O 0

D14

DQS

I/O 3
I/O 2
I/O 1
I/O 0

D15

DQS

I/O 3
I/O 2
I/O 1
I/O 0

D16

DQS10

RESET

PCK
PCK

Serial PD

SA0

SA1

SA2

SCL

SDA

D0 - D17

DDQ

D0 - D17

VREF

DDSPD

SPD

(DM0)

(DM1)

(DM2)

(DM3)

(DM4)

(DM5)

(DM6)

(DM7)

(DM8)

MOSEL VITELIC

V827332N04S

V827332N04S Rev. 1.1 May 2002

Pin Configurations (Front Side/Back Side)

Pin

Front

Pin

Front

Pin

Front

Pin

Back

Pin

Back

Pin

Back

6
7

12
13

18
19

24
25

30
31

VREF

DQ0

VSS

DQ1

DQS0

DQ2
VDD

DQ3

VSS

DQ8
DQ9

DQS1

VDDQ

CK1

VSS

DQ10

DQ11

CKE0

VDDQ

DQ16

DQ17

DQS2

VSS

DQ18

VDDQ

DQ19

37
38

43
44

49
50

54
55

60
61

DQ24

VSS

DQ25

DQS3

VDD

DQ26

DQ27

Vss

CB0*

CB1*

VDD

DQS8*

CB2*

VSS

CB3*

BA1

Key

DQ32

VDDQ

DQ33

DQS4

DQ34

VSS

BA0

DQ35
DQ40

67
68

73
74

79
80

85
86

91
92

VDDQ

DQ41

CAS

VSS

DQS5

DQ42

DQ43

VDD

DQ48

DQ49

VSS

CK2

VDDQ

DQS6

DQ50
DQ51

VSS

VDDID

DQ56

DQ57

VDD

DQS7

DQ58

DQ59

VSS

SDA
SCL

98
99

100

101

102

103

104
105

106

107

108

109

110
111

112

113

114

115

116
117

118

119

120

121

122
123

VSS

DQ4

DQ5

VDDQ

DM0

DQ6
DQ7

VSS

A13*

VDDQ

DQ12

DQ13

DM1

VDD

DQ14

DQ15
CKE1

VDDQ

BA2*

DQ20

A12*

VSS

DQ21

A11

DM2

VDD

DQ22

DQ23

124

125

126

127

128

129
130

131

132

133

134

135
136

137

138

139

140

141
142

143

144

145

146
147

148

149

150

151

152
153

VSS

DQ28

DQ29

VDDQ

DM3

DQ30

VSS

DQ31

CB4*

CB5*

VDDQ

CK0*

VSS

DM8*

A10

CB6*

VDDQ

CB7*

key

VSS

DQ36
DQ37

VDD

DM4

DQ38

DQ39

VSS

DQ44

154

155

156

157

158

159
160

161

162

163

164

165
166

167

168

169

170

171
172

173

174

175

176

177
178

179

180

181

182

183
184

RAS

DQ45

VDDQ

CS0

CS1

DM5

VSS

DQ46

DQ47

VDDQ

DQ52
DQ53

VDD

DM6

DQ54

DQ55

VDDQ

DQ60

DQ61

VSS

DM7

DQ62

DQ63

VDDQ

SA0

SA1

SA2

VDDSPD

Notes:

* These pins are not used in this module.

Pin Names

Pin Pin

Description

CK1, CK1, CK2, CK2 Differential

Clock

Inputs

CS0

Chip Select Input

CKE0

Clock Enable Input

RAS, CAS, WE Commend

Sets

Inputs

A0 ~ A11

Address

BA0, BA1

Bank Address

DQ0~DQ63 Data

Inputs/Outputs

DQS0~DQS7 Data

Strobe

Inputs/Outputs

DM0~DM7 Data-in

Mask

Key

VDD Power

Supply

VDDQ DQs

Power

Supply

VSS Ground

VREF Reference

Power

Supply

VDDSPD

Power Supply for SPD

SA0~SA2 E

PROM Address Inputs

SCL E

PROM Clock

SDA E

PROM Data I/O

VDDID VDD

Identification

Flag

Do not Use

NC No

Connection

Pin Pin

Description

MOSEL VITELIC

V827332N04S

V827332N04S Rev. 1.1 May 2002

Serial Presence Detect Information

Bin Sort:
A1 (PC1600 @ CL2)
B0 (PC2100B @ CL2.5)
B1 (PC2100A @ CL2)

Byte #

Function described

Function Supported

Hex value

A1 B0

Defines # of Bytes written into serial memory at module manufacturer

128bytes

80h

Total # of Bytes of SPD memory device

256bytes

08h

Fundamental memory type

SDRAM DDR

07h

# of row address on this assembly

0Ch

# of column address on this assembly

0Bh

# of module Rows on this assembly

1 Bank

01h

Data width of this assembly

72 bits

48h

.........Data width of this assembly

00h

VDDQ and interface standard of this assembly

SSTL 2.5V

04h

DDR SDRAM cycle time at CAS Latency =2.5

8ns

7.5ns

7ns

80h

75h

70h

DDR SDRAM Access time from clock at CL=2.5

±0.8ns ±0.75n ±0.75n

80h

75h

DIMM configuration type(Non-parity, Parity, ECC)

Non-parity, ECC

02h

Refresh rate & type

15.6us & Self refresh

80h

Primary DDR SDRAM width

04h

Error checking DDR SDRAM data width

04h

Minimum clock delay for back-to-back random column

address

CCD

=1CLK 01h

DDR SDRAM device attributes : Burst lengths supported

2,4,8

0Eh

DDR SDRAM device attributes : # of banks on each DDR SDRAM

4 banks

04h

DDR SDRAM device attributes : CAS Latency supported

2,2.5

0Ch

DDR SDRAM device attributes : CS Latency

0CLK

01h

DDR SDRAM device attributes : WE Latency

1CLK

02h

DDR SDRAM module attributes

Registered address&

control inputs and On-card

DLL

26h

DDR SDRAM device attributes : General

+/-0.2V voltage tolerance

00h

DDR SDRAM cycle time at CL =2

10ns

7.5ns

A0h

75h

DDR SDRAM Access time from clock at CL =2

±0.8ns

±08n

±0.75

80h

75h

DDR SDRAM cycle time at CL =1.5

00h

DDR SDRAM Access time from clock at CL =1.5

00h

Minimum row precharge time (=t

)

20ns 20ns 18ns 50h 50h 48h

Minimum row activate to row active delay(=t

RRD

) 15ns

15ns

14ns

3Ch

38h

MOSEL VITELIC

V827332N04S

V827332N04S Rev. 1.1 May 2002

Minimum RAS to CAS delay(=t

RCD

) 20ns

20ns

18ns

50h

48h

Minimum active to precharge time(=t

RAS

) 50ns

45ns

32h

2Dh

Module Row density

256MB

40h

Command and address signal input setup time

1.1ns

0.9ns

B0h

90h

Command and address signal input hold time

1.1ns

0.9ns

B0h

90h

Data signal input setup time

0.6ns

0.5ns

60h

50h

Data signal input hold time

0.6ns

0.5ns

60h

50h

36-40

Superset information (may be used in future)

00h

SDRAM device minimum active to active/auto-refresh time

(=t

)

70ns 65ns 60ns

46h 41h 3Ch

SDRAM device minimum active to autorefresh to active/auto-refresh

time (=t

RFC

)

80ns 75ns 67ns

50h 4Bh 43h

SDRAM device maximum device cycle time (=t

CK MAX

)

12ns 12ns 12ns

30h 30h 30h

SDRAM device maximum skew between DQS and DQ signals

(=t

DQSQ

)

0.6ns 0.5ns 0.5ns

3Ch 32h 32h

SDRAM device maximum read datahold skew factor (=t

QHS

)

1ns 0.75ns

0.75ns

A0h

75h

SPD data revision code

Initial release

00h

Checksum for Bytes 0 ~ 62

Manufacturer JEDEC ID code

Mosel Vitelic

40h

65 -71

....... Manufacturer JEDEC ID code

00h

Manufacturing location

02=Taiwan 05=China

0A=S-CH

73-90

Module part number (ASCII)

V827332N04S

Manufacturer revison code (For PCB)

Manufacturer revison code (For component)

Manufacturing date (Week)

Manufacturing date (Year)

95~98

Assembly serial #

99~127 Manufacturer specific data (may be used in future)

Undefined

00h

128~255 Open for customer use

Undefined

00h

Byte #

Function described

Function Supported

Hex value

A1 B0

Serial Presence Detect Information (cont.)

MOSEL VITELIC

V827332N04S

V827332N04S Rev. 1.1 May 2002

DC Operating Conditions

= 0 to 70°C, Voltage referenced to V

= 0V)

Notes: 1. V

DDQ

must not exceed the level of V

2. V

(min) is acceptable -1.5V AC pulse width with ð 5ns of duration.

3. The value of V

REF

is approximately equal to 0.5V

DDQ

AC Operating Conditions

= 0 to 70 °C, Voltage referenced to V

= 0V)

Notes: 1. VID is the magnitude of the difference between the input level on CK and the input on CK.

2. The value of VIX is expected to equal 0.5*V

DDQ

of the transmitting device and must track variations in the DC level of the

same.

Parameter

Symbol

Min

Typ.

Max

Unit

Note

Power Supply Voltage

2.3

2.5

2.7

Power Supply Voltage

DDQ

2.3

2.5

2.7

Input High Voltage

REF

+ 0.15

DDQ

+ 0.3

Input Low Voltage

-0.3

REF

- 0.15

I/O Termination Voltage

REF

- 0.04

REF

+ 0.04

Reference Voltage

REF

1.15

1.25

1.35

Input Leakage Current

-2

µA

Output Leakage Current

-5

µA

Output High Current (V

OUT

= 1.95V)

-16.8

Output Low Current (V

OUT

= 0.35V)

16.8

Parameter Symbol

Min

Max

Unit

Note

Input High (Logic 1) Voltage, DQ, DQS and DM signals

IH(AC)

REF

+ 0.31

Input Low (Logic 0) Voltage, DQ, DQS and DM signals

IL(AC)

REF

- 0.31

Input Differential Voltage, CK and CK inputs

ID(AC)

0.7

DDQ

+ 0.6

Input Crossing Point Voltage, CK and CK inputs

IX(AC)

0.5*V

DDQ-0.2

0.5*V

DDQ+0.2

MOSEL VITELIC

V827332N04S

V827332N04S Rev. 1.1 May 2002

AC Operating Test Conditions

= 0 to 70°C, Voltage referenced to V

= 0V)

Input/Output Capacitance

= 2.5V, V

DDQ

= 2.5V, T

= 25°C, f = 1MHz)

Parameter Value

Unit

Reference Voltage

DDQ

x 0.5

Termination Voltage

DDQ

x 0.5

AC Input High Level Voltage (V

, min)

REF

+ 0.31

AC Input Low Level Voltage (V

, max)

REF

- 0.31

Input Timing Measurement Reference Level Voltage

REF

Output Timing Measurement Reference Level Voltage

Input Signal maximum peak swing

1.5

Input minimum Signal Slew Rate

V/ns

Termination Resistor (R

) 50

Ohm

Series Resistor (R

)

25 Ohm

Output Load Capacitance for Access Time Measurement (C

) 30

Parameter

Symbol Min

Max

Unit

Input capacitance (A

~ A

, BA

~ BA

, RAS, CAS, WE) CIN

60 75

Input capacitance (CKE

) CIN

Input capacitance (CS

) CIN

Input capacitance (CLK

, CLK

) CIN

Data & DQS input/output capacitance (DQ

~DQ

) C

OUT

Input capacitance (DM0~DM8)

CIN

Output Load Circuit (SSTL_2)

Output

Z0=50

LOAD

=30pF

REF

=0.5*V

DDQ

=50

=0.5*V

DDQ

MOSEL VITELIC

V827332N04S

V827332N04S Rev. 1.1 May 2002

DDR SDRAM I

SPEC TABLE

* Module I

was calculated on the basis of component I

and can be differently measured according to DQ loading cap.

Detailed test conditions for DDR SDRAM IDD1 & IDD

IDD1 : Operating current: One bank operation

1. Typical Case : Vdd = 2.5V, T=25' C

2. Worst Case : Vdd = 2.7V, T= 10' C

3. Only one bank is accessed with tRC(min), Burst Mode, Address and Control inputs on NOP edge are changing once

per clock cycle. lout = 0mA

4. Timing patterns

- DDR200(100Mhz, CL=2) : tCK = 10ns, CL2, BL=4, tRCD = 2*tCK, tRAS = 5*tCK

Read : A0 N R0 N N P0 N A0 N - repeat the same timing with random address changing
*50% of data changing at every burst

- DDR266B(133Mhz, CL=2.5) : tCK = 7.5ns, CL=2.5, BL=4, tRCD = 3*tCK, tRC = 9*tCK, tRAS = 5*tCK

Read : A0 N N R0 N P0 N N N A0 N - repeat the same timing with random address changing
*50% of data changing at every burst

- DDR266A (133Mhz, CL=2) : tCK = 7.5ns, CL=2, BL=4, tRCD = 3*tCK, tRC = 9*tCK, tRAS = 5*tCK

Read : A0 N N R0 N P0 N N N A0 N - repeat the same timing with random address changing
*50% of data changing at every burst

Legend : A=Activate, R=Read, W=Write, P=Precharge, N=NOP

Symbol

A1(PC1600@CL=2) B0(PC2100B@CL=2.5)

B1(PC2100A@CL=2)

Unit

Typical

Worst

Typical

Worst

Typical

Worst

IDD0

1450

1440

1350

1440

1080

1170

IDD1

1650

1710

1575

1710

1280

1395

IDD2P

750

720

675

720

540

585

IDD2F

895

945

655

945

720

765

IDD2Q

830

810

765

810

630

675

IDD3P

980

765

720

765

585

630

IDD3N

900

990

900

990

720

810

IDD4R

1980

2250

1980

2250

1620

1845

IDD4W

2115

2385

2115

2385

1710

1890

IDD5

2115

2385

2115

2385

1710

1890

IDD6

Normal

Low power

IDD7

3375

3825

3375

3825

2745

3150

MOSEL VITELIC

V827332N04S

V827332N04S Rev. 1.1 May 2002

AC Characteristics

(AC operating conditions unless otherwise noted)

Parameter Symbol

(PC2100A) (PC2100B) (PC1600)

Unit Note

Min Max Min Max Min Max

Row Cycle Time

- 65 - 70 - ns

Auto Refresh Row Cycle Time

RFC

- 75 - 80 - ns

Row Active Time

RAS

45 120K 48 120K 50 120K

Row Address to Column Address Delay

RCD

18 - 20 - 20 - ns

Row Active to Row Active Delay

RRD

Column Address to Column Address Delay

CCD

1 - 1 - 1 -

CLK

Row Precharge Time

- 20 - 20 - ns

Write Recovery Time

15 - 15 - 15 - ns

Last Data-In to Read Command

DRL

1 - 1 - 1 -

CLK

Auto Precharge Write Recovery + Precharge Time

DAL

35 - 35 - 35 - ns

System Clock Cycle Time

CAS Latency = 2.5

7 12

7.5 12 8 12

CAS Latency = 2

7.5

Clock High Level Width

0.45 0.55 0.45 0.55 0.45 0.55

CLK

Clock Low Level Width

0.45 0.55 0.45 0.55 0.45 0.55

CLK

Data-Out edge to Clock edge Skew

-0.75 0.75 -0.75 0.75 -0.8 0.8 ns

DQS-Out edge to Clock edge Skew

DQSCK

-0.75 0.75 -0.75 0.75 -0.8 0.8 ns

DQS-Out edge to Data-Out edge Skew

DQSQ

- 0.5 -

0.5

- 0.6

Data-Out hold time from DQS

HPmin

-0.75ns

- t

HPmin

-0.75ns

- t

HPmin

-0.75ns

- ns 1

Clock Half Period

CH/L

min

- t

CH/L

min

- t

CH/L

min

- ns 1

Input Setup Time (fast slew rate)

0.9 - 0.9 - 1.1 - ns

2,3,5,6

Input Hold Time (fast slew rate)

0.9 - 0.9 - 1.1 - ns

2,3,5,6

Input Setup Time (slow slew rate)

1.0 - 1.0 - 1.1 - ns

2,4,5,6

Input Hold Time (slow slew rate)

1.0 - 1.0 - 1.1 - ns

2,4,5,6

Input Pulse Width

IPW

2.2 - 2.2 - - -

Write DQS High Level Width

DQSH

0.4 0.6 0.4 0.6 0.4 0.6

CLK

Write DQS Low Level Width

DQSL

0.4 0.6 0.4 0.6 0.4 0.6

CLK

CLK to First Rising edge of DQS-In

DQSS

0.75 1.25 0.75 1.25 0.75 1.25

CLK

Data-In Setup Time to DQS-In (DQ & DM)

0.5 - 0.5 - 0.6 - ns 7

Data-in Hold Time to DQS-In (DQ & DM)

0.5 - 0.5 - 0.6 - ns 7

DQ & DM Input Pulse Width

DIPW

1.75 -

1.75

- 2 -

Read DQS Preamble Time

RPRE

0.9 1.1 0.9 1.1 0.9 1.1

CLK

Read DQS Postamble Time

RPST

0.4 0.6 0.4 0.6 0.4 0.6

CLK

MOSEL VITELIC

V827332N04S

V827332N04S Rev. 1.1 May 2002

AC Characteristics (cont.)

Notes: 1. This calculation accounts for tDQSQ(max), the pulse width distortion of on-chip circuit and jitter.

2. Data sampled at the rising edges of the clock : A0~A11, BA0~BA1, CKE, CS, RAS, CAS, WE.
3. For command/address input slew rate >=1.0V/ns
4. For command/address input slew rate >=0.5V/ns and <1.0V/ns
5. CK, CK slew rates are >=1.0V/ns
6. These parameters guarantee device timing, but they are not necessarily tested on each device, and they may be guaranteed

by design or tester correlation.

7. Data latched at both rising and falling edges of Data Strobes(DQS) : DQ, DM
8. Minimum of 200 cycles of stable input clocks after Self Refresh Exit command, where CKE is held high, is required to complete

Self Refresh Exit and lock the internal DLL circuit of DDR SDRAM.

Absolute Maximum Ratings

Note: Operation at above absolute maximum rating can adversely affect device reliability

Write DQS Preamble Setup Time

WPRES

0 - 0 - 0 -

CLK

Write DQS Preamble Hold Time

WPREH

0.25 - 0.25 - 0.25 -

CLK

Write DQS Postamble Time

WPST

0.4 0.6 0.4 0.6 0.4 0.6

CLK

Mode Register Set Delay

MRD

2 - 2 - 2 -

CLK

Power Down Exit Time

PDEX

10 - 10 - 10 - ns

Exit Self Refresh to Non-Read Command

XSNR

75 - 75 - 80 - ns

Exit Self Refresh to Read Command

XSRD

200 - 200 - 200 -

CLK

Average Periodic Refresh Interval

REFI

- 15.6 - 15.6 - 15.6

Parameter Symbol

Rating

Unit

Ambient Temperature

°C

Storage Temperature

STG

-55 ~ 125

°C

Voltage on Any Pin relative to V

, V

OUT

-0.5 ~ 3.6

Voltage on V

relative to V

-0.5 ~ 3.6

Voltage on V

DDQ

relative to V

DDQ

-0.5 ~ 3.6

Output Short Circuit Current

50 mA

Power Dissipation

8 W

Soldering Temperature · Time

SOLDER

260 · 10

°C · Sec

Parameter Symbol

(PC2100A) (PC2100B) (PC1600)

Unit Note

Min Max Min Max Min Max

MOSEL VITELIC

V827332N04S

V827332N04S Rev. 1.1 May 2002

Module Dimensions (Standard)

NOTE: 1. All dimensions in inches (millimeters) MAX or typical where noted.

MIN

1.705 (43.31)
1.695 (43.05)

PIN 1

.700 (17.78)

TYP.

.098 (2.50) D

(2X)

.091 (2.30) TYP.

.250 (6.35) TYP.

4.750 (120.65)

.050 (1.27)

TYP.

.091 (2.30)

TYP.

.040 (1.02)

TYP.

.079 (2.00) R

(4X)

.035 (0.90) R

PIN 92

FRONT VIEW

.054 (1.37)
.046 (1.17)

5.256 (133.50)
5.244 (133.20)

2.55 (64.77)

1.95 (49.53)

.394 (10.00)

TYP.

.125 (3.175)

MAX

BACK VIEW

PIN 184

PIN 93

U11

U12

U13

U10

U14

U15

U16

U17

U18

U19

U20

U21

U22

MOSEL VITELIC

V827332N04S

V827332N04S Rev. 1.1 May 2002

Module Dimensions (Low Profile)

NOTE: 1. All dimensions in inches (millimeters) MAX or typical where noted.

MIN

U11

U12

U14

U15

U16

U17

U18

U13

U10

U19

U20

U21

U22

.054 (1.37)
.046 (1.17)

.125 (3.175)

MAX

1.205 (30.61)
1.195 (30.35)

PIN 1

.700 (17.78)

TYP.

.098 (2.50) D

(2X)

.091 (2.30) TYP.

.250 (6.35) TYP.

4.750 (120.65)

.050 (1.27)

TYP.

.091 (2.30)

TYP.

.040 (1.02)

TYP.

.079 (2.00) R

(4X)

.035 (0.90) R

PIN 92

FRONT VIEW

5.256 (133.50)
5.244 (133.20)

2.55 (64.77)

1.95 (49.53)

.394 (10.00)

TYP.

BACK VIEW

PIN 184

PIN 93

MOSEL VITELIC

V827332N04S

V827332N04S Rev. 1.1 May 2002

WORLDWIDE OFFICES

Printed in U.S.A.

The information in this document is subject to change without
notice.

MOSEL VITELIC makes no commitment to update or keep cur-
rent the information contained in this document. No part of this
document may be copied or reproduced in any form or by any
means without the prior written consent of MOSEL-VITELIC.

MOSEL VITELIC subjects its products to normal quality control
sampling techniques which are intended to provide an assurance
of high quality products suitable for usual commercial applica-
tions. MOSEL VITELIC does not do testing appropriate to provide
100% product quality assurance and does not assume any liabil-
ity for consequential or incidental arising from any use of its prod-
ucts. If such products are to be used in applications in which
personal injury might occur from failure, purchaser must do its
own quality assurance testing appropriate to such applications.

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