MOSEL VITELIC
1
V8274128N24S
2.5 VOLT 128M x 72 HIGH PERFORMANCE
REGISTERED ECC DDR SDRAM MODULE
PRELIMINARY
V8274128N24S Rev. 1.0 March 2003
Features
184 Pin Registered 128M x 72 bit
Organization DDR SDRAM Modules
Utilizes High Performance 64M x 4 DDR
SDRAM in SOC Packages
Single +2.5V ( 0.2V) Power Supply
Programmable CAS Latency, Burst Length, and
Wrap Sequence (Sequential & Interleave)
Auto Refresh (CBR) and Self Refresh
All Inputs, Outputs are SSTL-2 Compatible
8192 Refresh Cycles every 64 ms
Serial Presence Detect (SPD)
DDR SDRAM Performance
Description
The V8274128N24S memory module is
organized 134,217,728x 72 bits in a 184 pin
memory module. The 128M x 72 memory module
uses 36 Mosel-Vitelic 64M x 4 DDR SDRAM. The
x72 modules are ideal for use in high performance
computer systems where increased memory
density and fast access times are required.
Component Used
-6
-7
-75
-8
t
CK
Clock Frequency
(max.)
166
(PC333)
143
(PC266A)
133
(PC266B)
125
(PC200)
t
AC
Clock Access Time
CAS Latency = 2.5
6
7
7.5
8
Module Speed
A1
PC1600 (100MHz @ CL2)
B0
PC2100B (133MHz @ CL2.5)
B1
PC2100A (133MHz @ CL2)
C0
PC2700 (166MHz @ CL2.5)
MOSEL VITELIC
V8274128N24S
5
V8274128N24S Rev. 1.0 March 2003
Serial Presence Detect Information
Bin Sort:
A1 (PC1600 @ CL2)
B0 (PC2100B @ CL2.5)
B1 (PC2100A @ CL2)
C0 (PC2700 @ CL2.5)
Byte #
Function described
Function Supported
Hex value
A1 B0
B1
C0
A1
B0
B1
C0
0
Defines # of Bytes written into serial memory at module manufac-
turer
128bytes 80h
1
Total # of Bytes of SPD memory device
256bytes
08h
2
Fundamental memory type
SDRAM DDR
07h
3
# of row address on this assembly
13
0Dh
4
# of column address on this assembly
11
0Bh
5
# of module Rows on this assembly
2 Bank
02h
6
Data width of this assembly
72 bits
48h
7
.........Data width of this assembly
-
00h
8
VDDQ and interface standard of this assembly
SSTL 2.5V
04h
9
DDR SDRAM cycle time at CAS Latency =2.5
8ns
7.5ns
7ns
6ns
80h
75h
70h
60h
10
DDR SDRAM Access time from clock at CL=2.5
0.8ns 0.75n 0.75n 0.70n
80h
75h
75h
70h
11
DIMM configuration type(Non-parity, Parity, ECC)
Non-parity, ECC
02h
12
Refresh rate & type
7.8us & Self refresh
82h
13
Primary DDR SDRAM width
x4
04h
14
Error checking DDR SDRAM data width
x4
04h
15
Minimum clock delay for back-to-back random column
address
t
CCD
=1CLK 01h
16
DDR SDRAM device attributes : Burst lengths supported
2,4,8
0Eh
17
DDR SDRAM device attributes : # of banks on each DDR SDRAM
4 banks
04h
18
DDR SDRAM device attributes : CAS Latency supported
2,2.5
0Ch
19
DDR SDRAM device attributes : CS Latency
0CLK
01h
20
DDR SDRAM device attributes : WE Latency
1CLK
02h
21
DDR SDRAM module attributes
Registered address&
control inputs and On-card
DLL
26h
22
DDR SDRAM device attributes : General
+/-0.2V voltage tolerance
00h
23
DDR SDRAM cycle time at CL =2
10ns
10ns
7.5ns
7.5ns
A0h
A0h
75h
75h
24
DDR SDRAM Access time from clock at CL =2
0.8ns 0.75ns 0.75ns 0.70ns 80h
75h
75h
70h
25
DDR SDRAM cycle time at CL =1.5
-
-
-
-
00h
26
DDR SDRAM Access time from clock at CL =1.5
-
-
-
-
00h
27
Minimum row precharge time (=t
RP
)
20ns 20ns 15ns 18ns
50h 50h 3Ch
48h
PDF 
ZIP
