MC804256K32, MC804256K36
256Kx32, 256Kx36 Flow-Through
Synchronous Burst SRAM
DS13, Rev 1.2 8/25/99
Preliminary Information
Page 1
1999 MoSys Inc., All Rights Reserved, 1020 Stewart Drive, Sunnyvale, CA 94086
High performance, low power flow-through SRAM
Ultra low power for high capacity applications
High performance
66, 83, 100 MHz Speed grades
2-1-1-1 Burst Read
1-1-1-1 Burst Write
2-1-1-1-1-1-1-1... burst operation
Low power
Low active power
Ultra low power ZZ standby mode
Single 3.3V supply (VDD)
Isolated 3.3V or 2.5V I/O supply (VDDQ)
Compatibility
Individual Byte Write and Global Write masking
Interleave and burst address support
Two chip enables for easy expansion
Industry standard 100-Pin SRAM pinout
Industry standard SRAM specification
Applications
Ideal for high speed, low power communica-
tions buffers
Power sensitive portable DSP applications
______________________________________________
Overview
The MoSys MC804256K is a low power flow-through
synchronous SRAM. Fabricated using an advanced low
power, high performance CMOS process, the MoSys
MC804256K is forward pin and function compatible with
standard 32Kx32/36, 64Kx32/36 and 128Kx32/36 SRAM
devices. These devices also include additional operating
features like low power ZZ standby mode and linear
burst order addressing. These additional operating fea-
tures are defined so that, with proper implementation,
designs can work transparently with 32Kx32/36,
64Kx32/36, 128Kx32/36 and 256Kx32/36 configurations.
This allows the designer maximum configuration flexi-
bility within a single footprint layout.
The MoSys MC804256K32/36 supports flow-through
SRAM operating modes at maximum burst frequency
including indefinite pipeline read or write (2-1-1-1-1-1-
1...)
Parameter
Symbol
-15
-12
-10
Units
Cycle Time
tKC
15
12
10
ns
Access Time
tKQ
10
9
8.5
ns
Clock to High-Z
tKQHZ
8.6
7.5
5
ns
The MC804256K is packaged in a standard 100-pin
LQFP.
Lowest Power
The MC804256K flow-through SRAM affords systems
dramatic power savings due to the benefits of its pro-
prietary MoSys technology. Peak operating power of a
typical SRAM is 5x that of the MC804256K. This makes
it ideal for portable applications as well as applications
requiring a large amount of static RAM.
Part Number Designation
Example
: MC804256K32L-15 I
Device Designation:
MC8:, Series: 04
Organization:
256K32, 256K36
Package Type:
L=LQFP
Speed: 15
66 MHz
12
83 MHz
10
100 MHz
Temp:
I = Industrial Temperature, optional
1
NC, (DQP3)
80
NC, (DQP2)
10
VSSQ
71
VSSQ
19
DQ26
62
A17
DQ7
39
2
DQ17
79
DQ16
11
VDDQ
70
A6
VDDQ
31
LBO
#
20
VDDQ
61
VDD
VDDQ
40
VSS
3
DQ18
78
DQ15
12
DQ23
69
A7
DQ10
DQ9
32
A5
21
VSSQ
60
VSS
VSSQ
41
VDD
4
VDDQ
77
VDDQ
13
DQ24
68
CE1
#
33
A4
22
DQ27
59
CL
K
DQ6
42
5
VSSQ
76
VSSQ
14
NC
67
CE2
VSS
34
A3
23
DQ28
58
GW
#
DQ5
43
6
DQ19
75
DQ14
15
VDD
66
BW
4#
NC
35
A2
24
DQ29
57
BW
E#
DQ4
44
A10
28
DQ31
53
ADV#
DQ2
48
A14
7
DQ20
74
DQ13
16
NC
65
BW
3#
VDD
36
A1
25
DQ30
56
OE#
DQ3
45
A11
29
DQ32
52
A8
DQ1
49
A15
8
DQ21
73
DQ12
17
VSS
64
BW
2#
ZZ
37
A0
26
VSSQ
55
ADSC#
VSSQ
46
A12
30
NC, (DQP4)
51
A9
NC, (DQP1)
50
A16
9
DQ22
72
DQ11
18
DQ25
63
BW
1#
DQ8
38
100
91
82
99
90
81
98
89
97
88
96
87
95
86
94
85
93
84
92
83
27
VDDQ
54
ADSP#
VDDQ
47
A13
100 Pin LQFP
20 mm x 14 mm body
0.65 mm nominal pin pitch
NC
NC
NC
NC
Figure 1. Pin Function
MC804256K32, MC804256K36
256Kx32, 256Kx36 Flow-Through
Synchronous Burst SRAM
DS13, Rev 1.2 8/25/99
Preliminary Information
Page 2
1999 MoSys Inc., All Rights Reserved, 1020 Stewart Drive, Sunnyvale, CA 94086
GW#
BWE#
D Q
Address
Register
CE#
CLK
D Q
DQ[32:25]
CLK
D Q
ByteWrite
CLK
D Q
DQ[16:9]
CLK
D Q
DQ[8:1]
CLK
D Q
Enable
Register
CE#
CLK
D Q
Enable
Delay
Register
CLK
256K x32/36
Memory
Array
Binary
Counter
CLK
CE#
CLR#
Input
Register
CLK
ADSC#
ADV#
ADSP#
A[17:0]
BW3#
BW4#
BW2#
BW1#
CE2
CE1#
OE#
OE
4
18
16
18
32/36
DATA[32:1]
LBO#
Q0
Q1
DQ[24:17]
Registers
ByteWrite
Registers
ByteWrite
Registers
32/36
32/36
Figure 2 Functional Block Diagram
MC804256K32, MC804256K36
256Kx32, 256Kx36 Flow-Through
Synchronous Burst SRAM
DS13, Rev 1.2 8/25/99
Preliminary Information
Page 3
1999 MoSys Inc., All Rights Reserved, 1020 Stewart Drive, Sunnyvale, CA 94086
Table 1. Pin Description
Pin Number
Symbol
Type
Description
92, 50, 49, 48, 47, 46, 45, 44, 81, 82, 99,
100, 32, 33, 34, 35, 36, 37
A[17:0]
Input
Host Addresses
96, 95, 94, 93
BW[4:1]#
Input
Processor host bus byte enables.
88
GW#
Input
Global Write from cache controller
87
BWE#
Input
Byte Write Enable from controller
89
CLK
Input
Host bus clock
98
CE1#
Input
ADSP# mask and ADSC# chip enable
97
CE2
Input
Depth expansion chip enable
86
OE#
Input
Asynchronous output enable
83
ADV#
Input
Burst address counter advance
84
ADSP#
Input
ADS# of processor
85
ADSC#
Input
ADS# of controller
64
ZZ
Input
Low power sleep mode
31
LBO#
Input
Linear Burst Order
29, 28, 25, 24, 23, 22, 19, 18, 13, 12, 9,
8, 7, 6, 3, 2, 79, 78, 75, 74, 73, 72, 69,
68, 63, 62, 59, 58, 57, 56, 53, 52
DQ[32:1]
I/O
Data I/O pins
30, 1, 80, 51
NC/DQP[4:1]
I/O
Data parity I/O pins
14, 16, 38, 39, 42, 43, 66
NC
-
unused
15, 41, 65, 91
VDD
3.3 Volts
Power
17, 40, 67, 90
VSS
Ground
Ground
4, 11, 20, 27, 54, 61, 70, 77
VDDQ
I/O
Supply
I/O Buffer Supply
5, 10, 21, 26, 55, 60, 71, 76
VSSQ
I/O
Ground
I/O Buffer Ground
Table 2. Absolute Maximum Ratings
Symbol
Parameter
Min
Max
Units
VDD
Core Supply Voltage
4.0
V
VDDQ
I/O Supply Voltage
VDD
V
Vih
Input High Voltage
VDDQ +0.5
V
Vil
Input Low Voltage
VSSQ - 0.5
V
Ts
Storage Temperature
-65
150
C
Notes: Max Vih is not to exceed maximum VDDQ
MC804256K32, MC804256K36
256Kx32, 256Kx36 Flow-Through
Synchronous Burst SRAM
DS13, Rev 1.2 8/25/99
Preliminary Information
Page 4
1999 MoSys Inc., All Rights Reserved, 1020 Stewart Drive, Sunnyvale, CA 94086
Table 3. Recommended Operating Conditions
Symbol
Parameter
Condition
Min
Max
Units
VDD
Supply Voltage
3.3V 5%
3.135
3.465
V
VDDQ
I/O Supply Voltage
2.5V +38%/-5%
2.375
3.465
V
Vih
Input High Voltage
1.8
VDDQ + 0.3
V
Vil
Input Low Voltage
-0.3
0.8
V
Voh
Output High Voltage
Ioh = -5 mA
2.4
V
Vol
Output Low Voltage
Iol = 5 mA
0.4
V
TAC
Commercial Operating Temp.
0
70
C
TAI
Industrial Operating Temp.
-40
85
C
Table 4. Absolute Maximum AC Operating Conditions
Symbol
Parameter
Min
Max
Units
Vih
Input High Voltage
1.8
VDDQ+1.0
V
Vil
Input Low Voltage
VSSQ
-
1.0
0.8
V
tOVR
Overshoot/Undershoot Voltage Duration
0.2*tCY
ns
tSET
Overshoot/Undershoot Settling Time
0.8*tCY
ns
Table 5. Maximum DC Current Requirements
Symbol
Condition
Current
Units
I
DD
Operating current, device selected; all inputs < Vil or > Vih; cycle time > tKC min,
VDD= max, 0 pF load
50
mA
I
DD1
Idle current, device deselected; ADSP#, ADSC#, GW#, BW#s, ADV# and all other
inputs except ZZ > 2.8 volts; cycle time > tKC min, VDD= max, 0 pF load
10
mA
I
DDZ
Sleep mode, clock stopped, all inputs > 2.8 v, VDD= max
2
mA
MC804256K32, MC804256K36
256Kx32, 256Kx36 Flow-Through
Synchronous Burst SRAM
DS13, Rev 1.2 8/25/99
Preliminary Information
Page 5
1999 MoSys Inc., All Rights Reserved, 1020 Stewart Drive, Sunnyvale, CA 94086
Table 6. AC Timing Characteristics at Recommended Operating Conditions
-10
(100 MHz)
-12
(83 MHz)
-15
(66 MHz)
Sym
Parameter
Min
Max
Min
Max
Min
Max
Units
tAAH
ADV# hold
0.5
0.5
0.5
ns
tAAS
ADV# setup
2
2
2
ns
tADSH
ADSx# hold
0.5
0.5
0.5
ns
tADSS
ADSx# setup
2
2
2
ns
tAH
Address hold
0.5
0.5
0.5
ns
tAS
Address setup
2
2
2
ns
tCEH
Chip Enable hold
0.5
0.5
0.5
ns
tCES
Chip Enable setup
2
2
2
ns
tDH
Write Data hold
0.5
0.5
0.5
ns
tDS
Write Data setup
2
2
2
ns
tKC
Clock cycle
10
12
15
ns
tKH
Clock high
4.5
5.5
6.5
ns
tKL
Clock low
4.5
5.5
6.5
ns
tKQ
Clock to output valid
8.5
9
10
ns
tKQHZ
Clock to output high-Z
1.5
5.0
1.5
7.5
1.5
8.6
ns
tKQLZ
Clock to output low-Z
0
0
0
ns
tKQX
Clock to output invalid
1.5
1.5
1.5
ns
tOELZ
OE# to output low-Z
0
0
0
ns
tOEHZ
OE# to output high-Z
3.5
4.5
4.8
ns
tOEQ
OE# to output valid
3.5
4.5
4.8
ns
tOEQX
OE# to output invalid
0
0
0
ns
tWS
GW#, BWx# setup
2
2
2
ns
tWH
GW#, BWx# hold
0.5
0.5
0.5
ns
tZZs
ZZ standby
100
100
100
ns
tZZREC
ZZ recovery
100
100
100
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