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MC68HC08KH12/H
REV. 1.0
68HC08KH12
68HC708KH12
Advance Information
June 7, 1999
Semiconductor Products Sector
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Rev. 1.0
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MOTOROLA
Motorola reserves the right to make changes without further notice to
any products herein to improve reliability, function or design. Motorola
does not assume any liability arising out of the application or use of any
product or circuit described herein; neither does it convey any license
under its patent rights nor the rights of others. Motorola products are not
designed, intended, or authorized for use as components in systems
intended for surgical implant into the body, or other applications intended
to support or sustain life, or for any other application in which the failure
of the Motorola product could create a situation where personal injury or
death may occur. Should Buyer purchase or use Motorola products for
any such unintended or unauthorized application, Buyer shall indemnify
and hold Motorola and its officers, employees, subsidiaries, affiliates,
and distributors harmless against all claims, costs, damages, and
expenses, and reasonable attorney fees arising out of, directly or
indirectly, any claim of personal injury or death associated with such
unintended or unauthorized use, even if such claim alleges that Motorola
was negligent regarding the design or manufacture of the part.
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MC68HC(7)08KH12
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MOTOROLA
List of Sections
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List of Sections
Section 1. General Description .......................................23
Section 2. Memory Map ...................................................33
Section 3. Random-Access Memory (RAM) ...................45
Section 4. Read-Only Memory (ROM) .............................47
Section 5. Configuration Register (CONFIG) .................49
Section 6. Central Processor Unit (CPU) .......................51
Section 7. System Integration Module (SIM) .................61
Section 8. Clock Generator Module (CGM) ....................87
Section 9. Universal Serial Bus Module (USB) ............113
Section 10. Monitor ROM (MON) ...................................149
Section 11. Timer Interface Module (TIM) ....................161
Section 12. I/O Ports ......................................................183
Section 13. Computer Operating Properly (COP) .......207
Section 14. External Interrupt (IRQ) .............................213
Section 15. Keyboard Interrupt Module (KBI) ..............219
Section 16. Break Module (BREAK) .............................241
Section 17. Preliminary Electrical Specifications .......247
Section 18. Mechanical Specifications ........................259
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List of Sections
MOTOROLA
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MOTOROLA
Table of Contents
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Table of Contents
General Description
1.1
Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
1.2
Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
1.3
Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
1.4
MCU Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26
1.5
Pin Assignments . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28
1.5.1
Quad Flat Pack (QFP) Package . . . . . . . . . . . . . . . . . . . . . 28
1.5.2
Power Supply Pins
(V
DDA
, V
SSA
, V
DD1
, V
SS1
, V
DD2
, and V
SS2
) . . . . . . . . . . 29
1.5.3
Oscillator Pins (OSC1 and OSC2) . . . . . . . . . . . . . . . . . . . 30
1.5.4
External Reset Pin (RST) . . . . . . . . . . . . . . . . . . . . . . . . . . 30
1.5.5
External Interrupt Pin (IRQ1/V
PP
) . . . . . . . . . . . . . . . . . . . . 30
1.5.6
USB Data Pins
(DPLUS0DPLUS4 and DMINUS0DMINUS4). . . . . . . 30
1.5.7
Voltage Regulator Out (REGOUT) . . . . . . . . . . . . . . . . . . . 30
1.5.8
Port A Input/Output (I/O) Pins (PTA7PTA0) . . . . . . . . . . . 31
1.5.9
Port B I/O Pins (PTB7PTB0) . . . . . . . . . . . . . . . . . . . . . . . 31
1.5.10
Port C I/O Pins (PTC4PTC0). . . . . . . . . . . . . . . . . . . . . . . 31
1.5.11
Port D I/O Pins (PTD7/KBD7PTD0/KBD0) . . . . . . . . . . . . 31
1.5.12
Port E I/O Pins (PTE4, PTE3/KBE3, PTE2/KBE2/TCH1,
PTE1/KBE1/TCH0, PTE0/KBE0/TCLK) . . . . . . . . . . . . . 31
1.5.13
Port F I/O Pins (PTF7/KBF7PTF0/KBF0) . . . . . . . . . . . . . 32
Section 2. Memory Map
2.1
Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33
2.2
Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33
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2.3
I/O Section . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35
2.4
Monitor ROM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43
Section 3. Random-Access Memory (RAM)
3.1
Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45
3.2
Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45
3.3
Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45
Section 4. Read-Only Memory (ROM)
4.1
Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47
4.2
Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47
4.3
Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47
Section 5. Configuration Register (CONFIG)
5.1
Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49
5.2
Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49
5.3
Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49
Section 6. Central Processor Unit (CPU)
6.1
Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51
6.2
Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51
6.3
Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52
6.4
CPU Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52
6.4.1
Accumulator (A). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53
6.4.2
Index Register (H:X) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54
6.4.3
Stack Pointer (SP). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55
6.4.4
Program Counter (PC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56
6.4.5
Condition Code Register (CCR) . . . . . . . . . . . . . . . . . . . . . 57
6.5
Arithmetic/Logic Unit (ALU) . . . . . . . . . . . . . . . . . . . . . . . . . . . 59
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Section 7. System Integration Module (SIM)
7.1
Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 61
7.2
Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 62
7.3
SIM Bus Clock Control and Generation . . . . . . . . . . . . . . . . . . 65
7.3.1
Bus Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 65
7.3.2
Clock Start-Up from POR . . . . . . . . . . . . . . . . . . . . . . . . . . 66
7.3.3
Clocks in Stop Mode and Wait Mode . . . . . . . . . . . . . . . . . 66
7.4
Reset and System Initialization. . . . . . . . . . . . . . . . . . . . . . . . . 66
7.4.1
External Pin Reset. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 67
7.4.2
Active Resets from Internal Sources . . . . . . . . . . . . . . . . . . 67
7.4.2.1
Power-On Reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 68
7.4.2.2
Computer Operating Properly (COP) Reset . . . . . . . . . . 69
7.4.2.3
Illegal Opcode Reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . 70
7.4.2.4
Illegal Address Reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . 70
7.4.2.5
Universal Serial Bus Reset . . . . . . . . . . . . . . . . . . . . . . . 70
7.5
SIM Counter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 71
7.5.1
SIM Counter During Power-On Reset . . . . . . . . . . . . . . . . . 71
7.5.2
SIM Counter During Stop Mode Recovery . . . . . . . . . . . . . 71
7.5.3
SIM Counter and Reset States . . . . . . . . . . . . . . . . . . . . . . 71
7.6
Exception Control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 72
7.6.1
Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 72
7.6.1.1
Hardware Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 74
7.6.1.2
SWI Instruction. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 76
7.6.2
Interrupt Status Registers . . . . . . . . . . . . . . . . . . . . . . . . . . 76
7.6.2.1
Interrupt Status Register 1 . . . . . . . . . . . . . . . . . . . . . . . . 77
7.6.2.2
Interrupt Status Register 2 . . . . . . . . . . . . . . . . . . . . . . . . 78
7.6.2.3
Interrupt Status Register 3 . . . . . . . . . . . . . . . . . . . . . . . . 78
7.6.3
Reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 79
7.6.4
Break Interrupts. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 79
7.6.5
Status Flag Protection in Break Mode. . . . . . . . . . . . . . . . . 79
7.7
Low-Power Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 79
7.7.1
Wait Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 80
7.7.2
Stop Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 81
7.8
SIM Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 83
7.8.1
Break Status Register (BSR). . . . . . . . . . . . . . . . . . . . . . . . 83
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7.8.2
Reset Status Register (RSR) . . . . . . . . . . . . . . . . . . . . . . . 84
7.8.3
Break Flag Control Register (BFCR). . . . . . . . . . . . . . . . . . 85
Section 8. Clock Generator Module (CGM)
8.1
Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 87
8.2
Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 88
8.3
Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 89
8.4
Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 89
8.4.1
Crystal Oscillator Circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . 91
8.4.2
Phase-Locked Loop Circuit (PLL) . . . . . . . . . . . . . . . . . . . . 91
8.4.3
PLL Circuits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 91
8.4.4
Acquisition and Tracking Modes . . . . . . . . . . . . . . . . . . . . . 93
8.4.5
Manual and Automatic PLL Bandwidth Modes . . . . . . . . . . 93
8.4.6
Programming the PLL . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 94
8.4.7
Special Programming Exceptions . . . . . . . . . . . . . . . . . . . . 95
8.4.8
Base Clock Selector Circuit. . . . . . . . . . . . . . . . . . . . . . . . . 96
8.4.9
CGM External Connections. . . . . . . . . . . . . . . . . . . . . . . . . 96
8.5
I/O Signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 98
8.5.1
Crystal Amplifier Input Pin (OSC1) . . . . . . . . . . . . . . . . . . . 98
8.5.2
Crystal Amplifier Output Pin (OSC2) . . . . . . . . . . . . . . . . . . 98
8.5.3
External Filter Capacitor Pin (CGMXFC). . . . . . . . . . . . . . . 98
8.5.4
PLL Analog Power Pin (V
DDA
) . . . . . . . . . . . . . . . . . . . . . . 98
8.5.5
PLL Analog Ground Pin (V
SSA
) . . . . . . . . . . . . . . . . . . . . . . 98
8.5.6
Buffered Crystal Clock Output (CGMVOUT) . . . . . . . . . . . . 99
8.5.7
CGMVSEL. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 99
8.5.8
Oscillator Enable Signal (SIMOSCEN) . . . . . . . . . . . . . . . . 99
8.5.9
Crystal Output Frequency Signal (CGMXCLK) . . . . . . . . . . 99
8.5.10
CGM Base Clock Output (CGMOUT) . . . . . . . . . . . . . . . . . 99
8.5.11
CGM CPU Interrupt (CGMINT) . . . . . . . . . . . . . . . . . . . . . . 99
8.6
CGM Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 100
8.6.1
PLL Control Register (PCTL) . . . . . . . . . . . . . . . . . . . . . . 102
8.6.2
PLL Bandwidth Control Register (PBWC) . . . . . . . . . . . . . 104
8.6.3
PLL Multiplier Select Registers (PMSH:PMSL). . . . . . . . . 105
8.6.4
PLL Reference Divider Select Register (PRDS) . . . . . . . . 106
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8.7
Interrupts. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 107
8.8
Special Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 107
8.8.1
Wait Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 107
8.8.2
CGM During Break Interrupts . . . . . . . . . . . . . . . . . . . . . . 108
8.9
Acquisition/Lock Time Specifications . . . . . . . . . . . . . . . . . . . 108
8.9.1
Acquisition/Lock Time Definitions . . . . . . . . . . . . . . . . . . . 108
8.9.2
Parametric Influences on Reaction Time . . . . . . . . . . . . . 109
8.9.3
Choosing a Filter Capacitor. . . . . . . . . . . . . . . . . . . . . . . . 111
8.9.4
Reaction Time Calculation . . . . . . . . . . . . . . . . . . . . . . . . 111
Section 9. Universal Serial Bus Module (USB)
9.1
Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 113
9.2
Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 114
9.3
Overview. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 115
9.4
I/O Register Description of the HUB function . . . . . . . . . . . . . 116
9.4.1
USB HUB Root Port Control Register (HRPCR) . . . . . . . . 120
9.4.2
USB HUB Downstream Port Control Register
(HDP1CR-HDP4CR) . . . . . . . . . . . . . . . . . . . . . . . . . . 121
9.4.3
USB SIE Timing Interrupt Register (SIETIR). . . . . . . . . . . 123
9.4.4
USB SIE Timing Status Register (SIETSR) . . . . . . . . . . . 125
9.4.5
USB HUB Address Register (HADDR) . . . . . . . . . . . . . . . 127
9.4.6
USB HUB Interrupt Register 0 (HIR0) . . . . . . . . . . . . . . . . 128
9.4.7
USB HUB Control Register 0 (HCR0) . . . . . . . . . . . . . . . . 129
9.4.8
USB HUB Endpoint1 Control & Data Register (HCDR) . . 131
9.4.9
USB HUB Status Register (HSR) . . . . . . . . . . . . . . . . . . . 132
9.4.10
USB HUB Endpoint 0 Data Registers 0-7
(HE0D0-HE0D7). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 134
9.5
I/O Register Description of the Embedded Device Function . 134
9.5.1
USB Embedded Device Address Register (DADDR) . . . . 138
9.5.2
USB Embedded Device Interrupt Register 0 (DIR0) . . . . . 138
9.5.3
USB Embedded Device Interrupt Register 1 (DIR1) . . . . . 140
9.5.4
USB Embedded Device Control Register 0 (DCR0) . . . . . 141
9.5.5
USB Embedded Device Control Register 1 (DCR1) . . . . . 143
9.5.6
USB Embedded Device Status Register (DSR) . . . . . . . . 144
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9.5.7
USB Embedded Device Control Register 2 (DCR2) . . . . . 146
9.5.8
USB Embedded Device Endpoint 0 Data Registers
(DE0D0-DE0D7). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 147
9.5.9
USB Embedded Device Endpoint 1/2 Data Registers
(DE1D0-DE1D7). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 148
Section 10. Monitor ROM (MON)
10.1
Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 149
10.2
Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 149
10.3
Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 150
10.4
Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 150
10.4.1
Entering Monitor Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . 152
10.4.2
Data Format . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 154
10.4.3
Echoing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 154
10.4.4
Break Signal . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 155
10.4.5
Commands . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 155
10.4.6
Baud Rate . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 159
Section 11. Timer Interface Module (TIM)
11.1
Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 161
11.2
Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 162
11.3
Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 162
11.4
Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 163
11.4.1
TIM Counter Prescaler . . . . . . . . . . . . . . . . . . . . . . . . . . . 165
11.4.2
Input Capture. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 165
11.4.3
Output Compare . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 165
11.4.3.1
Unbuffered Output Compare . . . . . . . . . . . . . . . . . . . . . 166
11.4.3.2
Buffered Output Compare . . . . . . . . . . . . . . . . . . . . . . . 166
11.4.4
Pulse Width Modulation (PWM) . . . . . . . . . . . . . . . . . . . . 167
11.4.4.1
Unbuffered PWM Signal Generation . . . . . . . . . . . . . . . 168
11.4.4.2
Buffered PWM Signal Generation . . . . . . . . . . . . . . . . . 169
11.4.4.3
PWM Initialization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 170
11.5
Interrupts. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 171
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11.6
Wait Mode. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 171
11.7
TIM During Break Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . 172
11.8
I/O Signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 172
11.8.1
TIM Clock Pin (PTE0/TCLK) . . . . . . . . . . . . . . . . . . . . . . . 172
11.8.2
TIM Channel I/O Pins (PTE1/TCH0:PTE2/TCH1). . . . . . . 173
11.9
I/O Registers. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 173
11.9.1
TIM Status and Control Register (TSC) . . . . . . . . . . . . . . 173
11.9.2
TIM Counter Registers (TCNTH:TCNTL) . . . . . . . . . . . . . 175
11.9.3
TIM Counter Modulo Registers (TMODH:TMODL) . . . . . . 176
11.9.4
TIM Channel Status and Control Registers (TSC0:TSC1) 177
11.9.5
TIM Channel Registers (TCH0H/LTCH1H/L) . . . . . . . . . 181
Section 12. I/O Ports
12.1
Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 183
12.2
Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 184
12.3
Port A . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 186
12.3.1
Port A Data Register (PTA) . . . . . . . . . . . . . . . . . . . . . . . . 186
12.3.2
Data Direction Register A (DDRA) . . . . . . . . . . . . . . . . . . 186
12.4
Port B . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 188
12.4.1
Port B Data Register (PTB) . . . . . . . . . . . . . . . . . . . . . . . . 188
12.4.2
Data Direction Register B (DDRB) . . . . . . . . . . . . . . . . . . 189
12.5
Port C . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 190
12.5.1
Port C Data Register (PTC). . . . . . . . . . . . . . . . . . . . . . . . 190
12.5.2
Data Direction Register C (DDRC) . . . . . . . . . . . . . . . . . . 191
12.6
Port D . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 192
12.6.1
Port D Data Register (PTD). . . . . . . . . . . . . . . . . . . . . . . . 193
12.6.2
Data Direction Register D (DDRD) . . . . . . . . . . . . . . . . . . 193
12.7
Port E . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 195
12.7.1
Port E Data Register (PTE) . . . . . . . . . . . . . . . . . . . . . . . . 195
12.7.2
Data Direction Register E (DDRE) . . . . . . . . . . . . . . . . . . 196
12.7.3
Port-E Optical Interface Enable Register . . . . . . . . . . . . . 198
12.8
Port F . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 202
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12.8.1
Port F Data Register (PTF) . . . . . . . . . . . . . . . . . . . . . . . . 202
12.8.2
Data Direction Register F (DDRF). . . . . . . . . . . . . . . . . . . 203
12.9
Port Options . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 204
12.9.1
Port Option Control Register (POC) . . . . . . . . . . . . . . . . . 204
Section 13. Computer Operating Properly (COP)
13.1
Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 207
13.2
Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 207
13.3
Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 208
13.4
I/O Signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 209
13.4.1
CGMXCLK. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 209
13.4.2
COPCTL Write . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 209
13.4.3
Power-On Reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 210
13.4.4
Internal Reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 210
13.4.5
Reset Vector Fetch . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 210
13.4.6
COPD (COP Disable) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 210
13.4.7
COPRS (COP Rate Select). . . . . . . . . . . . . . . . . . . . . . . . 210
13.5
COP Control Register (COPCTL) . . . . . . . . . . . . . . . . . . . . . . 211
13.6
Interrupts. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 211
13.7
Monitor Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 211
13.8
Low-Power Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 212
13.8.1
Wait Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 212
13.8.2
Stop Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 212
13.9
COP Module During Break Mode . . . . . . . . . . . . . . . . . . . . . . 212
Section 14. External Interrupt (IRQ)
14.1
Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 213
14.2
Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 213
14.3
Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 213
14.4
Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 214
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14.4.1
IRQ1/V
PP
Pin . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 215
14.5
IRQ Module During Break Interrupts . . . . . . . . . . . . . . . . . . . 217
14.6
IRQ Status and Control Register (ISCR) . . . . . . . . . . . . . . . . 217
Section 15. Keyboard Interrupt Module (KBI)
15.1
Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 219
15.2
Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 220
15.3
Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 220
15.4
Port-D Keyboard Interrupt Block Diagram . . . . . . . . . . . . . . . 222
15.4.1
Port-D Keyboard Interrupt Functional Description. . . . . . . 223
15.4.2
Port-D Keyboard Initialization . . . . . . . . . . . . . . . . . . . . . . 224
15.4.3
Port-D Keyboard Interrupt Registers . . . . . . . . . . . . . . . . . 225
15.4.3.1
Port-D Keyboard Status and Control Register: . . . . . . . 225
15.4.3.2
Port-D Keyboard Interrupt Enable Register . . . . . . . . . . 226
15.5
Port-E Keyboard Interrupt Block Diagram . . . . . . . . . . . . . . . 228
15.5.1
Port-E Keyboard Interrupt Functional Description. . . . . . . 229
15.5.2
Port-E Keyboard Initialization . . . . . . . . . . . . . . . . . . . . . . 230
15.5.3
Port-E Keyboard Interrupt Registers . . . . . . . . . . . . . . . . . 231
15.5.3.1
Port-E Keyboard Status and Control Register . . . . . . . . 231
15.5.3.2
Port-E Keyboard Interrupt Enable Register . . . . . . . . . . 232
15.6
Port-F Keyboard Interrupt Block Diagram. . . . . . . . . . . . . . . . 234
15.6.1
Port-F Keyboard Interrupt Functional Description . . . . . . . 235
15.6.2
Port-F Keyboard Initialization . . . . . . . . . . . . . . . . . . . . . . 236
15.6.3
Port-F Keyboard Interrupt Registers . . . . . . . . . . . . . . . . . 237
15.6.3.1
Port-F Keyboard Status and Control Register . . . . . . . . 237
15.6.3.2
Port-F Keyboard Interrupt Enable Register . . . . . . . . . . 238
15.6.3.3
Port-F Pull-up Enable Register . . . . . . . . . . . . . . . . . . . 239
15.7
Wait Mode. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 239
15.8
Stop Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 239
15.9
Keyboard Module During Break Interrupts . . . . . . . . . . . . . . . 239
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Section 16. Break Module (BREAK)
16.1
Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 241
16.2
Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 241
16.3
Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 242
16.4
Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 242
16.4.1
Flag Protection During Break Interrupts . . . . . . . . . . . . . . 244
16.4.2
CPU During Break Interrupts. . . . . . . . . . . . . . . . . . . . . . . 244
16.4.3
TIM During Break Interrupts . . . . . . . . . . . . . . . . . . . . . . . 244
16.4.4
COP During Break Interrupts . . . . . . . . . . . . . . . . . . . . . . 244
16.5
Break Module Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 244
16.5.1
Break Status and Control Register (BRKSCR) . . . . . . . . . 245
16.5.2
Break Address Registers (BRKH and BRKL) . . . . . . . . . . 245
16.6
Low-Power Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 246
16.6.1
Wait Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 246
16.6.2
Stop Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 246
Section 17. Preliminary Electrical Specifications
17.1
Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 247
17.2
Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 247
17.3
Absolute Maximum Ratings . . . . . . . . . . . . . . . . . . . . . . . . . . 248
17.4
Functional Operating Range. . . . . . . . . . . . . . . . . . . . . . . . . . 249
17.5
Thermal Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 249
17.6
DC Electrical Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . 250
17.7
Control Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 251
17.8
Oscillator Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . 251
17.9
USB DC Electrical Characteristics . . . . . . . . . . . . . . . . . . . . . 252
17.10 USB Low Speed Source Electrical Characteristics. . . . . . . . . 253
17.11 USB High Speed Source Electrical Characteristics . . . . . . . . 254
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17.12 HUB Repeater Electrical Characteristics . . . . . . . . . . . . . . . . 255
17.13 USB Signaling Levels . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 256
17.14 TImer Interface Module Characteristics . . . . . . . . . . . . . . . . . 256
17.15 Clock Generation Module Characteristics . . . . . . . . . . . . . . . 257
17.15.1
CGM Component Specifications . . . . . . . . . . . . . . . . . . . . 257
17.15.2
CGM Electrical Specifications . . . . . . . . . . . . . . . . . . . . . . 257
17.15.3
Acquisition/Lock Time Specifications . . . . . . . . . . . . . . . . 258
Section 18. Mechanical Specifications
18.1
Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 259
18.2
Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 259
18.3
Plastic Quad Flat Pack (QFP). . . . . . . . . . . . . . . . . . . . . . . . . 260
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List of Figures
Figure
Title
Page
1-1
MCU Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
1-2
64-Pin QFP Assignments (Top View) . . . . . . . . . . . . . . . . . . . . 28
1-3
Power Supply Bypassing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29
2-1
Memory Map. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34
2-2
Control, Status, and Data Registers . . . . . . . . . . . . . . . . . . . . . 36
5-1
Configuration Register (CONFIG). . . . . . . . . . . . . . . . . . . . . . . 50
6-1
CPU Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53
6-2
Accumulator (A) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53
6-3
Index Register (H:X) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54
6-4
Stack Pointer (SP) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55
6-5
Program Counter (PC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56
6-6
Condition Code Register (CCR) . . . . . . . . . . . . . . . . . . . . . . . . 57
7-1
SIM Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 63
7-2
SIM I/O Register Summary. . . . . . . . . . . . . . . . . . . . . . . . . . . . 64
7-3
SIM Clock Signals. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 65
7-4
External Reset Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 67
7-5
Internal Reset Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 68
7-6
Sources of Internal Reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 68
7-7
POR Recovery . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 69
7-8
Interrupt Processing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 73
7-9
Interrupt Entry . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 74
7-10
Interrupt Recovery . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 74
7-11
Interrupt Recognition Example . . . . . . . . . . . . . . . . . . . . . . . . . 75
7-12
Interrupt Status Register 1 (INT1). . . . . . . . . . . . . . . . . . . . . . . 77
7-13
Interrupt Status Register 2 (INT2). . . . . . . . . . . . . . . . . . . . . . . 78
7-14
Interrupt Status Register 2 (INT2). . . . . . . . . . . . . . . . . . . . . . . 78
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Figure
Title
Page
7-15
Wait Mode Entry Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 80
7-16
Wait Recovery from Interrupt or Break . . . . . . . . . . . . . . . . . . . 81
7-17
Wait Recovery from Internal Reset. . . . . . . . . . . . . . . . . . . . . . 81
7-18
Stop Mode Entry Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 82
7-19
Stop Mode Recovery from Interrupt or Break . . . . . . . . . . . . . . 82
7-20
Break Status Register (BSR) . . . . . . . . . . . . . . . . . . . . . . . . . . 83
7-21
Reset Status Register (RSR) . . . . . . . . . . . . . . . . . . . . . . . . . . 84
7-22
Break Flag Control Register (BFCR) . . . . . . . . . . . . . . . . . . . . 85
8-1
CGM Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 90
8-2
CGM External Connections . . . . . . . . . . . . . . . . . . . . . . . . . . . 97
8-3
PLL Control Register (PCTL) . . . . . . . . . . . . . . . . . . . . . . . . . 102
8-4
PLL Bandwidth Control Register (PBWC) . . . . . . . . . . . . . . . 104
8-5
PLL Multiplier Select Registers (PMSH:PMSL) . . . . . . . . . . . 105
8-6
PLL Reference Divider Select Register (PRDS). . . . . . . . . . . 106
9-1
USB Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 116
9-2
USB HUB Root Port Control Register (HRPCR) . . . . . . . . . . 120
9-3
USB HUB Downstream Port Control Registers
(HDP1CR-HDP4CR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 121
9-4
USB SIE Timing Interrupt Register (SIETIR) . . . . . . . . . . . . . 123
9-5
USB SIE Timing Status Register (SIETSR) . . . . . . . . . . . . . . 125
9-6
USB HUB Address Register (HADDR) . . . . . . . . . . . . . . . . . . 127
9-7
USB HUB Interrupt Register 0 (HIR0) . . . . . . . . . . . . . . . . . . 128
9-8
USB HUB Control Register 0 (HCR0). . . . . . . . . . . . . . . . . . . 129
9-9
USB HUB Control Register 1 (HCR1). . . . . . . . . . . . . . . . . . . 131
9-10
USB HUB Status Register (HSR) . . . . . . . . . . . . . . . . . . . . . . 132
9-11
USB HUB Endpoint 0 Data Register (HE0D0-HE0D7). . . . . . 134
9-12
USB Embedded Device Address Register (DADDR) . . . . . . . 138
9-13
USB Embedded Device Interrupt Register 0 (DIR0). . . . . . . . 138
9-14
USB Embedded Device Interrupt Register 1 (DIR1). . . . . . . . 140
9-15
USB Embedded Device Control Register 0 (DCR0). . . . . . . . 141
9-16
USB Embedded Device Control Register 1 (DCR1). . . . . . . . 143
9-17
USB Embedded Device Status Register (DSR) . . . . . . . . . . . 144
9-18
USB Embedded Device Control Register 2 (DCR2). . . . . . . . 146
9-19
USB Embedded Device Endpoint 0 Data Register
(UE0D0-UE0D7) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 147
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Figure
Title
Page
9-20
USB Embedded Device Endpoint 0 Data Register
(UE0D0-UE0D7) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 148
10-1
Monitor Mode Circuit. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 151
10-2
Monitor Data Format. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 154
10-3
Sample Monitor Waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . 154
10-4
Read Transaction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 154
10-5
Break Transaction. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 155
11-1
TIM Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 163
11-2
PWM Period and Pulse Width . . . . . . . . . . . . . . . . . . . . . . . . 168
11-3
TIM Status and Control Register (TSC) . . . . . . . . . . . . . . . . . 174
11-4
TIM Counter Registers (TCNTH:TCNTL) . . . . . . . . . . . . . . . . 176
11-5
TIM Counter Modulo Registers (TMODH:TMODL). . . . . . . . . 177
11-6
TIM Channel Status and Control Registers (TSC0:TSC1) . . . 178
11-7
CHxMAX Latency . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 181
11-8
TIM Channel Registers (TCH0H/L:TCH1H/L). . . . . . . . . . . . . 182
12-1
Port A Data Register (PTA) . . . . . . . . . . . . . . . . . . . . . . . . . . 186
12-2
Data Direction Register A (DDRA) . . . . . . . . . . . . . . . . . . . . . 187
12-3
Port A I/O Circuit. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 187
12-4
Port B Data Register (PTB) . . . . . . . . . . . . . . . . . . . . . . . . . . 188
12-5
Data Direction Register B (DDRB) . . . . . . . . . . . . . . . . . . . . . 189
12-6
Port B I/O Circuit. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 189
12-7
Port C Data Register (PTC) . . . . . . . . . . . . . . . . . . . . . . . . . . 190
12-8
Data Direction Register C (DDRC) . . . . . . . . . . . . . . . . . . . . . 191
12-9
Port C I/O Circuit. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 192
12-10 Port D Data Register (PTD) . . . . . . . . . . . . . . . . . . . . . . . . . . 193
12-11 Data Direction Register D (DDRD) . . . . . . . . . . . . . . . . . . . . . 194
12-12 Port D I/O Circuit. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 194
12-13 Port E Data Register (PTE) . . . . . . . . . . . . . . . . . . . . . . . . . . 195
12-14 Data Direction Register E (DDRE) . . . . . . . . . . . . . . . . . . . . . 197
12-15 Port E I/O Circuit. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 197
12-16 Optical Interface Enable Register E (EOIER) . . . . . . . . . . . . . 198
12-17 Optical Interface Voltage References . . . . . . . . . . . . . . . . . . . 200
12-18 Port E Optical Coupling Interface . . . . . . . . . . . . . . . . . . . . . . 201
12-19 Port F Data Register (PTF). . . . . . . . . . . . . . . . . . . . . . . . . . . 202
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Figure
Title
Page
12-20 Data Direction Register F (DDRF) . . . . . . . . . . . . . . . . . . . . . 203
12-21 Port F I/O Circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 203
12-22 Port Option Control Register (POC) . . . . . . . . . . . . . . . . . . . . 204
13-1
COP Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 208
13-2
Configuration Register (CONFIG). . . . . . . . . . . . . . . . . . . . . . 210
13-3
COP Control Register (COPCTL) . . . . . . . . . . . . . . . . . . . . . . 211
14-1
IRQ Module Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . 215
14-2
IRQ Status and Control Register (ISCR) . . . . . . . . . . . . . . . . 217
15-1
Port-D Keyboard Interrupt Block Diagram . . . . . . . . . . . . . . . 222
15-2
Port-D Keyboard Status and Control Register (KBDSCR) . . . 225
15-3
Port-D Keyboard Interrupt Enable Register (KBDIER) . . . . . . 226
15-4
Port-E Keyboard Interrupt Block Diagram . . . . . . . . . . . . . . . 228
15-5
Port-E Keyboard Status and Control Register (KBESCR) . . . 231
15-6
Port-E Keyboard Interrupt Enable Register (KBEIER) . . . . . . 232
15-7
Port-F Keyboard Interrupt Block Diagram. . . . . . . . . . . . . . . . 234
15-8
Port-F Keyboard Status and Control Register (KBFSCR) . . . 237
15-9
Port-F Keyboard Interrupt Enable Register (KBFIER) . . . . . . 238
15-10 Port F Pull-up Enable Register (PFPER) . . . . . . . . . . . . . . . . 239
16-1
Break Module Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . 243
16-2
Break Status and Control Register (BRKSCR). . . . . . . . . . . . 245
16-3
Break Address Registers (BRKH and BRKL) . . . . . . . . . . . . . 246
18-1
64-Pin Quad-Flat-Pack (Case 840C-04). . . . . . . . . . . . . . . . . 260
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List of Tables
21
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List of Tables
Table
Title
Page
2-1
Vector Addresses ..................................................................... 43
7-1
Signal Name Conventions ........................................................ 65
7-2
PIN Bit Set Timing .................................................................... 67
7-3
Interrupt Sources ...................................................................... 76
7-4
SIM Registers ........................................................................... 83
8-1
CGM Numeric Example ............................................................ 95
8-2
CGM I/O Register Summary................................................... 101
8-3
PRE[1:0] Programming........................................................... 104
9-1
HUB Control Register Summary............................................. 117
9-2
HUB Data Register Summary................................................. 119
9-3
Embedded Device Control Register Summary ....................... 135
9-4
Embedded Device Data Register Summary ........................... 136
10-1
Mode Selection ...................................................................... 152
10-2
Mode Differences.................................................................... 153
10-3
READ (Read Memory) Command .......................................... 156
10-4
WRITE (Write Memory) Command......................................... 156
10-5
IREAD (Indexed Read) Command ......................................... 157
10-6
IWRITE (Indexed Write) Command ........................................ 157
10-7
READSP (Read Stack Pointer) Command ............................. 158
10-8
RUN (Run User Program) Command ..................................... 158
10-9
Monitor Baud Rate Selection .................................................. 159
11-1
TIM I/O Register Summary ..................................................... 164
11-2
Prescaler Selection................................................................. 175
11-3
Mode, Edge, and Level Selection ........................................... 180
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MOTOROLA
Table
Title
Page
12-1
I/O Port Register Summary..................................................... 184
12-2
Port A Pin Functions ............................................................... 188
12-3
Port B Pin Functions ............................................................... 190
12-4
Port C Pin Functions............................................................... 192
12-5
Port D Pin Functions............................................................... 195
12-6
Port E Pin Functions ............................................................... 198
12-7
Port F Pin Functions ............................................................... 204
13-1
COP I/O Port Register Summary............................................ 208
14-1
IRQ I/O Port Register Summary ............................................. 215
15-1
KBI I/O Register Summary ..................................................... 221
16-1
Break I/O Register Summary.................................................. 243
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General Description
23
Advance Information -- MC68HC(7)08KH12
Section 1. General Description
1.1 Contents
1.2
Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
1.3
Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
1.4
MCU Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26
1.5
Pin Assignments . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28
1.5.1
Quad Flat Pack (QFP) Package . . . . . . . . . . . . . . . . . . . . . 28
1.5.2
Power Supply Pins
(V
DDA
, V
SSA
, V
DD1
, V
SS1
, V
DD2
, and V
SS2
) . . . . . . . . . . 29
1.5.3
Oscillator Pins (OSC1 and OSC2) . . . . . . . . . . . . . . . . . . . 30
1.5.4
External Reset Pin (RST) . . . . . . . . . . . . . . . . . . . . . . . . . . 30
1.5.5
External Interrupt Pin (IRQ1/V
PP
) . . . . . . . . . . . . . . . . . . . . 30
1.5.6
USB Data Pins
(DPLUS0DPLUS4 and DMINUS0DMINUS4). . . . . . . 30
1.5.7
Voltage Regulator Out (REGOUT) . . . . . . . . . . . . . . . . . . . 30
1.5.8
Port A Input/Output (I/O) Pins (PTA7PTA0) . . . . . . . . . . . 31
1.5.9
Port B I/O Pins (PTB7PTB0) . . . . . . . . . . . . . . . . . . . . . . . 31
1.5.10
Port C I/O Pins (PTC4PTC0). . . . . . . . . . . . . . . . . . . . . . . 31
1.5.11
Port D I/O Pins (PTD7/KBD7PTD0/KBD0) . . . . . . . . . . . . 31
1.5.12
Port E I/O Pins (PTE4, PTE3/KBE3, PTE2/KBE2/TCH1,
PTE1/KBE1/TCH0, PTE0/KBE0/TCLK) . . . . . . . . . . . . . 31
1.5.13
Port F I/O Pins (PTF7/KBF7PTF0/KBF0) . . . . . . . . . . . . . 32
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General Description
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1.2 Introduction
The MC68HC(7)08KH12 is a member of the low-cost, high-performance
M68HC08 Family of 8-bit microcontroller units (MCUs). The M68HC08
Family is based on the customer-specified integrated circuit (CSIC)
design strategy. All MCUs in the family use the enhanced M68HC08
central processor unit (CPU08) and are available with a variety of
modules, memory sizes and types, and package types.
1.3 Features
Features of the MC68HC(7)08KH12 include the following:
High-Performance M68HC08 Architecture
Fully Upward-Compatible Object Code with M6805, M146805,
and M68HC05 Families
6 MHz Internal Bus Operation
Low-Power Design (Fully Static with Stop and Wait Modes)
12 KBytes of User ROM (MC68HC08KH12) or One-Time
Programmable (OTP) ROM (MC68HC708KH12)
On-Chip Programming Firmware for Use with Host Personal
Computer
ROM/OTPROM Data Security
1
384 Bytes of On-Chip Random Access Memory (RAM)
42 General Purpose I/O, 29 with Software Configurable Pullups
16-Bit, 2-Channel Timer Interface Module (TIM)
20-Bit Keyboard Interrupt Port
5 LED Direct Drive Port Pins
48MHz Phase-Locked Loop
1. No security feature is absolutely secure. However, Motorola's strategy is to make reading or
copying the ROM/OTPROM difficult for unauthorized users.
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General Description
25
Full Universal Serial Bus Specification 1.1 Composite HUB with
Embedded
1
Functions:
1
12MHz Upstream Port
4
12MHz/1.5MHz Downstream Ports
1
Hub Control Endpoint (Endpoint0) with 8 byte transmit
buffer and 8 byte receive buffer
1
Hub Interrupt Endpoint (Endpoint1) with 1 byte transmit
buffer
1
Device Control Endpoint (Endpoint0) with 8 byte transmit
buffer and 8 byte receive buffer
Device Interrupt Endpoints (Endpoint1 and Endpoint2) share
with 8 byte transmit buffer
On-chip 3.3V regulator for USB Transceiver
System Protection Features
Optional Computer Operating Properly (COP) Reset
Illegal Opcode Detection with Optional Reset
Illegal Address Detection with Optional Reset
Master Reset Pin with Internal Pullup and Power-On Reset
An External Asynchronous Interrupt Pin with Internal Pullup
(IRQ1)
64-pin plastic quad flatpack (QFP) package
1. Embedded device supports only bulk and interrupt transfers, and does not support
isochronous transfers.
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General Description
MOTOROLA
Features of the CPU08 include the following:
Enhanced HC05 Programming Model
Extensive Loop Control Functions
16 Addressing Modes (Eight More Than the HC05)
16-Bit Index Register and Stack Pointer
Memory-to-Memory Data Transfers
Fast 8
8 Multiply Instruction
Fast 16/8 Divide Instruction
Binary-Coded Decimal (BCD) Instructions
Optimization for Controller Applications
Third Party C Language Support
1.4 MCU Block Diagram
Figure 1-1
shows the structure of the MC68HC(7)08KH12.
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MC68HC(7)08KH12
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General Description
27
General Description
MCU Block Diagram
Figure 1-1. MCU Block Diagram
DS Port 1
PORTS ARE SOFTWARE CONFIGURABLE WITH PULLUP DEVICE IF INPUT PORT
SOFTWARE CONFIGURABLE LED DIRECT DRIVE 3mA SOURCE /10mA SINK or STANDARD DRIVE
PIN CONTAINS INTEGRATED PULLUP DEVICE
PIN HAS INTERRUPT CAPABILITY
PIN HAS INTERRUPT AND INTEGRATED PULLUP DEVICE.
PIN HAS OPTICAL COUPLING INTERFACE
OSC1
OSC2
RST
IRQ1/VPP
VDD1
VSS1
PTC4PTC0
REGOUT
PTB7PTB0
PTA7PTA0
PTE3/KBE3
PTE0/KBE0
VDD2
VSS2
VSSA
VDDA
CGMXFC
DPLUS4
TCH0/PTE1
TCH1/PTE2
TCLK/PTE0
PORT C
DDRC
PORT B
DDRB
PORT A
DDRA
POR
T D
DDRD
POR
T E
DDRE
POR
T F
DDRF
Embedded USB Function
384 bytes RAM
12k-bytes ROM/OTPROM
68HC08 CPU
CPU CONTROL
ALU
CPU REGISTERS
ACCUMULATOR
INDEX REGISTER
STACK POINTER
PROGRAM COUNTER
CONDITION CODE REGISTER
V 1 1 H
I
N Z C
DMINUS4
DPLUS3
DMINUS3
DPLUS2
DMINUS2
DPLUS1
DMINUS1
DPLUS0
US Port
DMINUS0
MONITOR ROM
240 bytes
COP MODULE
TIMER INTERFACE
MODULE
POWER-ON RESET
MODULE
BREAK MODULE
IRQ MODULE
SYSTEM INTEGRATION
MODULE
CLOCK GENERATION
MODULE AND PLL
POWER SUPPLY
AND
VOLTAGE REGULATION
PTD7/KBD7
PTD0/KBD0
DS Port 2
DS Port 3
DS Port 4
PTF7/KBF7
PTF0/KBF0
PTE4
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General Description
MOTOROLA
1.5 Pin Assignments
1.5.1 Quad Flat Pack (QFP) Package
Figure 1-2
Shows the 64-pin QFP assignments.
Figure 1-2. 64-Pin QFP Assignments (Top View)
DMINUS0
DPLUS0
REGOUT
VSSA
OSC2
OSC1
CGMXFC
VDDA
DPLUS1
DMINUS1
DPLUS2
DMINUS2
DPLUS3
1
2
3
4
5
6
7
8
9
10
11
12
13
DMINUS3
DPLUS4
DMINUS4
14
15
16
PTB4
PTB5
PTB6
PTB7
PTA0
PTA1
PTA2
PTA3
PTB3
PTB2
PTB1
PTB0
PTD7/KBD7
47
46
45
44
42
42
41
40
39
38
37
36
PTD6/KBD6
PTD5/KBD5
PTD4/KBD4
35
34
33
PTF5/KBF5
PTF4/KBF4
PTF3/KBF3
PTF2/KBF2
PTF1/KBF1
PTF0/KBF0
RST
IRQ1
/VPP
PTF6/KBF6
PTF7/KBF7
VSS2
VDD2
PTA7
63
62
61
60
59
58
57
56
55
54
53
52
PTA6
PTA5
PTA4
51
50
49
PTC0
VDD1
VSS1
PTE0/KBE0/TCLK
PTE1/KBE1/TCH0
PTE2/KBE2/TCH1
PTE3/KBE3
PTE4
PTC1
PTC2
PTC3
PTC4
PTD0/KBD0
18
19
20
21
22
23
24
25
26
27
28
29
PTD1/KBD1
PTD2/KBD2
PTD3/KBD3
30
31
32
64
17
48
68HC(7)08KH12
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General Description
Pin Assignments
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General Description
29
1.5.2 Power Supply Pins (V
DDA
, V
SSA
, V
DD1
, V
SS1
, V
DD2
, and V
SS2
)
V
DDA
and V
SSA
are the analog power supply and ground pins used by
the on-chip Phase-Locked Loop circuit.
V
DD2
and V
SS2
are the power supply and ground pins used by the
internal circuitry of the chip.
V
DD1
and V
SS1
are the power supply and ground pins to the I/O pads.
The MCU operates from a single power supply.
Fast signal transitions on MCU pins place high, short-duration current
demands on the power supply. To prevent noise problems, take special
care to provide power supply bypassing at the MCU as
Figure 1-3
shows. Place the bypass capacitors as close to the MCU power pins as
possible. Use high-frequency-response ceramic capacitors for C
BYPASS
.
C
BULK
are optional bulk current bypass capacitors for use in applications
that require the port pins to source high current levels.
Figure 1-3. Power Supply Bypassing
MCU
C
BULK
C
BYPASS
10nF
V
SS1
+
NOTE: Values shown are typical values.
V
DD2
C
BYPASS
10nF
V
DD2
C
BYPASS
10nF
V
SS2
V
SSA
V
DDA
Vbus
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1.5.3 Oscillator Pins (OSC1 and OSC2)
The OSC1 and OSC2 pins are the connections for the on-chip oscillator
circuit.
(See Section 8. Clock Generator Module (CGM)
.)
1.5.4 External Reset Pin (RST)
A logic zero on the RST pin forces the MCU to a known start-up state.
RST is bidirectional, allowing a reset of the entire system. It is driven low
when any internal reset source is asserted. The RST pin contains an
internal pullup device. (
(See Section 7. System Integration Module
(SIM)
.)
1.5.5 External Interrupt Pin (IRQ1/V
PP
)
IRQ1/V
PP
is an asynchronous external interrupt pin. IRQ1/V
PP
is also
the OTPROM programming power pin. The IRQ1/V
PP
pin contain an
internal pullup device.
(See Section 14. External Interrupt (IRQ)
.)
1.5.6 USB Data Pins (DPLUS0DPLUS4 and DMINUS0DMINUS4)
DPLUS0DPLUS4 and DMINUS0DMINUS4 are the differential data
lines used by the USB module.
(See Section 9. Universal Serial Bus
Module (USB)
.)
1.5.7 Voltage Regulator Out (REGOUT)
REGOUT is the 3.3V output of the on-chip voltage regulator. It is used
to supply the voltage for the external pullup resistor required by the USB
on either DPLUS or DMINUS lines, depending on type of USB function.
REGOUT is also used internally for the USB data driver and the Phase-
locked Loop circuit. The REGOUT pin requires an external bulk
capacitor 1
F or larger and a bypass capacitor.
(See Section 9.
Universal Serial Bus Module (USB)
.)
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Pin Assignments
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General Description
31
1.5.8 Port A Input/Output (I/O) Pins (PTA7PTA0)
PTA7PTA0 are general-purpose bidirectional I/O port pins.
(See
Section 12. I/O Ports
.) Each pin contains a software configurable pull-
up device when the pin is configured as an input.
(See 12.9 Port
Options
.)
1.5.9 Port B I/O Pins (PTB7PTB0)
PTB7PTB0 are general-purpose bidirectional I/O port pins.
(See
Section 12. I/O Ports
.) Each pin contains a software configurable pull-
up device when the pin is configured as an input.
(See 12.9 Port
Options
.)
1.5.10 Port C I/O Pins (PTC4PTC0)
PTC4PTC0 are general-purpose bidirectional I/O port pins.
(See
Section 12. I/O Ports
.) Port C pins are software configurable to be LED
Direct Drive ports. Each pin contains a software configurable pull-up
device when the pin is configured as an input.
(See 12.9 Port Options
.)
1.5.11 Port D I/O Pins (PTD7/KBD7PTD0/KBD0)
PTD7/KBD7PTD0/KBD0 are general-purpose bidirectional I/O port
pins.
(See Section 12. I/O Ports
.) Any or all of the port D pins can be
programmed to serve as external interrupt pins.
(See Section 15.
Keyboard Interrupt Module (KBI)
.)
1.5.12 Port E I/O Pins (PTE4, PTE3/KBE3, PTE2/KBE2/TCH1,
PTE1/KBE1/TCH0, PTE0/KBE0/TCLK)
Port-E is a 5-bit special function port which shares three of its pins with
the Timer Interface Module and four of its pins with Keyboard Interrupt
Module (
see Section 12. I/O Ports
,
Section 15. Keyboard Interrupt
Module (KBI)
and
Section 11. Timer Interface Module (TIM)
). In
addition, PTE3-PTE0 has built-in optical coupling interface for optical
mouse application.
(See Section 12. I/O Ports
.)
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1.5.13 Port F I/O Pins (PTF7/KBF7PTF0/KBF0)
PTF7/KBF7PTF0/KBF0 are general-purpose bidirectional I/O port pins.
(See Section 12. I/O Ports
.) Any or all of the port F pins can be
programmed to serve as external interrupt pins.
(See Section 15.
Keyboard Interrupt Module (KBI)
.)
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Memory Map
33
Advance Information -- MC68HC(7)08KH12
Section 2. Memory Map
2.1 Contents
2.2
Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33
2.3
I/O Section . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35
2.4
Monitor ROM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43
2.2 Introduction
The CPU08 can address 64 Kbytes of memory space. The memory
map, shown in
Figure 2-1
, includes:
11776 bytes of ROM or OTPROM
384 bytes of RAM
26 bytes of user-defined vectors
240 bytes of Monitor ROM
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Memory Map
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Memory Map
MOTOROLA
$0000
$005F
I/O REGISTERS (80 BYTES)
$0060
$01DF
RAM (384 BYTES)
$01E0
$CDFF
UNIMPLEMENTED (52, 256 BYTES)
$D000
$FDFF
ROM/OTPROM (11776 BYTES)
$FE00
BREAK STATUS REGISTER (BSR)
$FE01
RESET STATUS REGISTER (RSR)
$FE02
RESERVED
$FE03
BREAK FLAG CONTROL REGISTER (BFCR)
$FE04
INTERRUPT STATUS REGISTER 1 (INT1)
$FE05
INTERRUPT STATUS REGISTER 2 (INT2)
$FE06
RESERVED
$FE07
RESERVED
$FE08
$FE0B
RESERVED (4 BYTES)
$FE0C
BREAK ADDRESS HIGH REGISTER (BRKH)
$FE0D
BREAK ADDRESS LOW REGISTER (BRKL)
$FE0E
BREAK STATUS AND CONTROL REGISTER (BSCR)
$FE0F
RESERVED
$FE10
$FEFF
MONITOR ROM (240 BYTES)
$FF00
$FF00 to $FF8C
UNIMPLEMENTED (141 BYTES)
$FF8D
RESERVED
$FFE5
$FF8E to $FFE5
UNIMPLEMENTED (88 BYTES)
$FFE6
$FFFF
VECTORS (26 BYTES)
Figure 2-1. Memory Map
background image
Memory Map
I/O Section
MC68HC(7)08KH12
--
Rev. 1.0
Advance Information
MOTOROLA
Memory Map
35
2.3 I/O Section
Addresses $0000$005F, shown in
Figure 2-2
, contain most of the
control, status, and data registers. Additional I/O registers have the
following addresses:
$FE00 (Break Status Register, BSR)
$FE01 (Reset Status Register, RSR)
$FE02 (Reserved)
$FE03 (Break Flag Control Register, BFCR)
$FE04 (Interrupt Status Register 1, INT1)
$FE05 (Interrupt Status Register 2, INT2)
$FE06 (Reserved)
$FE07 (Reserved)
$FE08 (Reserved)
$FE09 (Reserved)
$FE0A (Reserved)
$FE0B (Reserved)
$FE0C and $FE0D (Break Address Registers, BRKH and BRKL)
$FE0E (Break Status and Control Register, BSCR)
$FF8D (Reserved)
$FFFF (COP Control Register, COPCTL)
background image
Memory Map
Advance Information
MC68HC(7)08KH12
--
Rev. 1.0
36
Memory Map
MOTOROLA
Addr.
Name
Bit 7
6
5
4
3
2
1
Bit 0
$0000
Port A Data Register (PTA)
R:
PTA7
PTA6
PTA5
PTA4
PTA3
PTA2
PTA1
PTA0
W:
$0001
Port B Data Register (PTB)
R:
PTB7
PTB6
PTB5
PTB4
PTB3
PTB2
PTB1
PTB0
W:
$0002
Port C Data Register (PTC)
R:
0
0
0
PTC4
PTC3
PTC2
PTC1
PTC0
W:
$0003
Port D Data Register (PTD)
R:
PTD7
PTD6
PTD5
PTD4
PTD3
PTD2
PTD1
PTD0
W:
$0004
Data Direction Register A (DDRA)
R:
DDRA7
DDRA6
DDRA5
DDRA4
DDRA3
DDRA2
DDRA1
DDRA0
W:
$0005
Data Direction Register B (DDRB)
R:
DDRB7
DDRB6
DDRB5
DDRB4
DDRB3
DDRB2
DDRB1
DDRB0
W:
$0006
Data Direction Register C (DDRC)
R:
0
0
0
DDRC4
DDRC3
DDRC2
DDRC1
DDRC0
W:
$0007
Data Direction Register D (DDRD)
R:
DDRD7
DDRD6
DDRD5
DDRD4
DDRD3
DDRD2
DDRD1
DDRD0
W:
$0008
Port E Data Register (PTE)
R:
0
0
0
PTE4
PTE3
PTE2
PTE1
PTE0
W:
$0009
Port F Data Register (PTF)
R:
PTF7
PTF6
PTF5
PTF4
PTF3
PTF2
PTF1
PTF0
W:
$000A
Data Direction Register E (DDRE)
R:
0
0
0
DDRE4
DDRE3
DDRE2
DDRE1
DDRE0
W:
$000B
Data Direction Register F (DDRF)
R:
DDRF7
DDRF6
DDRF5
DDRF4
DDRF3
DDRF2
DDRF1
DDRF0
W:
$000C
Port D Keyboard Status and
Control Register (KBDSCR)
R:
0
0
0
0
KEYDF
0
IMASKD
MODED
W:
ACKD
$000D
Port D Keyboard Interrupt Enable
Register (KBDIER)
R: KBDIE7
KBDIE6
KBDIE5
KBDIE4
KBDIE3
KBDIE2
KBDIE1
KBDIE0
$000E
Port E Keyboard Status and
Control Register (KBESCR)
R:
0
0
0
0
KEYEF
0
IMASKE
MODEE
W:
ACKE
$000F
Port E Keyboard Interrupt Enable
Register (KBEIER)
R:
PEPE3
PEPE2
PEPE1
PEPE0
KBEIE3
KBEIE2
KBEIE1
KBEIE0
W:
= Unimplemented
R
= Reserved
Figure 2-2. Control, Status, and Data Registers
background image
Memory Map
I/O Section
MC68HC(7)08KH12
--
Rev. 1.0
Advance Information
MOTOROLA
Memory Map
37
$0010
TIM Status and Control Register
(TSC)
R:
TOF
TOIE
TSTOP
0
0
PS2
PS1
PS0
W:
0
TRST
$0011
Unimplemented
R:
W:
$0012
TIM Counter Register High
(TCNTH)
R:
Bit 15
14
13
12
11
10
9
Bit 8
W:
$0013
TIM Counter Register Low
(TCNTL)
R:
Bit 7
6
5
4
3
2
1
Bit 0
W:
$0014
TIM Counter Modulo Register High
(TMODH)
R:
Bit 15
14
13
12
11
10
9
Bit 8
W:
$0015
TIM Counter Modulo Register Low
(TMODL)
R:
Bit 7
6
5
4
3
2
1
Bit 0
W:
$0016
TIM Channel 0 Status and Control
Register (TSC0)
R:
CH0F
CH0IE
MS0B
MS0A
ELS0B
ELS0A
TOV0
CH0MAX
W:
0
$0017
TIM Channel 0 Register High
(TCH0H)
R:
Bit 15
14
13
12
11
10
9
Bit 8
W:
$0018
TIM Channel 0 Register Low
(TCH0L)
R:
Bit 7
6
5
4
3
2
1
Bit 0
W:
$0019
TIM Channel 1 Status and Control
Register (TSC1)
R:
CH1F
CH1IE
0
MS1A
ELS1B
ELS1A
TOV1
CH1MAX
W:
0
$001A
TIM Channel 1 Register High
(TCH1H)
R:
Bit 15
14
13
12
11
10
9
Bit 8
$001B
TIM Channel 1 Register Low
(TCH1L)
R:
Bit 7
6
5
4
3
2
1
Bit 0
W:
$001C
PORT E Optical Interface Enable
Register (EOIER)
R:
YREF2
YREF1
YREF0
XREF2
XREF1
XREF0
OIEY
OIEX
W:
$001D Port Option Control Register (POC)
R:
0
0
LDD
0
0
PCP
PBP
PAP
W:
$001E
IRQ Status and Control Register
(ISCR)
R:
0
0
0
0
IRQF1
0
IMASK1
MODE1
W
ACK1
$001F
Configuration Register
(CONFIG)
R:
0
0
0
0
SSREC
COPRS
STOP
COPD
W:
One-time writable register
Addr.
Name
Bit 7
6
5
4
3
2
1
Bit 0
= Unimplemented
R
= Reserved
Figure 2-2. Control, Status, and Data Registers (Continued)
background image
Memory Map
Advance Information
MC68HC(7)08KH12
--
Rev. 1.0
38
Memory Map
MOTOROLA
$0020
USB Embedded Device Endpoint 0
Data Register 0 (DE0D0)
R: DE0R07
DE0R06
DE0R05
DE0R04
DE0R03
DE0R02
DE0R01
DE0R00
W: DE0T07
DE0T06
DE0T05
DE0T04
DE0T03
DE0T02
DE0T01
DE0T00
$0021
USB Embedded Device Endpoint 0
Data Register 1 (DE0D1)
R: DE0R17
DE0R16
DE0R15
DE0R14
DE0R13
DE0R12
DE0R11
DE0R10
W: DE0T17
DE0T16
DE0T15
DE0T14
DE0T13
DE0T12
DE0T11
DE0T10
$0022
USB Embedded Device Endpoint 0
Data Register 2 (DE0D2)
R: DE0R27
DE0R26
DE0R25
DE0R24
DE0R23
DE0R22
DE0R21
DE0R20
W: DE0T27
DE0T26
DE0T25
DE0T24
DE0T23
DE0T22
DE0T21
DE0T20
$0023
USB Embedded Device Endpoint 0
Data Register 3 (DE0D3)
R: DE0R37
DE0R36
DE0R35
DE0R34
DE0R33
DE0R32
DE0R31
DE0R30
W: DE0T37
DE0T36
DE0T35
DE0T34
DE0T33
DE0T32
DE0T31
DE0T30
$0024
USB Embedded Device Endpoint 0
Data Register 4 (DE0D4)
R: DE0R47
DE0R46
DE0R45
DE0R44
DE0R43
DE0R42
DE0R41
DE0R40
W: DE0T47
DE0T46
DE0T45
DE0T44
DE0T43
DE0T42
DE0T41
DE0T40
$0025
USB Embedded Device Endpoint 0
Data Register 5 (DE0D5)
R: DE0R57
DE0R56
DE0R55
DE0R54
DE0R53
DE0R52
DE0R51
DE0R50
W: DE0T57
DE0T56
DE0T55
DE0T54
DE0T53
DE0T52
DE0T51
DE0T50
$0026
USB Embedded Device Endpoint 0
Data Register 6 (DE0D6)
R: DE0R67
DE0R66
DE0R65
DE0R64
DE0R63
DE0R62
DE0R61
DE0R60
W: DE0T67
DE0T66
DE0T65
DE0T64
DE0T63
DE0T62
DE0T61
DE0T60
$0027
USB Embedded Device Endpoint 0
Data Register 7 (DE0D7)
R: DE0R77
DE0R76
DE0R75
DE0R74
DE0R73
DE0R72
DE0R71
DE0R70
W: DE0T77
DE0T76
DE0T75
DE0T74
DE0T73
DE0T72
DE0T71
DE0T70
$0028
USB Embedded Device Endpoint
1/2 Data Register 0 (DE1D0)
R:
W: DE1T07
DE1T06
DE1T05
DE1T04
DE1T03
DE1T02
DE1T01
DE1T00
$0029
USB Embedded Device Endpoint
1/2 Data Register 1 (DE1D1)
R:
W: DE1T17
DE1T16
DE1T15
DE1T14
DE1T13
DE1T12
DE1T11
DE1T10
$002A
USB Embedded Device Endpoint
1/2 Data Register 2 (DE1D2)
R:
W: DE1T27
DE1T26
DE1T25
DE1T24
DE1T23
DE1T22
DE1T21
DE1T20
$002B
USB Embedded Device Endpoint
1/2 Data Register 3 (DE1D3)
R:
W: DE1T37
DE1T36
DE1T35
DE1T34
DE1T33
DE1T32
DE1T31
DE1T30
$002C
USB Embedded Device Endpoint
1/2 Data Register 4 (DE1D4)
R:
W: DE1T47
DE1T46
DE1T45
DE1T44
DE1T43
DE1T42
DE1T41
DE1T40
$002D
USB Embedded Device Endpoint
1/2 Data Register 5 (DE1D5)
R:
W: DE1T57
DE1T56
DE1T55
DE1T54
DE1T53
DE1T52
DE1T51
DE1T50
$002E
USB Embedded Device Endpoint
1/2 Data Register 6 (DE1D6)
R:
W: DE1T67
DE1T66
DE1T65
DE1T64
DE1T63
DE1T62
DE1T61
DE1T60
$002F
USB Embedded Device Endpoint
1/2 Data Register 7 (DE1D7)
R:
W: DE1T77
DE1T76
DE1T75
DE1T74
DE1T73
DE1T72
DE1T71
DE1T70
Addr.
Name
Bit 7
6
5
4
3
2
1
Bit 0
= Unimplemented
R
= Reserved
Figure 2-2. Control, Status, and Data Registers (Continued)
background image
Memory Map
I/O Section
MC68HC(7)08KH12
--
Rev. 1.0
Advance Information
MOTOROLA
Memory Map
39
$0030
USB HUB Endpoint 0 Data
Register 0 (HE0D0)
R: HE0R07
HE0R06
HE0R05
HE0R04
HE0R03
HE0R02
HE0R01
HE0R00
W: HE0T07
HE0T06
HE0T05
HE0T04
HE0T03
HE0T02
HE0T01
HE0T00
$0031
USB HUB Endpoint 0 Data
Register 1 (HE0D1)
R: HE0R17
HE0R16
HE0R15
HE0R14
HE0R13
HE0R12
HE0R11
HE0R10
W: HE0T17
HE0T16
HE0T15
HE0T14
HE0T13
HE0T12
HE0T11
HE0T10
$0032
USB HUB Endpoint 0 Data
Register 2 (HE0D2)
R: HE0R27
HE0R26
HE0R25
HE0R24
HE0R23
HE0R22
HE0R21
HE0R20
W: HE0T27
HE0T26
HE0T25
HE0T24
HE0T23
HE0T22
HE0T21
HE0T20
$0033
USB HUB Endpoint 0 Data
Register 3 (HE0D3)
R: HE0R37
HE0R36
HE0R35
HE0R34
HE0R33
HE0R32
HE0R31
HE0R30
W: HE0T37
HE0T36
HE0T35
HE0T34
HE0T33
HE0T32
HE0T31
HE0T30
$0034
USB HUB Endpoint 0 Data
Register 4 (HE0D4)
R: HE0R47
HE0R46
HE0R45
HE0R44
HE0R43
HE0R42
HE0R41
HE0R40
W: HE0T47
HE0T46
HE0T45
HE0T44
HE0T43
HE0T42
HE0T41
HE0T40
$0035
USB HUB Endpoint 0 Data
Register 5 (HE0D5)
R: HE0R57
HE0R56
HE0R55
HE0R54
HE0R53
HE0R52
HE0R51
HE0R50
W: HE0T57
HE0T56
HE0T55
HE0T54
HE0T53
HE0T52
HE0T51
HE0T50
$0036
USB HUB Endpoint 0 Data
Register 6 (HE0D6)
R: HE0R67
HE0R66
HE0R65
HE0R64
HE0R63
HE0R62
HE0R61
HE0R60
W: HE0T67
HE0T66
HE0T65
HE0T64
HE0T63
HE0T62
HE0T61
HE0T60
$0037
USB HUB Endpoint 0 Data
Register 7 (HE0D7)
R: HE0R77
HE0R76
HE0R75
HE0R74
HE0R73
HE0R72
HE0R71
HE0R70
W: HE0T77
HE0T76
HE0T75
HE0T74
HE0T73
HE0T72
HE0T71
HE0T70
$0038
Unimplemented
R:
W:
$0039
Unimplemented
R:
W:
$003A
PLL Control Register
(PCTL)
R:
PLLIE
PLLF
PLLON
BCS
PRE1
PRE0
0
0
W:
$003B
PLL Bandwidth Control Register
(PBWC)
R:
AUTO
LOCK
ACQ
0
0
0
0
0
W:
$003C
PLL Multiplier Select Register High
(PMSH)
R:
MUL11
MUL10
MUL9
MUL8
W:
$003D
PLL Multiplier Select Register Low
(PMSL)
R:
MUL7
MUL6
MUL5
MUL4
MUL3
MUL2
MUL1
MUL0
W:
$003E
Unimplemented
R:
W:
$003F
PLL Reference Divider Select
Register (PRDS)
R:
RDS3
RDS2
RDS1
RDS0
W:
Addr.
Name
Bit 7
6
5
4
3
2
1
Bit 0
= Unimplemented
R
= Reserved
Figure 2-2. Control, Status, and Data Registers (Continued)
background image
Memory Map
Advance Information
MC68HC(7)08KH12
--
Rev. 1.0
40
Memory Map
MOTOROLA
$0040
Port F Keyboard Status and Control
Register (KBFSCR)
R:
0
0
0
0
KEYFF
0
IMASKF
MODEF
W:
ACKF
$0041
Port F Keyboard Interrupt Enable
Register (KBFIER)
R:
KBFIE7
KBFIE6
KBFIE5
KBFIE4
KBFIE3
KBFIE2
KBFIE1
KBFIE0
W:
$0042
Port F Pull-up Enable Register
(PFPER)
R:
PFPE7
PFPE6
PFPE5
PFPE4
PFPE3
PFPE2
PFPE1
PFPE0
W:
$0043
Unimplemented
R:
W:
$0044
Unimplemented
R:
W:
$0045
Unimplemented
R:
W:
$0046
Unimplemented
R:
W:
$0047
USB Embedded Device Control
Register 2 (DCR2)
R:
0
0
0
0
ENABLE2 ENABLE1 DSTALL2
DSTALL1
W:
$0048
USB Embedded Device Address
Register (DADDR)
R:
DEVEN
DADD6
DADD5
DADD4
DADD3
DADD2
DADD1
DADD0
W:
$0049
USB Embedded Device Interrupt
Register 0 (DIR0)
R: TXD0F
RXD0F
0
0
TXD0IE
RXD0IE
0
0
W:
TXD0FR RXD0FR
$004A
USB Embedded Device Interrupt
Register 1 (DIR1)
R: TXD1F
0
0
0
TXD1IE
0
0
0
W:
TXD1FR
$004B
USB Embedded Device Control
Register 0 (DCR0)
R:
T0SEQ
DSTALL0
TX0E
RX0E
TP0SIZ3 TP0SIZ2 TP0SIZ1 TP0SIZ0
W:
$004C
USB Embedded Device Control
Register 1 (DCR1)
R:
T1SEQ
ENDADD
TX1E
0
TP1SIZ3 TP1SIZ2 TP1SIZ1 TP1SIZ0
W:
$004D
USB Embedded Device Status
Register (DSR)
R: DRSEQ DSETUP DTX1ST
0
RP0SIZ3 RP0SIZ2 RP0SIZ1 RP0SIZ0
W:
DTX1STR
$004E
Unimplemented
R:
W:
$004F
Unimplemented
R:
W:
Addr.
Name
Bit 7
6
5
4
3
2
1
Bit 0
= Unimplemented
R
= Reserved
Figure 2-2. Control, Status, and Data Registers (Continued)
background image
Memory Map
I/O Section
MC68HC(7)08KH12
--
Rev. 1.0
Advance Information
MOTOROLA
Memory Map
41
$0050
Unimplemented
R:
W:
$0051
USB HUB Downstream Port 1
Control Register (HDP1CR)
R:
PEN1
LOWSP1
RST1
RESUM1
SUSP1
0
D1+
D1
W:
$0052
USB HUB Downstream Port 2
Control Register (HDP2CR)
R:
PEN2
LOWSP2
RST2
RESUM2
SUSP2
0
D2+
D2
W:
$0053
USB HUB Downstream Port 3
Control Register (HDP3CR)
R:
PEN3
LOWSP3
RST3
RESUM3
SUSP3
0
D3+
D3
W:
$0054
USB HUB Downstream Port 4
Control Register (HDP4CR)
R:
PEN4
LOWSP4
RST4
RESUM4
SUSP4
0
D4+
D4
W:
$0055
Unimplemented
R:
W:
$0056
USB SIE Timing Interrupt Register
(SIETIR)
R:
SOFF
EOF2F
EOPF
TRANF
SOFIE
EOF2IE
EOPIE
TRANIE
W:
$0057
USB SIE Timing Status Register
(SIETSR)
R:
RSTF
0
LOCKF
0
0
0
0
0
W:
RSTFR
LOCKFR
SOFFR
EOF2FR
EOPFR
TRANFR
$0058
USB HUB Address Register
(HADDR)
R:
USBEN
ADD6
ADD5
ADD4
ADD3
ADD2
ADD1
ADD0
W:
$0059
USB HUB Interrupt Register 0
(HIR0)
R:
TXDF
RXDF
0
0
TXDIE
RXDIE
0
0
W:
TXDFR
RXDFR
$005A
Unimplemented
R:
W:
$005B
USB HUB Control Register 0
(HCR0)
R:
TSEQ
STALL0
TXE
RXE
TPSIZ3
TPSIZ2
TPSIZ1
TPSIZ0
W:
$005C
USB HUB Endpoint1 Control &
Data Register (HCDR)
R:
STALL1
PNEW
PCHG5
PCHG4
PCHG3
PCHG2
PCHG1
PCHG0
W:
$005D
USB HUB Status Register (HSR)
R:
RSEQ
SETUP
TX1ST
0
RPSIZ3
RPSIZ2
RPSIZ1
RPSIZ0
W:
TX1STR
$005E
USB HUB Root Port Control
Register (HRPCR)
R:
0
0
0
RESUM0 SUSPND
0
D0+
D0
W:
$005F
Unimplemented
R:
W:
Addr.
Name
Bit 7
6
5
4
3
2
1
Bit 0
= Unimplemented
R
= Reserved
Figure 2-2. Control, Status, and Data Registers (Continued)
background image
Memory Map
Advance Information
MC68HC(7)08KH12
--
Rev. 1.0
42
Memory Map
MOTOROLA
$FE00
Break Status Register
(BSR)
R:
R
R
R
R
R
R
SBSW
R
W:
$FE01
Reset Status Register
(RSR)
R:
POR
PIN
COP
ILOP
ILAD
USB
0
0
W:
$FE02
Reserved
R:
W:
$FE03
Break Flag Control Register
(BFCR)
R:
BCFE
R
R
R
R
R
R
R
W:
$FE04
Interrupt Status Register 1 (INT1)
R:
IF6
IF5
IF4
IF3
IF2
IF1
0
0
W:
R
R
R
R
R
R
R
R
$FE05
Interrupt Status Register 2 (INT2)
R:
0
0
0
IF11
IF10
IF9
IF8
IF7
W:
R
R
R
R
R
R
R
R
$FE06
Reserved
R:
W:
$FE07
Reserved
R:
W:
$FE08
Unimplemented
R:
W:
$FE09
Unimplemented
R:
W:
$FE0A
Unimplemented
R:
W:
$FE0B
Unimplemented
R:
W:
$FE0C
Break Address Register High
(BRKH)
R:
Bit 15
14
13
12
11
10
9
Bit 8
W:
$FE0D
Break Address Register Low
(BRKL)
R:
Bit 7
6
5
4
3
2
1
Bit 0
W:
$FE0E
Break Status and Control Register
(BRKSCR)
R:
BRKE
BRKA
0
0
0
0
0
0
W:
$FF8D
Reserved
R:
W:
$FFFF
COP Control Register
(COPCTL)
R:
Low byte of reset vector
W:
Writing clears COP counter (any value)
Addr.
Name
Bit 7
6
5
4
3
2
1
Bit 0
= Unimplemented
R
= Reserved
Figure 2-2. Control, Status, and Data Registers (Continued)
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Memory Map
Monitor ROM
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Memory Map
43
Table 2-1
is a list of vector locations.
2.4 Monitor ROM
The 240 bytes at addresses $FE10$FEFF are reserved ROM
addresses that contain the instructions for the monitor functions.
(See
Section 10. Monitor ROM (MON)
.)
Table 2-1. Vector Addresses
Address
Vector
$FFE6
PLL Vector (High)
$FFE7
PLL Vector (Low)
$FFE8
Port-F Keyboard Vector (High)
$FFE9
Port-F Keyboard Vector (Low)
$FFEA
Port-D Keyboard Vector (High)
$FFEB
Port-D Keyboard Vector (Low)
$FFEC
Port-E Keyboard Vector (High)
$FFED
Port-E Keyboard Vector (Low)
$FFEE
TIM Overflow Vector (High)
$FFEF
TIM Overflow Vector (Low)
$FFF0
TIM Channel 1 Vector (High)
$FFF1
TIM Channel 1 Vector (Low)
$FFF2
TIM Channel 0 Vector (High)
$FFF3
TIM Channel 0 Vector (Low)
$FFF4
USB Device Endpoint Interrupt Vector (High)
$FFF5
USB Device Endpoint Interrupt Vector (Low)
$FFF6
USB HUB Endpoint Interrupt Vector (High)
$FFF7
USB HUB Endpoint Interrupt Vector (Low)
$FFF8
USB SIE Timing Interrupt Vector (High)
$FFF9
USB SIE Timing Interrupt Vector (Low)
$FFFA
IRQ1 Vector (High)
$FFFB
IRQ1 Vector (Low)
$FFFC
SWI Vector (High)
$FFFD
SWI Vector (Low)
$FFFE
Reset Vector (High)
$FFFF
Reset Vector (Low)
Priority
Lo
w
High
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Memory Map
MOTOROLA
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Random-Access Memory (RAM)
45
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Section 3. Random-Access Memory (RAM)
3.1 Contents
3.2
Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45
3.3
Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45
3.2 Introduction
This section describes the 384 bytes of RAM.
3.3 Functional Description
Addresses $0060 through $01DF are RAM locations. The location of the
stack RAM is programmable. The 16-bit stack pointer allows the stack to
be anywhere in the 64-Kbyte memory space.
NOTE:
For correct operation, the stack pointer must point only to RAM
locations.
Within page zero are 160 bytes of RAM. Because the location of the
stack RAM is programmable, all page zero RAM locations can be used
for I/O control and user data or code. When the stack pointer is moved
from its reset location at $00FF, direct addressing mode instructions can
access efficiently all page zero RAM locations. Page zero RAM,
therefore, provides ideal locations for frequently accessed global
variables.
Before processing an interrupt, the CPU uses five bytes of the stack to
save the contents of the CPU registers.
NOTE:
For M6805 compatibility, the H register is not stacked.
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Random-Access Memory (RAM)
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During a subroutine call, the CPU uses two bytes of the stack to store
the return address. The stack pointer decrements during pushes and
increments during pulls.
NOTE:
Be careful when using nested subroutines. The CPU may overwrite data
in the RAM during a subroutine or during the interrupt stacking
operation.
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Read-Only Memory (ROM)
47
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Section 4. Read-Only Memory (ROM)
4.1 Contents
4.2
Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47
4.3
Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47
4.2 Introduction
This section describes the 11,776 bytes of read-only memory (ROM)
and 26 bytes of user vectors, available on the MC68HC08KH12 device
(ROM part).
On the MC68HC708KH12 (OTP part), the ROM is replaced with 11,776
bytes One-Time Programmable (OTP) ROM. Programming tools are
available from Motorola. Contact your local Motorola representative for
more information.
4.3 Functional Description
These addresses are user ROM locations:
$D000 $FDFF
$FFE6 $FFFF (These locations are reserved for user-defined interrupt
and reset vectors.)
NOTE:
A secutiry feature prevents viewing of the ROM contents.
1
1. No security feature is absolutely secure. However, Motorola's strategy is to make reading or
copying the ROM contents difficult for unauthorized users.
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Read-Only Memory (ROM)
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Configuration Register (CONFIG)
49
Advance Information -- MC68HC(7)08KH12
Section 5. Configuration Register (CONFIG)
5.1 Contents
5.2
Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49
5.3
Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49
5.2 Introduction
This section describes the configuration register (CONFIG). The
configuration register enables or disables the following options:
Stop mode recovery time (32 CGMXCLK cycles or 4096
CGMXCLK cycles)
STOP instruction
Computer operating properly module (COP)
COP reset period (COPRS), (2
13
2
4
)
CGMXCLK or
(2
18
2
4
)
CGMXCLK
5.3 Functional Description
The configuration register is used in the initialization of various options.
The configuration register can be written once after each reset. All of the
configuration register bits are cleared during reset. Since the various
options affect the operation of the MCU it is recommended that this
register be written immediately after reset. The configuration register is
located at $001F. The configuration register may be read at anytime.
This configuration register exists on both the MC68HC708KH12
(OTP part) and MC68HC08KH12 (ROM part).
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Configuration Register (CONFIG)
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Configuration Register (CONFIG)
MOTOROLA
NOTE:
The CONFIG register is a special register containing one-time writable
latches after each reset. Upon a reset, the CONFIG register defaults to
the predetermined settings as shown in
Figure 5-1
.
SSREC -- Short stop recovery bit
SSREC enables the CPU to exit stop mode with a delay of 32
CGMXCLK cycles instead of a 4096 CGMXCLK cycle delay.
1 = Stop mode recovery after 32 CGMXCLK cycles
0 = Stop mode recovery after 4096 CGMXCLK cycles
NOTE:
Exiting stop mode by pulling reset will result in the long stop recovery.
If using an external crystal, do not set the SSREC bit.
COPRS -- COP reset period selection bit
1 = COP reset cycle is (2
13
2
4
)
CGMXCLK
0 = COP reset cycle is (2
18
2
4
)
CGMXCLK
STOP -- STOP instruction enable bit
STOP enables the STOP instruction.
1 = STOP instruction enabled
0 = STOP instruction treated as illegal opcode
COPD -- COP disable bit
COPD disables the COP module.
See Section 13. Computer
Operating Properly (COP)
.
1 = COP module disabled
0 = COP module enabled
Address:
$001F
Bit 7
6
5
4
3
2
1
Bit 0
Read:
0
0
0
0
SSREC
COPRS
STOP
COPD
Write:
Reset:
0
0
0
0
0
0
0
0
= Unimplemented
Figure 5-1. Configuration Register (CONFIG)
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Central Processor Unit (CPU)
51
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Section 6. Central Processor Unit (CPU)
6.1 Contents
6.2
Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51
6.3
Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52
6.4
CPU Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52
6.4.1
Accumulator (A). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53
6.4.2
Index Register (H:X) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54
6.4.3
Stack Pointer (SP). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55
6.4.4
Program Counter (PC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56
6.4.5
Condition Code Register (CCR) . . . . . . . . . . . . . . . . . . . . . 57
6.5
Arithmetic/Logic Unit (ALU) . . . . . . . . . . . . . . . . . . . . . . . . . . . 59
6.2 Introduction
This section describes the central processor unit. The M68HC08 CPU is
an enhanced and fully object-code-compatible version of the M68HC05
CPU. The
CPU08 Reference Manual (Motorola document number
CPU08RM/AD) contains a description of the CPU instruction set,
addressing modes, and architecture.
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Central Processor Unit (CPU)
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6.3 Features
Features of the CPU include the following:
Full Upward, Object-Code Compatibility with M68HC05 Family
16-Bit Stack Pointer with Stack Manipulation Instructions
16-Bit Index Register with X-Register Manipulation Instructions
8-MHz CPU Internal Bus Frequency
64-Kbyte Program/Data Memory Space
16 Addressing Modes
Memory-to-Memory Data Moves Without Using Accumulator
Fast 8-Bit by 8-Bit Multiply and 16-Bit by 8-Bit Divide Instructions
Enhanced Binary-Coded Decimal (BCD) Data Handling
Modular Architecture with Expandable Internal Bus Definition for
Extension of Addressing Range Beyond 64 Kbytes
Low-Power Stop and Wait Modes
6.4 CPU Registers
Figure 6-1
shows the five CPU registers. CPU registers are not part of
the memory map.
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CPU Registers
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Central Processor Unit (CPU)
53
Figure 6-1. CPU Registers
6.4.1 Accumulator (A)
The accumulator is a general-purpose 8-bit register. The CPU uses the
accumulator to hold operands and the results of arithmetic/logic
operations.
ACCUMULATOR (A)
INDEX REGISTER (H:X)
STACK POINTER (SP)
PROGRAM COUNTER (PC)
CONDITION CODE REGISTER (CCR)
CARRY/BORROW FLAG
ZERO FLAG
NEGATIVE FLAG
INTERRUPT MASK
HALF-CARRY FLAG
TWO'S COMPLEMENT OVERFLOW FLAG
V 1 1 H
I
N Z C
H
X
0
0
0
0
7
15
15
15
7
0
Bit 7
6
5
4
3
2
1
Bit 0
Read:
Write:
Reset:
Unaffected by reset
Figure 6-2. Accumulator (A)
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6.4.2 Index Register (H:X)
The 16-bit index register allows indexed addressing of a 64-Kbyte
memory space. H is the upper byte of the index register, and X is the
lower byte. H:X is the concatenated 16-bit index register.
In the indexed addressing modes, the CPU uses the contents of the
index register to determine the conditional address of the operand.
The index register can serve also as a temporary data storage location.
Bit
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
Bit
0
Read:
Write:
Reset:
0
0
0
0
0
0
0
0
X
X
X
X
X
X
X
X
X = Indeterminate
Figure 6-3. Index Register (H:X)
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55
6.4.3 Stack Pointer (SP)
The stack pointer is a 16-bit register that contains the address of the next
location on the stack. During a reset, the stack pointer is preset to
$00FF. The reset stack pointer (RSP) instruction also sets the least
significant byte to $FF but does not affect the most significant byte. The
stack pointer decrements as data is pushed onto the stack and
increments as data is pulled from the stack.
In the stack pointer 8-bit offset and 16-bit offset addressing modes, the
stack pointer can function as an index register to access data on the
stack. The CPU uses the contents of the stack pointer to determine the
conditional address of the operand.
NOTE:
The location of the stack is arbitrary and may be relocated anywhere in
RAM. Moving the SP out of page zero ($0000 to $00FF) frees direct
address (page zero) space. For correct operation, the stack pointer must
point only to RAM locations.
Bit
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
Bit
0
Read:
Write:
Reset:
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
Figure 6-4. Stack Pointer (SP)
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6.4.4 Program Counter (PC)
The program counter is a 16-bit register that contains the address of the
next instruction or operand to be fetched.
Normally, the program counter automatically increments to the next
sequential memory location every time an instruction or operand is
fetched. Jump, branch, and interrupt operations load the program
counter with an address other than that of the next sequential location.
During reset, the program counter is loaded with the reset vector
address located at $FFFE and $FFFF. The vector address is the
address of the first instruction to be executed after exiting the reset state.
Bit
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
Bit
0
Read:
Write:
Reset:
Loaded with vector from $FFFE and $FFFF
Figure 6-5. Program Counter (PC)
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6.4.5 Condition Code Register (CCR)
The 8-bit condition code register contains the interrupt mask and five
flags that indicate the results of the instruction just executed. Bits 6 and
5 are set permanently to logic one. The following paragraphs describe
the functions of the condition code register.
V -- Overflow Flag
The CPU sets the overflow flag when a two's complement overflow
occurs. The signed branch instructions BGT, BGE, BLE, and BLT use
the overflow flag.
1 = Overflow
0 = No overflow
H -- Half-Carry Flag
The CPU sets the half-carry flag when a carry occurs between
accumulator bits 3 and 4 during an ADD or ADC operation. The half-
carry flag is required for binary-coded decimal (BCD) arithmetic
operations. The DAA instruction uses the states of the H and C flags
to determine the appropriate correction factor.
1 = Carry between bits 3 and 4
0 = No carry between bits 3 and 4
Bit 7
6
5
4
3
2
1
Bit 0
Read:
V
1
1
H
I
N
Z
C
Write:
Reset:
X
1
1
X
1
X
X
X
X = Indeterminate
Figure 6-6. Condition Code Register (CCR)
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I -- Interrupt Mask
When the interrupt mask is set, all maskable CPU interrupts are
disabled. CPU interrupts are enabled when the interrupt mask is
cleared. When a CPU interrupt occurs, the interrupt mask is set
automatically after the CPU registers are saved on the stack, but
before the interrupt vector is fetched.
1 = Interrupts disabled
0 = Interrupts enabled
NOTE:
To maintain M6805 compatibility, the upper byte of the index register (H)
is not stacked automatically. If the interrupt service routine modifies H,
then the user must stack and unstack H using the PSHH and PULH
instructions.
After the I bit is cleared, the highest-priority interrupt request is
serviced first.
A return from interrupt (RTI) instruction pulls the CPU registers from
the stack and restores the interrupt mask from the stack. After any
reset, the interrupt mask is set and can only be cleared by the clear
interrupt mask software instruction (CLI).
N -- Negative flag
The CPU sets the negative flag when an arithmetic operation, logic
operation, or data manipulation produces a negative result, setting bit
7 of the result.
1 = Negative result
0 = Non-negative result
Z -- Zero flag
The CPU sets the zero flag when an arithmetic operation, logic
operation, or data manipulation produces a result of $00.
1 = Zero result
0 = Non-zero result
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Central Processor Unit (CPU)
59
C -- Carry/Borrow Flag
The CPU sets the carry/borrow flag when an addition operation
produces a carry out of bit 7 of the accumulator or when a subtraction
operation requires a borrow. Some instructions -- such as bit test and
branch, shift, and rotate -- also clear or set the carry/borrow flag.
1 = Carry out of bit 7
0 = No carry out of bit 7
6.5 Arithmetic/Logic Unit (ALU)
The ALU performs the arithmetic and logic operations defined by the
instruction set.
Refer to the
CPU08 Reference Manual (Motorola document number
CPU08RM/AD) for a description of the instructions and addressing
modes and more detail about CPU architecture.
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Central Processor Unit (CPU)
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System Integration Module (SIM)
61
Advance Information -- MC68HC(7)08KH12
Section 7. System Integration Module (SIM)
7.1 Contents
7.2
Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 62
7.3
SIM Bus Clock Control and Generation . . . . . . . . . . . . . . . . . . 65
7.3.1
Bus Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 65
7.3.2
Clock Start-Up from POR . . . . . . . . . . . . . . . . . . . . . . . . . . 66
7.3.3
Clocks in Stop Mode and Wait Mode . . . . . . . . . . . . . . . . . 66
7.4
Reset and System Initialization. . . . . . . . . . . . . . . . . . . . . . . . . 66
7.4.1
External Pin Reset. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 67
7.4.2
Active Resets from Internal Sources . . . . . . . . . . . . . . . . . . 67
7.4.2.1
Power-On Reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 68
7.4.2.2
Computer Operating Properly (COP) Reset . . . . . . . . . . 69
7.4.2.3
Illegal Opcode Reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . 70
7.4.2.4
Illegal Address Reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . 70
7.4.2.5
Universal Serial Bus Reset . . . . . . . . . . . . . . . . . . . . . . . 70
7.5
SIM Counter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 71
7.5.1
SIM Counter During Power-On Reset . . . . . . . . . . . . . . . . . 71
7.5.2
SIM Counter During Stop Mode Recovery . . . . . . . . . . . . . 71
7.5.3
SIM Counter and Reset States . . . . . . . . . . . . . . . . . . . . . . 71
7.6
Exception Control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 72
7.6.1
Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 72
7.6.1.1
Hardware Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 74
7.6.1.2
SWI Instruction. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 76
7.6.2
Interrupt Status Registers . . . . . . . . . . . . . . . . . . . . . . . . . . 76
7.6.2.1
Interrupt Status Register 1 . . . . . . . . . . . . . . . . . . . . . . . . 77
7.6.2.2
Interrupt Status Register 2 . . . . . . . . . . . . . . . . . . . . . . . . 78
7.6.2.3
Interrupt Status Register 3 . . . . . . . . . . . . . . . . . . . . . . . . 78
7.6.3
Reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 79
7.6.4
Break Interrupts. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 79
7.6.5
Status Flag Protection in Break Mode. . . . . . . . . . . . . . . . . 79
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7.7
Low-Power Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 79
7.7.1
Wait Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 80
7.7.2
Stop Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 81
7.8
SIM Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 83
7.8.1
Break Status Register (BSR). . . . . . . . . . . . . . . . . . . . . . . . 83
7.8.2
Reset Status Register (RSR) . . . . . . . . . . . . . . . . . . . . . . . 84
7.8.3
Break Flag Control Register (BFCR). . . . . . . . . . . . . . . . . . 85
7.2 Introduction
This section describes the system integration module (SIM), which
supports up to 24 external and/or internal interrupts. Together with the
CPU, the SIM controls all MCU activities. A block diagram of the SIM is
shown in
Figure 7-1
.
Figure 7-2
is a summary of the SIM I/O registers.
The SIM is a system state controller that coordinates CPU and exception
timing. The SIM is responsible for:
Bus clock generation and control for CPU and peripherals
top/wait/reset/break entry and recovery
Internal clock control
Master reset control, including power-on reset (POR) and COP
timeout
Interrupt control:
Acknowledge timing
Arbitration control timing
Vector address generation
CPU enable/disable timing
Modular architecture expandable to 128 interrupt sources
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Figure 7-1. SIM Block Diagram
STOP/WAIT
CLOCK
CONTROL
CLOCK GENERATORS
POR CONTROL
RESET PIN CONTROL
SIM RESET STATUS REGISTER
INTERRUPT CONTROL
AND PRIORITY DECODE
MODULE STOP
MODULE WAIT
CPU STOP (FROM CPU)
CPU WAIT (FROM CPU)
SIMOSCEN (TO CGM)
CGMOUT (FROM CGM)
INTERNAL CLOCKS
MASTER
RESET
CONTROL
RESET
PIN LOGIC
ILLEGAL OPCODE (FROM CPU)
ILLEGAL ADDRESS (FROM ADDRESS
MAP DECODERS)
COP TIMEOUT (FROM COP MODULE)
INTERRUPT SOURCES
CPU INTERFACE
RESET
CONTROL
SIM
COUNTER
COP CLOCK
CGMXCLK (FROM CGM)
2
USB RESET (FROM USB MODULE)
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Addr.
Register Name
Bit 7
6
5
4
3
2
1
Bit 0
$FE00
Break Status Register
(BSR)
Read:
R
R
R
R
R
R
SBSW
R
Write:
Reset:
0
$FE01
Reset Status Register
(RSR)
Read:
POR
PIN
COP
ILOP
ILAD
USB
0
0
Write:
Reset:
1
0
0
0
0
0
0
0
$FE03
Break Flag Control Register
(BFCR)
Read:
BCFE
R
R
R
R
R
R
R
Write:
Reset:
0
$FE04
Interrupt Status Register 1
(INT1)
Read:
IF6
IF5
IF4
IF3
IF2
IF1
0
0
Write:
R
R
R
R
R
R
R
R
Reset:
0
0
0
0
0
0
0
0
$FE05
Interrupt Status Register 2
(INT2)
Read:
0
0
0
IF11
IF10
IF9
IF8
IF7
Write:
R
R
R
R
R
R
R
R
Reset:
0
0
0
0
0
0
0
0
$FE06
Interrupt Status Register 3
(INT3)
Read:
0
0
0
0
0
0
0
0
Write:
R
R
R
R
R
R
R
R
Reset:
0
0
0
0
0
0
0
0
= Unimplemented
R
= Reserved for factory test
Figure 7-2. SIM I/O Register Summary
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Table 7-1
shows the internal signal names used in this section.
7.3 SIM Bus Clock Control and Generation
The bus clock generator provides system clock signals for the CPU and
peripherals on the MCU. The system clocks are generated from an
incoming clock, CGMOUT, as shown in
Figure 7-3
.
Figure 7-3. SIM Clock Signals
7.3.1 Bus Timing
In user mode, the internal bus frequency is the oscillator frequency
(CGMXCLK) divided by four.
Table 7-1. Signal Name Conventions
Signal Name
Description
CGMXCLK
Buffered OSC1 from the oscillator
CGMOUT
The CGMXCLK frequency divided by two. This signal is again
divided by two in the SIM to generate the internal bus clocks
(Bus clock = CGMXCLK divided by four)
IAB
Internal address bus
IDB
Internal data bus
PORRST
Signal from the power-on reset module to the SIM
IRST
Internal reset signal
R/W
Read/write signal
2
BUS CLOCK
GENERATORS
SIM
SIM COUNTER
From
PLL/OSCILLATOR
From
PLL/OSCILLATOR
CGMOUT
CGMXCLK
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7.3.2 Clock Start-Up from POR
When the power-on reset module generates a reset, the clocks to the
CPU and peripherals are inactive and held in an inactive phase until after
the 4096 CGMXCLK cycle POR timeout has completed. The RST pin is
driven low by the SIM during this entire period. The IBUS clocks start
upon completion of the timeout.
7.3.3 Clocks in Stop Mode and Wait Mode
Upon exit from stop mode by an interrupt, break, or reset, the SIM allows
CGMXCLK to clock the SIM counter. The CPU and peripheral clocks do
not become active until after the stop delay timeout. This timeout is
selectable as 4096 or 32 CGMXCLK cycles.
(See 7.7.2 Stop Mode
.)
In wait mode, the CPU clocks are inactive. The SIM also produces two
sets of clocks for other modules. Refer to the wait mode subsection of
each module to see if the module is active or inactive in wait mode.
Some modules can be programmed to be active in wait mode.
7.4 Reset and System Initialization
The MCU has these reset sources:
Power-on reset module (POR)
External reset pin (RST)
Computer operating properly module (COP)
Illegal opcode
Illegal address
Universal Serial Bus module (USB)
All of these resets produce the vector $FFFEFFFF ($FEFEFEFF in
monitor mode) and assert the internal reset signal (IRST). IRST causes
all registers to be returned to their default values and all modules to be
returned to their reset states.
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An internal reset clears the SIM counter
(see 7.5 SIM Counter
), but an
external reset does not. Each of the resets sets a corresponding bit in
the reset status register (RSR).
(See 7.8 SIM Registers
.)
7.4.1 External Pin Reset
The RST pin circuits include an internal pullup device. Pulling the
asynchronous RST pin low halts all processing. The PIN bit of the reset
status register (RSR) is set as long as RST is held low for a minimum of
67 CGMXCLK cycles, assuming that the POR was not the source of the
reset. See
Table 7-2
for details.
Figure 7-4
shows the relative timing.
Figure 7-4. External Reset Timing
7.4.2 Active Resets from Internal Sources
All internal reset sources actively pull the RST pin low for 32 CGMXCLK
cycles to allow resetting of external peripherals. The internal reset signal
IRST continues to be asserted for an additional 32 cycles.
See Figure 7-
5
. An internal reset can be caused by an illegal address, illegal opcode,
COP timeout, or POR.
(See Figure 7-6. Sources of Internal Reset
.)
Note that for POR resets, the SIM cycles through 4096 CGMXCLK
cycles during which the SIM forces the RST pin low. The internal reset
signal then follows the sequence from the falling edge of RST shown in
Figure 7-5
.
Table 7-2. PIN Bit Set Timing
Reset Type
Number of Cycles Required to Set PIN
POR
4163 (4096 + 64 + 3)
All others
67 (64 + 3)
RST
IAB
PC
VECT H
VECT L
CGMOUT
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Figure 7-5. Internal Reset Timing
The COP reset is asynchronous to the bus clock.
Figure 7-6. Sources of Internal Reset
The active reset feature allows the part to issue a reset to peripherals
and other chips within a system built around the MCU.
7.4.2.1 Power-On Reset
When power is first applied to the MCU, the power-on reset module
(POR) generates a pulse to indicate that power-on has occurred. The
external reset pin (RST) is held low while the SIM counter counts out
4096 CGMXCLK cycles. Sixty-four CGMXCLK cycles later, the CPU and
memories are released from reset to allow the reset vector sequence to
occur. At power-on, the following events occur:
A POR pulse is generated.
The internal reset signal is asserted.
The SIM enables the oscillator to drive CGMXCLK.
Internal clocks to the CPU and modules are held inactive for 4096
CGMXCLK cycles to allow stabilization of the oscillator.
The RST pin is driven low during the oscillator stabilization time.
The POR bit of the reset status register (RSR) is set and all other
bits in the register are cleared.
IRST
RST
RST PULLED LOW BY MCU
IAB
32 CYCLES
32 CYCLES
VECTOR HIGH
CGMXCLK
ILLEGAL ADDRESS RST
ILLEGAL OPCODE RST
COPRST
POR
INTERNAL RESET
USB
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Figure 7-7. POR Recovery
7.4.2.2 Computer Operating Properly (COP) Reset
An input to the SIM is reserved for the COP reset signal. The overflow of
the COP counter causes an internal reset and sets the COP bit in the
reset status register (RSR). The SIM actively pulls down the RST pin for
all internal reset sources.
To prevent a COP module timeout, write any value to location $FFFF.
Writing to location $FFFF clears the COP counter and stages 12 through
5 of the SIM counter. The SIM counter output, which occurs at least
every 2
12
2
4
CGMXCLK cycles, drives the COP counter. The COP
should be serviced as soon as possible out of reset to guarantee the
maximum amount of time before the first timeout.
The COP module is disabled if the RST pin or the IRQ1/V
PP
pin is held
at V
DD
+ V
HI
while the MCU is in monitor mode. The COP module can
be disabled only through combinational logic conditioned with the high
voltage signal on the RST or the IRQ1/V
PP
pin. This prevents the COP
from becoming disabled as a result of external noise. During a break
state, V
DD
+ V
HI
on the RST pin disables the COP module.
PORRST
OSC1
CGMXCLK
CGMOUT
RST
IAB
4096
CYCLES
32
CYCLES
32
CYCLES
$FFFE
$FFFF
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7.4.2.3 Illegal Opcode Reset
The SIM decodes signals from the CPU to detect illegal instructions. An
illegal instruction sets the ILOP bit in the reset status register (RSR) and
causes a reset.
If the stop enable bit, STOP, in the mask option register is logic zero, the
SIM treats the STOP instruction as an illegal opcode and causes an
illegal opcode reset. The SIM actively pulls down the RST pin for all
internal reset sources.
7.4.2.4 Illegal Address Reset
An opcode fetch from an unmapped address generates an illegal
address reset. The SIM verifies that the CPU is fetching an opcode prior
to asserting the ILAD bit in the reset status register (RSR) and resetting
the MCU. A data fetch from an unmapped address does not generate a
reset. The SIM actively pulls down the RST pin for all internal reset
sources.
7.4.2.5 Universal Serial Bus Reset
The USB module will detect a reset signal on the bus by the presence of
an extended SE0 at the USB data pins of the upstream port. The reset
signaling is specified to be present for a minimum of 10 ms. An active
device (powered and not in the suspend state) seeing a single-ended
zero on its USB data inputs for more than 2.5
s may treat that signal as
a reset, but must have interpreted the signaling as a reset within 5.5
s.
For USB device, an SE0 condition between 4 and 8 low speed bit times
or 32 and 64 high speed bit times represents a valid USB reset. After the
reset is removed, the device will be in the attached, but not yet
addressed or configured state (refer to Section 9.1 of the USB
specification). The device must be able to accept device address via a
SET_ADDRESS command (refer to section 9.4 of the USB specification)
no later than 10 ms after the reset is removed.
Reset can wake a device from the suspended mode. A device may take
up to 10 ms to wake up from the suspended state.
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7.5 SIM Counter
The SIM counter is used by the power-on reset module (POR) and in
stop mode recovery to allow the oscillator time to stabilize before
enabling the internal bus (IBUS) clocks. The SIM counter also serves as
a prescalar for the computer operating properly module (COP). The SIM
counter uses 12 stages for counting, followed by a 13th stage that
triggers a reset of SIM counters and supplies the clock for the COP
module. The SIM counter is clocked by the falling edge of CGMXCLK.
7.5.1 SIM Counter During Power-On Reset
The power-on reset module (POR) detects power applied to the MCU.
At power-on, the POR circuit asserts the signal PORRST. Once the SIM
is initialized, it enables the oscillator to drive the bus clock state machine.
7.5.2 SIM Counter During Stop Mode Recovery
The SIM counter also is used for stop mode recovery. The STOP
instruction clears the SIM counter. After an interrupt, break, or reset, the
SIM senses the state of the short stop recovery bit, SSREC, in the mask
option register. If the SSREC bit is a logic one, then the stop recovery is
reduced from the normal delay of 4096 CGMXCLK cycles down to 32
CGMXCLK cycles. This is ideal for applications using canned oscillators
that do not require long start-up times from stop mode. External crystal
applications should use the full stop recovery time, that is, with SSREC
cleared in the configuration register (CONFIG).
7.5.3 SIM Counter and Reset States
External reset has no effect on the SIM counter. (
See 7.7.2 Stop Mode
for details.) The SIM counter is free-running after all reset states. (
See
7.4.2 Active Resets from Internal Sources
for counter control and
internal reset recovery sequences.)
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7.6 Exception Control
Normal, sequential program execution can be changed in three different
ways:
Interrupts
Maskable hardware CPU interrupts
Non-maskable software interrupt instruction (SWI)
Reset
Break interrupts
7.6.1 Interrupts
An interrupt temporarily changes the sequence of program execution to
respond to a particular event.
Figure 7-8
flow charts the handling of
system interrupts.
Interrupts are latched, and arbitration is performed in the SIM at the start
of interrupt processing. The arbitration result is a constant that the CPU
uses to determine which vector to fetch. Once an interrupt is latched by
the SIM, no other interrupt can take precedence, regardless of priority,
until the latched interrupt is serviced (or the I bit is cleared).
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Figure 7-8. Interrupt Processing
NO
NO
NO
YES
NO
NO
YES
NO
YES
YES
FROM RESET
BREAK
I BIT SET?
IRQ1
INTERRUPT?
USB
INTERRUPT?
FETCH NEXT
INSTRUCTION
UNSTACK CPU REGISTERS.
STACK CPU REGISTERS
SET I BIT
LOAD PC WITH INTERRUPT VECTOR
EXECUTE INSTRUCTION.
YES
YES
I BIT SET?
INTERRUPT?
YES
OTHER
INTERRUPTS?
NO
SWI
INSTRUCITON?
RTI
INSTRUCITON?
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At the beginning of an interrupt, the CPU saves the CPU register
contents on the stack and sets the interrupt mask (I bit) to prevent
additional interrupts. At the end of an interrupt, the RTI instruction
recovers the CPU register contents from the stack so that normal
processing can resume.
Figure 7-9
shows interrupt entry timing.
Figure
7-10
shows interrupt recovery timing.
Figure 7-9
.
Interrupt Entry
Figure 7-10. Interrupt Recovery
7.6.1.1 Hardware Interrupts
A hardware interrupt does not stop the current instruction. Processing of
a hardware interrupt begins after completion of the current instruction.
When the current instruction is complete, the SIM checks all pending
hardware interrupts. If interrupts are not masked (I bit clear in the
condition code register), and if the corresponding interrupt enable bit is
MODULE
IDB
R/W
INTERRUPT
DUMMY
SP
SP 1
SP 2
SP 3
SP 4
VECT H
VECT L
START ADDR
IAB
DUMMY
PC 1[7:0] PC 1[15:8]
X
A
CCR
V DATA H
V DATA L
OPCODE
I BIT
MODULE
IDB
R/W
INTERRUPT
SP 4
SP 3
SP 2
SP 1
SP
PC
PC + 1
IAB
CCR
A
X
PC 1[7:0] PC 1[15:8] OPCODE
OPERAND
I BIT
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set, the SIM proceeds with interrupt processing; otherwise, the next
instruction is fetched and executed.
If more than one interrupt is pending at the end of an instruction
execution, the highest priority interrupt is serviced first.
Figure 7-11
demonstrates what happens when two interrupts are pending. If an
interrupt is pending upon exit from the original interrupt service routine,
the pending interrupt is serviced before the LDA instruction is executed.
Figure 7-11
.
Interrupt Recognition Example
The LDA opcode is prefetched by both the INT1 and INT2 RTI
instructions. However, in the case of the INT1 RTI prefetch, this is a
redundant operation.
NOTE:
To maintain compatibility with the M6805 Family, the H register is not
pushed on the stack during interrupt entry. If the interrupt service routine
modifies the H register or uses the indexed addressing mode, software
should save the H register and then restore it prior to exiting the routine.
CLI
LDA
INT1
PULH
RTI
INT2
BACKGROUND ROUTINE
#$FF
PSHH
INT1 INTERRUPT SERVICE ROUTINE
PULH
RTI
PSHH
INT2 INTERRUPT SERVICE ROUTINE
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7.6.1.2 SWI Instruction
The SWI instruction is a non-maskable instruction that causes an
interrupt regardless of the state of the interrupt mask (I bit) in the
condition code register.
NOTE:
A software interrupt pushes PC onto the stack. A software interrupt does
not push PC 1, as a hardware interrupt does.
7.6.2 Interrupt Status Registers
The flags in the interrupt status registers identify maskable interrupt
sources.
Table 7-3
summarizes the interrupt sources and the interrupt
status register flags that they set. The interrupt status registers can be
useful for debugging.
Table 7-3. Interrupt Sources
Source
Flag
Mask
(1)
INT
Register
Flag
Priority
(2)
Vector Address
SWI Instruction
--
0
$FFFC$FFFD
IRQ1 Pin
IRQF1
IMASK1
IF1
1
$FFFA$FFFB
HUB Start of Frame Interrupt
SOFF
SOFIE
IF2
2
$FFF8$FFF9
HUB 2nd End of Frame Point Interrupt
EOF2F
EOF2IE
HUB End of Packet Interrupt
EOPF
EOPIE
HUB Bus Signal Transition Detect Interrupt
TRANF
TRANIE
HUB Endpoint0 Transmit Interrupt
TXDF
TXDIE
IF3
3
$FFF6$FFF7
HUB Endpoint0 Receive Interrupt
RXDF
RXDIE
Device Endpoint 0 Transmit Interrupt
TXD0F
TXD0IE
IF4
4
$FFF4$FFF5
Device Endpoint 0 Receive Interrupt
RXD0F
RXD0IE
USB Endpoint1/2 Transmit Interrupt
TXD1F
TXD1IE
TIM Channel 0
CH0F
CH0IE
IF5
5
$FFF2$FFF3
TIM Channel 1
CH1F
CH1IE
IF6
6
$FFF0$FFF1
TIM Overflow
TOF
TOIE
IF7
7
$FFEE$FFEF
Port-E Keyboard Pin Interrupt
KEYEF
IMASKE
IF8
8
$FFEC$FFED
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7.6.2.1 Interrupt Status Register 1
I
F
6I
F
1 -- Interrupt Flags 16
These flags indicate the presence of interrupt requests from the
sources shown in
Table 7-3
.
1 = Interrupt request present
0 = No interrupt request present
Bit 0 and Bit 1 -- Always read 0
Port-D Keyboard Pin Interrupt
KEYDF
IMASKD
IF9
9
$FFEA$FFEB
Port-F Keyboard Pin Interrupt
KEYFF
IMASKF
IF10
10
$FFE8$FFE9
Phase-locked Loop Interrupt
PLLF
PLLIE
IF11
11
$FFE6$FFE7
(1) The I bit in the condition code register is a global mask for all interrupts sources except the SWI instruction.
(2) 0= highest priority
Table 7-3. Interrupt Sources
Source
Flag
Mask
(1)
INT
Register
Flag
Priority
(2)
Vector Address
Address:
$FE04
Bit 7
6
5
4
3
2
1
Bit 0
Read:
IF6
IF5
IF4
IF3
IF2
IF1
0
0
Write:
R
R
R
R
R
R
R
R
Reset:
0
0
0
0
0
0
0
0
R
= Reserved
Figure 7-12. Interrupt Status Register 1 (INT1)
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7.6.2.2 Interrupt Status Register 2
I
F
11I
F
7 -- Interrupt Flags 117
These flags indicate the presence of interrupt requests from the
sources shown in
Table 7-3
.
1 = Interrupt request present
0 = No interrupt request present
7.6.2.3 Interrupt Status Register 3
Bits 70 -- Always read 0
Address:
$FE05
Bit 7
6
5
4
3
2
1
Bit 0
Read:
0
0
0
IF11
IF10
IF9
IF8
IF7
Write:
R
R
R
R
R
R
R
R
Reset:
0
0
0
0
0
0
0
0
R
= Reserved
Figure 7-13. Interrupt Status Register 2 (INT2)
Address:
$FE06
Bit 7
6
5
4
3
2
1
Bit 0
Read:
0
0
0
0
0
0
0
0
Write:
R
R
R
R
R
R
R
R
Reset:
0
0
0
0
0
0
0
0
R
= Reserved
Figure 7-14. Interrupt Status Register 2 (INT2)
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7.6.3 Reset
All reset sources always have equal and highest priority and cannot be
arbitrated.
7.6.4 Break Interrupts
The break module can stop normal program flow at a software-
programmable break point by asserting its break interrupt output.
(See
Section 16. Break Module (BREAK)
.) The SIM puts the CPU into the
break state by forcing it to the SWI vector location. Refer to the break
interrupt subsection of each module to see how each module is affected
by the break state.
7.6.5 Status Flag Protection in Break Mode
The SIM controls whether status flags contained in other modules can
be cleared during break mode. The user can select whether flags are
protected from being cleared by properly initializing the break clear flag
enable bit (BCFE) in the break flag control register (BFCR).
Protecting flags in break mode ensures that set flags will not be cleared
while in break mode. This protection allows registers to be freely read
and written during break mode without losing status flag information.
Setting the BCFE bit enables the clearing mechanisms. Once cleared in
break mode, a flag remains cleared even when break mode is exited.
Status flags with a two-step clearing mechanism -- for example, a read
of one register followed by the read or write of another -- are protected,
even when the first step is accomplished prior to entering break mode.
Upon leaving break mode, execution of the second step will clear the
flag as normal.
7.7 Low-Power Modes
Executing the WAIT or STOP instruction puts the MCU in a low-power-
consumption mode for standby situations. The SIM holds the CPU in a
non-clocked state. The operation of each of these modes is described
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below. Both STOP and WAIT clear the interrupt mask (I) in the condition
code register, allowing interrupts to occur.
7.7.1 Wait Mode
In wait mode, the CPU clocks are inactive while the peripheral clocks
continue to run.
Figure 7-15
shows the timing for wait mode entry.
A module that is active during wait mode can wake up the CPU with an
interrupt if the interrupt is enabled. Stacking for the interrupt begins one
cycle after the WAIT instruction during which the interrupt occurred. In
wait mode, the CPU clocks are inactive. Refer to the wait mode
subsection of each module to see if the module is active or inactive in
wait mode. Some modules can be programmed to be active in wait
mode.
Wait mode can also be exited by a reset or break. A break interrupt
during wait mode sets the SIM break stop/wait bit, SBSW, in the break
status register (BSR). If the COP disable bit, COPD, in the mask option
register is logic zero, then the computer operating properly module
(COP) is enabled and remains active in wait mode.
Figure 7-15. Wait Mode Entry Timing
Figure 7-16
and
Figure 7-17
show the timing for WAIT recovery.
WAIT ADDR + 1
SAME
SAME
IAB
IDB
PREVIOUS DATA
NEXT OPCODE
SAME
WAIT ADDR
SAME
R/W
NOTE: Previous data can be operand data or the WAIT opcode, depending on the
last instruction.
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Figure 7-16. Wait Recovery from Interrupt or Break
Figure 7-17. Wait Recovery from Internal Reset
7.7.2 Stop Mode
In stop mode, the SIM counter is reset and the system clocks are
disabled. An interrupt request from a module can cause an exit from stop
mode. Stacking for interrupts begins after the selected stop recovery
time has elapsed. Reset or break also causes an exit from stop mode.
The SIM disables the oscillator signals (CGMOUT and CGMXCLK) in
stop mode, stopping the CPU and peripherals. Stop recovery time is
selectable using the SSREC bit in the configuration register (CONFIG).
If SSREC is set, stop recovery is reduced from the normal delay of 4096
CGMXCLK cycles down to 32. This is ideal for applications using canned
oscillators that do not require long startup times from stop mode.
NOTE:
External crystal applications should use the full stop recovery time by
clearing the SSREC bit.
$6E0C
$6E0B
$00FF
$00FE
$00FD
$00FC
$A6
$A6
$01
$0B
$6E
$A6
IAB
IDB
EXITSTOPWAIT
NOTE: EXITSTOPWAIT = RST pin OR CPU interrupt OR break interrupt
IAB
IDB
RST
$A6
$A6
$6E0B
RST V CT H RST V CT L
$A6
CGMXCLKCGMXCLK
32
Cycles
32
Cycles
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A break interrupt during stop mode sets the SIM break stop/wait bit
(SBSW) in the break status register (BSR).
The SIM counter is held in reset from the execution of the STOP
instruction until the beginning of stop recovery. It is then used to time the
recovery period.
Figure 7-18
shows stop mode entry timing.
NOTE:
To minimize stop current, all pins configured as inputs should be driven
to a logic 1 or logic 0.
Figure 7-18. Stop Mode Entry Timing
Figure 7-19. Stop Mode Recovery from Interrupt or Break
STOP ADDR + 1
SAME
SAME
IAB
IDB
PREVIOUS DATA
NEXT OPCODE
SAME
STOP ADDR
SAME
R/W
CPUSTOP
NOTE: Previous data can be operand data or the STOP opcode, depending on the last
instruction.
CGMXCLK
INT/BREAK
IAB
STOP + 2
STOP + 2
SP
SP 1
SP 2
SP 3
STOP +1
STOP RECOVERY PERIOD
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7.8 SIM Registers
The SIM has three memory mapped registers.
Table 7-4
shows the
mapping of these registers.
7.8.1 Break Status Register (BSR)
The break status register contains a flag to indicate that a break caused
an exit from stop or wait mode.
SBSW -- SIM Break Stop/Wait
This status bit is useful in applications requiring a return to wait
or stop mode after exiting from a break interrupt. Clear SBSW
by writing a logic zero to it. Reset clears SBSW.
1 = Stop mode or wait mode was exited by break interrupt
0 = Stop mode or wait mode was not exited by break
interrupt
SBSW can be read within the break state SWI routine. The user can
modify the return address on the stack by subtracting one from it. The
following code is an example of this. Writing zero to the SBSW bit clears
it.
Table 7-4. SIM Registers
Address
Register
Access Mode
$FE00
BSR
User
$FE01
RSR
User
$FE03
BFCR
User
Address:
$FE00
Bit 7
6
5
4
3
2
1
Bit 0
Read:
R
R
R
R
R
R
SBSW
R
Write:
Note 1
Reset:
0
R
= Reserved
1. Writing a logic zero clears SBSW
Figure 7-20. Break Status Register (BSR)
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7.8.2 Reset Status Register (RSR)
This register contains six flags that show the source of the last reset.
Clear the SIM reset status register by reading it. A power-on reset sets
the POR bit and clears all other bits in the register.
;
;
;
This code works if the H register has been pushed onto the stack in the break
service routine software. This code should be executed at the end of the
break service routine software.
HIBYTE
EQU
5
LOBYTE
EQU
6
;
If not SBSW, do RTI
BRCLR
SBSW,BSR, RETURN
;
;
See if wait mode or stop mode was exited
by break
TST
LOBYTE,SP
; If RETURNLO is not zero,
BNE
DOLO
; then just decrement low byte.
DEC
HIBYTE,SP
; Else deal with high byte, too.
DOLO
DEC
LOBYTE,SP
; Point to WAIT/STOP opcode.
RETURN
PULH
RTI
; Restore H register.
Address:
$FE01
Bit 7
6
5
4
3
2
1
Bit 0
Read:
POR
PIN
COP
ILOP
ILAD
USB
0
0
Write:
POR:
1
0
0
0
0
0
0
0
= Unimplemented
Figure 7-21. Reset Status Register (RSR)
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POR -- Power-On Reset Bit
1 = Last reset caused by POR circuit
0 = Read of RSR
PIN -- External Reset Bit
1 = Last reset caused by external reset pin (RST)
0 = POR or read of RSR
COP -- Computer Operating Properly Reset Bit
1 = Last reset caused by COP counter
0 = POR or read of RSR
ILOP -- Illegal Opcode Reset Bit
1 = Last reset caused by an illegal opcode
0 = POR or read of RSR
ILAD -- Illegal Address Reset Bit (opcode fetches only)
1 = Last reset caused by an opcode fetch from an illegal
address
0 = POR or read of RSR
USB --Universal Serial Bus Reset Bit
1 = Last reset caused by an USB module
0 = POR or read of RSR
7.8.3 Break Flag Control Register (BFCR)
The break control register contains a bit that enables software to clear
status bits while the MCU is in a break state.
Address:
$FE03
Bit 7
6
5
4
3
2
1
Bit 0
Read:
BCFE
R
R
R
R
R
R
R
Write:
Reset:
0
0
0
0
0
0
0
0
R
= Reserved
Figure 7-22. Break Flag Control Register (BFCR)
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BCFE -- Break Clear Flag Enable Bit
This read/write bit enables software to clear status bits by
accessing status registers while the MCU is in a break state.
To clear status bits during the break state, the BCFE bit must
be set.
1 = Status bits clearable during break
0 = Status bits not clearable during break
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Section 8. Clock Generator Module (CGM)
8.1 Contents
8.2
Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 88
8.3
Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 89
8.4
Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 89
8.4.1
Crystal Oscillator Circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . 91
8.4.2
Phase-Locked Loop Circuit (PLL) . . . . . . . . . . . . . . . . . . . . 91
8.4.3
PLL Circuits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 91
8.4.4
Acquisition and Tracking Modes . . . . . . . . . . . . . . . . . . . . . 93
8.4.5
Manual and Automatic PLL Bandwidth Modes . . . . . . . . . . 93
8.4.6
Programming the PLL . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 94
8.4.7
Special Programming Exceptions . . . . . . . . . . . . . . . . . . . . 95
8.4.8
Base Clock Selector Circuit. . . . . . . . . . . . . . . . . . . . . . . . . 96
8.4.9
CGM External Connections. . . . . . . . . . . . . . . . . . . . . . . . . 96
8.5
I/O Signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 98
8.5.1
Crystal Amplifier Input Pin (OSC1) . . . . . . . . . . . . . . . . . . . 98
8.5.2
Crystal Amplifier Output Pin (OSC2) . . . . . . . . . . . . . . . . . . 98
8.5.3
External Filter Capacitor Pin (CGMXFC). . . . . . . . . . . . . . . 98
8.5.4
PLL Analog Power Pin (V
DDA
) . . . . . . . . . . . . . . . . . . . . . . 98
8.5.5
PLL Analog Ground Pin (V
SSA
) . . . . . . . . . . . . . . . . . . . . . . 98
8.5.6
Buffered Crystal Clock Output (CGMVOUT) . . . . . . . . . . . . 99
8.5.7
CGMVSEL. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 99
8.5.8
Oscillator Enable Signal (SIMOSCEN) . . . . . . . . . . . . . . . . 99
8.5.9
Crystal Output Frequency Signal (CGMXCLK) . . . . . . . . . . 99
8.5.10
CGM Base Clock Output (CGMOUT) . . . . . . . . . . . . . . . . . 99
8.5.11
CGM CPU Interrupt (CGMINT) . . . . . . . . . . . . . . . . . . . . . . 99
8.6
CGM Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 100
8.6.1
PLL Control Register (PCTL) . . . . . . . . . . . . . . . . . . . . . . 102
8.6.2
PLL Bandwidth Control Register (PBWC) . . . . . . . . . . . . . 104
8.6.3
PLL Multiplier Select Registers (PMSH:PMSL). . . . . . . . . 105
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8.6.4
PLL Reference Divider Select Register (PRDS) . . . . . . . . 106
8.7
Interrupts. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 107
8.8
Special Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 107
8.8.1
Wait Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 107
8.8.2
CGM During Break Interrupts . . . . . . . . . . . . . . . . . . . . . . 108
8.9
Acquisition/Lock Time Specifications . . . . . . . . . . . . . . . . . . . 108
8.9.1
Acquisition/Lock Time Definitions . . . . . . . . . . . . . . . . . . . 108
8.9.2
Parametric Influences on Reaction Time . . . . . . . . . . . . . 109
8.9.3
Choosing a Filter Capacitor. . . . . . . . . . . . . . . . . . . . . . . . 111
8.9.4
Reaction Time Calculation . . . . . . . . . . . . . . . . . . . . . . . . 111
8.2 Introduction
This section describes the clock generator module (CGM). The CGM
generates the crystal clock signal, CGMXCLK, which operates at the
frequency of the crystal. The CGM also generates the base clock signal,
CGMOUT, which is based on either the crystal clock divided by two or
the phase-locked loop (PLL) clock, CGMPCLK, divided by two. This is
the clock from which the SIM derives the system clocks, including the
bus clock, which is at a frequency of CGMOUT/2. The PLL also
generates a CGMVCLK clock, at 48MHz, for use as the USBCLK. The
PLL is a fully functional frequency generator designed for use with
crystals or ceramic resonators.
This CGM is optimized to generate a 48MHz reference frequency for the
USB module, from a 6MHz crystal.
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8.3 Features
Features of the CGM include:
VCO Center-Of-Range Frequuency tuned to 48MHz for Low-Jitter
Clock Reference for USB Module
Low-Frequency Crystal Operation with Low-Power Operation and
High-Output Frequency Resolution
Programmable Reference Divider for Even Greater Resolution
Programmable Prescaler for Power-of-Two Increases in Bus
Frequency
Automatic Bandwidth Control Mode for Low-Jitter Operation
Automatic Frequency Lock Detector
CPU Interrupt on Entry or Exit from Locked Condition
8.4 Functional Description
The CGM consists of three major submodules:
Crystal oscillator circuit -- The crystal oscillator circuit generates
the constant crystal frequency clock, CGMXCLK.
Phase-locked loop (PLL) -- The PLL generates the
programmable VCO frequency clock, CGMVCLK and CGMPCLK.
Base clock selector circuit -- This software-controlled circuit
selects either CGMXCLK divided by two or the PLL clock,
CGMPCLK, divided by two as the base clock, CGMOUT. The SIM
derives the system clocks from CGMOUT.
Figure 8-1
shows the structure of the CGM.
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Figure 8-1. CGM Block Diagram
BCS
PHASE
DETECTOR
LOOP
FILTER
FREQUENCY
DIVIDER
VOLTAGE
CONTROLLED
OSCILLATOR
AUTOMATIC
MODE
CONTROL
LOCK
DETECTOR
CLOCK
CGMXCLK
CGMOUT
CGMVDV
CGMVCLK
SIMOSCEN
INTERRUPT
CONTROL
CGMINT
CGMRDV
PLL ANALOG
2
CGMRCLK
OSC2
OSC1
SELECT
CIRCUIT
V
DDA
CGMXFC
V
SSA
LOCK
AUTO
ACQ
PLLIE
PLLF
MUL[11:0]
REFERENCE
DIVIDER
RDS[3:0]
FREQUENCY
DIVIDER
PRE[1:0]
CGMPCLK
USBCLK
P
N
R
CLOCK
SELECT
CIRCUIT
PHASE-LOCKED LOOP (PLL)
OSCILLATOR (OSC)
48MHz
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8.4.1 Crystal Oscillator Circuit
The crystal oscillator circuit consists of an inverting amplifier and an
external crystal. The OSC1 pin is the input to the amplifier and the OSC2
pin is the output. The SIMOSCEN signal from the system integration
module (SIM) enables the crystal oscillator circuit.
The CGMXCLK signal is the output of the crystal oscillator circuit and
runs at a rate equal to the crystal frequency. CGMXCLK is then buffered
to produce CGMRCLK, the PLL reference clock.
CGMXCLK can be used by other modules which require precise timing
for operation. The duty cycle of CGMXCLK is not guaranteed to be 50%
and depends on external factors, including the crystal and related
external components. An externally generated clock also can feed the
OSC1 pin of the crystal oscillator circuit. Connect the external clock to
the OSC1 pin and let the OSC2 pin float.
8.4.2 Phase-Locked Loop Circuit (PLL)
The PLL is a frequency generator that can operate in either acquisition
mode or tracking mode, depending on the accuracy of the output
frequency. The PLL can change between acquisition and tracking
modes either automatically or manually.
8.4.3 PLL Circuits
The PLL consists of these circuits:
Voltage-controlled oscillator (VCO)
Reference divider
Frequency prescaler
Modulo VCO frequency divider
Phase detector
Loop filter
Lock detector
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The operating range of the VCO is programmable for a wide range of
frequencies and for maximum immunity to external noise, including
supply and CGM/XFC noise. The VCO frequency is bound to a range
from roughly 40MHz to 56MHz, f
VRS
. Modulating the voltage on the
CGM/XFC pin changes the frequency within this range. By design, f
VRS
is tuned to a nominal center-of-range frequency of 48MHz.
CGMRCLK is the PLL reference clock, a buffered version of CGMXCLK.
CGMRCLK runs at a frequency, f
RCLK
, and is fed to the PLL through a
programmable modulo reference divider, which divides f
RCLK
by a factor
R. This feature allows frequency steps of higher resolution. The divider's
output is the final reference clock, CGMRDV, running at a frequency
f
RDV
= f
RCLK
/R.
The VCO's output clock, CLK, running at a frequency f
VCLK
is fed back
through a programmable prescale divider and a programmable modulo
divider. The prescaler divides the VCO clock by a power-of-two factor P
and the modulo divider reduces the VCO clock by a factor, N. The
dividers' output is the VCO feedback clock, CGMVDV, running at a
frequency f
VDV
= f
VCLK
/(N
2
P
). (See
8.4.6 Programming the PLL
for
more information.)
The phase detector then compares the VCO feedback clock, CGMVDV,
with the final reference clock, CGMRDV. A correction pulse is generated
based on the phase difference between the two signals. The loop filter
then slightly alters the DC voltage on the external capacitor connected
to CGM/XFC based on the width and direction of the correction pulse.
The filter can make fast or slow corrections depending on its mode,
described in
8.4.4 Acquisition and Tracking Modes
. The value of the
external capacitor and the reference frequency determines the speed of
the corrections and the stability of the PLL.
The lock detector compares the frequencies of the VCO feedback clock,
CGMVDV, and the final reference clock, CGMRDV. Therefore, the
speed of the lock detector is directly proportional to the final reference
frequency, f
RDV
. The circuit determines the mode of the PLL and the lock
condition based on this comparison.
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8.4.4 Acquisition and Tracking Modes
The PLL filter is manually or automatically configurable into one of two
operating modes:
Acquisition mode -- In acquisition mode, the filter can make large
frequency corrections to the VCO. This mode is used at PLL
startup or when the PLL has suffered a severe noise hit and the
VCO frequency is far off the desired frequency. When in
acquisition mode, the ACQ bit is clear in the PLL bandwidth control
register. (See
8.6.2 PLL Bandwidth Control Register
(PBWC)
.)
Tracking mode -- In tracking mode, the filter makes only small
corrections to the frequency of the VCO. PLL jitter is much lower
in tracking mode, but the response to noise is also slower. The
PLL enters tracking mode when the VCO frequency is nearly
correct, such as when the PLL is selected as the base clock
source. (See
8.4.8 Base Clock Selector Circuit
.) The PLL is
automatically in tracking mode when not in acquisition mode or
when the ACQ bit is set.
8.4.5 Manual and Automatic PLL Bandwidth Modes
This CGM is optimized for Automatic PLL Bandwidth Mode, and is the
mode recommended for most users.
In automatic bandwidth control mode (AUTO=1), the lock detector
automatically switches between acquisition and tracking modes.
Automatic bandwidth control mode also is used to determine when the
VCO clock, CGMVCLK, is safe to use as the source for the base clock,
CGMOUT. (See
8.6.2 PLL Bandwidth Control Register (PBWC)
.) If
PLL interrupts are enabled, the software can wait for a PLL interrupt
request and then check the LOCK bit. If interrupts are disabled, software
can poll the LOCK bit continuously (during PLL startup, usually) or at
periodic intervals. In either case, when the LOCK bit is set, the VCO
clock is safe to use as the source for the base clock. (See
8.4.8 Base
Clock Selector Circuit
.) If the VCO is selected as the source for the
base clock and the LOCK bit is clear, the PLL has suffered a severe
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noise hit and the software must take appropriate action, depending on
the application. (See
8.7 Interrupts
for information and precautions on
using interrupts.) The following conditions apply when the PLL is in
automatic bandwidth control mode:
The ACQ bit (See
8.6.2 PLL Bandwidth Control Register
(PBWC)
.) is a read-only indicator of the mode of the filter. (See
8.4.4 Acquisition and Tracking Modes
.)
The ACQ bit is set when the VCO frequency is within a certain
tolerance,
TRK
, and is cleared when the VCO frequency is out of
a certain tolerance,
UNT
. (See
8.9 Acquisition/Lock Time
Specifications
for more information.)
The LOCK bit is a read-only indicator of the locked state of the
PLL.
The LOCK bit is set when the VCO frequency is within a certain
tolerance,
LOCK
, and is cleared when the VCO frequency is out of
a certain tolerance
UNL
. (See
8.9 Acquisition/Lock Time
Specifications
for more information.)
CPU interrupts can occur if enabled (PLLIE = 1) when the PLL's
lock condition changes, toggling the LOCK bit. (See
8.6.1 PLL
Control Register (PCTL)
.)
8.4.6 Programming the PLL
The following procedure shows how to program the PLL.
1. Choose the desired bus frequency, f
BUS
.
The relationship between the VCO frequency f
VCLK
and the bus
frequency f
BUS
is
The VCO frequency need to be at 48MHz for the USB module
reference clock.
Choose P = 0, 1, 2, or 3 for a bus frequency of 12MHz, 6MHz,
3MHz, or 1.5MHz respectively.
f
VCLK
2
P
-------------
4
f
BUS
=
48MHz
2
P
--------------------
4
f
BUS
=
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2. Choose a practical PLL (crystal) reference frequency, f
RCLK
, and
the reference clock divider, R.
Frequency errors to the PLL are corrected at a rate of f
RCLK
/R. For
stability and lock time reduction, this rate must be as fast as
possible. The VCO frequency must be an integer multiple of this
rate. The relationship between the VCO frequency f
VCLK
and the
reference frequency f
RCLK
is
Choose the reference divider R = 1 for fast lock. Choose a f
RCLK
frequency with an integer divisor of f
BUS
and solve for N.
3. Program the PLL registers accordingly:
a.
In the PRE bits of the PLL control register (PCTL), program
the binary equivalent of P.
b.
In the PLL multiplier select register low (PMSL) and the PLL
multiplier select register high (PMSH), program the binary
equivalent of N.
c.
In the PLL reference divider select register (PRDS), program
the binary coded equivalent of R.
Table 8-1
provides a numeric example (numbers are in hexadecimal
notation):
8.4.7 Special Programming Exceptions
The programming method described in
8.4.6 Programming the PLL
does not account for three possible exceptions. A value of zero for R, N,
or L is meaningless when used in the equations given. To account for
these exceptions:
Table 8-1. CGM Numeric Example
f
BUS
f
RCLK
P
N
R
6MHz
6MHz
1
004
1
f
VCLK
2
P
N
R
-----------------
f
RCLK
(
)
=
hence: 48MHz
2
P
N
R
-----------------
f
RCLK
(
)
=
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A zero value for R or N is interpreted exactly the same as a value of one.
A zero value for L disables the PLL and prevents its selection as the
source for the base clock. (See
8.4.8 Base Clock Selector Circuit
.)
8.4.8 Base Clock Selector Circuit
This circuit is used to select either the crystal clock, CGMXCLK, or the
PLL clock, CGMPCLK, as the source of the base clock, CGMOUT. The
two input clocks go through a transition control circuit that waits up to
three CGMXCLK cycles and three CGMPCLK cycles to change from
one clock source to the other. During this time, CGMOUT is held in
stasis. The output of the transition control circuit is then divided by two
to correct the duty cycle. Therefore, the bus clock frequency, which is
one-half of the base clock frequency, is one-fourth the frequency of the
selected clock (CGMXCLK or CGMPCLK).
The BCS bit in the PLL control register (PCTL) selects which clock drives
CGMOUT. The VCO clock cannot be selected as the base clock source
if the PLL is not turned on. The PLL cannot be turned off if the VCO clock
is selected. The PLL cannot be turned on or off simultaneously with the
selection or deselection of the VCO clock.
This circuit is also used to select either the crystal clock, CGMXCLK or
the VCO clock, CGMVCLK, as the source of the USB clock, USBCLK.
8.4.9 CGM External Connections
In its typical configuration, the CGM requires seven external
components. Five of these are for the crystal oscillator and two are for
the PLL.
The crystal oscillator is normally connected in a Pierce oscillator
configuration, as shown in
Figure 8-2
.
Figure 8-2
shows only the logical
representation of the internal components and may not represent actual
circuitry. The oscillator configuration uses five components:
Crystal, X
1
Fixed capacitor, C
1
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Tuning capacitor, C
2
(can also be a fixed capacitor)
Feedback resistor, R
B
Series resistor, R
S
(optional)
The series resistor (R
S
) is included in the diagram to follow strict Pierce
oscillator guidelines and may not be required for all ranges of operation,
especially with high frequency crystals. Refer to the crystal
manufacturer's data for more information.
Figure 8-2
also shows the external components for the PLL:
Bypass capacitor, C
BYP
Filter capacitor, C
F
Routing should be done with great care to minimize signal cross talk and
noise.
See
Section 17. Preliminary Electrical Specifications
for capacitor
and resistor values.
Figure 8-2. CGM External Connections
SIMOSCEN
CGMXCLK
R
B
X
1
*R
S
can be zero (shorted) when used with higher-frequency crystals. Refer to manufacturer's data.
OSC1
OSC2
V
SSA
CGMXFC
V
DDA
V
DD
C
BYP
R
S
*
C
1
C
2
C
F
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8.5 I/O Signals
The following paragraphs describe the CGM I/O signals.
8.5.1 Crystal Amplifier Input Pin (OSC1)
The OSC1 pin is an input to the crystal oscillator amplifier.
8.5.2 Crystal Amplifier Output Pin (OSC2)
The OSC2 pin is the output of the crystal oscillator inverting amplifier.
8.5.3 External Filter Capacitor Pin (CGMXFC)
The CGMXFC pin is required by the loop filter to filter out phase
corrections. A small external capacitor is connected to this pin.
NOTE:
To prevent noise problems, C
F
should be placed as close to the
CGMXFC pin as possible, with minimum routing distances and no
routing of other signals across the C
F
connection.
8.5.4 PLL Analog Power Pin (V
DDA
)
V
DDA
is a power pin used by the analog portions of the PLL. Connect the
V
DDA
pin to the same voltage potential as the V
DD
pin.
NOTE:
Route V
DDA
carefully for maximum noise immunity and place bypass
capacitors as close as possible to the package.
8.5.5 PLL Analog Ground Pin (V
SSA
)
V
SSA
is a ground pin used by the analog portions of the PLL. Connect
the V
SSA
pin to the same voltage potential as the V
SS
pin.
NOTE:
Route V
SSA
carefully for maximum noise immunity and place bypass
capacitors as close as possible to the package.
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8.5.6 Buffered Crystal Clock Output (CGMVOUT)
CGMVOUT buffers the OSC1 clock for external use.
8.5.7 CGMVSEL
CGMVSEL must be tied low or floated.
8.5.8 Oscillator Enable Signal (SIMOSCEN)
The SIMOSCEN signal comes from the system integration module (SIM)
and enables the oscillator and PLL.
8.5.9 Crystal Output Frequency Signal (CGMXCLK)
CGMXCLK is the crystal oscillator output signal. It runs at the full speed
of the crystal (f
XCLK
) and comes directly from the crystal oscillator circuit.
Figure 8-2
shows only the logical relation of CGMXCLK to OSC1 and
OSC2 and may not represent the actual circuitry. The duty cycle of
CGMXCLK is unknown and may depend on the crystal and other
external factors. Also, the frequency and amplitude of CGMXCLK can be
unstable at startup.
8.5.10 CGM Base Clock Output (CGMOUT)
CGMOUT is the clock output of the CGM. This signal goes to the SIM,
which generates the MCU clocks. CGMOUT is a 50 percent duty cycle
clock running at twice the bus frequency. CGMOUT is software
programmable to be either the oscillator output, CGMXCLK, divided by
two or the VCO clock, CGMVCLK, divided by two.
8.5.11 CGM CPU Interrupt (CGMINT)
CGMINT is the interrupt signal generated by the PLL lock detector.
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8.6 CGM Registers
These registers control and monitor operation of the CGM:
PLL control register (PCTL) (See
8.6.1 PLL Control Register
(PCTL)
.)
PLL bandwidth control register (PBWC) (See
8.6.2 PLL
Bandwidth Control Register (PBWC)
.)
PLL multiplier select registers (PMSH:PMSL) (See
8.6.3 PLL
Multiplier Select Registers (PMSH:PMSL)
.)
PLL reference divider select register (PRDS) (See
8.6.4 PLL
Reference Divider Select Register (PRDS)
.)
Table 8-2
is a summary of the CGM registers.
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Table 8-2. CGM I/O Register Summary
Addr.
Register Name
Bit 7
6
5
4
3
2
1
Bit 0
$003A
PLL Control Register
(PCTL)
Read:
PLLIE
PLLF
PLLON
BCS
PRE1
PRE2
0
0
Write:
Reset:
0
0
1
0
1
0
0
0
$003B
PLL Bandwidth Control
Register
(PBWC)
Read:
AUTO
LOCK
ACQ
0
0
0
0
0
Write:
Reset:
0
0
0
0
0
0
0
0
$003C
PLL Multiplier Select
Register High
(PMSH)
Read:
0
0
0
0
MUL11
MUL10
MUL9
MUL8
Write:
Reset:
0
0
0
0
0
0
0
0
$003D
PLL Multiplier Select
Register Low
(PMSL)
Read:
MUL7
MUL6
MUL5
MUL4
MUL3
MUL2
MUL1
MUL0
Write:
Reset:
0
0
0
0
0
0
1
0
$003E
Unimplemented
Read:
Write:
Reset:
$003F
PLL Reference Divider
Select Register
(PRDS)
Read:
0
0
0
0
RDS3
RDS2
RDS1
RDS0
Write:
Reset:
0
0
0
0
0
0
0
1
= Unimplemented
NOTES:
1. When AUTO = 0, PLLIE is forced clear and is read-only.
2. When AUTO = 0, PLLF and LOCK read as clear.
3. When AUTO = 1, ACQ is read-only.
4. When PLLON = 0 or VRS7:VRS0 = $0, BCS is forced clear and is read-only.
5. When PLLON = 1, the PLL programming register is read-only.
6. When BCS = 1, PLLON is forced set and is read-only.
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8.6.1 PLL Control Register (PCTL)
The PLL control register contains the interrupt enable and flag bits, the
on/off switch, the base clock selector bit, the prescaler bits, and the VCO
power of two range selector bits.
PLLIE -- PLL Interrupt Enable Bit
This read/write bit enables the PLL to generate an interrupt request
when the LOCK bit toggles, setting the PLL flag, PLLF. When the
AUTO bit in the PLL bandwidth control register (PBWC) is clear,
PLLIE cannot be written and reads as logic zero. Reset clears the
PLLIE bit.
1 = PLL interrupts enabled
0 = PLL interrupts disabled
PLLF -- PLL Interrupt Flag Bit
This read-only bit is set whenever the LOCK bit toggles. PLLF
generates an interrupt request if the PLLIE bit also is set. PLLF
always reads as logic zero when the AUTO bit in the PLL bandwidth
control register (PBWC) is clear. Clear the PLLF bit by reading the
PLL control register. Reset clears the PLLF bit.
1 = Change in lock condition
0 = No change in lock condition
NOTE:
Do not inadvertently clear the PLLF bit. Any read or read-modify-write
operation on the PLL control register clears the PLLF bit.
Address:
$003A
Bit 7
6
5
4
3
2
1
Bit 0
Read:
PLLIE
PLLF
PLLON
BCS
PRE1
PRE2
0
0
Write:
Reset:
0
0
1
0
1
0
0
0
= Unimplemented
Figure 8-3. PLL Control Register (PCTL)
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PLLON -- PLL On Bit
This read/write bit activates the PLL and enables the VCO clock,
CGMVCLK. PLLON cannot be cleared if the VCO clock is driving the
base clock, CGMOUT (BCS = 1). (See
8.4.8 Base Clock Selector
Circuit
.) Reset sets this bit so that the loop can stabilize as the MCU
is powering up.
1 = PLL on
0 = PLL off
BCS -- Base Clock Select Bit
This read/write bit selects either the crystal oscillator clock
(CGMXCLK) or the VCO clocks (CGMPCLK and CGMVCLK) to use
as base clocks for the MCU.
BCS cannot be set while the PLLON bit is clear. After toggling BCS,
it may take up to three CGMXCLK and three CGMPCLK cycles to
complete the transition from one source clock to the other. During the
transition, CGMOUT is held in stasis. (See
8.4.8 Base Clock
Selector Circuit
.) Reset clears the BCS bit.
1 = Selects the VCO clocks for the base clock.
CGMPCLK divided by two drives CGMOUT,
CGMVCLK (48MHz) drives USBCLK
0 = Selects the crystal oscillator clock for the base clock.
CGMXCLK divided by two drives CGMOUT,
CGMXCLK drives USBCLK
NOTE:
PLLON and BCS have built-in protection that prevents the base clock
selector circuit from selecting the VCO clock as the source of the base
clock if the PLL is off. Therefore, PLLON cannot be cleared when BCS
is set, and BCS cannot be set when PLLON is clear. If the PLL is off
(PLLON = 0), selecting CGMPCLK/CGMVCLK requires two writes to the
PLL control register. (See
8.4.8 Base Clock Selector Circuit
.)
PRE1 and PRE0 -- Prescaler program bits
These read/write bits control a prescaler that selects the prescaler
power-of-two multiplier P. (See
8.4.3 PLL Circuits
and
8.4.6
Programming the PLL
.) PRE1:PRE0 cannot be written when the
PLLON bit is set. Reset clears these bits.
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8.6.2 PLL Bandwidth Control Register (PBWC)
The PLL bandwidth control register:
Indicates when the PLL is locked
In automatic bandwidth control mode, indicates when the PLL is in
acquisition or tracking mode
AUTO -- Automatic Bandwidth Control Bit
This read/write bit selects automatic or manual bandwidth control.
Since this CGM is optimized a frequency output of 48MHz for the USB
module, automatic control should be set. Reset clears the AUTO bit.
1 = Automatic bandwidth control (recommended)
0 = Manual bandwidth control
LOCK -- Lock Indicator Bit
When the AUTO bit is set, LOCK is a read-only bit that becomes set
when the VCO clock, CGMVCLK, is locked (running at the
programmed frequency). When the AUTO bit is clear, LOCK reads as
Table 8-3. PRE[1:0] Programming
PRE1
PRE0
P
Prescaler Multiplier
0
0
0
1
0
1
1
2
1
0
2
4
1
1
3
8
Address:
$003B
Bit 7
6
5
4
3
2
1
Bit 0
Read:
AUTO
LOCK
ACQ
0
0
0
0
0
Write:
Reset:
0
0
0
0
0
0
0
0
= Unimplemented
Figure 8-4. PLL Bandwidth Control Register (PBWC)
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logic zero and has no meaning. The write one function of this bit is
reserved for test, so this bit must
always be written a zero. Reset
clears the LOCK bit.
1 = VCO frequency correct or locked
0 = VCO frequency incorrect or unlocked
ACQ -- Acquisition Mode Bit
When the AUTO bit is set, ACQ is a read-only bit that indicates
whether the PLL is in acquisition mode or tracking mode. When the
AUTO bit is clear, ACQ is a read/write bit that controls whether the
PLL is in acquisition or tracking mode.
In automatic bandwidth control mode (AUTO = 1), the last-written
value from manual operation is stored in a temporary location and is
recovered when manual operation resumes. Reset clears this bit,
enabling acquisition mode.
1 = Tracking mode
0 = Acquisition mode
8.6.3 PLL Multiplier Select Registers (PMSH:PMSL)
The PLL multiplier select registers contain the programming information
for the modulo feedback divider.
Address:
$003C
PMSH
Bit 7
6
5
4
3
2
1
Bit 0
Read:
0
0
0
0
MUL11
MUL10
MUL9
MUL8
Write:
Reset:
0
0
0
0
0
0
0
0
Address:
$003D
PMSL
Read:
MUL7
MUL6
MUL5
MUL4
MUL3
MUL2
MUL1
MUL0
Write:
Reset:
0
0
0
0
0
0
1
0
= Unimplemented
Figure 8-5. PLL Multiplier Select Registers (PMSH:PMSL)
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MUL[11:0] -- Multiplier select bits
These read/write bits control the modulo feedback divider that selects
the VCO frequency multiplier N. (See
8.4.3 PLL Circuits
and
8.4.6
Programming the PLL
.) MUL[11:0] cannot be written when the
PLLON bit in the PCTL is set. A value of $0000 in the multiplier select
registers configures the modulo feedback divider the same as a value
of $0001. Reset initializes the registers to $002 for a default multiply
value of 2.
NOTE:
The multiplier select bits have built-in protection such that they cannot
be written when the PLL is on (PLLON = 1).
8.6.4 PLL Reference Divider Select Register (PRDS)
The PLL reference divider select register contains the programming
information for the modulo reference divider.
RDS[3:0] -- Reference Divider Select Bits
These read/write bits control the modulo reference divider that selects
the reference division factor R. (See
8.4.3 PLL Circuits
and
8.4.6
Programming the PLL
.) RDS[7:0] cannot be written when the
PLLON bit in the PCTL is set. A value of $00 in the reference divider
select register configures the reference divider the same as a value of
$01. (See
8.4.7 Special Programming Exceptions
.) Reset
initializes the register to $01 for a default divide value of 1.
NOTE:
The reference divider select bits have built-in protection such that they
cannot be written when the PLL is on (PLLON = 1).
Address:
$003F
Bit 7
6
5
4
3
2
1
Bit 0
Read:
0
0
0
0
RDS3
RDS2
RDS1
RDS0
Write:
Reset:
0
0
0
0
0
0
0
1
= Unimplemented
Figure 8-6. PLL Reference Divider Select Register (PRDS)
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8.7 Interrupts
When the AUTO bit is set in the PLL bandwidth control register (PBWC),
the PLL can generate a CPU interrupt request every time the LOCK bit
changes state. The PLLIE bit in the PLL control register (PCTL) enables
CPU interrupts from the PLL. PLLF, the interrupt flag in the PCTL,
becomes set whether interrupts are enabled or not. When the AUTO bit
is clear, CPU interrupts from the PLL are disabled and PLLF reads as
logic zero.
Software should read the LOCK bit after a PLL interrupt request to see
if the request was due to an entry into lock or an exit from lock. When the
PLL enters lock, the VCO clock, CGMPCLK, divided by two can be
selected as the CGMOUT source by setting BCS in the PCTL. When the
PLL exits lock, the VCO clock frequency is corrupt, and appropriate
precautions should be taken. If the application is not frequency sensitive,
interrupts should be disabled to prevent PLL interrupt service routines
from impeding software performance or from exceeding stack
limitations.
NOTE:
Software can select the CGMPCLK divided by two as the CGMOUT
source even if the PLL is not locked (LOCK = 0). Therefore, software
should make sure the PLL is locked before setting the BCS bit.
8.8 Special Modes
The WAIT instruction puts the MCU in low-power-consumption standby
modes.
8.8.1 Wait Mode
The WAIT instruction does not affect the CGM. Before entering wait
mode, software can disengage and turn off the PLL by clearing the BCS
and PLLON bits in the PLL control register (PCTL) to save power. Less
power-sensitive applications can disengage the PLL without turning it
off, so that the PLL clock is immediately available at WAIT exit. This
would also be the case when the PLL is to wake the MCU from wait
mode, such as when the PLL is first enabled and waiting for LOCK, or
LOCK is lost.
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8.8.2 CGM During Break Interrupts
The system integration module (SIM) controls whether status bits in
other modules can be cleared during the break state. The BCFE bit in
the SIM break flag control register (SBFCR) enables software to clear
status bits during the break state. (See
7.8.3 Break Flag Control
Register (BFCR)
.)
To allow software to clear status bits during a break interrupt, write a
logic one to the BCFE bit. If a status bit is cleared during the break state,
it remains cleared when the MCU exits the break state.
To protect the PLLF bit during the break state, write a logic zero to the
BCFE bit. With BCFE at logic zero (its default state), software can read
and write the PLL control register during the break state without affecting
the PLLF bit.
8.9 Acquisition/Lock Time Specifications
The acquisition and lock times of the PLL are, in many applications, the
most critical PLL design parameters. Proper design and use of the PLL
ensures the highest stability and lowest acquisition/lock times.
8.9.1 Acquisition/Lock Time Definitions
Typical control systems refer to the acquisition time or lock time as the
reaction time, within specified tolerances, of the system to a step input.
In a PLL, the step input occurs when the PLL is turned on or when it
suffers a noise hit. The tolerance is usually specified as a percent of the
step input or when the output settles to the desired value plus or minus
a percent of the frequency change. Therefore, the reaction time is
constant in this definition, regardless of the size of the step input. For
example, consider a system with a 5 percent acquisition time tolerance.
If a command instructs the system to change from 0 Hz to 1 MHz, the
acquisition time is the time taken for the frequency to reach
1 MHz
50 kHz. Fifty kHz = 5% of the 1 MHz step input. If the system is
operating at 1 MHz and suffers a 100 kHz noise hit, the acquisition time
is the time taken to return from 900 kHz to 1 MHz
5 kHz.
Five kHz = 5 percent of the 100-kHz step input.
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Other systems refer to acquisition and lock times as the time the system
takes to reduce the error between the actual output and the desired
output to within specified tolerances. Therefore, the acquisition or lock
time varies according to the original error in the output. Minor errors may
not even be registered. Typical PLL applications prefer to use this
definition because the system requires the output frequency to be within
a certain tolerance of the desired frequency regardless of the size of the
initial error.
The discrepancy in these definitions makes it difficult to specify an
acquisition or lock time for a typical PLL. Therefore, the definitions for
acquisition and lock times for this module are:
Acquisition time, t
ACQ
, is the time the PLL takes to reduce the error
between the actual output frequency and the desired output
frequency to less than the tracking mode entry tolerance,
TRK
.
Acquisition time is based on an initial frequency error,
(f
DES
f
ORIG
)/f
DES
, of not more than
100 percent. In automatic
bandwidth control mode (See
8.4.5 Manual and Automatic PLL
Bandwidth Modes
.), acquisition time expires when the ACQ bit
becomes set in the PLL bandwidth control register (PBWC).
Lock time, t
LOCK
, is the time the PLL takes to reduce the error
between the actual output frequency and the desired output
frequency to less than the lock mode entry tolerance,
LOCK
. Lock
time is based on an initial frequency error, (f
DES
f
ORIG
)/f
DES
, of not
more than
100 percent. In automatic bandwidth control mode,
lock time expires when the LOCK bit becomes set in the PLL
bandwidth control register (PBWC). (See
8.4.5 Manual and
Automatic PLL Bandwidth Modes
.)
Obviously, the acquisition and lock times can vary according to how
large the frequency error is and may be shorter or longer in many cases.
8.9.2 Parametric Influences on Reaction Time
Acquisition and lock times are designed to be as short as possible while
still providing the highest possible stability. These reaction times are not
constant, however. Many factors directly and indirectly affect the
acquisition time.
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The most critical parameter which affects the reaction times of the PLL
is the reference frequency, f
RDV
. This frequency is the input to the phase
detector and controls how often the PLL makes corrections. For stability,
the corrections must be small compared to the desired frequency, so
several corrections are required to reduce the frequency error.
Therefore, the slower the reference the longer it takes to make these
corrections. This parameter is under user control via the choice of crystal
frequency f
XCLK
and the R value programmed in the reference divider.
(See
8.4.3 PLL Circuits
,
8.4.6 Programming the PLL
, and
8.6.4
PLL Reference Divider Select Register (PRDS)
.)
Another critical parameter is the external filter capacitor. The PLL
modifies the voltage on the VCO by adding or subtracting charge from
this capacitor. Therefore, the rate at which the voltage changes for a
given frequency error (thus change in charge) is proportional to the
capacitor size. The size of the capacitor also is related to the stability of
the PLL. If the capacitor is too small, the PLL cannot make small enough
adjustments to the voltage and the system cannot lock. If the capacitor
is too large, the PLL may not be able to adjust the voltage in a
reasonable time. (See
8.9.3 Choosing a Filter Capacitor
.)
Also important is the operating voltage potential applied to V
DDA
. The
power supply potential alters the characteristics of the PLL. A fixed value
is best. Variable supplies, such as batteries, are acceptable if they vary
within a known range at very slow speeds. Noise on the power supply is
not acceptable, because it causes small frequency errors which
continually change the acquisition time of the PLL.
Temperature and processing also can affect acquisition time because
the electrical characteristics of the PLL change. The part operates as
specified as long as these influences stay within the specified limits.
External factors, however, can cause drastic changes in the operation of
the PLL. These factors include noise injected into the PLL through the
filter capacitor, filter capacitor leakage, stray impedances on the circuit
board, and even humidity or circuit board contamination.
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8.9.3 Choosing a Filter Capacitor
As described in
8.9.2 Parametric Influences on Reaction Time
, the
external filter capacitor, C
F
, is critical to the stability and reaction time of
the PLL. The PLL is also dependent on reference frequency and supply
voltage. The value of the capacitor must, therefore, be chosen with
supply potential and reference frequency in mind. For proper operation,
the external filter capacitor must be chosen according to this equation:
For the value of V
DDA
, choose the voltage potential at which the MCU is
operating. If the power supply is variable, choose a value near the
middle of the range of possible supply values.
This equation does not always yield a commonly available capacitor
size, so round to the nearest available size. If the value is between two
different sizes, choose the higher value for better stability. Choosing the
lower size may seem attractive for acquisition time improvement, but the
PLL may become unstable. Also, always choose a capacitor with a tight
tolerance (
20 percent or better) and low dissipation.
8.9.4 Reaction Time Calculation
The actual acquisition and lock times can be calculated using the
equations below. These equations yield nominal values under the
following conditions:
Correct selection of filter capacitor, C
F
(See
8.9.3 Choosing a
Filter Capacitor
.)
Room temperature operation
Negligible external leakage on CGMXFC
Negligible noise
The K factor in the equations is derived from internal PLL parameters.
K
ACQ
is the K factor when the PLL is configured in acquisition mode, and
K
TRK
is the K factor when the PLL is configured in tracking mode. (See
8.4.4 Acquisition and Tracking Modes
.) Reaction time is based on
C
F
C
FACT
V
DDA
f
RDV
-------------
=
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an initial frequency error, (f
DES
f
ORIG
)/f
DES
, of not more than
100
percent.
NOTE:
The inverse proportionality between the lock time and the reference
frequency.
In automatic bandwidth control mode, the acquisition and lock times are
quantized into units based on the reference frequency. (See
8.4.5
Manual and Automatic PLL Bandwidth Modes
.) A certain number of
clock cycles, n
ACQ
, is required to ascertain that the PLL is within the
tracking mode entry tolerance,
TRK
, before exiting acquisition mode. A
certain number of clock cycles, n
TRK
, is required to ascertain that the PLL
is within the lock mode entry tolerance,
LOCK
. Therefore, the acquisition
time, t
ACQ
, is an integer multiple of n
ACQ
/f
RDV
, and the acquisition to lock
time, t
AL
, is an integer multiple of n
TRK
/f
RDV
.
In manual mode, it is usually necessary to wait considerably longer than
t
LOCKMAX
before selecting the PLL clock (See
8.4.8 Base Clock
Selector Circuit
.), because the factors described in
8.9.2 Parametric
Influences on Reaction Time
may slow the lock time considerably.
Automatic bandwidth mode is recommended for most users.
t
ACQ
V
DDA
f
RDV
-------------
8
K
ACQ
-------------
=
t
AL
V
DDA
f
RDV
-------------
4
K
TRK
------------
=
t
LOCKMAX
t
ACQ
t
AL
256t
VRDV
+
+
=
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Section 9. Universal Serial Bus Module (USB)
9.1 Contents
9.2
Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 114
9.3
Overview. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 115
9.4
I/O Register Description of the HUB function . . . . . . . . . . . . . 116
9.4.1
USB HUB Root Port Control Register (HRPCR) . . . . . . . . 120
9.4.2
USB HUB Downstream Port Control Register
(HDP1CR-HDP4CR) . . . . . . . . . . . . . . . . . . . . . . . . . . 121
9.4.3
USB SIE Timing Interrupt Register (SIETIR). . . . . . . . . . . 123
9.4.4
USB SIE Timing Status Register (SIETSR) . . . . . . . . . . . 125
9.4.5
USB HUB Address Register (HADDR) . . . . . . . . . . . . . . . 127
9.4.6
USB HUB Interrupt Register 0 (HIR0) . . . . . . . . . . . . . . . . 128
9.4.7
USB HUB Control Register 0 (HCR0) . . . . . . . . . . . . . . . . 129
9.4.8
USB HUB Endpoint1 Control & Data Register (HCDR) . . 131
9.4.9
USB HUB Status Register (HSR) . . . . . . . . . . . . . . . . . . . 132
9.4.10
USB HUB Endpoint 0 Data Registers 0-7
(HE0D0-HE0D7). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 134
9.5
I/O Register Description of the Embedded Device Function . 134
9.5.1
USB Embedded Device Address Register (DADDR) . . . . 138
9.5.2
USB Embedded Device Interrupt Register 0 (DIR0) . . . . . 138
9.5.3
USB Embedded Device Interrupt Register 1 (DIR1) . . . . . 140
9.5.4
USB Embedded Device Control Register 0 (DCR0) . . . . . 141
9.5.5
USB Embedded Device Control Register 1 (DCR1) . . . . . 143
9.5.6
USB Embedded Device Status Register (DSR) . . . . . . . . 144
9.5.7
USB Embedded Device Control Register 2 (DCR2) . . . . . 146
9.5.8
USB Embedded Device Endpoint 0 Data Registers
(DE0D0-DE0D7). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 147
9.5.9
USB Embedded Device Endpoint 1/2 Data Registers
(DE1D0-DE1D7). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 148
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Universal Serial Bus Module (USB)
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Universal Serial Bus Module (USB)
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9.2 Features
Features of the general USB Module include the following:
Integrated 3.3 Volt Regulator with 3.3V Output Pin REGOUT
Integrated USB transceiver supporting both full speed and low
speed functions
USB Data Control Logic
Packet decoding/generation
CRC generation and checking
NRZI encoding/decoding
Bit stuffing/de-stuffing
USB reset support
Suspend and resume operations
Remote Wakeup support
STALL, NAK, and ACK handshake generation
Features of the HUB function include the following:
HUB Control Endpoint 0
8-byte transmit buffer
8-byte receive buffer
HUB Interrupt Endpoint 1
1-byte transmit buffer
USB interrupts
transaction interrupt driven
Start of Frame interrupt
EOF2 interrupt
End of Packet interrupt
Signal transition interrupt
Frame timer locked interrupt
HUB repeater and controller function
downstream and upstream connectivity
bus state evaluation
selective reset, suspend and resume
fault condition hardware detection
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Universal Serial Bus Module (USB)
Overview
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Features of the embedded device function include the following:
Device Control Endpoint 0 and Interrupt Endpoints 1 and 2
8-byte transmit buffer
8-byte receive buffer
Device Interrupt Endpoints 1 and 2
8-byte transmit buffer
USB generated interrupts
transaction interrupt driven
9.3 Overview
This section provides an overview of the Universal Serial Bus (USB)
module developed for the MC68HC(7)08KH12. This USB module is
designed to serve as a compound device, and operates from a reference
frequency of 48MHz, derived from the CGM
(see Section 8. Clock
Generator Module (CGM)
). An embedded full speed device function is
combined with a hub in a single USB module. For the hub sub-module,
five basic properties can be supported by the hardware or the software:
connectivity behavior, power management, device connect/disconnect
detection, bus fault detection and recovery, and full/low speed device
traffic control. Endpoint 0 of the hub sub-module functions as a
receive/transmit control endpoint. Endpoint 1 of the hub sub-module
functions as interrupt transfer to report the device change state. For the
embedded device sub-module, three types of USB data transfers are
supported: control, interrupt, and bulk (transmit only). Endpoint 0 of the
embedded device sub-module functions as a receive/transmit control
endpoint. Endpoints 1 and 2 of the embedded device sub-module can
function as interrupt or bulk, but only in the transmit direction.
A block diagram of the USB module is shown
Figure 9-1
. The USB
module manages communications between the host and the USB
function. The module is partitioned into eight functional blocks. These
blocks consist of a 3.3 volt regulator, a dual function transceiver, the hub
repeater function, the SIE (Serial Interface Engine), the frame counter
logic, the hub control logic, the embedded device control logic, and the
endpoint registers.
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Figure 9-1. USB Block Diagram
9.4 I/O Register Description of the HUB function
The USB hub function provides a set of control/status registers and
sixteen data registers that provide storage for the buffering of data
between the USB hub function and the CPU. These registers are shown
in
Table 9-1
and
Table 9-2
.
D0+
D0
T
R
ANSCEIV
ER
3.3V OUT
CPU BUS
T
R
ANSCEIV
ER
D1+
:
D4+
D1
:
D4
R
OOR POR
T
DO
WNSTREAM POR
TS
HUB REPEA
TER
REGULATOR
SERIAL
FR
AME
COUNTER
ENGINE
HUB
CONTROL
LOGIC
REGISTERS
ENDPOINT 0 - 8/8 B (CONTROL)
ENDPOINT 1 - 1 B (INTERRUPT)
ENDPOINT 0 - 8/8 (CONTROL)
ENDPOINT 1/2 - 8 B (TRANSMIT ONLY, INTERRUPT/BULK)
12MHz
USBCLK (FROM CGM)
EMBEDDED DE
VICE
CONTROL
LOGIC
INTERF
A
C
E
48MHz
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Universal Serial Bus Module (USB)
I/O Register Description of the HUB function
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Universal Serial Bus Module (USB)
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Table 9-1. HUB Control Register Summary
Addr.
Register Name
Bit 7
6
5
4
3
2
1
Bit 0
$0051
USB HUB Downstream Port 1
Control Register
(HDP1CR)
Read:
PEN1
LOWSP1
RST1
RESUM1
SUSP1
0
D1+
D1
Write:
Reset:
0
0
0
0
0
0
X
X
$0052
USB HUB Downstream Port 2
Control Register
(HDP2CR)
Read:
PEN2
LOWSP2
RST2
RESUM2
SUSP2
0
D2+
D2
Write:
Reset:
0
0
0
0
0
0
X
X
$0053
USB HUB Downstream Port 3
Control Register
(HDP3CR)
Read:
PEN3
LOWSP3
RST3
RESUM3
SUSP3
0
D3+
D3
Write:
Reset:
0
0
0
0
0
0
X
X
$0054
USB HUB Downstream Port 4
Control Register
(HDP4CR)
Read:
PEN4
LOWSP4
RST4
RESUM4
SUSP4
0
D4+
D4
Write:
Reset:
0
0
0
0
0
0
X
X
$0055
Unimplemented
Read:
Write:
Reset:
$0056
USB SIE Timing Interrupt
Register
(SIETIR)
Read:
SOFF
EOF2F
EOPF
TRANF
SOFIE
EOF2IE
EOPIE
TRANIE
Write:
Reset:
0
0
0
0
0
0
0
0
$0057
USB SIE Timing Status
Register
(SIETSR)
Read:
RSTF
0
LOCKF
0
0
0
0
0
Write:
RSTFR
LOCKFR SOFFR
EOF2FR
EOPFR TRANFR
Reset:
0**
0
0
0
0
0
0
0
$0058
USB HUB Address Register
(HADDR)
Read:
USBEN
ADD6
ADD5
ADD4
ADD3
ADD2
ADD1
ADD0
Write:
Reset:
0**
0
0
0
0
0
0
0
$0059
USB HUB Interrupt
Register 0
(HIR0)
Read:
TXDF
RXDF
0
0
TXDIE
RXDIE
0
0
Write:
TXDFR
RXDFR
Reset:
0
0
0
0
0
0
0
0
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$005A
Unimplemented
Read:
Write:
Reset:
$005B
USB HUB Control
Register 0
(HCR0)
Read:
TSEQ
STALL0
TXE
RXE
TPSIZ3
TPSIZ2
TPSIZ1
TPSIZ0
Write:
Reset:
0
0
0
0
0
0
0
0
$005C
USB HUB Endpoint 1
Control and Data Register
(HCDR)
Read:
STALL1
PNEW
PCHG5
PCHG4
PCHG3
PCHG2
PCHG1
PCHG0
Write:
Reset:
0
0
0
0
0
0
0
0
$005D
USB HUB Status Register
(HSR)
Read:
RSEQ
SETUP
TX1ST
0
RPSIZ3
RPSIZ2
RPSIZ1
RPSIZ0
Write:
TX1STR
Reset:
X
X
0
0
X
X
X
X
$005E
USB HUB Root Port Control
Register
(HRPCR)
Read:
0
0
0
RESUM0
SUSPND
0
D0+
D0
Write:
Reset:
0
0
0
0
0
0
X
X
= Unimplemented
X = Indeterminate
0** = Reset by POR only
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Universal Serial Bus Module (USB)
I/O Register Description of the HUB function
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Universal Serial Bus Module (USB)
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Table 9-2. HUB Data Register Summary
Addr.
Register Name
Bit 7
6
5
4
3
2
1
Bit 0
$0030
USB HUB Endpoint 0 Data
Register 0
(HE0D0)
Read: HE0R07 HE0R06 HE0R05 HE0R04 HE0R03 HE0R02 HE0R01 HE0R00
Write: HE0T07
HE0T06
HE0T05
HE0T04
HE0T03
HE0T02
HE0T01
HE0T00
Reset:
X
X
X
X
X
X
X
X
$0031
USB HUB Endpoint 0 Data
Register 1
(HE0D1)
Read: HE0R17 HE0R16 HE0R15 HE0R14 HE0R13 HE0R12 HE0R11 HE0R10
Write: HE0T17
HE0T16
HE0T15
HE0T14
HE0T13
HE0T12
HE0T11
HE0T10
Reset:
X
X
X
X
X
X
X
X
$0032
USB HUB Endpoint 0 Data
Register 2
(HE0D2)
Read: HE0R27 HE0R26 HE0R25 HE0R24 HE0R23 HE0R22 HE0R21 HE0R20
Write: HE0T27
HE0T26
HE0T25
HE0T24
HE0T23
HE0T22
HE0T21
HE0T20
Reset:
X
X
X
X
X
X
X
X
$0033
USB HUB Endpoint 0 Data
Register 3
(HE0D3)
Read: HE0R37 HE0R36 HE0R35 HE0R34 HE0R33 HE0R32 HE0R31 HE0R30
Write: HE0T37
HE0T36
HE0T35
HE0T34
HE0T33
HE0T32
HE0T31
HE0T30
Reset:
X
X
X
X
X
X
X
X
$0034
USB HUB Endpoint 0 Data
Register 4
(HE0D4)
Read: HE0R47 HE0R46 HE0R45 HE0R44 HE0R43 HE0R42 HE0R41 HE0R40
Write: HE0T47
HE0T46
HE0T45
HE0T44
HE0T43
HE0T42
HE0T41
HE0T40
Reset:
X
X
X
X
X
X
X
X
$0035
USB HUB Endpoint 0 Data
Register 5
(HE0D5)
Read: HE0R57 HE0R56 HE0R55 HE0R54 HE0R53 HE0R52 HE0R51 HE0R50
Write: HE0T57
HE0T56
HE0T55
HE0T54
HE0T53
HE0T52
HE0T51
HE0T50
Reset:
X
X
X
X
X
X
X
X
$0036
USB HUB Endpoint 0 Data
Register 6
(HE0D6)
Read: HE0R67 HE0R66 HE0R65 HE0R64 HE0R63 HE0R62 HE0R61 HE0R60
Write: HE0T67
HE0T66
HE0T65
HE0T64
HE0T63
HE0T62
HE0T61
HE0T60
Reset:
X
X
X
X
X
X
X
X
$0037
USB HUB Endpoint 0 Data
Register 7
(HE0D7)
Read: HE0R77 HE0R76 HE0R75 HE0R74 HE0R73 HE0R72 HE0R71 HE0R70
Write: HE0T77
HE0T76
HE0T75
HE0T74
HE0T73
HE0T72
HE0T71
HE0T70
Reset:
X
X
X
X
X
X
X
X
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9.4.1 USB HUB Root Port Control Register (HRPCR)
RESUM0 -- Force Resume to the Root Port
This read/write bit forces a resume signal ("K" state) onto the USB
root port data lines to initiate a remote wakeup. Software should
control the timing of the forced resume to be between 10 ms and 15
ms. Reset clears this bit.
1 = Force root port data lines to "K" state
0 = Default
SUSPND -- USB Suspend Control Bit
To save power, this read/write bit should be set by the software if at
least 3ms constant idle state is detected on USB bus. Setting this bit
puts the transceiver and regulator into a power savings mode.
This bit also determines the latch scheme for the data lines of the root
port and the downstream port. When this bit is 1, the current state
shown on the data lines will be reflected to the data register (D+/D)
directly. When the bit is 0, the data registers are the latched state
sampled at the last EOF2 sample point. The hub repeater's function
is affected by this bit too. The upstream and downstream traffic will be
blocked if this bit is set to 1. When the global resume or the
downstream remote wakeup signal is found by the suspend hub,
software is responsible to propagate the traffic between the root port
and the enabled downstream port by setting the RESUMx control bit.
Reset clears this bit.
Address:
$005E
Bit 7
6
5
4
3
2
1
Bit 0
Read:
0
0
0
RESUM0 SUSPND
0
D0+
D0
Write:
Reset:
0
0
0
0
0
0
X
X
= Unimplemented
X = Indeterminate
Figure 9-2. USB HUB Root Port Control Register (HRPCR)
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Universal Serial Bus Module (USB)
I/O Register Description of the HUB function
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EOF2 is generated by KH12 every millisecond, if SOF is not detected
when three or more EOF2 has occurred, software can set the
SUSPND-bit and put KH12 into suspend mode.
D0+/D0 -- Root Port Differential Data
These read only bits are the differential data shown on the HUB root
ports. When the bit SUSPND is 0, the data is the latched state at the
last EOF2 sample point. When the bit SUSPND is 1, the data reflects
the current state on the data line while accessing this register.
9.4.2 USB HUB Downstream Port Control Register (HDP1CR-HDP4CR)
PEN1-PEN4 -- Downstream Port Enable Control Bit
This read/write bit determines whether the enabled or disabled state
should be assigned to the downstream port. Setting this bit 1 to
enable the port and clear the bit to disable the port. In the enabled
state a full-speed port propagates all downstream signaling, a low-
speed port propagates downstream low-speed packet traffic when
preceded by the preamble PID. An enabled port propagates all
upstream signaling including full speed and low speed packets. This
Address: $0051
Bit 7
6
5
4
3
2
1
Bit 0
Read:
PEN1
LOWSP1
RST1
RESUM1
SUSP1
0
D1+
D1
Write:
Reset:
0
0
0
0
0
0
X
X
Address: $0054
Read:
PEN4
LOWSP4
RST4
RESUM4
SUSP4
0
D4+
D4
Write:
Reset:
0
0
0
0
0
0
X
X
= Unimplemented
X = Indeterminate
Figure 9-3. USB HUB Downstream Port Control Registers
(HDP1CR-HDP4CR)
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bit can be set to 1 by the host request only. It can be cleared either by
hardware when a fault condition was detected or by software through
the host request. Reset clears this bit.
1 = Downstream port is enabled
0 = Downstream port is disabled
LOWSP1-LOWSP4 -- Full Speed / Low Speed Port Control Bit
This read/write bit specifies the attached device in the downstream
port is low speed device or full speed device. Software is responsible
to detect the device attachment and whether a device is full or low
speed. Reset clears this bit.
1 = Downstream port is low speed
0 = Downstream port is full speed
NOTE:
after a port is enabled, HUB will automatically generate a low speed
keep awake signal to the port every millisecond.
RST1-RST4 -- Force Reset to the Downstream Port
This read/write bit forces a reset signal (SE0 state) onto the USB
downstream port data lines. This bit can be set by the host request
SetPortFeature (PORT_RESET) only. Software should control the
timing of the forced reset signaling downstream for at least 10 ms.
Reset clears this bit.
1 = Force downstream port data lines to SE0 state
0 = Default
RESUM1-RESUM4 -- Force Resume to the Downstream Port
This read/write bit forces a resume signal ("K" state) onto the USB
downstream port data lines. This bit is set to reflect the resume signal
when the software detects the remote resume signal on the data lines
of the selective suspend downstream port. Downstream selective
resume sequence to a port may also be initiated via the host request
ClearPortFeature (PORT_SUSPEND). Software should control the
timing of the forced resume signaling downstream for at least 20 ms.
To indicate the end of the resume, a low speed EOP signal will be
followed when this control bit changes from 1 to 0. Reset clears this
bit.
1 = Force downstream port data lines to "K" state
0 = Default
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Universal Serial Bus Module (USB)
I/O Register Description of the HUB function
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SUSP1-SUSP4 -- Downstream Port Selective Suspend Bit
This read/write bit forces the downstream port entering the selective
suspend mode. This bit can be set by the host request
SetPortFeature (PORT_SUSPEND) only. When this bit is set, the hub
prevents propagating any bus activity (except the port reset or port
resume request or the global reset signal) downstream, and the port
can only reflect upstream bus state changes via the endpoint 1 of the
hub. The blocking occurs at the next EOF2 point when this bit is set.
Reset clears this bit.
1 = Force downstream port enters the selective suspend mode
0 = Default
D1+/D1 to D4+/D4 -- Downstream Port Differential Data
These read only bits are the differential data shown on the HUB
downstream ports. When the bit SUSPND in the register HRPCR is 0,
the data is the latched state at the last EOF2 sample point. When the
bit SUSPND is 1, the data reflects the current state on the data line
while accessing this register.
9.4.3 USB SIE Timing Interrupt Register (SIETIR)
Address:
$0056
Bit 7
6
5
4
3
2
1
Bit 0
Read:
SOFF
EOF2F
EOPF
TRANF
SOFIE
EOF2IE
EOPIE
TRANIE
Write:
Reset:
0
0
0
0
0
0
0
0
= Unimplemented
Figure 9-4. USB SIE Timing Interrupt Register (SIETIR)
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SOFF -- Start Of Frame Detect Flag
This read only bit is set when a valid SOF PID is detected on the D0+
and D0 lines at the root port. Software must clear this flag by writing
a logic 1 to SOFFR bit in the SIETSR register. Reset clears this bit.
Writing to SOFF has no effect.
1 = Start Of Frame PID has been detected
0 = Start Of Frame PID has not been detected
EOF2F -- The second End Of Frame Point Flag
This read only bit is set when the internal frame timer counts to the bit
time that the hub must see upstream traffic terminated near the end
of frame. This bit time is defined as 10 bit times from the next Start of
Frame PID. Software must clear this flag by writing a logic 1 to
EOF2FR bit in the SIETSR register. Reset clears this bit. Writing to
EOF2F has no effect.
1 = Frame timer counts to the EOF2 point
0 = Frame timer does not count to the EOF2 point
EOPF -- End of Packet Detect Flag
This read only bit is set when a valid End-of-Packet sequence is
detected on the D0+ and D0 lines. Software must clear this flag by
writing a logic 1 to the EOPFR bit in the SIETSR register. Reset clears
this bit. Writing to EOPF has no effect.
1 = End-of-Packet sequence has been detected
0 = End-of-Packet sequence has not been detected
TRANF -- Bus Signal Transition Detect Flag
This read only bit is set if there is any bus activity on the upstream or
the downstream data lines. Generally speaking, this bit is used to
wakeup the suspended hub when there is any bus activity occurred.
Software must clear this flag by writing a logic 1 to the TRANFR bit in
the SIETSR register. Reset clears this bit. Writing to TRANF has no
effect.
1 = Signal transition has been detected
0 = Signal transition has not been detected
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Universal Serial Bus Module (USB)
I/O Register Description of the HUB function
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SOFIE -- Start Of Frame Interrupt Enable
This read/write bit enables the Start Of Frame to generate a USB
interrupt when the SOFF bit becomes set. Reset clears this bit.
1 = USB interrupt enabled for Start Of Frame
0 = USB interrupt disabled for Start Of Frame
EOF2IE -- The Second End of Frame Point Interrupt Enable
This read/write bit enables the Second End Of Frame to generate a
USB interrupt when the EOF2F bit becomes set. Reset clears this bit.
1 = USB interrupt enabled for the Second End Of Frame Point
0 = USB interrupt disabled for the Second End Of Frame Point
EOPIE -- End of Packet Detect Interrupt Enable
This read/write bit enables the USB to generate a interrupt request
when the EOPF bit becomes set. Reset clears the bit.
1 = USB interrupt enabled for End-of-Packet sequence detection
0 = USB interrupt disabled for End-of-Packet sequence detection
TRANIE -- Bus Signal Transition Detect Interrupt Enable
This read/write bit enables the Signal Transition to generate a USB
interrupt when the TRANF bit becomes set. Reset clears this bit.
1 = USB interrupt enabled for Bus Signal Transition
0 = USB interrupt disabled for Bus Signal Transition
9.4.4 USB SIE Timing Status Register (SIETSR)
Address:
$0057
Bit 7
6
5
4
3
2
1
Bit 0
Read:
RSTF
0
LOCKF
0
0
0
0
0
Write:
RSTFR
LOCKFR
SOFFR
EOF2FR
EOPFR
TRANFR
Reset:
0**
0
0
0
0
0
0
0
= Unimplemented
0** = Reset by POR only
Figure 9-5. USB SIE Timing Status Register (SIETSR)
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RSTF -- USB Reset Flag
This read only bit is set when a valid reset signal state is detected on
the D0+ and D0- lines. This reset detection will also generate an
internal reset signal to reset the CPU and other peripherals including
the USB module. This bit is cleared by writing a logic 1 to the RSTFR
bit.
NOTE:
** Please note RSTF bit is only be reset by a POR reset.
RSTFR -- Clear Reset Indicator Bit
Writing a logic 1 to this write only bit will clear the RSTF bit if it is set.
Writing a logic 0 to the RSTFR has no effect. Reset clears this bit.
LOCKF -- USB Frame Timer Locked
This read only bit is set when the internal frame timer is locked to the
host timer. This bit is cleared by writing a logic 1 to the LOCKFR bit.
Reset clears this bit.
LOCKFR -- Clear Frame Timer Locked Flag
Writing a logic 1 to this write only bit will clear the LOCKF bit if it is set.
Writing a logic 0 to the LOCKFR has no effect. Reset clears this bit.
SOFFR -- Start Of Frame Flag Reset
Writing a logic 1 to this write only bit will clear the SOFF bit if it is set.
Writing a logic 0 to the SOFFR has no effect. Reset clears this bit.
EOF2FR -- The Second End of Frame Point Flag Reset
Writing a logic 1 to this write only bit will clear the EOF2F bit if it is set.
Writing a logic 0 to the EOF2FR has no effect. Reset clears this bit.
EOPFR -- End of Packet Flag Reset
Writing a logic 1 to this write only bit will clear the EOPF bit if it is set.
Writing a logic 0 to the EOPFR has no effect. Reset clears this bit.
TRANFR -- Bus Signal Transition Flag Reset
Writing a logic 1 to this write only bit will clear the TRANF bit if it is set.
Writing a logic 0 to the TRANFR has no effect. Reset clears this bit.
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Universal Serial Bus Module (USB)
I/O Register Description of the HUB function
MC68HC(7)08KH12
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127
9.4.5 USB HUB Address Register (HADDR)
USBEN -- USB Module Enable
This read/write bit enables and disables the USB module. When
USBEN is cleared, the USB module will not respond to any tokens
and the external regulated output REGOUT will be turned off.
NOTE:
**USBEN bit can only be cleared by a POR reset.
1 = USB function enabled
0 = USB function disabled, USB transceiver is also disabled to
save power.
ADD6-ADD0 -- USB HUB Function Address
These bits specify the address of the HUB function. Reset clears these
bits.
Address:
$0058
Bit 7
6
5
4
3
2
1
Bit 0
Read:
USBEN
ADD6
ADD5
ADD4
ADD3
ADD2
ADD1
ADD0
Write:
Reset:
0**
0
0
0
0
0
0
0
0** = Reset by POR only
Figure 9-6. USB HUB Address Register (HADDR)
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9.4.6 USB HUB Interrupt Register 0 (HIR0)
TXDF -- HUB Endpoint 0 Data Transmit Flag
This read only bit is set after the data stored in HUB Endpoint 0
transmit buffers has been sent and an ACK handshake packet from
the host is received. Once the next set of data is ready in the transmit
buffers, software must clear this flag by writing a logic 1 to the TXDFR
bit. To enable the next data packet transmission, TXE must also be
set. If TXDF bit is not cleared, a NAK handshake will be returned in
the next IN transaction.
Reset clears this bit. Writing to TXDF has no effect.
1 = Transmit on HUB Endpoint 0 has occurred
0 = Transmit on HUB Endpoint 0 has not occurred
RXDF -- HUB Endpoint 0 Data Receive Flag
This read only bit is set after the USB HUB function has received a
data packet and responded with an ACK handshake packet. Software
must clear this flag by writing a logic 1 to the RXDFR bit after all of the
received data has been read. Software must also set RXE bit to one
to enable the next data packet reception. If RXDF bit is not cleared, a
NAK handshake will be returned in the next OUT transaction.
Reset clears this bit. Writing to RXDF has no effect.
1 = Receive on HUB Endpoint 0 has occurred
0 = Receive on HUB Endpoint 0 has not occurred
Address:
$0059
Bit 7
6
5
4
3
2
1
Bit 0
Read:
TXDF
RXDF
0
0
TXDIE
RXDIE
0
0
Write:
TXDFR
RXDFR
Reset:
0
0
0
0
0
0
0
0
= Unimplemented
Figure 9-7. USB HUB Interrupt Register 0 (HIR0)
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Universal Serial Bus Module (USB)
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TXDIE -- HUB Endpoint 0 Transmit Interrupt Enable
This read/write bit enables the Transmit HUB Endpoint 0 to generate
CPU interrupt requests when the TXDF bit becomes set. Reset clears
the TXDIE bit.
1 = USB interrupt enabled for Transmit HUB Endpoint 0
0 = USB interrupt disabled for Transmit HUB Endpoint 0
RXDIE -- HUB Endpoint 0 Receive Interrupt Enable
This read/write bit enables the Receive HUB Endpoint 0 to generate
CPU interrupt requests when the RXDF bit becomes set. Reset clears
the RXDIE bit.
1 = USB interrupt enabled for Receive HUB Endpoint 0
0 = USB interrupt disabled for Receive HUB Endpoint 0
TXDFR -- HUB Endpoint 0 Transmit Flag Reset
Writing a logic 1 to this write only bit will clear the TXDF bit if it is set.
Writing a logic 0 to TXDFR has no effect. Reset clears this bit.
RXDFR -- HUB Endpoint 0 Receive Flag Reset
Writing a logic 1 to this write only bit will clear the RXDF bit if it is set.
Writing a logic 0 to RXDFR has no effect. Reset clears this bit.
9.4.7 USB HUB Control Register 0 (HCR0)
Address:
$005B
Bit 7
6
5
4
3
2
1
Bit 0
Read:
TSEQ
STALL0
TXE
RXE
TPSIZ3
TPSIZ2
TPSIZ1
TPSIZ0
Write:
Reset:
0
0
0
0
0
0
0
0
Figure 9-8. USB HUB Control Register 0 (HCR0)
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TSEQ -- HUB Endpoint 0 Transmit Sequence Bit
This read/write bit determines which type of data packet (DATA0 or
DATA1) will be sent during the next IN transaction directed at
Endpoint 0. Toggling of this bit must be controlled by software. Reset
clears this bit.
1 = DATA1 Token active for next HUB Endpoint 0 transmit
0 = DATA0 Token active for next HUB Endpoint 0 transmit
STALL0 -- HUB Endpoint 0 Force Stall Bit
This read/write bit causes HUB Endpoint 0 to return a STALL
handshake when polled by either an IN or OUT token by the host. The
USB hardware clears this bit when a SETUP token is received. Reset
clears this bit.
1 = Send STALL handshake
0 = Default
TXE -- HUB Endpoint 0 Transmit Enable
This read/write bit enables a transmit to occur when the USB Host
controller sends an IN token to the HUB Endpoint 0. Software should
set this bit when data is ready to be transmitted. It must be cleared by
software when no more HUB Endpoint 0 data packets needs to be
transmitted. If this bit is 0 or the TXDF is set, the USB will respond with
a NAK handshake to any HUB Endpoint 0 IN tokens. Reset clears this
bit.
1 = Data is ready to be sent
0 = Data is not ready. Respond with NAK
RXE -- HUB Endpoint 0 Receive Enable
This read/write bit enables a receive to occur when the USB Host
controller sends an OUT token to the HUB Endpoint 0. Software
should set this bit when data is ready to be received. It must be
cleared by software when data cannot be received. If this bit is 0 or
the RXDF is set, the USB will respond with a NAK handshake to any
HUB Endpoint 0 OUT tokens. Reset clears this bit.
1 = Data is ready to be received
0 = Not ready for data. Respond with NAK
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Universal Serial Bus Module (USB)
I/O Register Description of the HUB function
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131
TPSIZ3-TPSIZ0 -- HUB Endpoint 0 Transmit Data Packet Size
These read/write bits store the number of transmit data bytes for the
next IN token request for HUB Endpoint 0. These bits are cleared by
reset.
9.4.8 USB HUB Endpoint1 Control & Data Register (HCDR)
STALL1 -- HUB Endpoint 1 Force Stall Bit
This read/write bit causes HUB Endpoint 1 to return a STALL
handshake when polled by the host. Reset clears this bit.
1 = Send STALL handshake
0 = Default
PNEW -- Port New Status Change
This read/write bit enables a transmit to occur when the USB Host
controller sends an IN token to HUB Endpoint 1. Software should set
this bit when there is any status change on the downstream ports,
embedded device or hub. It must be cleared by software when there
is no status change needs to be reported to the host through the
Endpoint1. If this bit is 0, a NAK handshake will be returned for next
IN token for HUB Endpoint 1. Reset clears this bit.
1 = Port status change bit is ready to be sent.
0 = Port status does not change. Respond with NAK.
Address:
$005C
Bit 7
6
5
4
3
2
1
Bit 0
Read:
STALL1
PNEW
PCHG5
PCHG4
PCHG3
PCHG2
PCHG1
PCHG0
Write:
Reset:
0
0
0
0
0
0
0
0
Figure 9-9. USB HUB Control Register 1 (HCR1)
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PCHG5-PCHG0 -- HUB and Port Status Change Bits
These read/write bits report the status change for the Hub, embedded
device and the four downstream ports. The Status Change Bitmap is
returned to the host through the HUB endpoint 1 if the bit PNEW is 1.
These bits are cleared by reset.
9.4.9 USB HUB Status Register (HSR)
Bit Name
Function
Value
Description
PCHG0
HUB status change
0
No status change in HUB
1
HUB status change detected
PCHG1
Port 1 status change
0
No status change in Port 1
1
Port 1 status change detected
PCHG2
Port 2 status change
0
No status change in Port 2
1
Port 2 status change detected
PCHG3
Port 3 status change
0
No status change in Port 3
1
Port 3 status change detected
PCHG4
Port 4 status change
0
No status change in Port 4
1
Port 4 status change detected
PCHG5
Embedded device
status change
0
No status change in
embedded device
1
Embedded device status
change detected
Address:
$005D
Bit 7
6
5
4
3
2
1
Bit 0
Read:
RSEQ
SETUP
TX1ST
0
RPSIZ3
RPSIZ2
RPSIZ1
RPSIZ0
Write:
TX1STR
Reset:
X
X
0
0
X
X
X
X
= Unimplemented
X = Indeterminate
Figure 9-10. USB HUB Status Register (HSR)
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Universal Serial Bus Module (USB)
I/O Register Description of the HUB function
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RSEQ -- HUB Endpoint 0 Receive Sequence Bit
This read only bit indicates the type of data packet last received for
HUB Endpoint 0 (DATA0 or DATA1).
1 = DATA1 Token received in last HUB Endpoint 0 Receive
0 = DATA0 Token received in last HUB Endpoint 0 Receive
SETUP -- HUB SETUP Token Detect Bit
This read only bit indicates that a valid SETUP token has been
received.
1 = Last token received for hub endpoint 0 was a SETUP token
0 = Last token received for hub endpoint 0 was not a SETUP token
TX1ST -- HUB Transmit First Flag
This read only bit is set if the HUB Endpoint 0 Data Transmit Flag
(TXDF) is set when the USB control logic is setting the HUB Endpoint
0 Data Receive Flag (RXDF). In other words, if an unserviced
Endpoint 0 Transmit Flag is still set at the end of an endpoint 0
reception, then this bit will be set. This bit lets the firmware know that
the Endpoint 0 transmission happened before the Endpoint 0
reception. Reset clears this bit.
1 = IN transaction occurred before SETUP/OUT
0 = IN transaction occurred after SETUP/OUT
TX1STR -- Clear HUB Transmit First Flag
Writing a logic 1 to this write only bit will clear the TX1ST bit if it is set.
Writing a logic 0 to the TX1STR has no effect. Reset clears this bit.
RPSIZ3-RPSIZ0 -- HUB Endpoint 0 Receive Data Packet Size
These read only bits store the number of data bytes received for the
last OUT or SETUP transaction for HUB Endpoint 0. These bits are
not affected by reset.
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9.4.10 USB HUB Endpoint 0 Data Registers 0-7 (HE0D0-HE0D7)
HE0Rx7-HE0Rx0 -- HUB Endpoint 0 Receive Data Buffer
These read only bits are serially loaded with OUT token or SETUP
token data directed at HUB Endpoint 0. The data is received over the
USB's D0+ and D0 pins.
HE0Tx7-HE0Tx0 -- HUB Endpoint 0 Transmit Data Buffer
These write only buffers are loaded by software with data to be sent
on the USB bus on the next IN token directed at HUB Endpoint 0.
9.5 I/O Register Description of the Embedded Device Function
The USB embedded device function provides a set of control/status
registers and twenty-four data registers that provide storage for the
buffering of data between the USB embedded device function and the
CPU. These registers are shown in
Table 9-3
and
Table 9-4
.
Address:
$0030
Bit 7
6
5
4
3
2
1
Bit 0
Read: HE0R07
HE0R06
HE0R05
HE0R04
HE0R03
HE0R02
HE0R01
HE0R00
Write:
HE0T07
HE0T06
HE0T05
HE0T04
HE0T03
HE0T02
HE0T01
HE0T00
Reset:
X
X
X
X
X
X
X
X
Address:
$0037
Read: HE0R77
HE0R76
HE0R75
HE0R74
HE0R73
HE0R72
HE0R71
HE0R70
Write:
HE0T77
HE0T76
HE0T75
HE0T74
HE0T73
HE0T72
HE0T71
HE0T70
Reset:
X
X
X
X
X
X
X
X
X = Indeterminate
Figure 9-11. USB HUB Endpoint 0 Data Register (HE0D0-HE0D7)
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Universal Serial Bus Module (USB)
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Table 9-3. Embedded Device Control Register Summary
Addr.
Register Name
Bit 7
6
5
4
3
2
1
Bit 0
$0047
USB Embedded Device
Control Register 2
(DCR2)
Read:
0
0
0
0
ENABLE2 ENABLE1 DSTALL2
DSTALL1
Write:
Reset:
0
0
0
0
0
0
0
0
$0048
USB Embedded Device
Address Register
(DADDR)
Read:
DEVEN
DADD6
DADD5
DADD4
DADD3
DADD2
DADD1
DADD0
Write:
Reset:
0
0
0
0
0
0
0
0
$0049
USB Embedded Device
Interrupt Register 0
(DIR0)
Read:
TXD0F
RXD0F
0
0
TXD0IE
RXD0IE
0
0
Write:
TXD0FR RXD0FR
Reset:
0
0
0
0
0
0
0
0
$004A
USB Embedded Device
Interrupt Register 1
(DIR1)
Read:
TXD1F
0
0
0
TXD1IE
0
0
0
Write:
TXD1FR
Reset:
0
0
0
0
0
0
0
0
$004B
USB Embedded Device
Control Register 0
(DCR0)
Read:
T0SEQ
DSTALL0
TX0E
RX0E
TP0SIZ3 TP0SIZ2 TP0SIZ1 TP0SIZ0
Write:
Reset:
0
0
0
0
0
0
0
0
$004C
USB Embedded Device
Control Register 1
(DCR1)
Read:
T1SEQ
ENDADD
TX1E
0