MOTOROLA
SEMICONDUCTOR TECHNICAL DATA
31
REV 6
Motorola, Inc. 1995
10/95
Octal D Flip-Flop with
Common Clock and Reset
HighPerformance SiliconGate CMOS
The MC54/74HC273A is identical in pinout to the LS273. The device
inputs are compatible with standard CMOS outputs; with pullup resistors,
they are compatible with LSTTL outputs.
This device consists of eight D flipflops with common Clock and Reset
inputs. Each flipflop is loaded with a lowtohigh transition of the Clock
input. Reset is asynchronous and active low.
Output Drive Capability: 10 LSTTL Loads
Outputs Directly Interface to CMOS, NMOS and TTL
Operating Voltage Range: 2.0 to 6.0 V
Low Input Current: 1.0
A
High Noise Immunity Characteristic of CMOS Devices
In Compliance with the Requirements Defined by JEDEC Standard
No. 7A
Chip Complexity: 264 FETs or 66 Equivalent Gates
LOGIC DIAGRAM
DATA
INPUTS
D0
11
CLOCK
D1
D2
D3
D4
D5
D6
D7
18
17
14
13
8
7
4
3
1
RESET
19
Q0
Q1
Q2
Q3
Q4
Q5
Q6
Q7
16
15
12
9
6
5
2
PIN 20 = VCC
PIN 10 = GND
NONINVERTING
OUTPUTS
Design Criteria
Value
Units
Internal Gate Count*
66
ea
Internal Gate Propagation Delay
1.5
ns
Internal Gate Power Dissipation
5.0
W
Speed Power Product
.0075
pJ
* Equivalent to a twoinput NAND gate.
MC54/74HC273A
PIN ASSIGNMENT
Q2
D1
D0
Q0
RESET
GND
Q3
D3
D2
Q1
5
4
3
2
1
10
9
8
7
6
14
15
16
17
18
19
20
11
12
13
Q6
D6
D7
Q7
VCC
CLOCK
Q4
D4
D5
Q5
FUNCTION TABLE
Inputs
Output
Reset
Clock
D
Q
L
X
X
L
H
H
H
H
L
L
H
L
X
No Change
H
X
No Change
DW SUFFIX
SOIC PACKAGE
CASE 751D04
N SUFFIX
PLASTIC PACKAGE
CASE 73803
ORDERING INFORMATION
MC54HCXXXAJ
MC74HCXXXAN
MC74HCXXXADW
MC74HCXXXADT
Ceramic
Plastic
SOIC
TSSOP
DT SUFFIX
TSSOP PACKAGE
CASE 948E02
J SUFFIX
CERAMIC PACKAGE
CASE 73203
1
20
1
20
1
20
1
20
MC54/74HC273A
MOTOROLA
HighSpeed CMOS Logic Data
DL129 -- Rev 6
32
MAXIMUM RATINGS*
Symbol
Parameter
Value
Unit
VCC
DC Supply Voltage (Referenced to GND)
0.5 to + 7.0
V
Vin
DC Input Voltage (Referenced to GND)
1.5 to VCC + 1.5
V
Vout
DC Output Voltage (Referenced to GND)
0.5 to VCC + 0.5
V
Iin
DC Input Current, per Pin
20
mA
Iout
DC Output Current, per Pin
25
mA
ICC
DC Supply Current, VCC and GND Pins
50
mA
PD
Power Dissipation in Still Air, Plastic or Ceramic DIP
SOIC Package
TSSOP Package
750
500
450
mW
Tstg
Storage Temperature
65 to + 150
_
C
TL
Lead Temperature, 1 mm from Case for 10 Seconds
Plastic DIP, SOIC or TSSOP Package
(Ceramic DIP)
260
300
_
C
* Maximum Ratings are those values beyond which damage to the device may occur.
Functional operation should be restricted to the Recommended Operating Conditions.
Derating -- Plastic DIP: 10 mW/
_
C from 65
_
to 125
_
C
Ceramic DIP: 10 mW/
_
C from 100
_
to 125
_
C
SOIC Package: 7 mW/
_
C from 65
_
to 125
_
C
TSSOP Package: 6.1 mW/
_
C from 65
_
to 125
_
C
For high frequency or heavy load considerations, see Chapter 2 of the Motorola HighSpeed CMOS Data Book (DL129/D).
RECOMMENDED OPERATING CONDITIONS
Symbol
Parameter
Min
Max
Unit
VCC
DC Supply Voltage (Referenced to GND)
2.0
6.0
V
Vin, Vout
DC Input Voltage, Output Voltage (Referenced to GND)
0
VCC
V
TA
Operating Temperature, All Package Types
55
+ 125
_
C
tr, tf
Input Rise and Fall Time
VCC = 2.0 V
(Figure 1)
VCC = 4.5 V
VCC = 6.0 V
0
0
0
1000
500
400
ns
DC ELECTRICAL CHARACTERISTICS
(Voltages Referenced to GND)
Symbol
Parameter
Test Conditions
VCC
V
Guaranteed Limit
Unit
Symbol
Parameter
Test Conditions
VCC
V
55 to
25
_
C
v
85
_
C
v
125
_
C
Unit
VIH
Minimum HighLevel Input
Voltage
Vout = 0.1 V or VCC 0.1 V
|Iout|
v
20
A
2.0
4.5
6.0
1.5
3.15
4.2
1.5
3.15
4.2
1.5
3.15
4.2
V
VIL
Maximum LowLevel Input
Voltage
Vout = 0.1 V or VCC 0.1 V
|Iout|
v
20
A
2.0
4.5
6.0
0.5
1.35
1.8
0.5
1.35
1.8
0.5
1.35
1.8
V
VOH
Minimum HighLevel Output
Voltage
Vin = VIH or VIL
|Iout|
v
20
A
2.0
4.5
6.0
1.9
4.4
5.9
1.9
4.4
5.9
1.9
4.4
5.9
V
Vin = VIH or VIL
|Iout|
v
4.0 mA
|Iout|
v
5.2 mA
4.5
6.0
3.98
5.48
3.84
5.34
3.7
5.2
This device contains protection
circuitry to guard against damage
due to high static voltages or electric
fields. However, precautions must
be taken to avoid applications of any
voltage higher than maximum rated
voltages to this highimpedance cir-
cuit. For proper operation, Vin and
Vout should be constrained to the
range GND
v
(Vin or Vout)
v
VCC.
Unused inputs must always be
tied to an appropriate logic voltage
level (e.g., either GND or VCC).
Unused outputs must be left open.
MC54/74HC273A
HighSpeed CMOS Logic Data
DL129 -- Rev 6
33
MOTOROLA
DC ELECTRICAL CHARACTERISTICS
(Voltages Referenced to GND)
Unit
Guaranteed Limit
VCC
V
Test Conditions
Parameter
Symbol
Unit
v
125
_
C
v
85
_
C
55 to
25
_
C
VCC
V
Test Conditions
Parameter
Symbol
VOL
Maximum LowLevel Output
Voltage
Vout = 0.1 V or VCC 0.1 V
|Iout|
v
20
A
2.0
4.5
6.0
0.1
0.1
0.1
0.1
0.1
0.1
0.1
0.1
0.1
V
Vin = VIH or VIL
|Iout|
v
4.0 mA
|Iout|
v
5.2 mA
4.5
6.0
0.26
0.26
0.33
0.33
0.4
0.4
Iin
Maximum Input Leakage Current
Vin = VCC or GND
6.0
0.1
1.0
1.0
A
ICC
Maximum Quiescent Supply
Current (per Package)
Vin = VCC or GND
Iout = 0
A
6.0
4.0
40
160
A
NOTE: Information on typical parametric values can be found in Chapter 2 of the Motorola HighSpeed CMOS Data Book (DL129/D).
AC ELECTRICAL CHARACTERISTICS
(CL = 50 pF, Input tr = tf = 6.0 ns)
Symbol
Parameter
VCC
V
Guaranteed Limit
Unit
Symbol
Parameter
VCC
V
55 to
25
_
C
v
85
_
C
v
125
_
C
Unit
fmax
Maximum Clock Frequency (50% Duty Cycle)
(Figures 1 and 4)
2.0
4.5
6.0
6.0
30
35
5.0
24
28
4.0
20
24
MHz
tPLH
tPHL
Maximum Propagation Delay, Clock to Q
(Figures 1 and 4)
2.0
4.5
6.0
145
29
25
180
36
31
220
44
38
ns
tPHL
Maximum Propagation Delay, Reset to Q
(Figures 2 and 4)
2.0
4.5
6.0
145
29
25
180
36
31
220
44
38
ns
tTLH
tTHL
Maximum Output Transition Time, Any Output
(Figures 1 and 4)
2.0
4.5
6.0
75
15
13
95
19
16
110
22
19
ns
Cin
Maximum Input Capacitance
10
10
10
pF
NOTE: For propagation delays with loads other than 50 pF, and information on typical parametric values, see Chapter 2 of the Motorola High
Speed CMOS Data Book (DL129/D).
CPD
Power Dissipation Capacitance (Per Enabled Output)*
Typical @ 25
C, VCC = 5.0 V
pF
CPD
Power Dissipation Capacitance (Per Enabled Output)*
48
pF
* Used to determine the noload dynamic power consumption: PD = CPD VCC2f + ICC VCC. For load considerations, see Chapter 2 of the
Motorola HighSpeed CMOS Data Book (DL129/D).
MC54/74HC273A
MOTOROLA
HighSpeed CMOS Logic Data
DL129 -- Rev 6
34
TIMING REQUIREMENTS
(CL = 50 pF, Input tr = tf = 6.0 ns)
Symbol
Parameter
Fig.
VCC
Volts
Guaranteed Limit
Unit
Symbol
Parameter
Fig.
VCC
Volts
55 to 25
_
C
v
85
_
C
v
125
_
C
Unit
Symbol
Parameter
Fig.
VCC
Volts
Min
Max
Min
Max
Min
Max
Unit
tsu
Minimum Setup Time, Data to Clock
3
2.0
4.5
6.0
60
12
10
75
15
13
90
18
15
ns
th
Minimum Hold Time, Clock to Data
3
2.0
4.5
6.0
3.0
3.0
3.0
3.0
3.0
3.0
3.0
3.0
3.0
ns
trec
Minimum Recovery Time, Reset Inactive to
Clock
2
2.0
4.5
6.0
5.0
5.0
5.0
5.0
5.0
5.0
5.0
5.0
5.0
ns
tw
Minimum Pulse Width, Clock
1
2.0
4.5
6.0
60
12
10
75
15
13
90
18
15
ns
tw
Minimum Pulse Width, Reset
2
2.0
4.5
6.0
60
12
10
75
15
13
90
18
15
ns
tr, tf
Maximum Input Rise and Fall Times
1
2.0
4.5
6.0
1000
500
400
1000
500
400
1000
500
400
ns
MC54/74HC273A
HighSpeed CMOS Logic Data
DL129 -- Rev 6
35
MOTOROLA
SWITCHING WAVEFORMS
Figure 1.
CLOCK
Q
tr
tf
VCC
GND
90%
50%
10%
90%
50%
10%
tPLH
tPHL
tTLH
tTHL
50%
DATA
CLOCK
VCC
Figure 2.
VALID
GND
* Includes all probe and jig capacitance
CL*
TEST POINT
DEVICE
UNDER
TEST
OUTPUT
Figure 3.
tw
1/fmax
VCC
GND
tsu
th
50%
RESET
Q
CLOCK
tw
50%
50%
50%
VCC
GND
VCC
GND
tPHL
Figure 4. Test Circuit
trec
EXPANDED LOGIC DIAGRAM
C
D R
Q
D0
3
2
Q0
C
D R
Q
D1
4
5
Q1
C
D R
Q
D2
7
6
Q2
C
D R
Q
D3
8
9
Q3
C
D R
Q
D4
13
12
Q4
C
D R
Q
D5
14
15
Q5
C
D R
Q
D6
17
16
Q6
C
D R
Q
D7
18
19
Q7
11
1
DATA
INPUTS
NONINVERTING
OUTPUTS
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