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Электронный компонент: 74HC4075

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MOTOROLA
SEMICONDUCTOR TECHNICAL DATA
1
REV 6
Motorola, Inc. 1995
10/95
Triple 3-Input OR Gate
HighPerformance SiliconGate CMOS
The MC74HC4075 is identical in pinout to the MC14075B. The device
inputs are compatible with standard CMOS outputs; with pullup resistors,
they are compatible with LSTTL outputs.
Output Drive Capability: 10 LSTTL Loads
Outputs Directly Interface to CMOS, NMOS, and TTL
Operating Voltage Range: 2 to 6 V
Low Input Current: 1
A
High Noise Immunity Characteristic of CMOS Devices
In Compliance with the Requirements Defined by JEDEC Standard
No. 7A
Chip Complexity: 42 FETs or 10.5 Equivalent Gates
LOGIC DIAGRAM
A1
13
12
11
5
4
3
8
2
1
B1
C1
A2
B2
C2
A3
B3
C3
10
6
9
Y3
Y2
Y1
Y = A + B + C
PIN 14 = VCC
PIN 7 = GND
MC74HC4075
FUNCTION TABLE
PIN ASSIGNMENT
11
12
13
14
8
9
10
5
4
3
2
1
7
6
Y3
A3
B3
C3
VCC
C1
Y1
B2
A2
B1
A1
GND
Y2
C2
Inputs
Output
A
B
C
Y
L
L
L
L
H
X
X
H
X
H
X
H
X
X
H
H
D SUFFIX
SOIC PACKAGE
CASE 751A03
N SUFFIX
PLASTIC PACKAGE
CASE 64606
1
14
1
14
ORDERING INFORMATION
MC74HCXXXXN
MC74HCXXXXD
Plastic
SOIC
MC74HC4075
MOTOROLA
HighSpeed CMOS Logic Data
DL129 -- Rev 6
2
MAXIMUM RATINGS*
Symbol
Parameter
Value
Unit
VCC
DC Supply Voltage (Referenced to GND)
0.5 to + 7.0
V
Vin
DC Input Voltage (Referenced to GND)
1.5 to VCC + 1.5
V
Vout
DC Output Voltage (Referenced to GND)
0.5 to VCC + 0.5
V
Iin
DC Input Current, per Pin
20
mA
Iout
DC Output Current, per Pin
25
mA
ICC
DC Supply Current, VCC and GND Pins
50
mA
PD
Power Dissipation in Still Air
Plastic DIP
SOIC Package
750
500
mW
Tstg
Storage Temperature
65 to + 150
_
C
TL
Lead Temperature, 1 mm from Case for 10 Seconds
(Plastic DIP or SOIC Package)
260
_
C
* Maximum Ratings are those values beyond which damage to the device may occur.
Functional operation should be restricted to the Recommended Operating Conditions.
Derating -- Plastic DIP: 10 mW/
_
C from 65
_
to 125
_
C
SOIC Package: 7 mW/
_
C from 65
_
to 125
_
C
For high frequency or heavy load considerations, see Chapter 2 of the Motorola HighSpeed CMOS Data Book (DL129/D).
RECOMMENDED OPERATING CONDITIONS
Symbol
Parameter
Min
Max
Unit
VCC
DC Supply Voltage (Referenced to GND)
2.0
6.0
V
Vin, Vout
DC Input Voltage, Output Voltage (Referenced to GND)
0
VCC
V
TA
Operating Temperature, All Package Types
55
+ 125
_
C
tr, tf
Input Rise and Fall Time
VCC = 2.0 V
(Figure 1)
VCC = 4.5 V
VCC = 6.0 V
0
0
0
1000
500
400
ns
DC ELECTRICAL CHARACTERISTICS
(Voltages Referenced to GND)
Symbol
Parameter
Test Conditions
VCC
V
Guaranteed Limit
Unit
Symbol
Parameter
Test Conditions
VCC
V
55 to
25
_
C
v
85
_
C
v
125
_
C
Unit
VIH
Minimum HighLevel Input
Voltage
Vout = 0.1 V or VCC 0.1 V
|Iout|
v
20
A
2.0
4.5
6.0
1.5
3.15
4.2
1.5
3.15
4.2
1.5
3.15
4.2
V
VIL
Maximum LowLevel Input
Voltage
Vout = 0.1 V or VCC 0.1 V
|Iout|
v
20
A
2.0
4.5
6.0
0.3
0.9
1.2
0.3
0.9
1.2
0.3
0.9
1.2
V
VOH
Minimum HighLevel Output
Voltage
Vin = VIH or VIL
|Iout|
v
20
A
2.0
4.5
6.0
1.9
4.4
5.9
1.9
4.4
5.9
1.9
4.4
5.9
V
Vin = VIH or VIL |Iout|
v
4.0 mA
|Iout|
v
5.2 mA
4.5
6.0
3.98
5.48
3.84
5.34
3.70
5.20
VOL
Maximum LowLevel Output
Voltage
Vin = VIH or VIL
|Iout|
v
20
A
2.0
4.5
6.0
0.1
0.1
0.1
0.1
0.1
0.1
0.1
0.1
0.1
V
Vin = VIH or VIL |Iout|
v
4.0 mA
|Iout|
v
5.2 mA
4.5
6.0
0.26
0.26
0.33
0.33
0.40
0.40
Iin
Maximum Input Leakage Current
Vin = VCC or GND
6.0
0.1
1.0
1.0
A
ICC
Maximum Quiescent Supply
Current (per Package)
Vin = VCC or GND
Iout = 0
A
6.0
2
20
40
A
NOTE: Information on typical parametric values can be found in Chapter 2 of the Motorola HighSpeed CMOS Data Book (DL129/D).
This device contains protection
circuitry to guard against damage
due to high static voltages or electric
fields. However, precautions must
be taken to avoid applications of any
voltage higher than maximum rated
voltages to this highimpedance cir-
cuit. For proper operation, Vin and
Vout should be constrained to the
range GND
v
(Vin or Vout)
v
VCC.
Unused inputs must always be
tied to an appropriate logic voltage
level (e.g., either GND or VCC).
Unused outputs must be left open.
MC74HC4075
HighSpeed CMOS Logic Data
DL129 -- Rev 6
3
MOTOROLA
AC ELECTRICAL CHARACTERISTICS
(CL = 50 pF, Input tr = tf = 6 ns)
Symbol
Parameter
VCC
V
Guaranteed Limit
Unit
Symbol
Parameter
VCC
V
55 to
25
_
C
v
85
_
C
v
125
_
C
Unit
tPLH,
tPHL
Maximum Propagation Delay, Input A, B, or C to Output Y
(Figures 1 and 2)
2.0
4.5
6.0
115
23
20
145
29
25
175
35
30
ns
tTLH,
tTHL
Maximum Output Transition Time, Any Output
(Figures 1 and 2)
2.0
4.5
6.0
75
15
13
95
19
16
110
22
19
ns
Cin
Maximum Input Capacitance
--
10
10
10
pF
NOTES:
1. For propagation delays with loads other than 50 pF, see Chapter 2 of the Motorola HighSpeed CMOS Data Book (DL129/D).
2. Information on typical parametric values can be found in Chapter 2 of the Motorola HighSpeed CMOS Data Book (DL129/D).
CPD
Power Dissipation Capacitance (Per Gate)*
Typical @ 25
C, VCC = 5.0 V
pF
CPD
Power Dissipation Capacitance (Per Gate)*
26
pF
* Used to determine the noload dynamic power consumption: PD = CPD VCC2f + ICC VCC. For load considerations, see Chapter 2 of the
Motorola HighSpeed CMOS Data Book (DL129/D).
tr
tf
VCC
GND
90%
50%
10%
INPUT
A, B OR C
OUTPUT Y
tPLH
tPHL
tTLH
tTHL
A
B
C
Y
Figure 1. Switching Waveforms
EXPANDED LOGIC DIAGRAM
(1/3 of the Device)
90%
50%
10%
* Includes all probe and jig capacitance
Figure 2. Test Circuit
CL*
TEST POINT
DEVICE
UNDER
TEST
OUTPUT
MC74HC4075
MOTOROLA
HighSpeed CMOS Logic Data
DL129 -- Rev 6
4
OUTLINE DIMENSIONS
N SUFFIX
PLASTIC DIP PACKAGE
CASE 64606
ISSUE L
NOTES:
1. LEADS WITHIN 0.13 (0.005) RADIUS OF TRUE
POSITION AT SEATING PLANE AT MAXIMUM
MATERIAL CONDITION.
2. DIMENSION L TO CENTER OF LEADS WHEN
FORMED PARALLEL.
3. DIMENSION B DOES NOT INCLUDE MOLD
FLASH.
4. ROUNDED CORNERS OPTIONAL.
1
7
14
8
B
A
F
H
G
D
K
C
N
L
J
M
SEATING
PLANE
DIM
MIN
MAX
MIN
MAX
MILLIMETERS
INCHES
A
0.715
0.770
18.16
19.56
B
0.240
0.260
6.10
6.60
C
0.145
0.185
3.69
4.69
D
0.015
0.021
0.38
0.53
F
0.040
0.070
1.02
1.78
G
0.100 BSC
2.54 BSC
H
0.052
0.095
1.32
2.41
J
0.008
0.015
0.20
0.38
K
0.115
0.135
2.92
3.43
L
0.300 BSC
7.62 BSC
M
0
10
0
10
N
0.015
0.039
0.39
1.01
_
_
_
_
D SUFFIX
PLASTIC SOIC PACKAGE
CASE 751A03
ISSUE F
MIN
MIN
MAX
MAX
MILLIMETERS
INCHES
DIM
A
B
C
D
F
G
J
K
M
P
R
8.55
3.80
1.35
0.35
0.40
0.19
0.10
0
5.80
0.25
8.75
4.00
1.75
0.49
1.25
0.25
0.25
7
6.20
0.50
0.337
0.150
0.054
0.014
0.016
0.008
0.004
0
0.228
0.010
0.344
0.157
0.068
0.019
0.049
0.009
0.009
7
0.244
0.019
1.27 BSC
0.050 BSC
NOTES:
1. DIMENSIONING AND TOLERANCING PER ANSI
Y14.5M, 1982.
2. CONTROLLING DIMENSION: MILLIMETER.
3. DIMENSIONS A AND B DO NOT INCLUDE
MOLD PROTRUSION.
4. MAXIMUM MOLD PROTRUSION 0.15 (0.006)
PER SIDE.
5. DIMENSION D DOES NOT INCLUDE DAMBAR
PROTRUSION. ALLOWABLE DAMBAR
PROTRUSION SHALL BE 0.127 (0.005) TOTAL
IN EXCESS OF THE D DIMENSION AT
MAXIMUM MATERIAL CONDITION.
A
B
P
7 PL
G
C
K
SEATING
PLANE
D
14 PL
M
J
R
X 45
1
7
8
14
0.25 (0.010)
T
B
A
M
S
S
B
0.25 (0.010)
M
M
F
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the suitability of its products for any particular purpose, nor does Motorola assume any liability arising out of the application or use of any product or circuit,
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MC74HC4075/D
*MC74HC4075/D*
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