MOTOROLA
SEMICONDUCTOR TECHNICAL DATA
1
REV 6
Motorola, Inc. 1995
10/95
8-Bit Equality Comparator
HighPerformance SiliconGate CMOS
The MC54/74HC688 is identical in pinout to the LS688. The device inputs
are compatible with standard CMOS outputs; with pullup resistors, they are
compatible with LSTTL outputs.
The HC688 compares two 8bit binary or BCD words and indicates
whether or not they are equal. By using the Cascade Input, two or more of
the devices may be cascaded to compare words of more than 8 bits.
Output Drive Capability: 10 LSTTL Loads
Outputs Directly Interface to CMOS, NMOS, and TTL
Operating Voltage Range: 2 to 6 V
Low Input Current: 1
A
High Noise Immunity Characteristic of CMOS Devices
In Compliance with the Requirements Defined by JEDEC Standard
No. 7A
Chip Complexity: 116 FETs or 29 Equivalent Gates
LOGIC DIAGRAM
2
4
6
8
11
13
15
17
3
5
7
9
1
A0
A1
A2
A3
A4
A5
A6
A7
CASCADE
INPUT
PIN 20 = VCC
PIN 10 = GND
19
A = B
OUTPUT
DATA
WORD
A
INPUTS
DATA
WORD
B
INPUTS
12
14
16
18
B0
B1
B2
B3
B4
B5
B6
B7
MC54/74HC688
PIN ASSIGNMENT
FUNCTION TABLE
A2
A1
B0
A0
CASCADE
INPUT
GND
B3
A3
B2
B1
5
4
3
2
1
10
9
8
7
6
14
15
16
17
18
19
20
11
12
13
B6
A7
A = B
VCC
B4
A5
B5
A6
Inputs
Output
Data
Words
Cascade
A = B
A = B
L
L
A > B
L
H
A < B
L
H
X
H
H
DW SUFFIX
SOIC PACKAGE
CASE 751D04
N SUFFIX
PLASTIC PACKAGE
CASE 73803
J SUFFIX
CERAMIC PACKAGE
CASE 73203
1
20
1
20
1
20
ORDERING INFORMATION
MC54HCXXXJ
MC74HCXXXN
MC74HCXXXDW
Ceramic
Plastic
SOIC
MC54/74HC688
MOTOROLA
HighSpeed CMOS Logic Data
DL129 -- Rev 6
2
MAXIMUM RATINGS*
Symbol
Parameter
Value
Unit
VCC
DC Supply Voltage (Referenced to GND)
0.5 to + 7.0
V
Vin
DC Input Voltage (Referenced to GND)
1.5 to VCC + 1.5
V
Vout
DC Output Voltage (Referenced to GND)
0.5 to VCC + 0.5
V
Iin
DC Input Current, per Pin
20
mA
Iout
DC Output Current, per Pin
25
mA
ICC
DC Supply Current, VCC and GND Pins
50
mA
PD
Power Dissipation in Still Air, Plastic or Ceramic DIP
SOIC Package
750
500
mW
Tstg
Storage Temperature
65 to + 150
_
C
TL
Lead Temperature, 1 mm from Case for 10 Seconds
(Plastic DIP or SOIC Package)
(Ceramic DIP)
260
300
_
C
* Maximum Ratings are those values beyond which damage to the device may occur.
Functional operation should be restricted to the Recommended Operating Conditions.
Derating -- Plastic DIP: 10 mW/
_
C from 65
_
to 125
_
C
Ceramic DIP: 10 mW/
_
C from 100
_
to 125
_
C
SOIC Package: 7 mW/
_
C from 65
_
to 125
_
C
For high frequency or heavy load considerations, see Chapter 2 of the Motorola HighSpeed CMOS Data Book (DL129/D).
RECOMMENDED OPERATING CONDITIONS
Symbol
Parameter
Min
Max
Unit
VCC
DC Supply Voltage (Referenced to GND)
2.0
6.0
V
Vin, Vout
DC Input Voltage, Output Voltage (Referenced to GND)
0
VCC
V
TA
Operating Temperature, All Package Types
55
+ 125
_
C
tr, tf
Input Rise and Fall Time
VCC = 2.0 V
(Figure 2)
VCC = 4.5 V
VCC = 6.0 V
0
0
0
1000
500
400
ns
DC ELECTRICAL CHARACTERISTICS
(Voltages Referenced to GND)
Symbol
Parameter
Test Conditions
VCC
V
Guaranteed Limit
Unit
Symbol
Parameter
Test Conditions
VCC
V
55 to
25
_
C
v
85
_
C
v
125
_
C
Unit
VIH
Minimum HighLevel Input
Voltage
Vout = 0.1 V or VCC 0.1 V
|Iout|
v
20
A
2.0
4.5
6.0
1.5
3.15
4.2
1.5
3.15
4.2
1.5
3.15
4.2
V
VIL
Maximum LowLevel Input
Voltage
Vout = 0.1 V or VCC 0.1 V
|Iout|
v
20
A
2.0
4.5
6.0
0.3
0.9
1.2
0.3
0.9
1.2
0.3
0.9
1.2
V
VOH
Minimum HighLevel Output
Voltage
Vin = VIH or VIL
|Iout|
v
20
A
2.0
4.5
6.0
1.9
4.4
5.9
1.9
4.4
5.9
1.9
4.4
5.9
V
Vin = VIH or VIL |Iout|
v
4.0 mA
|Iout|
v
5.2 mA
4.5
6.0
3.98
5.48
3.84
5.34
3.70
5.20
VOL
Maximum LowLevel Output
Voltage
Vin = VIH or VIL
|Iout|
v
20
A
2.0
4.5
6.0
0.1
0.1
0.1
0.1
0.1
0.1
0.1
0.1
0.1
V
Vin = VIH or VIL |Iout|
v
4.0 mA
|Iout|
v
5.2 mA
4.5
6.0
0.26
0.26
0.33
0.33
0.40
0.40
Iin
Maximum Input Leakage Current
Vin = VCC or GND
6.0
0.1
1.0
1.0
A
ICC
Maximum Quiescent Supply
Current (per Package)
Vin = VCC or GND
Iout = 0
A
6.0
8
80
160
A
NOTE: Information on typical parametric values can be found in Chapter 2 of the Motorola HighSpeed CMOS Data Book (DL129/D).
This device contains protection
circuitry to guard against damage
due to high static voltages or electric
fields. However, precautions must
be taken to avoid applications of any
voltage higher than maximum rated
voltages to this highimpedance cir-
cuit. For proper operation, Vin and
Vout should be constrained to the
range GND
v
(Vin or Vout)
v
VCC.
Unused inputs must always be
tied to an appropriate logic voltage
level (e.g., either GND or VCC).
Unused outputs must be left open.
MC54/74HC688
HighSpeed CMOS Logic Data
DL129 -- Rev 6
3
MOTOROLA
AC ELECTRICAL CHARACTERISTICS
(CL = 50 pF, Input tr = tf = 6 ns)
Symbol
Parameter
VCC
V
Guaranteed Limit
Unit
Symbol
Parameter
VCC
V
55 to
25
_
C
v
85
_
C
v
125
_
C
Unit
tPLH,
tPHL
Maximum Propagation Delay, Input A or B to Output A = B
(Figures 1 and 3)
2.0
4.5
6.0
210
42
36
265
53
45
315
63
54
ns
tPLH,
tPHL
Maximum Propagation Delay, Cascade Input to Output A = B
(Figures 2 and 3)
2.0
4.5
6.0
120
24
20
150
30
26
180
36
31
ns
tTLH,
tTHL
Maximum Output Transition Time, Any Output
(Figures 2 and 3)
2.0
4.5
6.0
75
15
13
95
19
16
110
22
19
ns
Cin
Maximum Input Capacitance
--
10
10
10
pF
NOTES:
1. For propagation delays with loads other than 50 pF, see Chapter 2 of the Motorola HighSpeed CMOS Data Book (DL129/D).
2. Information on typical parametric values can be found in Chapter 2 of the Motorola HighSpeed CMOS Data Book (DL129/D).
CPD
Power Dissipation Capacitance (Per Package)*
Typical @ 25
C, VCC = 5.0 V
pF
CPD
Power Dissipation Capacitance (Per Package)*
30
pF
* Used to determine the noload dynamic power consumption: PD = CPD VCC2f + ICC VCC. For load considerations, see Chapter 2 of the
Motorola HighSpeed CMOS Data Book (DL129/D).
SWITCHING WAVEFORMS
CASCADE
INPUT
tf
tr
VCC
GND
10%
50%
90%
tPHL
tPLH
10%
50%
90%
tTHL
tTLH
VCC
GND
50%
INPUT
A OR B
tPLH
tPHL
50%
A = B
OUTPUT
VALID
VALID
Figure 1.
Figure 2.
A = B
OUTPUT
TEST CIRCUITS
* Includes all probe and jig capacitance
CL*
TEST POINT
DEVICE
UNDER
TEST
OUTPUT
Figure 3.
MC54/74HC688
MOTOROLA
HighSpeed CMOS Logic Data
DL129 -- Rev 6
4
TYPICAL APPLICATION
Two or more HC688 8bit Equality Comparators may be cascaded to compare binary or BCD numbers having more than
8 bits. One method of accomplishing this is shown here.
An
Bn
An1
Bn1
Ao
Bo
HC688
8 MOST
SIGNIFICANT
BITS
A = B
OUTPUT
A = B
EXPANDED LOGIC DIAGRAM
CASCADE
INPUT
8 LEAST
SIGNIFICANT
BITS
A = B
OUTPUT
CASCADE
INPUT
CASCADE
INPUT
CASCADE
INPUT
HC688
HC688
A = B
19
2
4
6
8
11
13
15
17
3
5
7
9
1
A0
A1
A2
A3
A4
A5
A6
A7
12
14
16
18
B0
B1
B2
B3
B4
B5
B6
B7
MC54/74HC688
HighSpeed CMOS Logic Data
DL129 -- Rev 6
5
MOTOROLA
OUTLINE DIMENSIONS
J SUFFIX
CERAMIC PACKAGE
CASE 73203
ISSUE E
N SUFFIX
PLASTIC PACKAGE
CASE 73803
ISSUE E
DW SUFFIX
PLASTIC SOIC PACKAGE
CASE 751D04
ISSUE E
NOTES:
1. LEADS WITHIN 0.25 (0.010) DIAMETER, TRUE
POSITION AT SEATING PLANE, AT MAXIMUM
MATERIAL CONDITION.
2. DIMENSION L TO CENTER OF LEADS WHEN
FORMED PARALLEL.
3. DIMENSIONS A AND B INCLUDE MENISCUS.
DIM
MIN
MAX
MIN
MAX
INCHES
MILLIMETERS
A
23.88
25.15
0.940
0.990
B
6.60
7.49
0.260
0.295
C
3.81
5.08
0.150
0.200
D
0.38
0.56
0.015
0.022
F
1.40
1.65
0.055
0.065
G
2.54 BSC
0.100 BSC
H
0.51
1.27
0.020
0.050
J
0.20
0.30
0.008
0.012
K
3.18
4.06
0.125
0.160
L
7.62 BSC
0.300 BSC
M
0
15
0
15
N
0.25
1.02
0.010
0.040
_
_
_
_
A
20
1
10
11
B
F
C
SEATING
PLANE
D
H
G
K
N
J
M
L
NOTES:
1. DIMENSIONING AND TOLERANCING PER ANSI
Y14.5M, 1982.
2. CONTROLLING DIMENSION: INCH.
3. DIMENSION L TO CENTER OF LEAD WHEN
FORMED PARALLEL.
4. DIMENSION B DOES NOT INCLUDE MOLD
FLASH.
M
L
J
20 PL
M
B
M
0.25 (0.010)
T
DIM
MIN
MAX
MIN
MAX
MILLIMETERS
INCHES
A
25.66
27.17
1.010
1.070
B
6.10
6.60
0.240
0.260
C
3.81
4.57
0.150
0.180
D
0.39
0.55
0.015
0.022
G
2.54 BSC
0.100 BSC
J
0.21
0.38
0.008
0.015
K
2.80
3.55
0.110
0.140
L
7.62 BSC
0.300 BSC
M
0
15
0
15
N
0.51
1.01
0.020
0.040
_
_
_
_
E
1.27
1.77
0.050
0.070
1
11
10
20
A
SEATING
PLANE
K
N
F
G
D
20 PL
T
M
A
M
0.25 (0.010)
T
E
B
C
F
1.27 BSC
0.050 BSC
NOTES:
1. DIMENSIONING AND TOLERANCING PER
ANSI Y14.5M, 1982.
2. CONTROLLING DIMENSION: MILLIMETER.
3. DIMENSIONS A AND B DO NOT INCLUDE
MOLD PROTRUSION.
4. MAXIMUM MOLD PROTRUSION 0.150
(0.006) PER SIDE.
5. DIMENSION D DOES NOT INCLUDE
DAMBAR PROTRUSION. ALLOWABLE
DAMBAR PROTRUSION SHALL BE 0.13
(0.005) TOTAL IN EXCESS OF D DIMENSION
AT MAXIMUM MATERIAL CONDITION.
A
B
20
1
11
10
S
A
M
0.010 (0.25)
B
S
T
D
20X
M
B
M
0.010 (0.25)
P
10X
J
F
G
18X
K
C
T
SEATING
PLANE
M
R
X 45
_
DIM
MIN
MAX
MIN
MAX
INCHES
MILLIMETERS
A
12.65
12.95
0.499
0.510
B
7.40
7.60
0.292
0.299
C
2.35
2.65
0.093
0.104
D
0.35
0.49
0.014
0.019
F
0.50
0.90
0.020
0.035
G
1.27 BSC
0.050 BSC
J
0.25
0.32
0.010
0.012
K
0.10
0.25
0.004
0.009
M
0
7
0
7
P
10.05
10.55
0.395
0.415
R
0.25
0.75
0.010
0.029
_
_
_
_
MC54/74HC688
MOTOROLA
HighSpeed CMOS Logic Data
DL129 -- Rev 6
6
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the suitability of its products for any particular purpose, nor does Motorola assume any liability arising out of the application or use of any product or circuit,
and specifically disclaims any and all liability, including without limitation consequential or incidental damages. "Typical" parameters can and do vary in different
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MC54/74HC688/D
*MC54/74HC688/D*
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