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Электронный компонент: 74LS155

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5-1
FAST AND LS TTL DATA
DUAL 1-OF-4 DECODER/
DEMULTIPLEXER
The SN54 / 74LS155 and SN54 / 74LS156 are high speed Dual 1-of-4
Decoder/Demultiplexers. These devices have two decoders with common
2-bit Address inputs and separate gated Enable inputs. Decoder "a" has an
Enable gate with one active HIGH and one active LOW input. Decoder "b" has
two active LOW Enable inputs. If the Enable functions are satisfied, one
output of each decoder will be LOW as selected by the address inputs. The
LS156 has open collector outputs for wired-OR (DOT-AND) decoding and
function generator applications.
The LS155 and LS156 are fabricated with the Schottky barrier diode
process for high speed and are completely compatible with all Motorola TTL
families.
Schottky Process for High Speed
Multifunction Capability
Common Address Inputs
True or Complement Data Demultiplexing
Input Clamp Diodes Limit High Speed Termination Effects
ESD > 3500 Volts
CONNECTION DIAGRAM DIP (TOP VIEW)
NOTE:
The Flatpak version
has the same pinouts
(Connection Diagram) as
the Dual In-Line Package.
14
13
12
11
10
9
1
2
3
4
5
6
7
16
15
8
VCC
Ea
Eb
Eb
A0
O3b
O1b
O2b
O0b
Ea
A1
O3a
O2a
O1a
O0a GND
PIN NAMES
LOADING (Note a)
HIGH
LOW
A0, A1
Ea, Eb
Ea
O0 O3
Address Inputs
Enable (Active LOW) Inputs
Enable (Active HIGH) Input
Active LOW Outputs (Note b)
0.5 U.L.
0.5 U.L.
0.5 U.L.
10 U.L.
0.25 U.L.
0.25 U.L.
0.25 U.L.
5 (2.5) U.L.
NOTES:
a) 1 TTL Unit Load (U.L.) = 40
A HIGH/1.6 mA LOW.
b) The Output LOW drive factor is 2.5 U.L. for Military (54) and 5 U.L. for Commercial (74)
Temperature Ranges. The HIGH level drive for the LS156 must be established by an external
resistor.
SN54/74LS155
SN54/74LS156
DUAL 1-OF-4 DECODER /
DEMULTIPLEXER
LS156-OPEN-COLLECTOR
LOW POWER SCHOTTKY
J SUFFIX
CERAMIC
CASE 620-09
N SUFFIX
PLASTIC
CASE 648-08
16
1
16
1
ORDERING INFORMATION
SN54LSXXXJ
Ceramic
SN74LSXXXN
Plastic
SN74LSXXXD
SOIC
16
1
D SUFFIX
SOIC
CASE 751B-03
LOGIC SYMBOL
VCC = PIN 16
GND = PIN 8
1 2
13 3
14 15
E
E
A0
A0
A1
A1
0
1
2
3
0
1
2
3
DECODER a
DECODER b
7
6
5
4
9
10 11 12
5-2
FAST AND LS TTL DATA
SN54/74LS155
SN54/74LS156
LOGIC DIAGRAM
Ea Ea
A0
A1
EbEb
O0a
O1a
O2a
O3a
O0b
O1b
O2b
O3b
14
1
2
6
7
3
4
5
9
11
12
10
13
15
VCC = PIN 16
GND = PIN 8
= PIN NUMBERS
FUNCTIONAL DESCRIPTION
The LS155 and LS156 are Dual 1-of-4 Decoder/Demulti-
plexers with common Address inputs and separate gated
Enable inputs. When enabled, each decoder section accepts
the binary weighted Address inputs (A0, A1) and provides four
mutually exclusive active LOW outputs (O0O3). If the Enable
requirements of each decoder are not met, all outputs of that
decoder are HIGH.
Each decoder section has a 2-input enable gate. The
enable gate for Decoder "a" requires one active HIGH input
and one active LOW input (Ea
Ea). In demultiplexing applica-
tions, Decoder "a" can accept either true or complemented
data by using the Ea or Ea inputs respectively. The enable gate
for Decoder "b" requires two active LOW inputs (Eb
Eb). The
LS155 or LS156 can be used as a 1-of-8 Decoder/Demulti-
plexer by tying Ea to Eb and relabeling the common connection
as (A2). The other Eb and Ea are connected together to form
the common enable.
The LS155 and LS156 can be used to generate all four
minterms of two variables. These four minterms are useful in
some applications replacing multiple gate functions as shown
in Fig. a. The LS156 has the further advantage of being able to
AND the minterm functions by tying outputs together. Any
number of terms can be wired-AND as shown below.
f = (E + A0 + A1)
(E + A0 + A1)
(E + A0 + A1)
(E + A0 + A1)
where E = Ea + Ea; E = Eb + Eb
Figure a
E
A0
A1
E
A0
A1
E
A0
A1
E
A0
A1
O0
O1
O2
O3
E
A0
A1
E
A0
A1
E
A0
A1
E
A0
A1
O0
O1
O2
O3
TRUTH TABLE
ADDRESS
ENABLE "a"
OUTPUT "a"
ENABLE "b"
OUTPUT "b"
A0
A1
Ea
Ea
O0
O1
O2
O3
Eb
Eb
O0
O1
O2
O3
X
X
L
X
H
H
H
H
H
X
H
H
H
H
X
X
X
H
H
H
H
H
X
H
H
H
H
H
L
L
H
L
L
H
H
H
L
L
L
H
H
H
H
L
H
L
H
L
H
H
L
L
H
L
H
H
L
H
H
L
H
H
L
H
L
L
H
H
L
H
H
H
H
L
H
H
H
L
L
L
H
H
H
L
H = HIGH Voltage Level
L = LOW Voltage Level
X = Don't Care
5-3
FAST AND LS TTL DATA
SN54/74LS155
GUARANTEED OPERATING RANGES
Symbol
Parameter
Min
Typ
Max
Unit
VCC
Supply Voltage
54
74
4.5
4.75
5.0
5.0
5.5
5.25
V
TA
Operating Ambient Temperature Range
54
74
55
0
25
25
125
70
C
IOH
Output Current -- High
54, 74
0.4
mA
IOL
Output Current -- Low
54
74
4.0
8.0
mA
DC CHARACTERISTICS OVER OPERATING TEMPERATURE RANGE
(unless otherwise specified)
S
b l
P
Limits
U i
T
C
di i
Symbol
Parameter
Min
Typ
Max
Unit
Test Conditions
VIH
Input HIGH Voltage
2.0
V
Guaranteed Input HIGH Voltage for
All Inputs
VIL
Input LOW Voltage
54
0.7
V
Guaranteed Input LOW Voltage for
VIL
Input LOW Voltage
74
0.8
V
p
g
All Inputs
VIK
Input Clamp Diode Voltage
0.65
1.5
V
VCC = MIN, IIN = 18 mA
VOH
Output HIGH Voltage
54
2.5
3.5
V
VCC = MIN, IOH = MAX, VIN = VIH
VOH
Output HIGH Voltage
74
2.7
3.5
V
CC
, OH
,
IN
IH
or VIL per Truth Table
VOL
Output LOW Voltage
54, 74
0.25
0.4
V
IOL = 4.0 mA
VCC = VCC MIN,
VIN = VIL or VIH
VOL
Output LOW Voltage
74
0.35
0.5
V
IOL = 8.0 mA
VIN = VIL or VIH
per Truth Table
IIH
Input HIGH Current
20
A
VCC = MAX, VIN = 2.7 V
IIH
Input HIGH Current
0.1
mA
VCC = MAX, VIN = 7.0 V
IIL
Input LOW Current
0.4
mA
VCC = MAX, VIN = 0.4 V
IOS
Short Circuit Current (Note 1)
20
100
mA
VCC = MAX
ICC
Power Supply Current
10
mA
VCC = MAX
Note 1: Not more than one output should be shorted at a time, nor for more than 1 second.
AC CHARACTERISTICS
(TA = 25
C)
S
b l
P
Limits
U i
T
C
di i
Symbol
Parameter
Min
Typ
Max
Unit
Test Conditions
tPLH
tPHL
Propagation Delay
Address, Ea or Eb to Output
10
19
15
30
ns
Figure 1
V
5 0 V
tPLH
tPHL
Propagation Delay
Address to Output
17
19
26
30
ns
Figure 2
VCC = 5.0 V
CL = 15 pF
tPLH
tPHL
Propagation Delay
Ea to Output
18
18
27
27
ns
Figure 1
AC WAVEFORMS
Figure 1
Figure 2
VIN
VOUT
1.3 V
tPHL
1.3 V
1.3 V
1.3 V
tPLH
VIN
VOUT
1.3 V
tPHL
1.3 V
1.3 V
tPLH
1.3 V
5-4
FAST AND LS TTL DATA
SN54/74LS156
GUARANTEED OPERATING RANGES
Symbol
Parameter
Min
Typ
Max
Unit
VCC
Supply Voltage
54
74
4.5
4.75
5.0
5.0
5.5
5.25
V
TA
Operating Ambient Temperature Range
54
74
55
0
25
25
125
70
C
VOH
Output Voltage -- High
54, 74
5.5
V
IOL
Output Current -- Low
54
74
4.0
8.0
mA
DC CHARACTERISTICS OVER OPERATING TEMPERATURE RANGE
(unless otherwise specified)
S
b l
P
Limits
U i
T
C
di i
Symbol
Parameter
Min
Typ
Max
Unit
Test Conditions
VIH
Input HIGH Voltage
2.0
V
Guaranteed Input HIGH Voltage for
All Inputs
VIL
Input LOW Voltage
54
0.7
V
Guaranteed Input LOW Voltage for
VIL
Input LOW Voltage
74
0.8
V
p
g
All Inputs
VIK
Input Clamp Diode Voltage
0.65
1.5
V
VCC = MIN, IIN = 18 mA
IOH
Output HIGH Current
54, 74
100
A
VCC = MIN, VOH = MAX
VOL
Output LOW Voltage
54, 74
0.25
0.4
V
IOL = 4.0 mA
VCC = VCC MIN,
VIN = VIL or VIH
VOL
Output LOW Voltage
74
0.35
0.5
V
IOL = 8.0 mA
VIN = VIL or VIH
per Truth Table
IIH
Input HIGH Current
20
A
VCC = MAX, VIN = 2.7 V
IIH
Input HIGH Current
0.1
mA
VCC = MAX, VIN = 7.0 V
IIL
Input LOW Current
0.4
mA
VCC = MAX, VIN = 0.4 V
ICC
Power Supply Current
10
mA
VCC = MAX
AC CHARACTERISTICS
(TA = 25
C)
S
b l
P
Limits
U i
T
C
di i
Symbol
Parameter
Min
Typ
Max
Unit
Test Conditions
tPLH
tPHL
Propagation Delay
Address, Ea or Eb to Output
25
34
40
51
ns
Figure 1
V
5 0 V
tPLH
tPHL
Propagation Delay
Address to Output
31
34
46
51
ns
Figure 2
VCC = 5.0 V
CL = 15 pF
RL = 2.0 k
tPLH
tPHL
Propagation Delay
Ea to Output
32
32
48
48
ns
Figure 1
RL = 2.0 k
AC WAVEFORMS
Figure 1
Figure 2
VIN
VOUT
1.3 V
tPHL
1.3 V
1.3 V
1.3 V
tPLH
VIN
VOUT
1.3 V
tPHL
1.3 V
1.3 V
tPLH
1.3 V