5-72
FAST AND LS TTL DATA
DUAL D-TYPE POSITIVE
EDGE-TRIGGERED FLIP-FLOP
The SN54 / 74LS74A dual edge-triggered flip-flop utilizes Schottky TTL cir-
cuitry to produce high speed D-type flip-flops. Each flip-flop has individual
clear and set inputs, and also complementary Q and Q outputs.
Information at input D is transferred to the Q output on the positive-going
edge of the clock pulse. Clock triggering occurs at a voltage level of the clock
pulse and is not directly related to the transition time of the positive-going
pulse. When the clock input is at either the HIGH or the LOW level, the D input
signal has no effect.
LOGIC DIAGRAM (Each Flip-Flop)
SET (SD)
4 (10)
CLEAR (CD)
1 (13)
CLOCK
3 (11)
D
2 (12)
Q
5 (9)
Q
6 (8)
MODE SELECT -- TRUTH TABLE
OPERATING MODE
INPUTS
OUTPUTS
OPERATING MODE
SD
SD
D
Q
Q
Set
Reset (Clear)
*Undetermined
Load "1" (Set)
Load "0" (Reset)
L
H
L
H
H
H
L
L
H
H
X
X
X
h
l
H
L
H
H
L
L
H
H
L
H
* Both outputs will be HIGH while both SD and CD are LOW, but the output states are unpredictable
if SD and CD go HIGH simultaneously. If the levels at the set and clear are near VIL maximum then
we cannot guarantee to meet the minimum level for VOH.
H, h = HIGH Voltage Level
L, I = LOW Voltage Level
X = Don't Care
i, h (q) = Lower case letters indicate the state of the referenced input (or output) one set-up time
i, h (q) =
prior to the HIGH to LOW clock transition.
SN54/74LS74A
DUAL D-TYPE POSITIVE
EDGE-TRIGGERED FLIP-FLOP
LOW POWER SCHOTTKY
J SUFFIX
CERAMIC
CASE 632-08
N SUFFIX
PLASTIC
CASE 646-06
14
1
14
1
ORDERING INFORMATION
SN54LSXXJ
Ceramic
SN74LSXXN
Plastic
SN74LSXXD
SOIC
14
1
D SUFFIX
SOIC
CASE 751A-02
LOGIC SYMBOL
VCC = PIN 14
GND = PIN 7
2
3
5
D
Q
CP
Q
CD
1
4
6
12
11
9
D
Q
CP
Q
CD
13
10
8
SD
SD
5-73
FAST AND LS TTL DATA
SN54/74LS74A
GUARANTEED OPERATING RANGES
Symbol
Parameter
Min
Typ
Max
Unit
VCC
Supply Voltage
54
74
4.5
4.75
5.0
5.0
5.5
5.25
V
TA
Operating Ambient Temperature Range
54
74
55
0
25
25
125
70
C
IOH
Output Current -- High
54, 74
0.4
mA
IOL
Output Current -- Low
54
74
4.0
8.0
mA
DC CHARACTERISTICS OVER OPERATING TEMPERATURE RANGE
(unless otherwise specified)
Symbol
Parameter
Limits
Unit
Test Conditions
Symbol
Parameter
Min
Typ
Max
Unit
Test Conditions
VIH
Input HIGH Voltage
2.0
V
Guaranteed Input HIGH Voltage for
All Inputs
VIL
Input LOW Voltage
54
0.7
V
Guaranteed Input LOW Voltage for
All Inputs
VIL
Input LOW Voltage
74
0.8
V
Guaranteed Input LOW Voltage for
All Inputs
VIK
Input Clamp Diode Voltage
0.65
1.5
V
VCC = MIN, IIN = 18 mA
VOH
Output HIGH Voltage
54
2.5
3.5
V
VCC = MIN, IOH = MAX, VIN = VIH
or VIL per Truth Table
VOH
Output HIGH Voltage
74
2.7
3.5
V
VCC = MIN, IOH = MAX, VIN = VIH
or VIL per Truth Table
VOL
Output LOW Voltage
54, 74
0.25
0.4
V
IOL = 4.0 mA
VCC = VCC MIN,
VIN = VIL or VIH
per Truth Table
VOL
Output LOW Voltage
74
0.35
0.5
V
IOL = 8.0 mA
VIN = VIL or VIH
per Truth Table
IIH
Input High Current
Data, Clock
Set, Clear
20
40
A
VCC = MAX, VIN = 2.7 V
IIH
Data, Clock
Set, Clear
0.1
0.2
mA
VCC = MAX, VIN = 7.0 V
IIL
Input LOW Current
Data, Clock
Set, Clear
0.4
0.8
mA
VCC = MAX, VIN = 0.4 V
IOS
Output Short Circuit Current (Note 1)
20
100
mA
VCC = MAX
ICC
Power Supply Current
8.0
mA
VCC = MAX
Note 1: Not more than one output should be shorted at a time, nor for more than 1 second.
AC CHARACTERISTICS
(TA = 25
C, VCC = 5.0 V)
Symbol
Parameter
Limits
Unit
Test Conditions
Symbol
Parameter
Min
Typ
Max
Unit
Test Conditions
fMAX
Maximum Clock Frequency
25
33
MHz
Figure 1
VCC = 5.0 V
CL = 15 pF
tPLH
tPHL
Clock, Clear, Set to Output
13
25
ns
Figure 1
VCC = 5.0 V
CL = 15 pF
tPLH
tPHL
Clock, Clear, Set to Output
25
40
ns
Figure 1
CL = 15 pF
AC SETUP REQUIREMENTS
(TA = 25
C)
Symbol
Parameter
Limits
Unit
Test Conditions
Symbol
Parameter
Min
Typ
Max
Unit
Test Conditions
tW (H)
Clock
25
ns
Figure 1
VCC = 5.0 V
tW (L)
Clear, Set
25
ns
Figure 2
VCC = 5.0 V
ts
Data Setup Time -- HIGH
Data Setup Time --
LOW
20
ns
Figure 1
VCC = 5.0 V
ts
Data Setup Time -- HIGH
Data Setup Time --
LOW
20
ns
Figure 1
CC = 5.0 V
th
Hold Time
5.0
ns
Figure 1
5-74
FAST AND LS TTL DATA
SN54/74LS74A
Figure 1. Clock to Output Delays, Data
Set-Up and Hold Times, Clock Pulse Width
Figure 2. Set and Clear to Output Delays,
Set and Clear Pulse Widths
AC WAVEFORMS
tW
1.3 V
1.3 V
tW
1.3 V
1.3 V
1.3 V
1.3 V
1.3 V
1.3 V
tPLH
tPHL
tPLH
tPHL
SET
CLEAR
Q
Q
*The shaded areas indicate when the input is permitted to change for predictable output performance.
D *
CP
Q
Q
1.3 V
1.3 V
1.3 V
1.3 V
1.3 V
1.3 V
1.3 V
tPLH
tPHL
tPLH
tPHL
th(L)
ts(L)
tW(H)
tW(L)
ts(H)
th(H)
1
fMAX
1.3 V
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