MM908E624

Internal Rev 4.0, 12/2004

Freescale Semiconductor
Technical Data

This document contains certain information on a new product.

Specifications and information herein are subject to change without notice.

Integrated Triple High-Side

Switch with Embedded MCU

and LIN Serial Communication

for Relay Drivers

The 908E624 is an integrated single-package solution that

includes a high-performance HC08 microcontroller with a
SMARTMOS

analog control IC. The HC08 includes flash memory,

a timer, enhanced serial communications interface (ESCI), an
analog-to-digital converter (ADC), serial peripheral interface (SPI)
(only internal), and an internal clock generator module. The analog
control die provides three high-side outputs with diagnostic functions,
voltage regulator, watchdog, operational amplifier, and local
interconnect network (LIN) physical layer.

The single-package solution, together with LIN, provides optimal

application performance adjustments and space-saving PCB design.
It is well suited for the control of automotive high-current motors
applications using relays (e.g., window lifts, fans, and sun roofs).

Features
· High-Performance M68HC908EY16 Core
· 16 K Bytes of On-Chip Flash Memory
· 512 Bytes of RAM
· Internal Clock Generator Module
· Two 16-Bit, 2-Channel Timers
· 10-Bit Analog-to-Digital Converter (ADC)
· LIN Physical Layer Interface
· Low Dropout Voltage Regulator
· Three High-Side Outputs
· Two Wake-Up Inputs
· 16 Microcontroller I/Os

Figure 1. 908E624 Simplified Application Diagram

TRIPLE HIGH-SIDE SWITCH WITH

EMBEDDED MCU AND LIN

908E624

ORDERING INFORMATION

Device

Temperature

Range (T

)

Package

MM908E624ACDWB/R

-40°C to 85°C

54 SOICW

DW SUFFIX

98ASA99294D

54-TERMINAL SOICW

PTD1/TACH1

PTA0

-4

PWMin

PTD0/TACH0

IRQB_A

IRQB

RSTB_A

RSTB

PTE1/RxD

RxD

GND

EVSS

VSSA

VREFL

VDD

EVDD

VDDA

VREFH

LIN

HS3

L1
L2

HS1

HS2

OUT

-E

WDCONF

VSUP1

VSUP2

VBAT

LIN

Interface

Microcontroller

Ports

To Microcontroller A/D Channel

+5.0 V

VCC

AGND

PTB1;3

-7

PTC2

-4

Analog Integrated Circuit Device Data

Freescale Semiconductor

908E624

Internal Block Diagram

INTERNAL BLOCK DIAGRAM

Cont

rol

and S

t
at

us Regi

,

64 B

t
e

User Fl

ash,

15,

72 B

t
e

User RA

,

512 B

t
e

t
o

r ROM

,

310

t
e

User Fl

ash V

or S

pace

,

36

t
e

FLA

program

i
ng (burn i

) ROM

1024 B

t
e

-
B

i
t K

r
d

r
r
u

2-channel

r I

t
e

ace

t
y

l
e

2-channel

r I

t
e

ace

M68HC08 CPU

CPU

Regi

ers

odi

c Wakeup Ti

base

Arb

i
t
e

r M

l
e

heri

heral

t
e

ace

r
escal

r M

dul

r
n

l
C

l
o

r
a

Com

er Operat

i
n

r
operl

dul

l
e

i
n

t
Bre

r
-
O

t
M

l
e

r
n

l
S

t
e

I
n

t
e

grat

i
o

n M

dul

10 B

i
t
A

og-t

o-Di

t
a

Convert

r M

odul

hanced S

Com

uni

i
o

n I

t
e

ace

PTB

/AD

/TBC

VREFL

VSSA

EVSS

EVDD

VDDA

VREFH

PTB

/AD

/TBC

/AD

/
KBD

/KBD

/OSC

SVPP

/
SPSC

/
M

OSI

ISO

i
n

r
n

l
IR

Conf

i
g

urat

i
o

n Regi

MF Mo

POR

T A

DDRA

IRQ

DDA

VSSA

VSS

PORT

DDRB

/
S

PSCK

/
K

/
A

PORT

POR

T D

DDRC

DDRD

/
O

/
M

I
S

DDRE

PORT

/
T

ACH

/
T

ACH

/
R

/
T

Inte

Bus

PTD0/TACH0

PTE1/RXD

Vol

t
age

t
o

SPI

de C

ntr

t
Co

t
ro

i
ndow

hdog

Input 1

WDCONF

PWMIN

VSUP2

GND

LIN

SPSC

RXD

IRQ

RST

IRQ_A

RST_A

/AD

/SS

-E

Input 2

VSUP1

Hig

i
d

Drive

r
&

i
agnos

VSU

I
N

VSU

I
N Ph

ysica

Lay

AGND

i
gh Si

Drive

r
&

i
agnos

t
i
c

i
gh Si

Drive

r
&

i
agnos

t
i
c

I
N

VSU

Amplifier

Analog Die

MCU Die

i
gu

08E6

Simp

lified

Inte

rna

l

Bloc

Analog Integrated Circuit Device Data
Freescale Semiconductor

908E624

Terminal Connections

TERMINAL CONNECTIONS

Figure 3. Terminal Connections

Table 1. Terminal Definitions

A functional description of each terminal can be found in the

Functional Terminal Description

section beginning on page

Die

Terminal

Terminal Name

Formal Name

Definition

MCU

1
2
6
7
8

PTB7/AD7/TBCH1
PTB6/AD6/TBCH0

PTB5/AD5
PTB4/AD4
PTB3/AD3
PTB1/AD1

Port B I/Os

These terminals are special-function, bidirectional I/O port terminals
that are shared with other functional modules in the MCU.

MCU

3
4
5

PTC4/OSC1
PTC3/OSC2
PTC2/MCLK

Port C I/Os

These terminals are special-function, bidirectional I/O port terminals
that are shared with other functional modules in the MCU.

MCU

IRQ

External Interrupt

Input

This terminal is an asynchronous external interrupt input terminal.

MCU

RST

External Reset

This terminal is bidirectional, allowing a reset of the entire system. It is
driven low when any internal reset source is asserted.

MCU

12
13

PTD0/TACH0
PTD1/TACH1

Port D I/Os

These terminals are special-function, bidirectional I/O port terminals
that are shared with other functional modules in the MCU.

14, 15, 16,
20, 21, 22,

32, 41

No Connect

Not connected.

MCU

PTE1/RXD

Port E I/O

This terminal is a special-function, bidirectional I/O port terminal that
can is shared with other functional modules in the MCU.

PTA0/KBD0
PTA1/KBD1
PTA2/KBD2

PTA3/KBD3
PTA4/KBD4
VREFH
VDDA
EVDD
EVSS
VSSA
VREFL
PTE1/RXD
NC
RXD
WDCONF
+E
-E
OUT
VCC
AGND
VDD
NC
VSUP1
GND
LIN
VSUP2

FLSVPP

PTB7/AD7/TBCH1

PTB6/AD6/TBCH0

PTC4/OSC1
PTC3/OSC2

PTC2/MCLK

PTB5/AD5
PTB4/AD4
PTB3/AD3

IRQ

RST

PTB1/AD1

PTD0/TACH0

PTD1/TACH1

NC
NC
NC

PWMIN

RST_A

IRQ_A

NC
NC
NC

L1
L2

HS3
HS2
HS1

Analog Integrated Circuit Device Data

Freescale Semiconductor

908E624

Terminal Connections

MCU

43
48

VREFL

VREFH

ADC References

These terminals are the reference voltage terminals for the analog-to-
digital converter (ADC).

MCU

44
47

VSSA

VDDA

ADC Supply

Terminals

These terminals

are the power supply terminals for the analog-to-digital

converter.

MCU

45
46

EVSS

EVDD

MCU Power Supply

Terminals

These terminals are the ground and power supply terminals,
respectively. The MCU operates from a single-power supply.

MCU

49
50
52
53
54

PTA4/KBD4
PTA3/KBD3
PTA2/KBD2
PTA1/KBD1
PTA0/KBD0

Port A I/Os

These terminals are special-function, bidirectional I/O port terminals
that are shared with other functional modules in the MCU.

MCU

FLSVPP

Test Terminal

For test purposes only. Do not connect in the application.

Analog

PWMIN

Direct High-Side

Control Input

This terminal allows the enabling and PWM control of the high-side HS1
and HS2 terminals.

Analog

RST_A

Internal Reset Output This terminal is the reset output terminal of the analog die.

Analog

IRQ_A

Internal Interrupt

Output

This terminal is the interrupt output terminal of the analog die indicating
errors or wake-up events.

Analog

23
24

L1
L2

Wake-Up Inputs

These terminals are the wake-up inputs of the analog chip.

Analog

25
26
27

HS3
HS2
HS1

High-Side Output

These output terminals are low R

DS(ON)

high-side switches.

Analog

31
28

VSUP1
VSUP2

Power Supply

Terminals

These terminals are device power supply terminals.

Analog

LIN

LIN Bus

This terminal represents the single-wire bus transmitter and receiver.

Analog

30
34

GND

AGND

Power Ground

Terminals

These terminals are device power ground connections.

Analog

VDD

Voltage Regulator

Output

The +5.0 V voltage regulator output terminal is intended to supply the
embedded microcontroller.

Analog

VCC

Amplifier Power

Supply

This terminal is the single +5.0 V power supply for the operational
amplifier.

Analog

OUT

Amplifier Output

This terminal is the output of the operational amplifier.

Analog

37
38

-E

Amplifier Inputs

These terminals are the amplifier inverted and non-inverted inputs.

Analog

WDCONF

Watchdog

Configuration

Terminal

This input terminal is for configuration of the watchdog period and
allows the disabling of the watchdog.

Analog

RXD

LIN Transceiver

Output

This terminal is the output of LIN transceiver.

Table 1. Terminal Definitions (continued)

A functional description of each terminal can be found in the

Functional Terminal Description

section beginning on page

Die

Terminal

Terminal Name

Formal Name

Definition

Analog Integrated Circuit Device Data
Freescale Semiconductor

908E624

Maximum Ratings

MAXIMUM RATINGS

Table 2. Maximum Ratings

All voltages are with respect to ground unless otherwise noted. Exceeding limits on any terminal may cause permanent

damage to the device.

Rating

Symbol

Value

Unit

Electrical Ratings

Supply Voltage

Analog Chip Supply Voltage under Normal Operation (Steady-State)
Analog Chip Supply Voltage under Transient Conditions
MCU Chip Supply Voltage

SUP(SS)

SUP(

PK)

-0.3 to 27
-0.3 to 40

-0.3 to 5.5

Input Terminal Voltage

Analog Chip
Microcontroller Chip

IN(ANALOG)

IN(MCU)

-0.3 to V

+0.3

-0.3 to V

+0.3

Maximum Microcontroller Current per Terminal

All Terminals except VDD, VSS, PTA0:PTA6, PTC0:PTC1
PTA0:PTA6, PTC0:PTC1 Terminals

PIN(1)

PIN(2)

±15

±25

Maximum Microcontroller VSS Output Current

MVSS

100

Maximum Microcontroller VDD Input Current

MVDD

100

Current Sense Amplifier

Maximum Input Voltage, +E, -E Terminals
Maximum Input Current, +E, -E Terminals
Maximum Output Voltage, OUT Terminal
Maximum Output Current, OUT Terminal

+E-E

OUT

-0.3 to 7.0

±20

-0.3 to V

+0.3

±20

LIN Supply Voltage

Normal Operation (Steady-State)
Transient Input Voltage (per ISO7637 Specification) and with
External Components

(Figure 4,

page

15)

BUS(SS)

BUS(

PK)

-18 to 40

-150 to 100

L1 and L2 Terminal Voltage

Normal Operation with a 33 k

resistor

(Steady-State)

Transient Input Voltage (per ISO7637 Specification) and with
External Components

(Figure 4,

page

15)

WAKE(SS)

WAKE(PK)

-18 to 40

-100 to 100

ESD Voltage

Human Body Model

(1)

Machine Model

(2)

Charge Device Model

(3)

ESD1

ESD2

ESD3

±2000

±100

±500

Notes

ESD1 testing is performed in accordance with the Human Body Model (C

ZAP

= 100 pF, R

ZAP

= 1500

ESD2 testing is performed in accordance with the Machine Model (C

ZAP

=200 pF, R

ZAP

= 0

ESD3 testing is performed in accordance with Charge Device Model, Robotic (C

ZAP

= 4.0 pF).

Analog Integrated Circuit Device Data

Freescale Semiconductor

908E624

Maximum Ratings

Thermal Ratings

Operating Ambient Temperature

-40 to 85

°C

Operating Junction Temperature

(4)

Analog
MCU

J(ANALOG)

J(MCU)

-40 to 150
-40 to 125

°C
°C

Storage Temperature

STG

-40 to 150

°C

Peak Package Reflow Temperature During Solder Mounting

(5)

SOLDER

245

°C

Thermal Resistance, Junction to Ambient

(6)

(7)

°C/ W

Notes

Die temperature of analog and MCU is linked via the package. High temperature on analog die can lead to a high MCU temperature.

Terminal soldering temperature is for 10 seconds maximum duration. Not designed for immersion soldering. Exceeding these limits may
cause malfunction or permanent damage to the device.

All power outputs ON and dissipating equal power.

Per JEDEC JESD51-2 at natural convection, still air condition; and 2s2p thermal test board per JEDEC JESD51-7.

Table 2. Maximum Ratings (continued)

All voltages are with respect to ground unless otherwise noted. Exceeding limits on any terminal may cause permanent

damage to the device.

Rating

Symbol

Value

Unit

Analog Integrated Circuit Device Data
Freescale Semiconductor

908E624

Static Electrical Characteristics

STATIC ELECTRICAL CHARACTERISTICS

Table 3. Static Electrical Characteristics

All characteristics are for the analog chip only. Refer to the 68HC908EY16 datasheet for characteristics of the microcontroller

chip. Characteristics noted under conditions 9.0 V

SUP

16 V, -40

°C

125

°C unless otherwise noted. Typical values

noted reflect the approximate parameter mean at T

= 25

°C under nominal conditions unless otherwise noted.

Characteristic

Symbol

Min

Typ

Max

Unit

Supply Voltage Range

Nominal Operating Voltage

SUP

5.5

Functional Operating Voltage

(8)

SUPOP

Supply Current Range

Normal Mode

(9)

SUP

= 13.5 V, Analog Chip in Normal Mode, MCU Operating Using

Internal Oscillator at 32 MHz (8.0 MHz Bus Frequency), SPI, ESCI, ADC
Enabled

Stop Mode

(9)

(10)

SUP

= 13.5 V

Sleep Mode

(9)

(10)

SUP

= 13.5 V

RUN

STOP

SLEEP

µA

Digital Interface Ratings (Analog Die)

Output Terminal RST_A

Low-State Output Voltage (I

OUT

= -1.5 mA)

High-State Output Current (V

OUT

> 3.5 V)

Pulldown Current Limitation

OL_MAX

-1.5

250

0.4

-8.0

µA

Output Terminal IRQ_A

Low-State Output Voltage (I

OUT

= -1.5 mA)

High-State Output Voltage (I

OUT

= 250

µA)

3.85

0.4

Output Terminal RXD

Low-State Output Voltage (I

OUT

= -1.5 mA)

High-State Output Voltage (I

OUT

= 250

µA)

Capacitance

(11)

3.85

--
--

4.0

0.4

--
--

V
V

Input Terminal PWMIN

Input Logic Low Voltage
Input Logic High Voltage

Input Current

Capacitance

(11)

3.5
-10

--
--
--

4.0

1.5

V
V

µA

Terminal TXD, SSPullup Current

PULLUP

µA

Notes

Device is fully functional. All functions are operating. Overtemperature may occur.

Total current (I

VSUP1

+ I

VSUP2

) measured at GND terminal.

10.

Stop and Sleep mode current will increase if V

SUP

exceeds 15 V.

11.

This parameter is guaranteed by process monitoring but is not production tested.

Analog Integrated Circuit Device Data

Freescale Semiconductor

908E624

Static Electrical Characteristics

System Resets and Interrupts

Low-Voltage Reset (LVR)

Threshold

LVRON

3.6

4.0

4.4

Low-Voltage Interrupt (LVI)

Threshold
Hysteresis

LVI

LVI_

HYS

5.7

6.0

1.0

6.6

High-Voltage Interrupt (HVI)

Threshold
Hysteresis

HVI

HVI_

HYS

19.25

220

20.5

Voltage Regulator

(12)

Normal Mode Output Voltage

2.0 mA < I

< 50 mA, 5.5 V < V

SUP

< 27 V

DDRUN

4.75

5.0

5.25

Normal Mode Output Current Limitation

(13)

DDRUN

110

200

Dropout Voltage

(14)

= 50 mA

DDDROP

0.1

0.2

Stop Mode Output Voltage

(15)

DDSTOP

4.75

5.0

5.25

Stop Mode Regulator Current Limitation

DDSTOP

4.0

8.0

Line Regulation

Normal Mode, 5.5 V < V

SUP

< 27 V, I

= 10 mA

Stop Mode, 5.5 V < V

SUP

< 27 V, I

= 2.0 mA

RUN

STOP

--
--

20
10

150
100

Load Regulation

Normal Mode, 1.0 mA < I

< 50 mA, V

SUP

= 18 V

Stop Mode, 1.0 mA < I

< 5 mA, V

SUP

= 18 V

RUN

STOP

--
--

40
40

150
150

Overtemperature Pre-Warning (Junction)

(16)

PRE

120

135

160

°C

Thermal Shutdown Temperature (Junction)

(16)

155

170

°C

Temperature Threshold Difference

-T

PRE

TSD-TPRE

°C

Notes

12.

Specification with external capacitor 1.0

µF< C < 10 µF and 200 m ESR 1.0 . Capacitor value up to 47 µF can be used.

13.

Total VDD regulator current. A 5.0 mA current for operational amplifier is included. Digital output supplied from VDD.

14.

Measured when voltage has dropped 100 mV below its nominal value.

15.

When switching from Normal to Stop mode or from Stop mode to Normal mode, the output voltage can vary within the output voltage
specification.

16.

This parameter is guaranteed by process monitoring but not production tested

Table 3. Static Electrical Characteristics (continued)

All characteristics are for the analog chip only. Refer to the 68HC908EY16 datasheet for characteristics of the microcontroller

chip. Characteristics noted under conditions 9.0 V

SUP

16 V, -40

°C

125

°C unless otherwise noted. Typical values

noted reflect the approximate parameter mean at T

= 25

°C under nominal conditions unless otherwise noted.

Characteristic

Symbol

Min

Typ

Max

Unit

Analog Integrated Circuit Device Data
Freescale Semiconductor

908E624

Static Electrical Characteristics

Window Watchdog Configuration Terminal (WDCONF)

External Resistor Range

EXT

100

Watchdog Period Accuracy with External Resistor (Excluding Resistor
Accuracy)

(17)

CACC

-15

LIN Physical Layer

LIN Transceiver Output Level

Recessive State, TXD HIGH, I

OUT

= 1.0

µA

Dominant State, TXD LOW, 500

External Pullup Resistor

LIN_REC

LIN_DOM

SUP

-1

--
--

1.4

Normal Mode Pullup Resistor to V

SUP

Stop, Sleep Mode Pullup Current Source

2.0

µA

Output Current Shutdown Threshold

OV-CUR

150

Output Current Shutdown Delay

OV-DELAY

µs

Leakage Current to GND

VSUP Disconnected, V

BUS

at 18 V

Recessive State, V

SUP

8.0 V to 18 V, V

BUS

8.0 V to 18 V, V

BUS

SUP

GND Disconnected, V

GND

= V

SUP

, V

BUS

at -18 V

BUS

-1.0

1.0

3.0

1.0

µA

LIN Receiver

Receiver Threshold Dominant
Receiver Threshold Recessive
Receiver Threshold Center
Receiver Threshold Hysteresis

BUS_DOM

BUS_REC

BUS_CNT

BUS_HYS

0.6

0.475

--
--

0.5

0.4

0.525
0.175

SUP

Notes

17.

Watchdog timing period calculation formula: P

= 0.991

EXT

+0.648 (R

EXT

in k

and P

in ms).

Table 3. Static Electrical Characteristics (continued)

All characteristics are for the analog chip only. Refer to the 68HC908EY16 datasheet for characteristics of the microcontroller

chip. Characteristics noted under conditions 9.0 V

SUP

16 V, -40

°C

125

°C unless otherwise noted. Typical values

noted reflect the approximate parameter mean at T

= 25

°C under nominal conditions unless otherwise noted.

Characteristic

Symbol

Min

Typ

Max

Unit

Analog Integrated Circuit Device Data

Freescale Semiconductor

908E624

Static Electrical Characteristics

High-Side Outputs HS1 and HS2

Switch On Resistance

= 25

C, I

LOAD

= 150 mA, V

SUP

> 9.0 V

= 125

C, I

LOAD

= 150 mA, V

SUP

> 9.0 V

= 125

C, I

LOAD

= 120 mA, 5.5 V < V

SUP

> 9.0 V

DS(ON)

2.0

3.0

2.5

4.5

Output Current Limit

LIM

300

600

Overtemperature Shutdown

(18)

(19)

HSSD

155

190

°C

Leakage Current

LEAK

µA

High-Side Output HS3

Switch On Resistance

= 25

C, I

LOAD

= 50 m A, V

SUP

> 9.0 V

= 125

C, I

LOAD

= 50 mA, V

SUP

> 9.0 V

= 125

C, I

LOAD

= 30 mA, 5.5 V < V

SUP

> 9.0 V

DS(ON)

7.0

Output Current Limitation

LIM

100

200

Overtemperature Shutdown

(18)

(19)

HSSD

155

190

°C

Leakage Current

LEAK

µA

Output Clamp Voltage

OUT

= -100 mA

-6.0

Notes

18.

This parameter is guaranteed by process monitoring but it is not production tested

19.

When overtemperature occurs, switch is turned off and latched off. Flag is set in SPI.

Table 3. Static Electrical Characteristics (continued)

All characteristics are for the analog chip only. Refer to the 68HC908EY16 datasheet for characteristics of the microcontroller

chip. Characteristics noted under conditions 9.0 V

SUP

16 V, -40

°C

125

°C unless otherwise noted. Typical values

noted reflect the approximate parameter mean at T

= 25

°C under nominal conditions unless otherwise noted.

Characteristic

Symbol

Min

Typ

Max

Unit

Analog Integrated Circuit Device Data
Freescale Semiconductor

908E624

Static Electrical Characteristics

Sense Current Amplifier

Rail to Rail Input Voltage

IMC

-0.1

+0.1

Output Voltage Range

Output Current ±1.0 mA
Output Current ±5.0 mA

OUT1

OUT2

0.1
0.3

--
--

-0.1

-0.3

Input Bias Current

250

Input Offset Current

-100

100

Input Offset Voltage

-25

Supply Voltage Rejection Ratio

(20)

SVR

Common Mode Rejection Ratio

(20)

CMR

Gain Bandwidth

(20)

GBP

1.0

MHz

Slew Rate

0.5

µs

Phase Margin (for Gain = 1, Load 100 pF/ /5.0 k

(20)

PHMO

Open Loop Gain

OLG

L1 and L2 Inputs

Negative Switching Threshold

5.5 V < V

SUP

< 6.0 V

6.0 V < V

SUP

< 18 V

18 V < V

SUP

< 27 V

THN

2.0
2.5
2.7

2.5
3.0
3.2

3.0
3.5
3.7

Positive Switching Threshold

5.5 V < V

SUP

< 6.0 V

6.0 V < V

SUP

< 18 V

18 V < V

SUP

< 27 V

THP

2.7

3.0

3.5

3.3

4.0

4.2

3.8

4.5

4.7

Hysteresis

5.5 V < V

SUP

< 27 V

HYST

0.5

1.3

Input Current

-0.2 V < V

< 40 V

-10

µA

Notes

20.

This parameter is guaranteed by process monitoring but is not production tested.

Table 3. Static Electrical Characteristics (continued)

All characteristics are for the analog chip only. Refer to the 68HC908EY16 datasheet for characteristics of the microcontroller

chip. Characteristics noted under conditions 9.0 V

SUP

16 V, -40

°C

125

°C unless otherwise noted. Typical values

noted reflect the approximate parameter mean at T

= 25

°C under nominal conditions unless otherwise noted.

Characteristic

Symbol

Min

Typ

Max

Unit

Analog Integrated Circuit Device Data

Freescale Semiconductor

908E624

Dynamic Electrical Characteristics

DYNAMIC ELECTRICAL CHARACTERISTICS

Table 4. Dynamic Electrical Characteristics

All characteristics are for the analog chip only. Please refer to the 68HC908EY16 datasheet for characteristics of the

microcontroller chip. Characteristics noted under conditions 9.0 V

SUP

16 V, -40

°C

125

°C unless otherwise noted.

Typical values noted reflect the approximate parameter mean at T

= 25

°C under nominal conditions unless otherwise noted.

Characteristic

Symbol

Min

Typ

Max

Unit

LIN Physical Layer

Driver Characteristics for Normal Slew Rate

(21)

(22)

Dominant Propagation Delay TXD to LIN

DOM-

MIN

µs

Dominant Propagation Delay TXD to LIN

DOM-

MAX

µs

Recessive Propagation Delay TXD to LIN

REC-

MIN

µs

Recessive Propagation Delay TXD to LIN

REC-

MAX

µs

Propagation Delay Symmetry: t

DOM-MIN

- t

REC-

MAX

dt1

-10.44

µs

Propagation Delay Symmetry: t

DOM-

MAX

- t

REC-

MIN

dt2

µs

Driver Characteristics for Slow Slew Rate

(21)

(23)

Dominant Propagation Delay TXD to LIN

DOM-

MIN

100

µs

Dominant Propagation Delay TXD to LIN

DOM-

MAX

100

µs

Recessive Propagation Delay TXD to LIN

REC-

MIN

100

µs

Recessive Propagation Delay TXD to LIN

REC-

MAX

100

µs

Propagation Delay Symmetry: t

DOM-

MIN

- t

REC-

MAX

dt1s

-22

µs

Propagation Delay Symmetry: t

DOM-MAX

- t

REC-

MIN

dt2s

µs

Driver Characteristics for Fast Slew Rate

LIN High Slew Rate (Programming Mode)

FAST

µs

Receiver Characteristics and Wake-Up Timings

Receiver Dominant Propagation Delay

(24)

3.5

6.0

µs

Receiver Recessive Propagation Delay

(24)

3.5

6.0

µs

Receiver Propagation Delay Symmetry

R-SYM

-2.0

2.0

µs

Bus Wake-Up Deglitcher

PROP

µs

Bus Wake-Up Event Reported

(25)

WAKE

µs

Notes

21.

SUP

from 7.0 V to 18 V, bus load R0 and C0 1.0 nF/1.0 k

, 6.8 nF/660 , 10 nF/500 . Measurement thresholds: 50% of TXD signal

to LIN signal threshold defined at each parameter.

22.

See

Figure 6

, page

23.

See

Figure 7

, page

24.

Measured between LIN signal threshold V

or V

and 50% of RXD signal.

25.

WAKE

is typically 2 internal clock cycles after LIN rising edge detected. See

Figure 8

and

Figure 9

, page

. In Sleep mode the V

rise time is strongly dependent upon the decoupling capacitor at VDD terminal.

Analog Integrated Circuit Device Data
Freescale Semiconductor

908E624

Dynamic Electrical Characteristics

SPI Interface Timing

SPI Operating Recommended Frequency

SPIOP

0.25

4.0

MHz

L1 AND L2 INPUTS

Wake-Up Filter Time

(26)

WUF

8.0

µs

Window Watchdog Configuration Terminal (WDCONF)

Watchdog Period

External Resistor R

EXT

= 10 k

(1%)

External Resistor R

EXT

= 100 k

(1%)

Without External Resistor R

EXT

(WDCONF Terminal Open)

--
--

10.558
99.748

150

--
--

205

State Machine Timing

Reset Low-Level Duration after V

High

RST

0.65

1.0

1.35

Interrupt Low-Level Duration

INT

7.0

µs

Normal Request Mode Timeout

TOUT

150

205

Delay Between SPI Command and HS1/HS2/HS3 Turn On

(27)

(28)

S-HS

3.0

µs

Delay Between SPI Command and HS1/HS2/HS3 Turn Off

(27)

(28)

S-HS

OFF

3.0

µs

Delay Between Normal Request and Normal Mode After W/D Trigger
Command

(29)

S-NR2N

6.0

µs

Delay Between SS Wake-Up (SS LOW to HIGH) and Normal Request Mode
(VDD On and Reset High)

W-SSB

µs

Delay Between SS Wake-Up (SS LOW to HIGH) and First Accepted SPI
Command

W-SPI

N/A

µs

Delay Between Interrupt Pulse and First SPI Command Accepted

S-1STSPI

N/A

µs

Minimum Time Between Two Rising Edges on SS

2SSB

µs

Notes

26.

This parameter is guaranteed by process monitoring but is not production tested.

27.

Delay between turn-on or turn-off command and high-side on or high-side off, excluding rise or fall time due to external load.

28.

Delay between the end of the SPI command (rising edge of the SS) and start of device activation/deactivation.

29.

This parameter is guaranteed by process monitoring but it is not production tested.

Table 4. Dynamic Electrical Characteristics (continued)

All characteristics are for the analog chip only. Please refer to the 68HC908EY16 datasheet for characteristics of the

microcontroller chip. Characteristics noted under conditions 9.0 V

SUP

16 V, -40

°C

125

°C unless otherwise noted.

Typical values noted reflect the approximate parameter mean at T

= 25

°C under nominal conditions unless otherwise noted.

Characteristic

Symbol

Min

Typ

Max

Unit

Analog Integrated Circuit Device Data
Freescale Semiconductor

908E624

Timing Diagrams

TIMING DIAGRAMS

Figure 4. Test Circuit for Transient Test Pulses

Figure 5. Test Circuit for LIN Timing Measurements

Figure 6. LIN Timing Measurements for Normal Slew Rate

LIN, L1, and L2

10k

1nF

Transient Pulse

Generator

Note Waveform in accordance with ISO7637 Part 1, Test Pulses 1, 2, 3a, and 3b.

10 k

1.0 nF

VSUP

RXD

TXD

LIN

R0 and C0 combinations:
- 1k Ohm and 1nF
- 660 Ohm and 6.8nF
- 500 Ohm and 10nF

R0 and C0 Combinations:
· 1.0 k

and 1.0 nF

· 600

and 6.8 nF

· 500

and 10 nF

Tdom-min

Tdom-max

TrL

TXD

LIN

RXD

Vrec

TrH

Trec-min

Trec-max

58.1% Vsup

40% Vsup

28.4% Vsup

42.2% Vsup

60% Vsup

74.4% Vsup

LIN_REC

DOM-MIN

58.1% V

SUP

40% V

SUP

28.4% V

SUP

DOM-MAX

42.4% V

SUP

60% V

SUP

74.4% V

SUP

REC-MAX

REC-MIN

Analog Integrated Circuit Device Data

Freescale Semiconductor

908E624

Timing Diagrams

Figure 7. LIN Timing Measurements for Slow Slew Rate

Figure 8. Wake-Up Sleep Mode Timing

Figure 9. Wake-Up Stop Mode Timing

Tdom-min

Tdom-max

TrL

TXD

LIN

RXD

Vrec

TrH

Trec-min

Trec-max

58.1% Vsup

40% Vsup

28.4% Vsup

42.2% Vsup

60% Vsup

74.4% Vsup

LIN_REC

DOM-MIN

61.6% V

SUP

40% V

SUP

25.1% V

SUP

DOM-MAX

38.9% V

SUP

60% V

SUP

77.8% V

SUP

REC-MAX

REC-MIN

VDD

LIN

Vrec

TpropWL

Twake

Dominant level

0.4VSUP

LIN_REC

0.4 V

SUP

Dominant Level

PROP

WAKE

IRQ_A

LIN

Vrec

TpropWL

Twake

Dominant level

0.4VSUP

PROP

WAKE

Dominant Level

0.4 V

SUP

LIN_REC

Analog Integrated Circuit Device Data
Freescale Semiconductor

908E624

Functional Description

Introduction

FUNCTIONAL DESCRIPTION

INTRODUCTION

The 908E624 was designed and developed as a highly

integrated and cost-effective solution for automotive and
industrial applications. For automotive body electronics, the
908E624 is well suited to perform relay control in applications
like window lift, sunroof, etc., via a three-wire LIN bus.

The device combines an HC908EY16 MCU core with flash

memory together with a SmartMOS IC chip. The SmartMOS
IC chip combines power and control in one chip. Power
switches are provided on the SmartMOS IC configured as

high-side outputs. Other ports are also provided, which
include an operational amplifier port and two wake-up
terminals. An internal voltage regulator provides power to the
MCU chip.

Also included in this device is a LIN physical layer, which

communicates using a single wire. This enables this device
to be compatible with three-wire bus systems, where one wire
is used for communication, one for battery, and one for
ground.

FUNCTIONAL TERMINAL DESCRIPTION

See

Figure 1, 908E624 Simplified Application Diagram

page

, for a graphic representation of the various terminals

referred to in the following paragraphs. Also, see the terminal
diagram on

page 3

for a depiction of the terminal locations on

the package.

PORT A I/O TERMINALS

These terminals are special-function, bidirectional I/O port

terminals that are shared with other functional modules in the
MCU. PTA0:PTA4 are shared with the keyboard interrupt
terminals KBD0:KBD4.

The PTA5/SPSCK terminal is not accessible in this device

and is internally connected to the SPI clock terminal of the
analog die. The PTA6/

terminal is likewise

not accessible.

For details refer to the 68HC908EY16 datasheet.

PORT B I/O TERMINALS

These terminals are special-function, bidirectional I/O port

terminals that are shared with other functional modules in the
MCU. All terminals are shared with the ADC module. The
PTB6:PTB7 terminals are also shared with the Timer B
module.

The PTB0/AD0 and PTB2/AD2 terminals are not

accessible in this device.

For details refer to the 68HC908EY16 datasheet.

PORT C I/O TERMINALS

These terminals are special-function, bidirectional I/O port

terminals that are shared with other functional modules in the
MCU.

For example, PTC2:PTC4 are shared with the ICG

module.

PTC0/MISO and PTC1/MOSI are not accessible in this

device and are internally connected to the MISO and MOSI
SPI terminals of the analog die.

For details refer to the 68HC908EY16 datasheet.

PORT D I/O TERMINALS

PTD1/TACH1 and PTD0/TACH0/BEMF are special-

function, bidirectional I/O port terminals that can also be
programmed to be timer terminals.

For details refer to the 68HC908EY16 datasheet.

PORT E I/O TERMINAL

PTE1/RXD and PTE0/TXD are special-function,

bidirectional I/O port terminals that can also be programmed
to be enhanced serial communication.

PTE0/TXD is internally connected to the TXD terminal of

the analog die.

The connection for the receiver must be done

externally.

For details refer to the 68HC908EY16 datasheet.

EXTERNAL INTERRUPT TERMINAL (IRQ)

The

IRQ

terminal is an asynchronous external interrupt

terminal. This terminal contains an internal pullup resistor that
is always activated, even when the

IRQ

terminal is pulled

LOW.

For details refer to the 68HC908EY16 datasheet.

EXTERNAL RESET TERMINAL (RST)

A logic [0] on the

RST

terminal forces the MCU to a known

startup state. It is driven LOW when any internal reset source
is asserted.

This terminal contains an internal pullup resistor that is

always activated, even when the reset terminal is pulled
LOW.

Important

To ensure proper operation, do not add any

external pullup resistor.

For details refer to the 68HC908EY16 datasheet.

MCU POWER SUPPLY TERMINALS (EVDD AND
EVSS)

EVDD

and EVSS

are the power supply and ground

terminals, respectively. The MCU operates from a single-
power supply.

Analog Integrated Circuit Device Data

Freescale Semiconductor

908E624

Functional Description

Functional Terminal Description

Fast signal transitions on MCU terminals place high, short-

duration current demands on the power supply. To prevent
noise problems, take special care to provide power supply
bypassing at the MCU.

For details refer to the 68HC908EY16 datasheet.

ADC SUPPLY TERMINALS (VDDA AND VSSA)

VDDA and VSSA

are the power supply terminals for the

analog-to-digital converter (ADC). It is recommended that a
high-quality ceramic decoupling capacitor be placed between
these terminals.

Important

VDDA is the supply for the ADC and should be

tied to the same potential as EVDD via separate traces.
VSSA is the ground terminal for the ADC and should be tied
to the same potential as EVSS via separate traces.

For details refer to the 68HC908EY16 datasheet.

ADC REFERENCE TERMINALS (VREFL AND
VREFH)

VREFL and VREFH are the reference voltage terminals for

the ADC. It is recommended that a high-quality ceramic
decoupling capacitor be placed between these terminals.

Important

VREFH is the high reference supply for the

ADC and should be tied to the same potential as VDDA via
separate traces. VREFL is the low reference supply for the
ADC and should be tied to the same potential as VSSA via
separate traces.

For details refer to the 68HC908EY16 datasheet.

TEST TERMINAL (FLSVPP)

This terminal is for test purposes only. Do not connect in

the application.

PWMIN TERMINAL

This terminal is the direct PWM input for high-side

outputs 1 and 2 (HS1 and HS2). If no PWM control is
required, PWMIN must be connected to VDD to enable the
HS1 and HS2 outputs.

LIN TRANSCEIVER OUTPUT TERMINAL (RXD)

This terminal is the output of LIN transceiver. The terminal

must be connected to the microcontroller's Enhanced Serial
Communications Interface (ESCI) module (RXD terminal).

RESET TERMINAL (RST_A)

RST_A

is the reset output terminal of the analog die and

must be connected to the

RST

terminal of the MCU.

Important

To ensure proper operation, do not add any

external pullup resistor.

INTERRUPT TERMINAL (IRQ_A)

IRQ_A

is the interrupt output terminal of the analog die

indicating errors or wake-up events. This terminal must be
connected to the

IRQ

terminal of the MCU.

WINDOW WATCHDOG CONFIGURATION
TERMINAL (WDCONF)

This terminal is the configuration terminal for the internal

watchdog. A resistor is connected to this terminal. The
resistor value defines the watchdog period. If the terminal is
open, the watchdog period is fixed to its default value.

The watchdog can be disabled (e.g., for flash

programming or software debugging) by connecting this
terminal to GND.

POWER SUPPLY TERMINALS (VSUP1 AND

VSUP2)

This VSUP1 power supply terminal supplies the voltage

regulator, the internal logic, and LIN transceiver.

This VSUP2 power supply terminal is the positive supply

for the high-side switches.

POWER GROUND TERMINAL (GND)

This terminal is the device ground connection.

HIGH-SIDE OUTPUT TERMINALS (HS1 AND HS2)

These terminals are high-side switch outputs to drive loads

such as relays or lamps. Each switch is protected with
overtemperature and current limit (overcurrent). The output
has an internal clamp circuitry for inductive load. The HS1
and HS2 outputs are controlled by SPI and have a direct
enabled input (PWMIN) for PWM capability.

HIGH-SIDE OUTPUT TERMINAL (HS3)

This high-side switch can be used to drive small lamps,

Hall-effect sensors, or switch pullup resistors. The switch is
protected with overtemperature and current limit
(overcurrent). The output is controlled only by SPI.

LIN BUS TERMINAL (LIN)

The LIN terminal represents the single-wire bus

transmitter and receiver. It is suited for automotive bus
systems and is based on the LIN bus specification.

WAKE-UP TERMINALS (L1 AND L2)

These terminals are high-voltage capable inputs used to

sense external switches and to wake up the device from
Sleep or Stop mode. During Normal mode the state of these
terminals can be read through SPI.

Analog Integrated Circuit Device Data
Freescale Semiconductor

908E624

Functional Description

Functional Terminal Description

SENSE AMPLIFIER TERMINALS (E+, E-, OUT, VCC)

These are the terminals of the single-supply sense

amplifier.

· The E+ and E- input terminals are the non-inverting and

inverting inputs of the amplifier, respectively.

· The OUT terminal is the output terminal of the current

sense amplifier.

· The VCC terminal is the +5.0 V single-supply

connection.

+5.0 V VOLTAGE REGULATOR OUTPUT
TERMINAL (VDD)

The VDD terminal is needed to place an external capacitor

to stabilize the regulated output voltage. The VDD terminal is

intended to supply the embedded microcontroller. The
terminal is protected against shorts to GND with an integrated
current limit (temperature shutdown could occur).

Important

The VDD, EVDD, VDDA, and VREFH terminals

must be connected together.

VOLTAGE REGULATOR AND SENSE AMPLIFIER
GROUND TERMINAL (AGND)

The AGND terminal is the ground terminal of the voltage

regulator and the Sense Amplifier.

Important

GND, AGND, VSS, EVSS, VSSA, and VREFL

terminals must be connected together.

Analog Integrated Circuit Device Data

Freescale Semiconductor

908E624

Functional Description

Functional Device Operation

FUNCTIONAL DEVICE OPERATION

OPERATIONAL MODES

908E624 ANALOG DIE MODES OF OPERATION

The 908E624 offers three operating modes: Normal (Run),

Stop, and Sleep. In Normal mode the device is active and is
operating under normal application conditions. The Stop and
Sleep modes are low-power modes with wake-up
capabilities.

In Stop mode the voltage regulator still supplies the MCU

with V

(limited current capability) and in Sleep mode the

voltage regulator is turned off (V

= 0 V).

Wake-up from Stop mode is initiated by a wake-up

interrupt. Wakeup from Sleep mode is done by a reset and
the voltage regulator is turned back on.

The selection of the different modes is controlled by the

MODE1:2 bits in the SPI Control register.

Figure 10

describes how transitions are done between the

different operating modes and

Table 6

, page

, gives an

overview of the operating mode.

Figure 10. Operating Modes and Transitions

Reset

Power

Down

Notes:
WD - means Watchdog
WD disabled - means Watchdog disabled (WDCONF terminal connected to GND)
WD trigger means Watchdog is triggered by SPI command
WD failed means no Watchdog trigger or trigger occurs in closed window
STOP Command - means STOP command sent via SPI
SLEEP Command - means SLEEP command send via SPI
Wake-Up - means L1 or L2 state change or LIN bus wake up or SS rising edge

Normal

Request

High and Reset Delay (t

RST

) expired

Normal

Normal Request timeout expired (NR

TOUT

)

tri

gge

Sleep

Wake-Up (Reset)

Stop

Low

Low (>NR

TOUT

) expired

and VSUV = 0

SLEEP Command

Low

Comm

and

a
k
e
-U

p Int

rru

WD dis

l
ed

Low

WD failed

Normal Request Timeout Expired (NR

TOUT

)

High and

Reset Delay (t

RST

) Expired

Low

WD Failed

LOW (>NR

TOUT

) Expired

and LVF = 0

Sleep Command

ep Comma

Wake-Up (Reset)

r
i
g

ger

s
abl

Power Up

ke-

p I

n
t
e
r
r
upt

Legend
WD: Watchdog
WD Disabled: Watchdog disabled (WDCONF terminal connected to GND)
WD Trigger: Watchdog is triggered by SPI command
WD Failed: No watchdog trigger or trigger occurs in closed window
Stop Command: Stop command sent via SPI
Sleep Command: Sleep command sent via SPI
Wake-Up: L1 or L2 state change or LIN bus wake-up or

rising edge

Low

Analog Integrated Circuit Device Data
Freescale Semiconductor

908E624

Functional Description

Functional Device Operation

INTERRUPTS

In Normal (Run) mode the 908E624 has four different

interrupt sources. An interrupt pulse on the

IRQ_A

terminal is

generated to report a fault to the MCU. All interrupts are not
maskable and cannot be disabled.

After an Interrupt the INTSRC bit in the SPI Status register

is set, indicating the source of the event. This interrupt source
information is only transferred once, and the INTSRC bit is
cleared automatically.

Low-Voltage Interrupt

Low-voltage interrupt (LVI) is related to external supply

voltage VSUP1. If this voltage falls below the LVI threshold,
it will set the LVF bit in the SPI Status register and an interrupt
will be initiated. The LVF bit remains set as long as the Low-
voltage condition is present.

During Sleep and Stop mode the low-voltage interrupt

circuitry is disabled.

High-Voltage Interrupt

High-voltage interrupt (HVI) is related to external supply

voltage VSUP1. If this voltage rises above the HVI threshold,
it will set the HVF bit in the SPI Status register and an
interrupt will be initiated. The HVF bit remains set as long as
the high-voltage condition is present.

During Sleep and Stop mode the low-voltage interrupt

circuitry is disabled.

Wake-Up Interrupts

In Stop mode the

IRQ_A

terminal reports wake-up events

on the L1, L2, or the LIN bus to the MCU. All wake-up
interrupts are not maskable and cannot be disabled.

After a wake-up interrupt, the INTSRC bit in the Serial

Peripheral Interface (SPI) Status register is set, indicating the
source of the event. This wake-up source information is only
transferred once, and the INTSRC bit is cleared
automatically.

Figure 11

, page

, describes the Stop/Wake-Up

procedure.

VOLTAGE REGULATOR TEMPERATURE
PREWARNING (VDDT)

Voltage regulator temperature prewarning (VDDT) is

generated if the voltage regulator temperature is above the
T

PRE

threshold, it will set the VDDT bit in the SPI Status

During Sleep and Stop mode the voltage regulator

temperature prewarning circuitry is disabled.

HIGH-SIDE SWITCH THERMAL SHUTDOWN
(HSST)

The high-side switch thermal shutdown HSST is

generated if one of the high-side switches HS1:HS3 is above
the HSST threshold, it will shutdown the corresponding High-
side switch, set the HSST flag in the SPI Status register and
an interrupt will be initiated. The HSST bit remains set as long
as the error condition is present.

During Sleep and Stop mode the high-side switch thermal

shutdown circuitry is disabled.

Table 6. Operating Modes Overview

Device

Mode

Voltage Regulator

Wake-Up

Capabilities

RST_A

Output

Watchdog

Function

HS1, HS2,

and HS3

LIN Interface

Sense

Amplifier

Reset

N/A

LOW

Disabled

Recessive only

Not active

Normal

Request

N/A

HIGH

150 ms time out if

WD enabled

Enabled

Transmit and

receive

Not active

Normal

(Run)

N/A

HIGH

Window WD if

enabled

Enabled

Transmit and

receive

Active

Stop

ON with limited

current capability

LIN wake-up,

L1, L2 state change,

rising edge

HIGH

Disabled

Recessive state with

wake-up capability

Not active

Sleep

OFF

LIN wake-up

L1, L2 state change

LOW

Disabled

Recessive state with

wake-up capability

Not active

Analog Integrated Circuit Device Data

Freescale Semiconductor

908E624

Functional Description

Functional Device Operation

Figure 11. Stop Mode/Wake-Up Procedure

ANALOG DIE INPUTS/OUTPUTS

High-Side Output Terminals HS1 and HS2

These are two high-side switches used to drive loads such

as relays or lamps. They are protected with overtemperature
and current limit (overcurrent) and include an active internal
clamp circuitry for inductive load drive. Control is done using
the SPI Control register. PWM capability is offered through
the PWMIN input terminal.

The high-side switch is turned on if both the HSxON bit in

the SPI Control register is set and the PWMIN input is HIGH
(refer to

Figure 12

, page

). In order to have HS1 on, the

PWMIN must be HIGH and bit HS1ON must be set. The
same applies to the HS2 output.

If no PWM control is required, PWMIN must be connected

to the VDD terminal.

Current Limit (Overcurrent) Protection

These high-side switches feature current limit to protect

them against overcurrent and short circuit conditions.

Overtemperature Protection

If an overtemperature condition occurs on any of the three

high-side switches, the faulty switch is turned off and latched
off until the HS1 (or HS2 or HS3) bit is set to "1" in the SPI
Control register. The failure is reported by the HSST bit in the
SPI Control register.

Sleep and Stop Mode

In Sleep and Stop modes the high-sides are disabled.

High-Side Output HS3

This high-side switch can be used to drive small lamps,

Hall-effect sensors, or switch pullup resistors. Control is done
using the SPI Control register. No direct PWM control is
possible on this terminal (refer to

Figure 13

, page

Current Limit (Overcurrent) Protection

This high-side feature switch feature current limit to protect

it against overcurrent and short circuit conditions.

Overtemperature Protection

If an overtemperature condition occurs on any of the three

high-side switches, the faulty switch is turned off and latched
off until the HS3 (or HS1 or HS2) bit is set to "1" in the SPI
Control register. The failure is reported by the HSST bit in the
SPI Control register.

Sleep and Stop Mode

In Sleep and Stop mode the high-side is disabled.

From Reset

initialize

operate

SPI:

2x STOP

Command

STOP

IRQ

interrupt

SPI: reason for

interrupt

operate

Switch to VREG

low current mode

Assert IRQ

Switch to VREG

high current mode

MCU

Power Die

Wake Up on

LIN or L1, L2?

Analog Integrated Circuit Device Data
Freescale Semiconductor

908E624

Functional Description

Functional Device Operation

Figure 12. High-Side HS1 and HS2 Circuitry

Figure 13. High-Side HS3 Circuitry

WINDOW WATCHDOG

The window watchdog is configurable using an external

resistor at the WDCONF terminal. The watchdog is cleared
through by the MODE1:2 bits in the SPI Control register (refer
to

Table 8

, page

A watchdog clear is only allowed in the open window. If the

watchdog is cleared in the closed window or has not been
cleared at the end of the open window, the watchdog will
generate a reset on the

RST_A

terminal and reset the whole

device.

Note

The watchdog clear in Normal request mode

(150 ms) (first watchdog clear) has no window.

Figure 14. Window Watchdog Operation

VSUP2

HSx

High-Side Driver

Charge Pump,

Current Limit Protection,

Overtemperature Protection

Control

On/Off

Status

MODE1:2

HSxON

PWMIN

VSUP2

HS3

High-Side Driver

Charge Pump,

Current Limit Protection,

Overtemperature Protection

Control

On/Off

Status

MODE1:2

HS3ON

Window closed

no watchdog clear allowed

Window open

for watchdog clear

WD timing x 50%

WD period (P

)

WD timing selected by resistor on WDCONF terminal.

Analog Integrated Circuit Device Data

Freescale Semiconductor

908E624

Functional Description

Functional Device Operation

Watchdog Configuration

If the WDCONF terminal is left open, the default watchdog

period is selected (typ. 150 ms). If no watchdog function is
required, the WDCONF terminal must be connected to GND.

The watchdog period is calculated using the following

formula:

[ms] = 0.991

EXT

] + 0.648

VOLTAGE REGULATOR

The 908E624 chip contains a low-power, low dropout

voltage regulator to provide internal power and external
power for the MCU. The on-chip regulator consist of two
elements, the main voltage regulator and the low-voltage
reset circuit.

The V

regulator accepts an unregulated input supply

and provides a regulated V

supply to all digital sections of

the device. The output of the regulator is also connected to
the VDD terminal to provide the 5.0 V to the microcontroller.

Current Limit (Overcurrent) Protection

The voltage regulator has current limit to protect the device

against overcurrent and short circuit conditions.

Overtemperature Protection

The voltage regulator also features an overtemperature

protection having an overtemperature warning (Interrupt -
VDDT) and an overtemperature shutdown.

Stop Mode

During Stop mode the Stop mode regulator supplies a

regulated output voltage. The Stop mode regulator has a
limited output current capability.

Sleep Mode

In Sleep mode the voltage regulator external V

is turned

off.

FACTORY TRIMMING AND CALIBRATION

To enhance the ease-of-use of the 908E624, various

parameters (e.g., ICG trim value) are stored in the flash
memory of the device. The following flash memory locations
are reserved for this purpose and might have a value different
from the "empty" (0xFF) state:

· 0xFD80:0xFDDF Trim and Calibration Values
· 0xFFFE:0xFFFF Reset Vector
In the event the application uses these parameters, one

has to take care not to erase or override these values. If these
parameters are not used, these flash locations can be erased
and otherwise used.

OPERATING MODES OF THE MCU

For a detailed description of the operating modes of the

MCU, refer to the MC68HC908EY16 datasheet.

Analog Integrated Circuit Device Data
Freescale Semiconductor

908E624

Functional Description

Functional Device Operation

LOGIC COMMANDS AND REGISTERS

908E624 SPI INTERFACE AND CONFIGURATION

The serial peripheral interface creates the communication

link between the microcontroller and the analog die of the
908E624.

The interface consists of four terminals (see

Figure 15

--Slave Select

· MOSI--Master-Out Slave-In
· MISO--Master-In Slave-Out
· SPSCK--Serial Clock
A complete data transfer via the SPI consists of 1 byte.

The master sends 8 bits of control information and the slave
replies with 8 bits of status data.

Figure 15. SPI Protocol

During the inactive phase of the

(High), the new data

transfer is prepared.

The falling edge of the

indicates the start of a new data

transfer and puts the MISO in the low-impedance state and
latches the analog status data (Register read data).

With the rising edge of the SPI clock, SPSCK the data is

moved to MISO/MOSI terminals. With the falling edge of the
SPI clock SPSCK the data is sampled by the Receiver.

The data transfer is only valid if exactly 8 sample clock

edges are present in the active (low) phase of

The rising edge of the slave select

indicates the end of

the transfer and latches the write data (MOSI) into the
register The

high forces MISO to the high impedance

state.

Rising edge of SPSCK

Change MISO/MOSI Output

Falling edge of SPSCK
Sample MISO/MOSI Input

Write data latch

MOSI

MISO

SPSCK

Read data latch

Analog Integrated Circuit Device Data

Freescale Semiconductor

908E624

Functional Description

Functional Device Operation

SPI REGISTER OVERVIEW

Table 7

summarizes the SPI Register bit meaning, reset

value, and bit reset condition.

SPI Control Register (Write)

Table 8

shows the SPI Control register bits by name.

LINSL2:1--LIN Baud Rate and Low-Power Mode
Selection Bits

These bits select the LIN slew rate and requested low-

power mode in accordance with

Table 9

. Reset clears the

LINSL2:1 bits.

LIN-PU--LIN Pullup Enable Bit

This bit controls the LIN pullup resistor during Sleep and

Stop modes.

· 1 = Pullup disconnected in Sleep and Stop modes.
· 0 = Pullup connected in Sleep and Stop modes.

HS3ON:HS1ON--High-Side H3:HS1 Enable Bit

This bit enables the HSx. Reset clears the HSx bit.
· 1 = HSx switched on (refer to Note below).
· 0 = HSx switched off.
Note

If no PWM on HS1 and HS2 is required, the PWMIN

terminal must be connected to the VDD terminal.

MODE2:1--Mode Section Bits

The MODE2:1 bits control the operating modes and the

watchdog in accordance with

Table 10

To safely enter Sleep or Stop mode and to ensure that

these modes are not affected by noise issue during SPI
transmission, the Sleep/Stop commands require two SPI
transmissions.

Table 7. SPI Register Overview

Read/Write

Information

Bit

Write

LINSL2

LINSL1

LIN-PU

HS3ON

HS2ON

HS1ON

MODE2

MODE1

Read

INTSRC

(30)

LINWU

LINFAIL

HVF

LVF

BATFAIL

(31)

VDDT

HSST

Write Reset Value

Write Reset Condition

POR,

RESET

POR,

RESET

POR

POR, RESET

POR,

RESET

POR,

RESET

Notes

30.

D7 signals interrupts and wake-up interrupts, D6:D0 indicated the source.

31.

The first SPI read after reset returns the BATFAIL flag state on bit D4.

Table 8. Control Bits Function (Write Operation)

LINSL2 LINSL1 LIN-PU HS3ON HS2ON HS1ON MODE2 MODE1

Table 9. LIN Baud Rate and Low-Power Mode Selection

Bits

LINSL2

LINSL1

Description

Baud Rate up to 20 kbps (normal)

Baud Rate up to 10 kbps (slow)

Fast Program Download

Baud Rate up to 100 kbps

Low-Power Mode (Sleep or Stop) Request

Table 10. Mode Selection Bits

MODE2

MODE1

Description

Sleep Mode

(32)

Stop Mode

(32)

Watchdog Clear

(33)

Run (Normal) Mode

Notes

32.

To enter Sleep and Stop mode, a special sequence of SPI
commands is implemented.

33.

The device stays in Run (Normal) mode.

Analog Integrated Circuit Device Data
Freescale Semiconductor

908E624

Functional Description

Functional Device Operation

Sleep Mode Sequence

The Sleep command, as shown in

Table 11

, has to be sent

twice.

Stop Mode Sequence

The Stop command, as shown in

Table 12

, has to be sent

twice.

SPI Status Register (Read)

Table 13

shows the SPI Status register bits by name.

INTSCR --Register Content Flags or Interrupt Source

This bit indicates if the register contents reflect the flags or

an interrupt/wake-up interrupt source.

· 1 = D6:D0 reflects the interrupt or wake-up source.
· 0 = No interrupt occurred. Other SPI bits report real time

status.

LINWU/LINFAIL--LIN Status Flag Bit

This bit indicates a LIN wake-up condition.
· 1 = LIN bus wake-up occurred or LIN overcurrent/

overtemperature occurred.

· 0 = No LIN bus wake-up occurred.

HVF --High-Voltage Flag Bit

This flag is set on an overvoltage (VSUP1) condition.
· 1 = High-voltage condition has occurred.
· 0 = no High-voltage condition.

LVF/BATFAIL--Low-Voltage Flag Bit

This flag is set on an undervoltage (VSUP1) condition.
· 1 = Low-voltage condition has occurred.
· 0 = No low-voltage condition.

VDDT--Voltage Regulator Status Flag Bit

This flag is set as pre-warning in case of an over-

temperature condition on the voltage regulator.

· 1 = Voltage regulator overtemperature condition, pre-

warning.

· 0 = No overtemperature detected.

HSST--High-Side Status Flag Bit

This flag is set on overtemperature conditions on one of

the high-side outputs.

· 1 = HSx off due to overtemperature.
· 0 = No overtemperature.

L2:L1-- Wake-Up Inputs L1, L2 Status Flag Bit

These flags reflect the status of the L2 and L1 input

terminals and indicate the wake-up source.

· 1 = L2:L1 input high or wake-up by L2:L1 (first register

read after wake-up indicated with INTSRC = 1).

· 0 = L2:L1 input low.

Table 11. Sleep Command Bits

LINSL2 LINSL1 LIN-PU HS3ON HS2ON HS1ON MODE

MODE

x = Don't care.

Table 12. Stop Command Bits

LINSL2 LINSL1 LIN-PU

HS3O

HS2O

HS1O

MODE2 MODE1

x = Don't care.

Table 13. Control Bits Function (Read Operation)

INTSRC

LINWU

LINFAIL

HVF

LVF

BATFAIL

VDDT

HSST

Analog Integrated Circuit Device Data

Freescale Semiconductor

908E624

Package Dimensions

PACKAGE DIMENSIONS

Important

For the most current revision of the package,

visit www.freescale.com and do a keyword search on the 98A
drawing number below.

CASE 1365-01

ISSUE O

DATE 09/19/01

NOTES:

ALL DIMENSIONS ARE IN MILLIMETERS.

DIMENSIONING AND TOLERANCING PER ASME

Y14.5M, 1994.

DATUMS B AND C TO BE DETERMINED AT THE PLANE

WHERE THE BOTTOM OF THE LEADS EXIT THE

PLASTIC BODY.

THIS DIMENSION DOES NOT INCLUDE MOLD FLASH,

PROTRUSION OR GATE BURRS. MOLD FLASH,

PROTRUSION OR GATE BURRS SHALL NOT EXCEED

0.15 MM PER SIDE. THIS DIMENSION IS DETERMINED

AT THE PLANE WHERE THE BOTTOM OF THE LEADS

EXIT THE PLASTIC BODY.

THIS DIMENSION DOES NOT INCLUDE INTERLEAD

FLASH OR PROTRUSIONS. INTERLEAD FLASH AND

PROTRUSIONS SHALL NOT EXCEED 0.25 MM PER

SIDE. THIS DIMENSION IS DETERMINED AT THE

PLANE WHERE THE BOTTOM OF THE LEADS EXIT THE

PLASTIC BODY.

THIS DIMENSION DOES NOT INCLUDE DAMBAR

PROTRUSION. ALLOWABLE DAMBAR PROTRUSION

SHALL NOT CAUSE THE LEAD WIDTH TO EXCEED 0.46

MM. DAMBAR CANNOT BE LOCATED ON THE LOWER

RADIUS OR THE FOOT. MINIMUM SPACE BETWEEN

PROTRUSION AND ADJACENT LEAD SHALL NOT LESS

THAN 0.07 MM.

EXACT SHAPE OF EACH CORNER IS OPTIONAL.

THESE DIMENSIONS APPLY TO THE FLAT SECTION

OF THE LEAD BETWEEN 0.1 MM AND 0.3 MM FROM

THE LEAD TIP.

THE PACKAGE TOP MAY BE SMALLER THAN THE

PACKAGE BOTTOM. THIS DIMENSION IS

DETERMINED AT THE OUTERMOST EXTREMES OF

THE PLASTIC BODY EXCLUSIVE OF MOLD FLASH, TIE

BAR BURRS, GATE BURRS AND INTER-LEAD FLASH,

BUT INCLUDING ANY MISMATCH BETWEEN THE TOP

AND BOTTOM OF THE PLASTIC BODY.

17.8

7.4

0.10

2.35

SEATING

PLANE

0.9

SECTION B-B

0.65

R0.08 MIN

(0.29)

0.38

0.30

(0.25)

PLATING

BASE METAL

SECTION A-A

ROTATED 90 CLOCKWISE

0.25

0.22

0.13

A B

7.6

18.0

10.3

5.15

54X

52X

2.65

0.3 A

2X 27 TIPS

B C

0.29

0.13

0.5

0.25

GAUGE PLANE

MIN

PIN 1 INDEX

DWB SUFFIX

54-TERMINAL SOIC WIDE BODY

PLASTIC PACKAGE

98ASA99294D

ISSUE O

MM908E624DWTAD

Rev 2.0, 12/2004

Freescale Semiconductor
Technical Data

Integrated Triple High-Side

Switch with Embedded MCU

and LIN Serial Communication

for Relay Drivers

Introduction

This package is a dual die package. There are two heat sources in

the package independently heating with P

and P

. This results in two

junction temperatures, T

and T

, and a thermal resistance matrix

with R

JAmn

For m, n = 1, R

JA11

is the thermal resistance from Junction 1 to

the reference temperature while only heat source 1 is heating with P

For m = 1, n = 2, R

JA12

is the thermal resistance from Junction 1

to the reference temperature while heat source 2 is heating with P

This applies to R

J21

and R

J22

, respectively.

The stated values are solely for a thermal performance

comparison of one package to another in a standardized
environment. This methodology is not meant to and will not predict
the performance of a package in an application-specific environment.
Stated values were obtained by measurement and simulation
according to the standards listed below.

54-TERMINAL

SOICW

908E624DW

DW SUFFIX

98ASA99294D

54-TERMINAL SOICW

Note

For package dimensions, refer to the 908E624

device datasheet.

JA11

JA21

JA12

JA22

Standards

Table 1. Thermal Performance Comparison

Thermal

Resistance

1 = Power Chip, 2 = Logic Chip (

°C/W)

m = 1,

n = 1

m = 1, n = 2
m = 2, n = 1

m = 2,

n = 2

JAmn

JBmn

JAmn

JCmn

Analog Integrated Circuit Device Data

Freescale Semiconductor

908E624DW

Figure 1. Thermal Test Board

Device on Thermal Test Board

JAmn

is the thermal resistance between die junction and

ambient air.

This device is a dual die package. Index m indicates the die

that is heated. Index n refers to the number of the die where
the junction temperature is sensed.

908E624 Terminal Connections

54-Terminal SOICW

0.65 mm Pitch

17.9 mm x 7.5 mm Body

PTA0/KBD0
PTA1/KBD1
PTA2/KBD2

PTA3/KBD3
PTA4/KBD4
VREFH
VDDA
EVDD
EVSS
VSSA
VREFL
PTE1/RXD
NC
RXD
WDCONF
+E
-E
OUT
VCC
AGND
VDD
NC
VSUP1
GND
LIN
VSUP2

FLSVPP

PTB7/AD7/TBCH1

PTB6/AD6/TBCH0

PTC4/OSC1
PTC3/OSC2

PTC2/MCLK

PTB5/AD5
PTB4/AD4
PTB3/AD3

IRQ

RST

PTB1/AD1

PTD0/TACH0

PTD1/TACH1

NC
NC
NC

PWMIN

RST_A

IRQ_A

NC
NC
NC

L1
L2

HS3
HS2
HS1

11
12
13
14
15
16
17
18
19
20

9
10

21
22
23
24
25
26
27

6
7
8

4
5

2
3

44
43
42
41
40
39
38
37
36
35

46
45

34
33
32
31
30
29
28

49
48
47

51
50

53
52

Material:

Single layer printed circuit board
FR4, 1.6 mm thickness
Cu traces, 0.07 mm thickness

Outline:

80 mm x 100 mm board area,
including edge connector for thermal
testing

Area A:

Cu heat-spreading areas on board
surface

Ambient Conditions: Natural convection, still air

Table 2. Thermal Resistance Performance

Terminal

Resistance

Area A

(mm

)

1 = Power Chip, 2 = Logic Chip (

C/W)

m = 1,

n = 1

m = 1, n = 2
m = 2, n = 1

m = 2,

n = 2

300

600

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MM908E624
Rev. 4.0
12/2004

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