Technical Data

DSP56301/D
Rev. 6, 11/2002

24-Bit Digital Signal
Processor

Figure 1. DSP56301 Block Diagram

PLL

OnCETM

Clock

Internal

Data

Bus

Switch

Program

RAM

4096

24 bits

(Default)

YAB

XAB
PAB

YDB

XDB

PDB

GDB

MODC/IRQC
MODB/IRQB

External

Data

Bus

MODA/IRQA

DSP56300

24-Bit

X Data

RAM

2048

bits

(Default)

Y Data

RAM

2048

bits

(Default)

DDB

DAB

Memory Expansion Area

Peripheral

Core

Expansion Area

SCI

JTAG

RESET

MODD/IRQD

PINIT/NMI

Boot-

strap

ROM

EXTAL

XTAL

Triple
Timer

Host

Interface

ESSI

Address

Generator

Unit

Six-Channel

DMA Unit

Program
Interrupt

Controller

Program

Decode

Controller

Program

Address

Generator

Data ALU

24+56

56-bit MAC

Two 56-bit Accumulators

56-bit Barrel Shifter

Power

Management

External

Bus

Interface

and

I-Cache

Control

External

Address

Bus

Switch

ddr

on-

Da
t

The DSP56301 is
intended for
general-purpose
digital signal
processing,
particularly in
multimedia and
telecommunication
applications, such as
video conferencing
and cellular
telephony

The

DSP56301

is a member of the

DSP56300

core family of programmable CMOS Digital
Signal Processors (DSPs). This family uses a
high-performance, single clock cycle per
instruction engine providing a twofold
performance increase over Motorola's popular
DSP56000 core family while retaining code
compatibility.

Significant architectural features of the DSP56300
core family include a barrel shifter, 24-bit
addressing, instruction cache, and DMA. The
DSP56301 offers 80/100 MIPS using an internal
80/100 MHz clock at 3.03.6 volts. The DSP56300
core family offers a rich instruction set and low
power dissipation, as well as increasing levels of
speed and power, enabling wireless,
telecommunications, and multimedia products.

Table of Contents

DSP56301 Features ............................................................................................................................................ iii
Target Applications ............................................................................................................................................ iv
Product Documentation...................................................................................................................................... iv

Chapter 1

Signal/ Connection Descriptions

1.1

Signal Groupings.............................................................................................................................................. 1-1

1.2

Power................................................................................................................................................................ 1-4

1.3

Ground.............................................................................................................................................................. 1-4

1.4

Clock ................................................................................................................................................................ 1-5

1.5

Phase Lock Loop (PLL) ................................................................................................................................... 1-6

1.6

External Memory Expansion Port (Port A)...................................................................................................... 1-6

1.7

Interrupt and Mode Control ............................................................................................................................. 1-9

1.8

Host Interface (HI32) ..................................................................................................................................... 1-11

1.9

Enhanced Synchronous Serial Interface 0 (ESSI0)........................................................................................ 1-19

1.10

Enhanced Synchronous Serial Interface 1 (ESSI1)........................................................................................ 1-21

1.11

Serial Communication Interface (SCI)........................................................................................................... 1-23

1.12

Timers............................................................................................................................................................. 1-24

1.13

JTAG/OnCE Interface .................................................................................................................................... 1-25

Chapter 2

Specifications

2.1

Introduction ...................................................................................................................................................... 2-1

2.2

Maximum Ratings ............................................................................................................................................ 2-1

2.4

Thermal Characteristics ................................................................................................................................... 2-2

2.5

DC Electrical Characteristics ........................................................................................................................... 2-3

2.6

AC Electrical Characteristics ........................................................................................................................... 2-4

Chapter 3

Packaging

3.1

Pin-Out and Package Information .................................................................................................................... 3-1

3.2

TQFP Package Description .............................................................................................................................. 3-2

3.3

TQFP Package Mechanical Drawing ............................................................................................................. 3-11

3.4

MAP-BGA Package Description ................................................................................................................... 3-12

3.5

MAP-BGA Package Mechanical Drawing .................................................................................................... 3-23

Chapter 4

Design Considerations

4.1

Thermal Design Considerations ....................................................................................................................... 4-1

4.2

Electrical Design Considerations ..................................................................................................................... 4-2

4.3

Power Consumption Considerations ................................................................................................................ 4-3

4.4

PLL Performance Issues .................................................................................................................................. 4-4

4.5

Input (EXTAL) Jitter Requirements................................................................................................................. 4-5

Appendix A

Power Consumption Benchmark

Index

Data Sheet Conventions

OVERBAR

Used to indicate a signal that is active when pulled low (For example, the RESET pin is active when
low.)

"asserted"

Means that a high true (active high) signal is high or that a low true (active low) signal is low

"deasserted"

Means that a high true (active high) signal is low or that a low true (active low) signal is high

Examples:

Signal/Symbol

Logic State

Signal State

Voltage

True

Asserted

False

Deasserted

True

Asserted

False

Deasserted

Note: Values for V

, V

, and V

are defined by individual product specifications.

iii

DSP56301 Features

High-Performance DSP56300 Core

· 80/100 million instructions per second (MIPS) with a 80/100 MHz clock at 3.03.6 V
· Object code compatible with the DSP56000 core with highly parallel instruction set
· Data Arithmetic Logic Unit (Data ALU) with fully pipelined 24

24-bit parallel

Multiplier-Accumulator (MAC), 56-bit parallel barrel shifter (fast shift and normalization; bit stream
generation and parsing), conditional ALU instructions, and 24-bit or 16-bit arithmetic support under
software control

· Program Control Unit (PCU) with Position Independent Code (PIC) support, addressing modes

optimized for DSP applications (including immediate offsets), on-chip instruction cache controller,
on-chip memory-expandable hardware stack, nested hardware DO loops, and fast auto-return interrupts

· Direct Memory Access (DMA) with six DMA channels supporting internal and external accesses;

one-, two-, and three-dimensional transfers (including circular buffering); end-of-block-transfer
interrupts; and triggering from interrupt lines and all peripherals

· Phase Lock Loop (PLL) allows change of low-power Divide Factor (DF) without loss of lock and

output clock with skew elimination

· Hardware debugging support including On-Chip Emulation (OnCE

) module, Joint Test Action

Group (JTAG) Test Access Port (TAP)

On-Chip Peripherals

· 32-bit parallel PCI/Universal Host Interface (HI32), PCI Rev. 2.1 compliant with glueless interface to

other DSP563xx buses or ISA interface requiring only 74LS45-style buffers

· Two enhanced synchronous serial interfaces (ESSI), each with one receiver and three transmitters

(allows six-channel home theater)

· Serial communications interface (SCI) with baud rate generator
· Triple timer module
· Up to forty-two programmable general-purpose input/output (GPIO) pins, depending on which

peripherals are enabled

On-Chip Memories

· 3 K

24-bit bootstrap ROM

· 8 K on-chip RAM total
· Program RAM, Instruction Cache, X data RAM, and Y data RAM sizes are programmable:

Program RAM

Size

Instruction Cache

Size

X Data RAM Size

Y Data RAM Size

Instruction

Cache

Switch

Mode

4096

24 bits

2048

24 bits

2048

24 bits

disabled

3072

24 bits

1024

24-bit

2048

24 bits

2048

24 bits

enabled

disabled

2048

24 bits

3072

24 bits

3072

24 bits

disabled

enabled

1024

24 bits

1024

24-bit

3072

24 bits

3072

24 bits

enabled

Off-Chip Memory Expansion

· Data memory expansion to two 16 M

24-bit word memory spaces in 24-Bit mode or two 64 K

16-bit memory spaces in 16-Bit Compatibility mode

· Program memory expansion to one 16 M

24-bit words memory space in 24-Bit mode or 64 K

16-bit in 16-Bit Compatibility mode

· External memory expansion port
· Chip Select Logic for glueless interface to SRAMs
· On-chip DRAM Controller for glueless interface to dynamic random access memory (DRAMs)

Reduced Power Dissipation

· Very low-power CMOS design
· Wait and Stop low-power standby modes
· Fully static design specified to operate down to 0 Hz (dc)
· Optimized power management circuitry (instruction-dependent, peripheral-dependent, and

mode-dependent)

Packaging

The DSP56301 is available in a 208-pin thin quad flat pack (TQFP) or a 252-pin molded array
process-ball grid array (MAP-BGA) package.

Target Applications

Examples of target applications include:

· Wireless and wireline infrastructure applications
· Multi-channel wireless local loop systems
· DSP resource boards
· High-speed modem banks
· Packet telephony

Product Documentation

The three documents listed in the following table are required for a complete description of the
DSP56301 and are necessary to design properly with the part. Documentation is available from the
following sources. (See the back cover for detailed information.)

· A local Motorola distributor
· A Motorola semiconductor sales office
· A Motorola Literature Distribution Center
· The World Wide Web (WWW)

Table 1. DSP56301

Documentation

Name

Description

Order Number

DSP56300 Family
Manual

Detailed description of the DSP56300 family processor core and
instruction set

DSP56300FM/AD

DSP56301 User's
Manual

Detailed functional description of the DSP56301 memory
configuration, operation, and register programming

DSP56301UM/D

DSP56301
Technical Data

DSP56301 features list and physical, electrical, timing, and
package specifications

DSP56301/D

1-1

Chapter 1

Signal/
Connection
Descriptions

1.1 Signal Groupings

The DSP56301 input and output signals are organized into functional groups, as shown in Table 1-1 and
illustrated in Figure 1-1.. The DSP56301 operates from a 3 V supply; however, some of the inputs can
tolerate 5 V. A special notice for this feature is added to the signal descriptions of those inputs.

Table 1-1. DSP56301 Functional Signal Groupings

Functional Group

Number of
Signals by

Package Type

Detailed

Description

TQFP

MAP-

BGA

Power (V

)

Table 1-2

Ground (GND)

Table 1-3

Clock

Table 1-4

PLL

Table 1-5

Address Bus

Port A

Table 1-6

Data Bus

Table 1-7

Bus Control

Table 1-8

Interrupt and Mode Control

Table 1-9

Host Interface (HI32)

Port B

Table 1-11

Enhanced Synchronous Serial Interface (ESSI)

Ports C and D

Table 1-12 and

Table 1-13

Serial Communication Interface (SCI)

Port E

Table 1-14

Timer

Table 1-15

JTAG/OnCE Port

Table 1-16

Notes:

The number of available power and ground signals is package-dependent. In the TQFP package
specific pins are dedicated internally to device subsystems. In the MAP-BGA package, power and
ground connections (except those providing PLL power) connect to internal power and ground
planes, respectively.

Port A signals define the external memory interface port, including the external address bus, data
bus, and control signals.

Port B signals are the HI32 port signals multiplexed with the GPIO signals.

Port C and D signals are the two ESSI port signals multiplexed with the GPIO signals.

Port E signals are the SCI port signals multiplexed with the GPIO signals.

Each device also includes several no connect (NC) pins. The number of NC connections is
package-dependent: the TQFP has 9 NCs and the MAP-BGA has 20 NCs. Do not connect any line,
component, trace, or via to these pins. See Chapter 3 for details.

1-2

Signal Groupings

Figure 1-1. Signals Identified by Functional Group

DSP56301

External
Address Bus

External
Data Bus

External
Bus
Control

Extended Synchronous

Serial Interface Port 0

(ESSI0)

Timers

PLL

JTAG/OnC

E Port

Power Inputs

PLL
Internal Logic
Address Bus
Data Bus
Bus Control
HI32
ESSI/SCI/Timer

A[0-23]

D[0-23]

AA[03]

RAS[03]

CAS

BCLK
BCLK

TCK
TDI
TDO
TMS
TRST
DE

CLKOUT

PCAP

PINIT/NMI

CCP

CCQ

CCA

CCD

CCN

CCH

CCS

Serial

Communications

Interface (SCI) Port

Grounds

PLL
PLL
Internal Logic
Address Bus
Data Bus
Bus Control
HI32
ESSI/SCI/Timer

GND

4
6
4

Interrupt

/Mode

Control

MODA/IRQA
MODB/IRQB
MODC/IRQC
MODD/IRQD
RESET

Host

Interface

(HI32) Port

PCI Bus

RXD
TXD
SCLK

SC[00-02]
SCK0
SRD0
STD0

TIO0
TIO1
TIO2

EXTAL

XTAL

Clock

Extended

Synchronous Serial

Interface Port 1

(ESSI1)

SC[10-12]
SCK1
SRD1
STD1

Universal
Bus

Port B
GPIO

Port E GPIO
PE0
PE1
PE2

Port C GPIO
PC[0-2]
PC3
PC4
PC5

Port D GPIO
PD[0-2]
PD3
PD4
PD5

Timer GPIO
TIO0
TIO1
TIO2

Port A

See Figure 1-2. for a listing of the
Host Interface/Port B Signals

Notes:

Power and ground connections are shown for the TQFP package. The MAP-BGA package uses one
V

CCP

for the PLL power input and 44 V

pins that connect to an internal power plane. The

MAP-BGA package uses two ground connections for the PLL (GND

and GND

) and 36 GND pins

that connect to an internal ground plane.

The HI32 port supports PCI and non-PCI bus configurations. Twenty-four HI32 signals can also be
configured as GPIO signals (PB[023]).

The ESSI0, ESSI1, and SCI signals are multiplexed with the Port C GPIO signals (PC[05]), Port D
GPIO signals (PD[05]), and Port E GPIO signals (PE[02]), respectively.

TIO[02] can be configured as GPIO signals.

1-3

Signal Groupings

Figure 1-2. Host Interface/Port B Detail Signal Diagram

DSP56301

HAD0
HAD1
HAD2
HAD3
HAD4
HAD5
HAD6
HAD7
HAD8
HAD9
HAD10
HAD11
HAD12
HAD13
HAD14
HAD15
HC0/HBE0
HC1/HBE1
HC2/HBE2
HC3/HBE3
HTRDY
HIRDY
HDEVSEL
HLOCK
HPAR
HPERR
HGNT
HREQ
HSERR
HSTOP
HIDSEL
HFRAME
HCLK
HAD16
HAD17
HAD18
HAD19
HAD20
HAD21
HAD22
HAD23
HAD24
HAD25
HAD26
HAD27
HAD28
HAD29
HAD30
HAD31
HRST
HINTA
PVCL

HA3
HA4
HA5
HA6
HA7
HA8
HA9
HA10
HD0
HD1
HD2
HD3
HD4
HD5
HD6
HD7
HA0
HA1
HA2
Tie to pull-up or V

HDBEN
HDBDR
HSAK
HBS
HDAK
HDRQ
HAEN
HTA
HIRQ
HWR/HRW
HRD/HDS
Tie to pull-up or V

Tie to pull-up or V

HD8
HD9
HD10
HD11
HD12
HD13
HD14
HD15
HD16
HD17
HD18
HD19
HD20
HD21
HD22
HD23
HRST
HINTA
Leave unconnected

PB0
PB1
PB2
PB3
PB4
PB5
PB6
PB7
PB8
PB9
PB10
PB11
PB12
PB13
PB14
PB15
PB16
PB17
PB18
PB19
PB20
PB21
PB22
PB23
Internal disconnect
Internal disconnect
Internal disconnect
Internal disconnect
Internal disconnect
Internal disconnect
Internal disconnect
Internal disconnect
Internal disconnect
Internal disconnect
Internal disconnect
Internal disconnect
Internal disconnect
Internal disconnect
Internal disconnect
Internal disconnect
Internal disconnect
Internal disconnect
Internal disconnect
Internal disconnect
Internal disconnect
Internal disconnect
Internal disconnect
Internal disconnect
Internal disconnect
Internal disconnect
Internal disconnect
Leave unconnected

Port B Signals

Host Interface (HI32)/

HP0
HP1
HP2
HP3
HP4
HP5
HP6
HP7
HP8
HP9
HP10
HP11
HP12
HP13
HP14
HP15
HP16
HP17
HP18
HP19
HP20
HP21
HP22
HP23
HP24
HP25
HP26
HP27
HP28
HP29
HP30
HP31
HP32
HP33
HP34
HP35
HP36
HP37
HP38
HP39
HP40
HP41
HP42
HP43
HP44
HP45
HP46
HP47
HP48
HP49
HP50
PVCL

Note:

HPxx is a reference only and is not a signal name. GPIO references formerly designated as HIOxx have been
renamed PBxx for consistency with other Motorola DSPs.

PCI Bus

Universal Bus

Port B GPIO

Host Port (HP)

Reference

1-4

Power

1.2 Power

1.3 Ground

Table 1-2. Power Inputs

Power

Name

Description

CCP

PLL Power
Isolated power for the Phase Lock Loop (PLL). The voltage should be well-regulated and the input
should be provided with an extremely low impedance path to the V

power rail.

CCQ

Quiet Power
Isolated power for the internal processing logic. This input must be tied externally to all other chip
power inputs. The user must provide adequate external decoupling capacitors.

CCA

Address Bus Power
Isolated power for sections of the address bus I/O drivers. This input must be tied externally to all
other chip power inputs. The user must provide adequate external decoupling capacitors.

CCD

Data Bus Power
Isolated power for sections of the data bus I/O drivers. This input must be tied externally to all other
chip power inputs. The user must provide adequate external decoupling capacitors.

CCN

Bus Control Power
Isolated power for the bus control I/O drivers. This input must be tied externally to all other chip
power inputs. The user must provide adequate external decoupling capacitors.

CCH

Host Power
Isolated power for the HI32 I/O drivers. This input must be tied externally to all other chip power
inputs. The user must provide adequate external decoupling capacitors.

CCS

ESSI, SCI, and Timer Power
Isolated power for the ESSI, SCI, and timer I/O drivers. This input must be tied externally to all
other chip power inputs. The user must provide adequate external decoupling capacitors.

Note:

These designations are package-dependent. Some packages connect all V

inputs except V

CCP

to each

other internally. On those packages, all power input except V

CCP

are labeled V

Table 1-3. Grounds

Ground

Name

Description

GND

PLL Ground
Ground dedicated for PLL use. The connection should be provided with an extremely
low-impedance path to ground. V

CCP

should be bypassed to GND

by a 0.47

F capacitor located

as close as possible to the chip package.

GND

PLL Ground 1
Ground dedicated for PLL use. The connection should be provided with an extremely
low-impedance path to ground.

GND

Quiet Ground
Isolated ground for the internal processing logic. This connection must be tied externally to all other
chip ground connections. The user must provide adequate external decoupling capacitors.

1-5

Clock

1.4 Clock

GND

Address Bus Ground
Isolated ground for sections of the address bus I/O drivers. This connection must be tied externally
to all other chip ground connections. The user must provide adequate external decoupling
capacitors.

GND

Data Bus Ground
Isolated ground for sections of the data bus I/O drivers. This connection must be tied externally to
all other chip ground connections. The user must provide adequate external decoupling capacitors.

GND

Bus Control Ground
Isolated ground for the bus control I/O drivers. This connection must be tied externally to all other
chip ground connections. The user must provide adequate external decoupling capacitors.

GND

Host Ground
Isolated ground for the HI32 I/O drivers. This connection must be tied externally to all other chip
ground connections. The user must provide adequate external decoupling capacitors.

GND

ESSI, SCI, and Timer Ground
Isolated ground for the ESSI, SCI, and timer I/O drivers. This connection must be tied externally to
all other chip ground connections. The user must provide adequate external decoupling capacitors.

Note:

These designations are package-dependent. Some packages connect all GND inputs except GND

and

GND

to each other internally. On those packages, all ground connections except GND

and GND

are

labeled GND.

Table 1-4. Clock Signals

Signal

Name

Type

State

During

Reset

Signal Description

EXTAL

Input

External Clock/Crystal Input
Interfaces the internal crystal oscillator input to an external
crystal or an external clock.

XTAL

Output

Chip-driven

Crystal Output
Connects the internal crystal oscillator output to an external
crystal. If an external clock is used, leave XTAL unconnected.

Table 1-3. Grounds

Ground

Name

Description

1-6

Phase Lock Loop (PLL)

1.5 Phase Lock Loop (PLL)

1.6 External Memory Expansion Port (Port A)

Note:

When the DSP56301 enters a low-power stand-by mode (Stop or Wait), it releases bus
mastership and tri-states the relevant Port A signals:

A[023]

D[023]

AA0/RAS0

AA3/RAS3

CAS

BCLK

, and

BCLK

. If hardware refresh of external DRAM is enabled, Port A

exits the Wait mode to allow the refresh to occur and then returns to the Wait mode.

1.6.1 External Address Bus

Table 1-5. Phase Lock Loop Signals

Signal

Name

Type

State

During

Reset

Signal Description

CLKOUT

Output

Chip-driven

Clock Output
Provides an output clock synchronized to the internal core clock
phase.

If the PLL is enabled and both the multiplication and division
factors equal one, then CLKOUT is also synchronized to EXTAL.

If the PLL is disabled, the CLKOUT frequency is half the
frequency of EXTAL.

PCAP

Input

PLL Capacitor
Connects an off-chip capacitor to the PLL filter. Connect one
capacitor terminal to PCAP and the other terminal to V

CCP

If the PLL is not used, PCAP can be tied to V

, GND, or left

floating.

PINIT/NMI

Input

PLL Initial/Non-Maskable Interrupt
During assertion of RESET, the value of PINIT/NMI is written into
the PLL Enable (PEN) bit of the PLL control register, determining
whether the PLL is enabled or disabled. After RESET
deassertion and during normal instruction processing, the
PINIT/NMI Schmitt-trigger input is a negative-edge-triggered
Non-Maskable Interrupt (NMI) request internally synchronized to
CLKOUT.

PINIT/NMI can tolerate 5 V.

Table 1-6. External Address Bus Signals

Signal

Name

Type

State

During

Reset

Signal Description

A[023]

Output

Tri-stated

Address Bus
When the DSP is the bus master, A[023] specify the address
for external program and data memory accesses. Otherwise, the
signals are tri-stated. To minimize power dissipation, A[023] do
not change state when external memory spaces are not being
accessed.

1-7

External Memory Expansion Port (Port A)

1.6.2 External Data Bus

1.6.3 External Bus Control

Table 1-7. External Data Bus Signals

Signal

Name

Type

State

During

Reset

Signal Description

D[023]

Input/Output

Tri-stated

Data Bus
When the DSP is the bus master, D[023] provide the
bidirectional data bus for external program and data memory
accesses. Otherwise, D[023] are tri-stated.

Table 1-8. External Bus Control Signals

Signal

Name

Type

State

During

Reset

Signal Description

AA0/RAS0
AA3/RAS3

Output

Tri-stated

Address Attribute or Row Address Strobe
As AA, these signals function as chip selects or additional
address lines. Unlike address lines, however, the AA lines do not
hold their state after a read or write operation. As RAS, these
signals can be used for Dynamic Random Access Memory
(DRAM) interface. These signals have programmable polarity.

Output

Tri-stated

Read Enable
When the DSP is the bus master, RD is asserted to read external
memory on the data bus (D[023]). Otherwise, RD is tri-stated.

Output

Tri-stated

Write Enable
When the DSP is the bus master, WR is asserted to write
external memory on the data bus (D[023]). Otherwise, WR is
tri-stated.

Input

Ignored Input

Transfer Acknowledge
If the DSP56301 is the bus master and there is no external bus
activity, or the DSP56301 is not the bus master, the TA input is
ignored. The TA input is a Data Transfer Acknowledge (DTACK)
function that can extend an external bus cycle indefinitely. Any
number of wait states (1, 2,..., infinity) can be added to the wait
states inserted by the BCR by keeping TA deasserted. In typical
operation, TA is deasserted at the start of a bus cycle, asserted
to enable completion of the bus cycle, and deasserted before the
next bus cycle. The current bus cycle completes one clock
period after TA is asserted synchronous to CLKOUT. The
number of wait states is determined by the TA input or by the
Bus Control Register (BCR), whichever is longer. The BCR can
set the minimum number of wait states in external bus cycles.

To use the TA functionality, the BCR must be programmed to at
least one wait state. A zero wait state access cannot be
extended by TA deassertion; otherwise improper operation may
result. TA can operate synchronously or asynchronously,
depending on the setting of the TAS bit in the Operating Mode
Register (OMR).

TA functionality cannot be used during DRAM-type accesses;
otherwise improper operation may result.

1-8

External Memory Expansion Port (Port A)

Output

Output
(deasserted)

Bus Request
Asserted when the DSP requests bus mastership and
deasserted when the DSP no longer needs the bus. BR can be
asserted or deasserted independently of whether the DSP56301
is a bus master or a bus slave. Bus "parking" allows BR to be
deasserted even though the DSP56301 is the bus master (see
the description of bus "parking" in the BB signal description). The
Bus Request Hole (BRH) bit in the BCR allows BR to be
asserted under software control, even though the DSP does not
need the bus. BR is typically sent to an external bus arbitrator
that controls the priority, parking and tenure of each master on
the same external bus. BR is affected only by DSP requests for
the external bus, never for the internal bus. During hardware
reset, BR is deasserted and the arbitration is reset to the bus
slave state.

Input

Ignored Input

Bus Grant
Must be asserted/deasserted synchronous to CLKOUT for
proper operation. An external bus arbitration circuit asserts BG
when the DSP56301 becomes the next bus master. When BG is
asserted, the DSP56301 must wait until BB is deasserted before
taking bus mastership. When BG is deasserted, bus mastership
is typically given up at the end of the current bus cycle. This may
occur in the middle of an instruction that requires more than one
external bus cycle for execution.

Input/
Output

Input

Bus Busy
Indicates that the bus is active and must be asserted and
deasserted synchronous to CLKOUT. Only after BB is
deasserted can the pending bus master become the bus master
(and then assert the signal again). The bus master can keep BB
asserted after ceasing bus activity, regardless of whether BR is
asserted or deasserted. This is called "bus parking" and allows
the current bus master to reuse the bus without re-arbitration
until another device requires the bus. BB is deasserted by an
"active pull-up" method (that is, BB is driven high and then
released and held high by an external pull-up resistor).

BB requires an external pull-up resistor.

Output

Driven high
(deasserted)

Bus Lock--BL is asserted at the start of an external divisible
Read-Modify-Write (RMW) bus cycle, remains asserted between
the read and write cycles, and is deasserted at the end of the
write bus cycle. This provides an "early bus start" signal for the
bus controller. BL may be used to "resource lock" an external
multi-port memory for secure semaphore updates. Early
deassertion provides an "early bus end" signal useful for external
bus control. If the external bus is not used during an instruction
cycle, BL remains deasserted until the next external indivisible
RMW cycle. The only instructions that assert BL automatically
are the BSET, CLR, and BCHG instructions when they are used
to modify external memory. An operation can also assert BL by
setting the BLH bit in the Bus Control Register.

Table 1-8. External Bus Control Signals (Continued)

Signal

Name

Type

State

During

Reset

Signal Description

1-9

Interrupt and Mode Control

1.7 Interrupt and Mode Control

The interrupt and mode control signals select the chip's operating mode as it comes out of hardware reset.
After

RESET

is deasserted, these inputs are hardware interrupt request lines.

CAS

Output

Tri-stated

Column Address Strobe
When the DSP is the bus master, DRAM uses CAS to strobe the
column address. Otherwise, if the Bus Mastership Enable (BME)
bit in the DRAM Control Register is cleared, the signal is
tri-stated.

BCLK

Output

Tri-stated

Bus Clock
When the DSP is the bus master, BCLK is active when the
OMR[ATE] is set. When BCLK is active and synchronized to
CLKOUT by the internal PLL, BCLK precedes CLKOUT by
one-fourth of a clock cycle.

BCLK

Output

Tri-stated

Bus Clock Not
When the DSP is the bus master, BCLK is the inverse of the
BCLK signal. Otherwise, the signal is tri-stated.

Table 1-9. Interrupt and Mode Control

Signal

Name

Type

State

During

Reset

Signal Description

MODA

IRQA

Input

Mode Select A
Selects the initial chip operating mode during hardware reset
and becomes a level-sensitive or negative-edge-triggered,
maskable interrupt request input IRQA during normal instruction
processing. MODA, MODB, MODC, and MODD select one of
sixteen initial chip operating modes, latched into the OMR when
the RESET signal is deasserted.

External Interrupt Request A
Internally synchronized to CLKOUT. If IRQA is asserted
synchronous to CLKOUT, multiple processors can be
re-synchronized using the WAIT instruction and asserting IRQA
to exit the Wait state. If the processor is in the Stop stand-by
state and IRQA is asserted, the processor exits the Stop state.

These inputs are 5 V tolerant.

Table 1-8. External Bus Control Signals (Continued)

Signal

Name

Type

State

During

Reset

Signal Description

1-10

Interrupt and Mode Control

MODB

IRQB

Input

Mode Select B
Selects the initial chip operating mode during hardware reset
and becomes a level-sensitive or negative-edge-triggered,
maskable interrupt request input IRQB during normal instruction
processing. MODA, MODB, MODC, and MODD select one of
sixteen initial chip operating modes, latched into the OMR when
the RESET signal is deasserted.

External Interrupt Request B
Internally synchronized to CLKOUT. If IRQB is asserted
synchronous to CLKOUT, multiple processors can be
re-synchronized using the WAIT instruction and asserting IRQB
to exit the Wait state. If the processor is in the Stop stand-by
state and IRQC is asserted, the processor will exit the Stop
state.

These inputs are 5 V tolerant.

MODC

IRQC

Input

Mode Select C
Selects the initial chip operating mode during hardware reset
and becomes a level-sensitive or negative-edge-triggered,
maskable interrupt request input IRQC during normal instruction
processing. MODA, MODB, MODC, and MODD select one of
sixteen initial chip operating modes, latched into the OMR when
the RESET signal is deasserted.

External Interrupt Request C
Internally synchronized to CLKOUT. If IRQC is asserted
synchronous to CLKOUT, multiple processors can be
re-synchronized using the WAIT instruction and asserting IRQC
to exit the Wait state. If the processor is in the Stop stand-by
state and IRQC is asserted, the processor exits the Stop state.

These inputs are 5 V tolerant.

MODD

IRQD

Input

Mode Select D
Selects the initial chip operating mode during hardware reset
and becomes a level-sensitive or negative-edge-triggered,
maskable interrupt request input IRQD during normal instruction
processing. MODA, MODB, MODC, and MODD select one of
sixteen initial chip operating modes, latched into the OMR when
the RESET signal is deasserted.

External Interrupt Request D
Internally synchronized to CLKOUT. If IRQD is asserted
synchronous to CLKOUT, multiple processors can be
re-synchronized using the WAIT instruction and asserting IRQD
to exit the Wait state. If the processor is in the Stop stand-by
state and IRQD is asserted, the processor exits the Stop state.

These inputs are 5 V tolerant.

Table 1-9. Interrupt and Mode Control (Continued)

Signal

Name

Type

State

During

Reset

Signal Description

1-11

Host Interface (HI32)

1.8 Host Interface (HI32)

The Host Interface (HI32) provides fast parallel data to a 32-bit port directly connected to the host bus.
The HI32 supports a variety of standard buses and directly connects to a PCI bus and a number of
industry-standard microcomputers, microprocessors, DSPs, and DMA hardware.

1.8.4 Host Port Usage Considerations

Careful synchronization is required when the system reads multiple-bit registers that are written by
another asynchronous system. This is a common problem when two asynchronous systems are connected
(as they are in the Host port). The considerations for proper operation are discussed in Table 1-10.

RESET

Input

Reset
Deassertion of RESET is internally synchronized to the clock out
(CLKOUT). When asserted, the chip is placed in the Reset state
and the internal phase generator is reset. The Schmitt-trigger
input allows a slowly rising input (such as a capacitor charging)
to reset the chip reliably. If RESET is deasserted synchronous to
CLKOUT, exact start-up timing is guaranteed, allowing multiple
processors to start synchronously and operate together in
"lock-step." When the RESET signal is deasserted, the initial
chip operating mode is latched from the MODA, MODB, MODC,
and MODD inputs. The RESET signal must be asserted after
power-up.

This input is 5 V tolerant.

Table 1-10. Host Port Usage Considerations

Action

Description

Asynchronous read of
receive byte registers

When reading the receive byte registers, Receive register High (RXH), Receive register
Middle (RXM), or Receive register Low (RXL), use interrupts or poll the Receive register
Data Full (RXDF) flag that indicates data is available. This assures that the data in the
receive byte registers is valid.

Asynchronous write to
transmit byte registers

Do not write to the transmit byte registers, Transmit register High (TXH), Transmit
register Middle (TXM), or Transmit register Low (TXL), unless the Transmit register Data
Empty (TXDE) bit is set, indicating that the transmit byte registers are empty. This
guarantees that the transmit byte registers transfer valid data to the Host Receive (HRX)
register.

Asynchronous write to
host vector

Change the Host Vector (HV) register only when the Host Command bit (HC) is clear.
This practice guarantees that the DSP interrupt control logic receives a stable vector.

Table 1-9. Interrupt and Mode Control (Continued)

Signal

Name

Type

State

During

Reset

Signal Description

1-12

Host Interface (HI32)

1.8.5 Host Port Configuration

HI32 signal functions vary according to the programmed configuration of the interface as determined by
the 24-bit DSP Control Register (DCTR). Refer to the DSP56301 User's Manual for details on HI32
configuration registers.

Table 1-11. Host Interface

Signal

Name

Type

State

During

Reset

Signal Description

HAD[07]

HA[310]

PB[07]

Input/Output

Input

Input or
Output

Tri-stated

Host Address/Data 07
When the HI32 is programmed to interface with a PCI bus and
the HI function is selected, these signals are lines 07 of the
Address/Data bus.

Host Address 310
When HI32 is programmed to interface with a universal, non-PCI
bus and the HI function is selected, these signals are lines 310
of the Address bus.

Port B 07
When the HI32 is configured as GPIO through the DCTR, these
signals are individually programmed through the HI32 Data
Direction Register (DIRH).

These inputs are 5 V tolerant.

HAD[815]

HD[07]

PB[815]

Input/Output

Input or
Output

Tri-stated

Host Address/Data 815
When the HI32 is programmed to interface with a PCI bus and
the HI function is selected, these signals are lines 815 of the
Address/Data bus.

Host Data 07
When HI32 is programmed to interface with a universal non-PCI
bus and the HI function is selected, these signals are lines 07 of
the Data bus.

Port B 815
When the HI32 is configured as GPIO through the DCTR, these
signals are individually programmed through the HI32 DIRH.

These inputs are 5 V tolerant.

1-13

Host Interface (HI32)

HC[03]/
HBE[03]

HA[02]

PB[1619]

Input/Output

Input

Input or
Output

Tri-stated

Command 03/Byte Enable 03
When the HI32 is programmed to interface with a PCI bus and
the HI function is selected, these signals are lines 07 of the
Address/Data bus.

Host Address 02
When HI32 is programmed to interface with a universal, non-PCI
bus and the HI function is selected, these signals are lines 02 of
the Address bus.

The fourth signal in this set should connect to a pull-up resistor
or directly to V

when a non-PCI bus is used.

Port B 1619
When the HI32 is configured as GPIO through the DCTR, these
signals are individually programmed through the HI32 DIRH.

These inputs are 5 V tolerant.

HTRDY

HDBEN

PB20

Input/
Output

Output

Input or
Output

Tri-stated

Host Target Ready
When the HI32 is programmed to interface with a PCI bus and
the HI function is selected, this is the Host Target Ready signal.

Host Data Bus Enable
When HI32 is programmed to interface with a universal, non-PCI
bus and the HI function is selected, this is the Host Data Bus
Enable signal.

Port B 20
When the HI32 is configured as GPIO through the DCTR, this
signal is individually programmed through the HI32 DIRH.

This input is 5 V tolerant.

HIRDY

HDBDR

PB21

Input/
Output

Output

Input or
Output

Tri-stated

Host Initiator Ready
When the HI32 is programmed to interface with a PCI bus and
the HI function is selected, this is the Host Initiator Ready signal.

Host Data Bus Direction
When HI32 is programmed to interface with a universal, non-PCI
bus and the HI function is selected, this is the Host Data Bus
Direction signal.

Port B 21
When the HI32 is configured as GPIO through the DCTR, this
signal is individually programmed through the HI32 DIRH.

This input is 5 V tolerant.

Table 1-11. Host Interface (Continued)

Signal

Name

Type

State

During

Reset

Signal Description

1-14

Host Interface (HI32)

HDEVSEL

HSAK

PB22

Input/
Output

Output

Input or
Output

Tri-stated

Host Device Select
When the HI32 is programmed to interface with a PCI bus and
the HI function is selected, this is the Host Device Select signal.

Host Select Acknowledge
When HI32 is programmed to interface with a universal, non-PCI
bus and the HI function is selected, this is the Host Select
Acknowledge signal.

Port B 22
When the HI32 is configured as GPIO through the DCTR, this
signal is individually programmed through the HI32 DIRH.

This input is 5 V tolerant.

HLOCK

HBS

PB23

Input

Input or
Output

Tri-stated

Host Lock
When the HI32 is programmed to interface with a PCI bus and
the HI function is selected, this is the Host Lock signal.

Host Bus Strobe
When HI32 is programmed to interface with a universal, non-PCI
bus and the HI function is selected, this is the Host Bus Strobe
Schmitt-trigger signal.

Port B 23
When the HI32 is configured as GPIO through the DCTR, this
signal is individually programmed through the HI32 DIRH.

This input is 5 V tolerant.

HPAR

HDAK

Input/
Output

Input

Tri-stated

Host Parity
When the HI32 is programmed to interface with a PCI bus and
the HI function is selected, this is the Host Parity signal.

Host DMA Acknowledge
When HI32 is programmed to interface with a universal, non-PCI
bus and the HI function is selected, this is the Host DMA
Acknowledge Schmitt-trigger signal.

Port B
When the HI32 is configured as GPIO through the DCTR, this
signal is internally disconnected.

This input is 5 V tolerant.

Table 1-11. Host Interface (Continued)

Signal

Name

Type

State

During

Reset

Signal Description

1-15

Host Interface (HI32)

HPERR

HDRQ

Input/
Output

Output

Tri-stated

Host Parity Error
When the HI32 is programmed to interface with a PCI bus and
the HI function is selected, this is the Host Parity Error signal.

Host DMA Request
When HI32 is programmed to interface with a universal, non-PCI
bus and the HI function is selected, this is the Host DMA
Request output.

Port B
When the HI32 is configured as GPIO through the DCTR, this
signal is internally disconnected.

This input is 5 V tolerant.

HGNT

HAEN

Input

Host Bus Grant
When the HI32 is programmed to interface with a PCI bus and
the HI function is selected, this is the Host Bus Grant signal.

Host Address Enable
When HI32 is programmed to interface with a universal, non-PCI
bus and the HI function is selected, this is the Host Address
Enable output signal.

Port B
When the HI32 is configured as GPIO through the DCTR, this
signal is internally disconnected.

This input is 5 V tolerant.

HREQ

HTA

Output

Tri-stated

Host Bus Request
When the HI32 is programmed to interface with a PCI bus and
the HI function is selected, this is the Host Bus Request signal.

Host Transfer Acknowledge--When HI32 is programmed to
interface with a universal, non-PCI bus and the HI function is
selected, this is the Host Data Bus Enable signal. HTA can be
programmed as active high or active low.

Port B
When the HI32 is configured as GPIO through the DCTR, this
signal is internally disconnected.

This input is 5 V tolerant.

Table 1-11. Host Interface (Continued)

Signal

Name

Type

State

During

Reset

Signal Description

1-16

Host Interface (HI32)

HSERR

HIRQ

Output, open
drain

Tri-stated

Host System Error
When the HI32 is programmed to interface with a PCI bus and
the HI function is selected, this is the Host System Error signal.

Host Interrupt Request
When HI32 is programmed to interface with a universal, non-PCI
bus and the HI function is selected, this is the Host Interrupt
Request signal.

Port B
When the HI32 is configured as GPIO through the DCTR, this
signal is internally disconnected.

This input is 5 V tolerant.

HSTOP

HWR/HRW

Input/
Output

Input

Tri-stated

Host Stop
When the HI32 is programmed to interface with a PCI bus and
the HI function is selected, this is the Host Stop signal.

Host Write/Host Read-Write
When HI32 is programmed to interface with a universal, non-PCI
bus and the HI function is selected, this is the Host Write/Host
Read-Write Schmitt-trigger signal.

Port B
When the HI32 is configured as GPIO through the DCTR, this
signal is internally disconnected.

This input is 5 V tolerant.

HIDSEL

HRD/HDS

Input

Host Initialization Device Select
When the HI32 is programmed to interface with a PCI bus and
the HI function is selected, this is the Host Initialization Device
Select signal.

Host Read/Host Data Strobe
When HI32 is programmed to interface with a universal, non-PCI
bus and the HI function is selected, this is the Host Data
Read/Host Data Strobe Schmitt-trigger signal.

Port B
When the HI32 is configured as GPIO through the DCTR, this
signal is internally disconnected.

This input is 5 V tolerant.

Table 1-11. Host Interface (Continued)

Signal

Name

Type

State

During

Reset

Signal Description

1-17

Host Interface (HI32)

HFRAME

Input/
Output

Tri-stated

Host Frame
When the HI32 is programmed to interface with a PCI bus and
the HI function is selected, this is the Host cycle Frame signal.

Non-PCI bus
When HI32 is programmed to interface with a universal, non-PCI
bus and the HI function is selected, this signal must be
connected to a pull-up resistor or directly to V

Port B
When the HI32 is configured as GPIO through the DCTR, this
signal is internally disconnected.

This input is 5 V tolerant.

HCLK

Input

Host Clock
When the HI32 is programmed to interface with a PCI bus and
the HI function is selected, this is the Host Bus Clock input.

Non-PCI bus
When HI32 is programmed to interface a universal non-PCI bus
and the HI function is selected, this signal must be connected to
a pull-up resistor or directly to V

Port B
When the HI32 is configured as GPIO through the DCTR, this
signal is internally disconnected.

This input is 5 V tolerant.

HAD[1631]

HD[823]

Input/Output

Tri-stated

Host Address/Data 1631
When the HI32 is programmed to interface with a PCI bus and
the HI function is selected, these signals are lines 1631 of the
Address/Data bus.

Host Data 823
When HI32 is programmed to interface with a universal, non-PCI
bus and the HI function is selected, these signals are lines 823
of the Data bus.

Port B
When the HI32 is configured as GPIO through the DCTR, these
signals are internally disconnected.

These inputs are 5 V tolerant.

Table 1-11. Host Interface (Continued)

Signal

Name

Type

State

During

Reset

Signal Description

1-18

Host Interface (HI32)

HRST

Input

Tri-stated

Hardware Reset
When the HI32 is programmed to interface with a PCI bus and
the HI function is selected, this is the Hardware Reset input.

Hardware Reset
When HI32 is programmed to interface with a universal, non-PCI
bus and the HI function is selected, this is the Hardware Reset
Schmitt-trigger signal.

Port B
When the HI32 is configured as GPIO through the DCTR, this
signal is internally disconnected.

This input is 5 V tolerant.

HINTA

Output, open
drain

Tri-stated

Host Interrupt A
When the HI function is selected, this signal is the Interrupt A
open-drain output.

Port B
When the HI32 is configured as GPIO through the DCTR, this
signal is internally disconnected.

This input is 5 V tolerant.

PVCL

Input

PCI Voltage Clamp
When the HI32 is programmed to interface with a PCI bus and
the HI function is selected and the PCI bus uses a 3 V signal
environment, connect this pin to V

(3.3 V) to enable the high

voltage clamping required by the PCI specifications. In all other
cases, including a 5 V PCI signal environment, leave the input
unconnected.

Table 1-11. Host Interface (Continued)

Signal

Name

Type

State

During

Reset

Signal Description

1-19

Enhanced Synchronous Serial Interface 0 (ESSI0)

1.9 Enhanced Synchronous Serial Interface 0 (ESSI0)

Two synchronous serial interfaces (ESSI0 and ESSI1) provide a full-duplex serial port for serial
communication with a variety of serial devices, including one or more industry-standard CODECs, other
DSPs, microprocessors, and peripherals that implement the Motorola Serial Peripheral Interface (SPI).

Table 1-12. Enhanced Synchronous Serial Interface 0 (ESSI0)

Signal

Name

Type

State

During

Reset

Signal Description

SC00

PC0

Input or
Output

Input

Serial Control 0
Functions in either Synchronous or Asynchronous mode. For
Asynchronous mode, this signal is the receive clock I/O
(Schmitt-trigger input). For Synchronous mode, this signal is
either for Transmitter 1 output or Serial I/O Flag 0.

Port C 0
The default configuration following reset is GPIO. For PC0,
signal direction is controlled through the Port Directions Register
(PRR0). The signal can be configured as ESSI signal SC00
through the Port Control Register (PCR0).

This input is 5 V tolerant.

SC01

PC1

Input/Output

Input or
Output

Input

Serial Control 1
Functions in either Synchronous or Asynchronous mode. For
Asynchronous mode, this signal is the receiver frame sync I/O.
For Synchronous mode, this signal is either Transmitter 2 output
or Serial I/O Flag 1.

Port C 1
The default configuration following reset is GPIO. For PC1,
signal direction is controlled through PRR0. The signal can be
configured as an ESSI signal SC01 through PCR0.

This input is 5 V tolerant.

SC02

PC2

Input/Output

Input or
Output

Input

Serial Control Signal 2
The frame sync for both the transmitter and receiver in
Synchronous mode, and for the transmitter only in Asynchronous
mode. When configured as an output, this signal is the internally
generated frame sync signal. When configured as an input, this
signal receives an external frame sync signal for the transmitter
(and the receiver in synchronous operation).

Port C 2
The default configuration following reset is GPIO. For PC2,
signal direction is controlled through PRR0. The signal can be
configured as an ESSI signal SC02 through PCR0.

This input is 5 V tolerant.

1-20

Enhanced Synchronous Serial Interface 0 (ESSI0)

SCK0

PC3

Input/Output

Input or
Output

Input

Serial Clock
Provides the serial bit rate clock for the ESSI interface for both
the transmitter and receiver in Synchronous modes, or the
transmitter only in Asynchronous modes.

Although an external serial clock can be independent of and
asynchronous to the DSP system clock, it must exceed the
minimum clock cycle time of 6 T (that is, the system clock
frequency must be at least three times the external ESSI clock
frequency). The ESSI needs at least three DSP phases inside
each half of the serial clock.

Port C 3
The default configuration following reset is GPIO. For PC3,
signal direction is controlled through PRR0. The signal can be
configured as an ESSI signal SCK0 through PCR0.

This input is 5 V tolerant.

SRD0

PC4

Input/Output

Input or
Output

Input

Serial Receive Data
Receives serial data and transfers the data to the ESSI receive
shift register. SRD0 is an input when data is being received.

Port C 4
The default configuration following reset is GPIO. For PC4,
signal direction is controlled through PRR0. The signal can be
configured as an ESSI signal SRD0 through PCR0.

This input is 5 V tolerant.

STD0

PC5

Input/Output

Input or
Output

Input

Serial Transmit Data
Transmits data from the serial transmit shift register. STD0 is an
output when data is being transmitted.

Port C 5
The default configuration following reset is GPIO. For PC5,
signal direction is controlled through PRR0. The signal can be
configured as an ESSI signal STD0 through PCR0.

This input is 5 V tolerant.

Table 1-12. Enhanced Synchronous Serial Interface 0 (ESSI0) (Continued)

Signal

Name

Type

State

During

Reset

Signal Description

1-21

Enhanced Synchronous Serial Interface 1 (ESSI1)

1.10 Enhanced Synchronous Serial Interface 1 (ESSI1)

Table 1-13. Enhanced Synchronous Serial Interface 1 (ESSI1)

Signal

Name

Type

State

During

Reset

Signal Description

SC10

PD0

Input or
Output

Input

Serial Control 0
Selection of Synchronous or Asynchronous mode determines
function. For Asynchronous mode, this signal is the receive clock
I/O (Schmitt-trigger input). For Synchronous mode, this signal is
either Transmitter 1 output or Serial I/O Flag 0.

Port D 0
The default configuration following reset is GPIO. For PD0,
signal direction is controlled through the Port Directions Register
(PRR1). The signal can be configured as an ESSI signal SC10
through the Port Control Register (PCR1).

This input is 5 V tolerant.

SC11

PD1

Input/Output

Input or
Output

Input

Serial Control 1
Selection of Synchronous or Asynchronous mode determines
function. For Asynchronous mode, this signal is the receiver
frame sync I/O. For Synchronous mode, this signal is either
Transmitter 2 output or Serial I/O Flag 1.

Port D 1
The default configuration following reset is GPIO. For PD1,
signal direction is controlled through PRR1. The signal can be
configured as an ESSI signal SC11 through PCR1.

This input is 5 V tolerant.

SC12

PD2

Input/Output

Input or
Output

Input

Serial Control Signal 2
Frame sync for both the transmitter and receiver in Synchronous
mode, for the transmitter only in Asynchronous mode. When
configured as an output, this signal is the internally generated
frame sync signal. When configured as an input, this signal
receives an external frame sync signal for the transmitter (and
the receiver in Synchronous operation).

Port D 2
The default configuration following reset is GPIO. For PD2,
signal direction is controlled through PRR1. The signal can be
configured as an ESSI signal SC12 through PCR1.

This input is 5 V tolerant.

1-22

Enhanced Synchronous Serial Interface 1 (ESSI1)

SCK1

PD3

Input/Output

Input or
Output

Input

Serial Clock
Provides the serial bit rate clock for the ESSI interface. Clock
input or output can be used by the transmitter and receiver in
Synchronous modes, by the transmitter only in Asynchronous
modes.

Although an external serial clock can be independent of and
asynchronous to the DSP system clock, it must exceed the
minimum clock cycle time of 6T (that is, the system clock
frequency must be at least three times the external ESSI clock
frequency). The ESSI needs at least three DSP phases inside
each half of the serial clock.

Port D 3
The default configuration following reset is GPIO. For PD3,
signal direction is controlled through PRR1. The signal can be
configured as an ESSI signal SCK1 through PCR1.

This input is 5 V tolerant.

SRD1

PD4

Input/Output

Input or
Output

Input

Serial Receive Data
Receives serial data and transfers it to the ESSI receive shift
register. SRD1 is an input when data is being received.

Port D 4
The default configuration following reset is GPIO. For PD4,
signal direction is controlled through PRR1. The signal can be
configured as an ESSI signal SRD1 through PCR1.

This input is 5 V tolerant.

STD1

PD5

Input/Output

Input or
Output

Input

Serial Transmit Data
Transmits data from the serial transmit shift register. STD1 is an
output when data is being transmitted.

Port D 5
The default configuration following reset is GPIO. For PD5,
signal direction is controlled through PRR1. The signal can be
configured as an ESSI signal STD1 through PCR1.

This input is 5 V tolerant.

Table 1-13. Enhanced Synchronous Serial Interface 1 (ESSI1) (Continued)

Signal

Name

Type

State

During

Reset

Signal Description

1-23

Serial Communication Interface (SCI)

1.11 Serial Communication Interface (SCI)

The Serial Communication interface (SCI) provides a full duplex port for serial communication with
other DSPs, microprocessors, or peripherals such as modems.

Table 1-14. Serial Communication Interface (SCI)

Signal

Name

Type

State

During

Reset

Signal Description

RXD

PE0

Input

Input or
Output

Input

Serial Receive Data
Receives byte-oriented serial data and transfers it to the SCI
receive shift register.

Port E 0
The default configuration following reset is GPIO. When
configured as PE0, signal direction is controlled through the SCI
Port Directions Register (PRR). The signal can be configured as
an SCI signal RXD through the SCI Port Control Register (PCR).

This input is 5 V tolerant.

TXD

PE1

Output

Input or
Output

Input

Serial Transmit Data
Transmits data from SCI transmit data register.

Port E 1
The default configuration following reset is GPIO. When
configured as PE1, signal direction is controlled through the SCI
PRR. The signal can be configured as an SCI signal TXD
through the SCI PCR.

This input is 5 V tolerant.

SCLK

PE2

Input/Output

Input or
Output

Input

Serial Clock
Provides the input or output clock used by the transmitter and/or
the receiver.

Port E 2
The default configuration following reset is GPIO. For PE2,
signal direction is controlled through the SCI PRR. The signal
can be configured as an SCI signal SCLK through the SCI PCR.

This input is 5 V tolerant.

1-24

Timers

1.12 Timers

The DSP56301 has three identical and independent timers. Each can use internal or external clocking,
interrupt the DSP56301 after a specified number of events (clocks), or signal an external device after
counting a specific number of internal events.

Table 1-15. Triple Timer Signals

Signal

Name

Type

State

During

Reset

Signal Description

TIO0

Input or
Output

Input

Timer 0 Schmitt-Trigger Input/Output
As an external event counter or in Measurement mode, TIO0 is
input. In Watchdog, Timer, or Pulse Modulation mode, TIO0 is
output.

The default mode after reset is GPIO input. This can be changed
to output or configured as a Timer Input/Output through the
Timer 0 Control/Status Register (TCSR0).

This input is 5 V tolerant.

TIO1

Input or
Output

Input

Timer 1 Schmitt-Trigger Input/Output
As an external event counter or in Measurement mode, TIO1 is
input. In Watchdog, Timer, or Pulse Modulation mode, TIO1 is
output.

The default mode after reset is GPIO input. This can be changed
to output or configured as a Timer Input/Output through the
Timer 1 Control/Status Register (TCSR1).

This input is 5 V tolerant.

TIO2

Input or
Output

Input

Timer 2 Schmitt-Trigger Input/Output
As an external event counter or in Measurement mode, TIO2 is
input. In Watchdog, Timer, or Pulse Modulation mode, TIO2 is
output.

The default mode after reset is GPIO input. This can be changed
to output or configured as a Timer Input/Output through the
Timer 2 Control/Status Register (TCSR2).

This input is 5 V tolerant.

1-25

JTAG/OnCE Interface

1.13 JTAG/OnCE Interface

Table 1-16. JTAG/OnCE Interface

Signal

Name

Type

State

During

Reset

Signal Description

TCK

Input

Test Clock
A test clock signal for synchronizing JTAG test logic.

This input is 5 V tolerant.

TDI

Input

Test Data Input
A test data serial signal for test instructions and data. TDI is
sampled on the rising edge of TCK and has an internal pull-up
resistor.

This input is 5 V tolerant.

TDO

Output

Tri-stated

Test Data Output
A test data serial signal for test instructions and data. TDO can
be tri-stated. The signal is actively driven in the shift-IR and
shift-DR controller states and changes on the falling edge of
TCK.

This input is 5 V tolerant.

TMS

Input

Test Mode Select
Sequences the test controller's state machine, is sampled on the
rising edge of TCK, and has an internal pull-up resistor.

This input is 5 V tolerant.

TRST

Input

Test Reset
Asynchronously initializes the test controller, has an internal
pull-up resistor, and must be asserted after power up.

This input is 5 V tolerant.

Input/Output

Input

Debug Event
Provides a way to enter Debug mode from an external command
controller (as input) or to acknowledge that the chip has entered
Debug mode (as output). When asserted as an input, DE causes
the DSP56300 core to finish the current instruction, save the
instruction pipeline information, enter Debug mode, and wait for
commands from the debug serial input line. When a debug
request or a breakpoint condition causes the chip to enter Debug
mode, DE is asserted as an output for three clock cycles. DE has
an internal pull-up resistor.

DE is not a standard part of the JTAG Test Access Port (TAP)
Controller. It connects to the OnCE module to initiate Debug
mode directly or to provide a direct external indication that the
chip has entered the Debug mode. All other interface with the
OnCE module must occur through the JTAG port.

This input is 5 V tolerant.

2-2

Absolute Maximum Ratings

2.3 Absolute Maximum Ratings

2.4 Thermal Characteristics

Table 2-1. Maximum Ratings

Rating

Symbol

Value

1, 2

Unit

Supply Voltage

0.3 to +4.0

All input voltages excluding "5 V tolerant" inputs

GND

0.3 to V

+ 0.3

All "5 V tolerant" input voltages

IN5

GND 0.3 to V

+ 3.95

Current drain per pin excluding V

and GND

Operating temperature range

40 to +100

Storage temperature

STG

55 to +150

Notes:

GND = 0 V, V

= 3.3 V

0.3 V, T

= 40

C to +100

C, CL = 50 pF

Absolute maximum ratings are stress ratings only, and functional operation at the maximum is not
guaranteed. Stress beyond the maximum rating may affect device reliability or cause permanent
damage to the device.

CAUTION: All "5 V Tolerant" input voltages cannot be more than 3.95 V greater than the supply
voltage; this restriction applies to "power on," as well as during normal operation. In any case, the
input voltages must not be higher than 5.75 V. "5 V Tolerant" inputs are inputs that tolerate 5 V.

Table 2-2. Thermal Characteristics

Characteristic

Symbol

TQFP
Value

PBGA

Value

PBGA

Value

Unit

Junction-to-ambient thermal resistance

49.5

48.4

25.2

C/W

Junction-to-case thermal resistance

7.2

C/W

Thermal characterization parameter

4.7

C/W

Notes:

Junction-to-ambient thermal resistance is based on measurements on a horizontal single-sided
printed circuit board per JEDEC Specification JESD51-3.

Junction-to-case thermal resistance is based on measurements using a cold plate per SEMI G30-88,
with the exception that the cold plate temperature is used for the case temperature.

These are simulated values. See note 1 for test board conditions.

These are simulated values. The test board has two 2-ounce signal layers and two 1-ounce solid
ground planes internal to the test board.

2-3

DC Electrical Characteristics

2.5 DC Electrical Characteristics

Table 2-3. DC Electrical Characteristics

Characteristics

Symbol

Min

Typ

Max

Unit

Supply voltage

3.0

3.3

3.6

Input high voltage
·

D[023], BG, BB, TA

MOD

/IRQ

, RESET, PINIT/NMI and all

JTAG/ESSI/SCI/Timer/HI32 pins

EXTAL

IHP

IHX

2.0
2.0

0.8

--
--

5.25

V
V

Input low voltage
·

D[023], BG, BB, TA, MOD

/IRQ

, RESET,

PINIT

All JTAG/ESSI/SCI/Timer/HI32 pins

EXTAL

ILP

ILX

0.3
0.3
0.3

--
--
--

0.8
0.8

0.2

V
V
V

Input leakage current

High impedance (off-state) input current (@ 2.4
V / 0.4 V)

TSI

Output high voltage
·

TTL (I

= 0.4 mA)

5,7

CMOS (I

= 10

2.4

0.01

--
--

V
V

Output low voltage
·

TTL (I

= 1.6 mA, open-drain pins I

= 6.7

mA)

5,7

CMOS (I

= 10

--
--

0.4

0.01

V
V

Internal supply current

In Normal mode

In Wait mode

In Stop mode

CCI

CCW

CCS

--
--
--

80 MHz

102

100

100 MHz

127

7.5

100

--
--
--

mA
mA

PLL supply current

2.5

Input capacitance

Notes:

Refers to MODA/IRQA, MODB/IRQB, MODC/IRQC, and MODD/IRQD pins.

Power Consumption Considerations on page 4-3 provides a formula to compute the estimated
current requirements in Normal mode. To obtain these results, all inputs must be terminated (that is,
not allowed to float). Measurements are based on synthetic intensive DSP benchmarks (see
Appendix A). The power consumption numbers in this specification are 90 percent of the measured
results of this benchmark. This reflects typical DSP applications. Typical internal supply current is
measured with V

= 3.0 V at T

= 100°C.

To obtain these results, all inputs must be terminated (that is, not allowed to float).

To obtain these results, all inputs that are not disconnected at Stop mode must be terminated (that is,
not allowed to float). PLL and XTAL signals are disabled during Stop state.

Periodically sampled and not 100 percent tested.

= 3.3 V

0.3 V; T

= 40°C to +100 °C, C

= 50 pF

This characteristic does not apply to XTAL and PCAP.

Driving EXTAL to the low V

IHX

or the high V

ILX

value may cause additional power consumption (DC

current). To minimize power consumption, the minimum V

IHX

should be no lower than

0.9

and the maximum V

ILX

should be no higher than 0.1

2-4

AC Electrical Characteristics

2.6 AC Electrical Characteristics

The timing waveforms shown in the AC electrical characteristics section are tested with a V

maximum

of 0.3 V and a V

minimum of 2.4 V for all pins except EXTAL, which is tested using the input levels

shown in Note 6 of Table 2-3. AC timing specifications, which are referenced to a device input signal,
are measured in production with respect to the 50 percent point of the respective input signal's transition.

Note:

Although the minimum value for the frequency of EXTAL is 0 MHz, the device AC test
conditions are 15 MHz and rated speed.

All specifications for the high impedance state are guaranteed by design.

2.6.1 Internal Clocks

Table 2-4. Internal Clocks, CLKOUT

Characteristics

Symbol

Expression

1, 2

Min

Typ

Max

Internal operation frequency and CLKOUT with PLL
enabled

(Ef

MF)/

(PDF

DF)

Internal operation frequency and CLKOUT with PLL
disabled

Ef/2

Internal clock and CLKOUT high period
·

With PLL disabled

With PLL enabled and MF

With PLL enabled and MF > 4

0.49

PDF

DF/MF

0.47

PDF

DF/MF

0.51

PDF

DF/MF

0.53

PDF

DF/MF

Internal clock and CLKOUT low period
·

With PLL disabled

With PLL enabled and MF

With PLL enabled and MF > 4

0.49

PDF

DF/MF

0.47

PDF

DF/MF

0.51

PDF

DF/MF

0.53

PDF

DF/MF

Internal clock and CLKOUT cycle time with PLL enabled

PDF

DF/MF

Internal clock and CLKOUT cycle time with PLL disabled

Instruction cycle time

CYC

Notes:

DF = Division Factor; Ef = External frequency; ET

= External clock cycle = 1/Ef;

MF = Multiplication Factor; PDF = Predivision Factor; T

= Internal clock cycle

See the PLL and Clock Generator section in the

DSP56300 Family Manual

for details on the PLL.

2-5

AC Electrical Characteristics

2.6.2 External Clock Operation

The DSP56301 system clock is derived from the on-chip oscillator or it is externally supplied. To use the
on-chip oscillator, connect a crystal and associated resistor/capacitor components to EXTAL and XTAL;
examples are shown in Figure 2-1.

If an externally supplied square wave voltage source is used, disable the internal oscillator circuit during
bootup by setting XTLD (PCTL Register bit 16 = 1--see the DSP56301 User's Manual). The external
square wave source connects to

EXTAL

;

XTAL

is not physically connected to the board or socket. Figure

2-2 shows the relationship between the

EXTAL

input and the internal clock and

CLKOUT

Figure 2-1. Crystal Oscillator Circuits

Figure 2-2. External Clock Timing

Suggested Component Values:
f

OSC

= 4 MHz

R = 680 k

10%

C = 56 pF

20%

Calculations were done for a 4/20 MHz crystal
with the following parameters:
·

of 30/20 pF,

of 7/6 pF,

series resistance of 100/20

, and

drive level of 2 mW.

Suggested Component Values:
f

OSC

= 32.768 kHz

R1 = 3.9 M

10%

C = 22 pF

20%

R2 = 200 k

10%

Calculations were done for a 32.768 kHz crystal
with the following parameters:
·

load capacitance (C

) of 12.5 pF,

shunt capacitance (C

) of 1.8 pF,

series resistance of 40 k

, and

drive level of 1

XTAL1

Fundamental Frequency

Fork Crystal Oscillator

XTAL

EXTAL

XTAL1

Fundamental Frequency

Crystal Oscillator

XTAL

EXTAL

OSC

= 20 MHz

R = 680 k

10%

C = 22 pF

20%

Note: Make sure that in
the PCTL Register:
·

XTLD (bit 16) = 0

If f

OSC

200 kHz,

XTLR (bit 15) = 1

Note: Make sure that in
the PCTL Register:
·

XTLD (bit 16) = 0

If f

OSC

> 200 kHz,

XTLR (bit 15) = 0

EXTAL

ILX

IHX

Midpoint

Note:

The midpoint is
0.5 (V

IHX

+ V

ILX

CLKOUT with

PLL disabled

CLKOUT with

PLL enabled

2-6

AC Electrical Characteristics

2.6.3 Phase Lock Loop (PLL) Characteristics

Table 2-5. Clock Operation

No.

Characteristics

Symbol

80 MHz

100 MHz

Min

Max

Min

Max

Frequency of EXTAL (EXTAL Pin Frequency)
The rise and fall time of this external clock should be 3 ns maximum.

80.0 MHz

100.0

MHz

EXTAL input high

1, 2

With PLL disabled (46.7%53.3% duty cycle

)

With PLL enabled (42.5%57.5% duty cycle

)

5.84 ns
5.31 ns

157.0

4.67 ns
4.25 ns

157.0

EXTAL input low

1, 2

With PLL disabled (46.7%53.3% duty cycle

)

With PLL enabled (42.5%57.5% duty cycle

)

5.84 ns
5.31 ns

157.0

4.67 ns
4.25 ns

157.0

EXTAL cycle time

With PLL disabled

With PLL enabled

12.50 ns
12.50 ns

273.1

10.00 ns
10.00 ns

273.1

CLKOUT change from EXTAL fall with PLL disabled

4.3 ns

11.0 ns

4.3 ns

11.0 ns

a. CLKOUT rising edge from EXTAL rising edge with PLL enabled
(MF = 1 or 2 or 4, PDF = 1, Ef > 15 MHz)

3,5

b. CLKOUT falling edge from EXTAL falling edge with PLL enabled
(MF

4, PDF

1, Ef / PDF > 15 MHz)

3,5

0.0 ns

1.8 ns

0.0 ns

1.8 ns

Instruction cycle time = I

CYC

= T

(see Table 2-4) (46.7%53.3% duty cycle)
·

With PLL disabled

With PLL enabled

CYC

25.0 ns

12.50 ns

8.53

20.0 ns

10.00 ns

8.53

Notes:

Measured at 50 percent of the input transition

The maximum value for PLL enabled is given for minimum VCO frequency (see Table 2-6) and maximum MF.

Periodically sampled and not 100 percent tested

The maximum value for PLL enabled is given for minimum VCO frequency and maximum DF.

The skew is not guaranteed for any other MF value.

The indicated duty cycle is for the specified maximum frequency for which a part is rated. The minimum clock high or low
time required for correction operation, however, remains the same at lower operating frequencies; therefore, when a
lower clock frequency is used, the signal symmetry may vary from the specified duty cycle as long as the minimum high
time and low time requirements are met.

Table 2-6. PLL Characteristics

Characteristics

80 MHz

100 MHz

Unit

Min

Max

Min

Max

Voltage Controlled Oscillator (VCO) frequency when
PLL enabled (MF

2/PDF)

160

200

MHz

PLL external capacitor (PCAP pin to V

CCP

) (C

PCAP

)

@ MF

@ MF > 4

(MF

580)

100

830

(MF

780)

140

1470

(MF

580)

100

830

(MF

780)

140

1470

Note:

PCAP

is the value of the PLL capacitor (connected between the PCAP pin and V

CCP

). The recommended value in pF for

PCAP

can be computed from one of the following equations:

(680

MF) 120, for MF

4, or

1100

MF, for MF > 4.

2-7

AC Electrical Characteristics

2.6.4 Reset, Stop, Mode Select, and Interrupt Timing

Table 2-7. Reset, Stop, Mode Select, and Interrupt Timing

No.

Characteristics

Expression

80 MHz

100 MHz

Unit

Min

Max

Min

Max

Delay from RESET assertion to all pins at reset value

26.0

Required RESET duration

Power on, external clock generator, PLL disabled

Power on, external clock generator, PLL enabled

Power on, internal oscillator

During STOP, XTAL disabled (PCTL Bit 16 = 0)

During STOP, XTAL enabled (PCTL Bit 16 = 1)

During normal operation

1000

75000

2.5

625.0

12.5

1.0
1.0

31.3
31.3

--
--
--
--
--
--

500.0

10.0
0.75
0.75
25.0
25.0

--
--
--
--
--
--

ms
ms

ns
ns

Delay from asynchronous RESET deassertion to first external
address output (internal reset deassertion)

Minimum

Maximum

3.25

+ 2.0

20.25 T

+ 10.0

42.6

263.1

34.5

212.5

ns
ns

Synchronous reset setup time from RESET deassertion to
CLKOUT Transition 1
·

Minimum

Maximum

7.4

12.5

5.9

10.0

ns
ns

Synchronous reset deasserted, delay time from the CLKOUT
Transition 1 to the first external address output
·

Minimum

Maximum

3.25

+ 1.0

20.25

+ 1.0

41.6

258.1

33.5

207.5

ns
ns

Mode select setup time

30.0

Mode select hold time

0.0

Minimum edge-triggered interrupt request assertion width

8.25

6.6

Minimum edge-triggered interrupt request deassertion width

8.25

7.1

Delay from IRQA, IRQB, IRQC, IRQD, NMI assertion to external
memory access address out valid
·

Caused by first interrupt instruction fetch

Caused by first interrupt instruction execution

4.25

+ 2.0

7.25

+ 2.0

55.1
92.6

--
--

44.5
74.5

--
--

ns
ns

Delay from IRQA, IRQB, IRQC, IRQD, NMI assertion to
general-purpose transfer output valid caused by first interrupt
instruction execution

+ 5.0

130.0

105.0

Delay from address output valid caused by first interrupt
instruction execute to interrupt request deassertion for level
sensitive fast interrupts

80 MHz:
3.75

+ WS

12.4

100 MHz:
3.75

+ WS

10.94

Note 8

Delay from RD assertion to interrupt request deassertion for
level sensitive fast interrupts

80 MHz:
3.25

+ WS

12.4

100 MHz:
3.25

+ WS

10.94

Note 8

2-8

AC Electrical Characteristics

Delay from WR assertion to interrupt request deassertion for
level sensitive fast interrupts

DRAM for all WS

SRAM WS = 1

SRAM WS = 2, 3

SRAM WS

80 MHz:

(WS + 3.5)

12.4

100 MHz:

(WS + 3.5)

10.94

80 MHz:

(WS + 3.5)

12.4

100 MHz:

(WS + 3.5)

10.94

80 MHz:

(WS + 3)

12.4

100 MHz:

(WS + 3)

10.94

80 MHz:

(WS + 2.5)

12.4

100 MHz:

(WS + 2.5)

10.94

Note 8

Synchronous interrupt setup time from IRQA, IRQB, IRQC,
IRQD, NMI assertion to the CLKOUT Transition 2

7.4

5.9

Synchronous interrupt delay time from the CLKOUT Transition
2 to the first external address output valid caused by the first
instruction fetch after coming out of Wait Processing state
·

Minimum

Maximum

8.25

+ 1.0

24.75

+ 5.0

116.6

314.4

83.5

252.5

ns
ns

Duration for IRQA assertion to recover from Stop state

7.4

5.9

Delay from IRQA assertion to fetch of first instruction (when
exiting Stop)

2, 3

PLL is not active during Stop (PCTL Bit 17 = 0) and Stop
delay is enabled (Operating Mode Register Bit 6 = 0)

PLL is not active during Stop (PCTL Bit 17 = 0) and Stop
delay is not enabled (Operating Mode Register Bit 6 = 1)

PLL is active during Stop (PCTL Bit 17 = 1) (Implies No Stop
Delay)

PLC

PDF + (128 K

PLC/2)

PLC

PDF + (23.75

0.5)

(9.25 ± 0.5)

1.6

290.6 ns

109.4

17.0

15.4 ms

121.9

1.3

232.5

87.5

13.6

12.3

97.5

Duration of level sensitive IRQA assertion to ensure interrupt
service (when exiting Stop)

2, 3

PLL is not active during Stop (PCTL Bit 17 = 0) and Stop
delay is enabled (Operating Mode Register Bit 6 = 0)

PLL is not active during Stop (PCTL Bit 17 = 0) and Stop
delay is not enabled (Operating Mode Register Bit 6 = 1)

PLL is active during Stop (PCTL Bit 17 = 1) (implies no Stop
delay)

PLC

PDF + (128K

PLC/2)

PLC

PDF +

(20.5

0.5)

5.5

17.0

15.4

68.8

13.6

12.3

55.0

Interrupt Request Rate
·

HI32, ESSI, SCI, Timer

DMA

IRQ, NMI (edge trigger)

IRQ, NMI (level trigger)

--
--
--
--

150.0
100.0
100.0
150.0

--
--
--
--

120.0

80.0
80.0

120.0

ns
ns
ns
ns

Table 2-7. Reset, Stop, Mode Select, and Interrupt Timing

(Continued)

No.

Characteristics

Expression

80 MHz

100 MHz

Unit

Min

Max

Min

Max

2-9

AC Electrical Characteristics

DMA Request Rate
·

Data read from HI32, ESSI, SCI

Data write to HI32, ESSI, SCI

Timer

IRQ, NMI (edge trigger)

--
--
--
--

75.0
87.5
25.0
37.5

--
--
--
--

60.0
70.0
20.0
30.0

ns
ns
ns
ns

Delay from IRQA, IRQB, IRQC, IRQD, NMI assertion to external
memory (DMA source) access address out valid

4.25

+ 2.0

55.1

44.5

Notes:

When using fast interrupts and IRQA, IRQB, IRQC, and IRQD are defined as level-sensitive, timings 19 through 21 apply to prevent
multiple interrupt service. To avoid these timing restrictions, the deasserted Edge-triggered mode is recommended when using fast
interrupts. Long interrupts are recommended when using Level-sensitive mode.

This timing depends on several settings:

· For PLL disable, using internal oscillator (PLL Control Register (PCTL) Bit 16 = 0) and oscillator disabled during Stop (PCTL Bit 17
= 0), a stabilization delay is required to assure that the oscillator is stable before programs are executed. Resetting the Stop delay
(Operating Mode Register Bit 6 = 0) provides the proper delay. While Operating Mode Register Bit 6 = 1 can be set, it is not
recommended, and these specifications do not guarantee timings for that case.

· For PLL disable, using internal oscillator (PCTL Bit 16 = 0) and oscillator enabled during Stop (PCTL Bit 17=1), no stabilization
delay is required and recovery is minimal (Operating Mode Register Bit 6 setting is ignored).

· For PLL disable, using external clock (PCTL Bit 16 = 1), no stabilization delay is required and recovery time is defined by the PCTL
Bit 17 and Operating Mode Register Bit 6 settings.

· For PLL enable, if PCTL Bit 17 is 0, the PLL is shutdown during Stop. Recovering from Stop requires the PLL to get locked. The
PLL lock procedure duration, PLL Lock Cycles (PLC), may be in the range of 0 to 1000 cycles. This procedure occurs in parallel with
the stop delay counter, and stop recovery ends when the last of these two events occurs. The stop delay counter completes count or
PLL lock procedure completion.

· PLC value for PLL disable is 0.

· The maximum value for ET

is 4096 (maximum MF) divided by the desired internal frequency (that is, for 66 MHz it is 4096/66 MHz

= 62

s). During the stabilization period, T

, T

and T

is not constant, and their width may vary, so timing may vary as well.

Periodically sampled and not 100 percent tested.

Value depends on clock source:

· For an external clock generator, RESET duration is measured while RESET is asserted, V

is valid, and the EXTAL input is active

and valid.

· For an internal oscillator, RESET duration is measured while RESET is asserted and V

is valid. The specified timing reflects the

crystal oscillator stabilization time after power-up. This number is affected both by the specifications of the crystal and other
components connected to the oscillator and reflects worst case conditions.

· When the V

is valid, but the other "required RESET duration" conditions (as specified above) have not been yet met, the device

circuitry is in an uninitialized state that can result in significant power consumption and heat-up. Designs should minimize this state to
the shortest possible duration.

If PLL does not lose lock.

= 3.3 V

0.3 V; T

= 40°C to +100°C, C

= 50 pF.

WS = number of wait states (measured in clock cycles, number of T

Use the expression to compute a maximum value.

Figure 2-3. Reset Timing

Table 2-7. Reset, Stop, Mode Select, and Interrupt Timing

(Continued)

No.

Characteristics

Expression

80 MHz

100 MHz

Unit

Min

Max

Min

Max

RESET

Reset Value

First Fetch

All Pins

A[023]

2-13

AC Electrical Characteristics

2.6.5 External Memory Expansion Port (Port A)

2.6.5.1 SRAM Timing

Table 2-8. SRAM Read and Write Accesses

3,6

No.

Characteristics

Symbol

Expression

80 MHz

100 MHz

Unit

Min

Max

Min

Max

100

Address valid and AA
assertion pulse width

, t

(WS + 1)

4.0 [1

(WS + 2)

4.0 [4

(WS + 3)

4.0 [WS

21.0
71.0

133.5

--
--
--

16.0
56.0

106.0

--
--
--

ns
ns
ns

101

Address and AA valid
to WR assertion

0.25

2.0 [WS = 1]

0.75

2.0 [2

1.25

2.0 [WS

1.1
7.4

13.6

--
--
--

0.5
5.5

10.5

--
--
--

ns
ns
ns

102

WR assertion pulse
width

1.5

4.0 [WS = 1]

4.0 [2

(WS

0.5)

4.0 [WS

14.8
21.0
39.8

--
--
--

11.0
16.0
31.0

--
--
--

ns
ns
ns

103

WR deassertion to
address not valid

0.25

2.0 [1

1.25

4.0 [4

2.25

4.0 [WS

1.1

11.6
24.1

--
--
--

0.5
8.5

18.5

--
--
--

ns
ns
ns

104

Address and AA valid
to input data valid

, t

(WS + 0.75)

5.0 [WS

16.9

12.5

105

RD assertion to input
data valid

(WS + 0.25)

5.0 [WS

10.6

7.5

106

RD deassertion to
data not valid (data
hold time)

OHZ

0.0

107

Address valid to WR
deassertion

(WS + 0.75)

4.0 [WS

17.9

13.5

108

Data valid to WR
deassertion (data
setup time)

)

(WS

0.25)

3.0 [WS

6.4

4.5

109

Data hold time from
WR deassertion

0.25

2.0 [1

1.25

2.0 [4

2.25

2.0 [WS

1.1

13.6
26.1

--
--
--

0.5

10.5
20.5

--
--
--

ns
ns
ns

110

WR assertion to data
active

0.75

3.7 [WS = 1]

0.25

3.7 [2

0.25

3.7 [WS

5.7

0.6
6.8

--
--
--

3.8

1.2
6.2

--
--
--

ns
ns
ns

111

WR deassertion to
data high impedance

0.25

+ 0.2 [1

1.25

+ 0.2 [4

2.25

+ 0.2 [WS

--
--
--

3.3

15.8
28.3

--
--
--

2.7

12.7
22.7

ns
ns
ns

112

Previous RD
deassertion to data
active (write)

1.25

4.0 [1

2.25

4.0 [4

3.25

4.0 [WS

11.6
24.1
36.6

--
--
--

8.5

18.5
28.5

--
--
--

ns
ns
ns

2-14

AC Electrical Characteristics

113

RD deassertion time

0.75

4.0 [1

1.75

4.0 [4

2.75

4.0 [WS

5.4

17.9
30.4

--
--
--

3.5

13.5
23.5

--
--
--

ns
ns
ns

114

WR deassertion time

0.5

4.0 [WS = 1]

4.0 [2

2.5

4.0 [4

3.5

4.0 [WS

2.3
8.5

27.3
39.8

--
--
--
--

1.0
6.0

21.0
31.0

--
--
--
--

ns
ns
ns
ns

115

Address valid to RD
assertion

0.5

4.0

2.3

1.0

116

RD assertion pulse
width

(WS + 0.25)

4.0

11.6

8.5

117

RD deassertion to
address not valid

0.25

2.0 [1

1.25

2.0 [4

2.25

2.0 [WS

1.1

13.6
26.1

--
--
--

0.5

10.5
20.5

--
--
--

ns
ns
ns

118

TA setup before RD
or WR deassertion

0.25

+ 2.0

5.1

4.5

119

TA hold after RD or
WR deassertion

Notes:

WS is the number of wait states specified in the BCR.

Timings 100, 107 are guaranteed by design, not tested.

All timings for 100 MHz are measured from 0.5 ·

Vcc to 0.5

Vcc

Timing 118 is relative to the deassertion edge of RD or WR even if TA remains active.

Timings 110, 111, and 112, are not helpful and are not specified for 100 MHz.

= 3.3 V

0.3 V; T

= 40°C to +100°C, C

= 50 pF

Table 2-8. SRAM Read and Write Accesses

3,6

(Continued)

No.

Characteristics

Symbol

Expression

80 MHz

100 MHz

Unit

Min

Max

Min

Max

2-17

AC Electrical Characteristics

Table 2-9. DRAM Page Mode Timings, Two Wait States

1, 2, 3, 7

No.

Characteristics

Symbol

Expression

80 MHz

Unit

Min

Max

131

Page mode cycle time for two consecutive accesses of the
same direction

Page mode cycle time for mixed (read and write) accesses

2.75

37.5

34.4

132

CAS assertion to data valid (read)

CAC

1.5

6.5

12.3

133

Column address valid to data valid (read)

2.5

6.5

24.8

134

CAS deassertion to data not valid (read hold time)

OFF

0.0

135

Last CAS assertion to RAS deassertion

RSH

1.75

4.0

17.9

136

Previous CAS deassertion to RAS deassertion

RHCP

3.25

4.0

36.6

137

CAS assertion pulse width

CAS

1.5

4.0

14.8

138

Last CAS deassertion to RAS deassertion

BRW[10] = 00
BRW[10] = 01
BRW[10] = 10
BRW[10] = 11

CRP

Not supported

3.5

6.0

4.5

6.0

6.5

6.0

37.8
50.3
75.3

--
--
--
--

ns
ns
ns
ns

139

CAS deassertion pulse width

1.25

4.0

11.6

140

Column address valid to CAS assertion

ASC

4.0

8.5

141

CAS assertion to column address not valid

CAH

1.75

4.0

17.9

142

Last column address valid to RAS deassertion

RAL

4.0

33.5

143

WR deassertion to CAS assertion

RCS

1.25

11.6

144

CAS deassertion to WR assertion

RCH

0.5

3.7

2.6

145

CAS assertion to WR deassertion

WCH

1.5

4.2

14.6

146

WR assertion pulse width

2.5

4.5

26.8

147

Last WR assertion to RAS deassertion

RWL

2.75

4.3

30.1

148

WR assertion to CAS deassertion

CWL

2.5

4.3

27.0

149

Data valid to CAS assertion (write)

0.25

3.0

0.1

150

CAS assertion to data not valid (write)

1.75

4.0

17.9

151

WR assertion to CAS assertion

WCS

4.3

8.2

152

Last RD assertion to RAS deassertion

ROH

2.5

4.0

27.3

153

RD assertion to data valid

1.75

6.5

15.4

154

RD deassertion to data not valid

0.0

155

WR assertion to data active

0.75

1.5

7.9

156

WR deassertion to data high impedance

0.25

3.1

Notes:

The number of wait states for Page mode access is specified in the DCR.

The refresh period is specified in the DCR.

The asynchronous delays specified in the expressions are valid for the DSP56301.

All the timings are calculated for the worst case. Some of the timings are better for specific cases (for
example, t

equals 3

for read-after-read or write-after-write sequences).

BRW[10] (DRAM Control Register bits) defines the number of wait states that should be inserted in each
DRAM out-of-page access.

RD deassertion always occurs after CAS deassertion; therefore, the restricted timing is t

OFF

and not t

GZ.

At this time, there are no DRAMs fast enough to fit with two wait states Page mode @ 100MHz (see Table
2-14). However, DRAM speeds are approaching two-wait-state compatibility.

2-18

AC Electrical Characteristics

Table 2-10. DRAM Page Mode Timings, Three Wait States

1, 2, 3

No.

Characteristics

Symbol

Expression

80 MHz

100 MHz

Unit

Min

Max

Min

Max

131

Page mode cycle time for two consecutive accesses of the
same direction

Page mode cycle time for mixed (read and write) accesses

3.5

50.0

43.7

40.0

35.0

132

CAS assertion to data valid (read)

CAC

5.7

19.3

14.3

133

Column address valid to data valid (read)

5.7

31.8

24.3

134

CAS deassertion to data not valid (read hold time)

OFF

0.0

135

Last CAS assertion to RAS deassertion

RSH

2.5

4.0

27.3

21.0

136

Previous CAS deassertion to RAS deassertion

RHCP

4.5

4.0

52.3

41.0

137

CAS assertion pulse width

CAS

4.0

21.0

16.0

138

Last CAS deassertion to RAS assertion

BRW[10] = 00

BRW[10] = 01

BRW[10] = 10

BRW[10] = 11

CRP

Not supported

3.75

6.0

4.75

6.0

6.75

6.0

40.9
53.4
78.4

--
--
--
--

31.5
41.5
61.5

--
--
--
--

ns
ns
ns
ns

139

CAS deassertion pulse width

1.5

4.0

14.8

11.0

140

Column address valid to CAS assertion

ASC

4.0

8.5

6.0

141

CAS assertion to column address not valid

CAH

2.5

4.0

27.3

21.0

142

Last column address valid to RAS deassertion

RAL

4.0

46.0

36.0

143

WR deassertion to CAS assertion

RCS

1.25

4.0

11.6

8.5

144

CAS deassertion to WR assertion

RCH

0.75

4.0

5.4

3.5

145

CAS assertion to WR deassertion

WCH

2.25

4.2

23.9

18.3

146

WR assertion pulse width

3.5

4.5

39.3

30.5

147

Last WR assertion to RAS deassertion

RWL

3.75

4.3

42.6

33.2

148

WR assertion to CAS deassertion

CWL

3.25

4.3

36.3

28.2

149

Data valid to CAS assertion (write)

0.5

4.8

2.0

0.2

150

CAS assertion to data not valid (write)

2.5

4.0

27.3

21.0

151

WR assertion to CAS assertion

WCS

1.25

4.3

11.3

8.2

152

Last RD assertion to RAS deassertion

ROH

3.5

4.0

39.8

31.0

153

RD assertion to data valid

2.5

5.7

25.6

19.3

154

RD deassertion to data not valid

0.0

155

WR assertion to data active

0.75

1.5

7.9

6.0

156

WR deassertion to data high impedance

0.25

3.1

2.5

Notes:

The number of wait states for Page mode access is specified in the DCR.

The refresh period is specified in the DCR.

The asynchronous delays specified in the expressions are valid for DSP56301

All the timings are calculated for the worst case. Some of the timings are better for specific cases (for example, t

equals 4

for read-after-read or write-after-write sequences).

BRW[10] (DRAM control register bits) defines the number of wait states that should be inserted in each DRAM out-of
page-access.

RD deassertion always occurs after CAS deassertion; therefore, the restricted timing is t

OFF

and not t

2-19

AC Electrical Characteristics

Table 2-11. DRAM Page Mode Timings, Four Wait States

1, 2, 3

No.

Characteristics

Symbol

Expression

80 MHz

100 MHz

Unit

Min

Max

Min

Max

131

Page mode cycle time for two consecutive accesses of the
same direction

Page mode cycle time for mixed (read and write) accesses

4.5

62.5

56.2

50.0

45.0

132

CAS assertion to data valid (read)

CAC

2.75

5.7

28.7

21.8

133

Column address valid to data valid (read)

3.75

5.7

41.2

31.8

134

CAS deassertion to data not valid (read hold time)

OFF

0.0

135

Last CAS assertion to RAS deassertion

RSH

3.5

4.0

39.8

31.0

136

Previous CAS deassertion to RAS deassertion

RHCP

4.0

71.0

56.0

137

CAS assertion pulse width

CAS

2.5

4.0

27.3

21.0

138

Last CAS deassertion to RAS assertion

BRW[10] = 00

BRW[10] = 01

BRW[10] = 10

BRW[10] = 11

CRP

Not supported

4.25

6.0

5.25

6.0

7.25

6.0

47.2
59.6
84.6

--
--
--
--

36.5
46.5
66.5

--
--
--
--

ns
ns
ns
ns

139

CAS deassertion pulse width

4.0

21.0

16.0

140

Column address valid to CAS assertion

ASC

4.0

8.5

6.0

141

CAS assertion to column address not valid

CAH

3.5

4.0

39.8

31.0

142

Last column address valid to RAS deassertion

RAL

4.0

58.5

46.0

143

WR deassertion to CAS assertion

RCS

1.25

4.0

11.8

8.5

144

CAS deassertion to WR assertion

RCH

1.25

3.7

11.9

8.8

145

CAS assertion to WR deassertion

WCH

3.25

4.2

36.4

28.3

146

WR assertion pulse width

4.5

51.8

40.5

147

Last WR assertion to RAS deassertion

RWL

4.75

4.3

55.1

43.2

148

WR assertion to CAS deassertion

CWL

3.75

4.3

42.6

33.2

149

Data valid to CAS assertion (write)

0.5

4.8

1.5

0.2

150

CAS assertion to data not valid (write)

3.5

4.0

39.8

31.0

151

WR assertion to CAS assertion

WCS

1.25

4.3

11.3

8.2

152

Last RD assertion to RAS deassertion

ROH

4.5

4.0

52.3

41.0

153

RD assertion to data valid

3.25

5.7

34.9

26.8

154

RD deassertion to data not valid

0.0

155

WR assertion to data active

0.75

1.5

7.9

6.0

156

WR deassertion to data high impedance

0.25

3.1

2.5

Notes:

The number of wait states for Page mode access is specified in the DCR.

The refresh period is specified in the DCR.

The asynchronous delays specified in the expressions are valid for DSP56301.

All the timings are calculated for the worst case. Some of the timings are better for specific cases (for example, t

equals

for read-after-read or write-after-write sequences).

BRW[10] (DRAM control register bits) defines the number of wait states that should be inserted in each DRAM out-of-page
access. N/A = does not apply because 100 MHz requires a minimum of three wait states.

RD deassertion always occurs after CAS deassertion; therefore, the restricted timing is t

OFF

and not t

2-21

AC Electrical Characteristics

Figure 2-17. DRAM Out-of-Page Wait States Selection Guide

Table 2-12. DRAM Out-of-Page and Refresh Timings, Eight Wait States

1, 2

No.

Characteristics

Symbol

Expression

80 MHz

Unit

Min

Max

157

Random read or write cycle time

112.5

158

RAS assertion to data valid (read)

RAC

4.75

6.5

52.9

159

CAS assertion to data valid (read)

CAC

2.25

6.5

21.6

160

Column address valid to data valid (read)

6.5

31.0

161

CAS deassertion to data not valid (read hold time)

OFF

0.0

162

RAS deassertion to RAS assertion

3.25

4.0

36.6

163

RAS assertion pulse width

RAS

5.75

4.0

67.9

164

CAS assertion to RAS deassertion

RSH

3.25

4.0

36.6

165

RAS assertion to CAS deassertion

CSH

4.75

4.0

55.4

166

CAS assertion pulse width

CAS

2.25

4.0

24.1

167

RAS assertion to CAS assertion

RCD

2.5

29.3

33.3

168

RAS assertion to column address valid

RAD

1.75

19.9

23.9

169

CAS deassertion to RAS assertion

CRP

4.25

4.0

49.1

Chip Frequency
(MHz)

DRAM Type

RAC

ns)

100

4 Wait States

8 Wait States

11 Wait States

15 Wait States

Note:

This figure should be used for primary selection. For
exact and detailed timings, see the following tables.

120

2-22

AC Electrical Characteristics

170

CAS deassertion pulse width

2.75

6.0

28.4

171

Row address valid to RAS assertion

ASR

3.25

4.0

36.6

172

RAS assertion to row address not valid

RAH

1.75

4.0

17.9

173

Column address valid to CAS assertion

ASC

0.75

4.0

5.4

174

CAS assertion to column address not valid

CAH

3.25

4.0

36.6

175

RAS assertion to column address not valid

5.75

4.0

67.9

176

Column address valid to RAS deassertion

RAL

4.0

46.0

177

WR deassertion to CAS assertion

RCS

3.8

21.2

178

CAS deassertion to WR

assertion

RCH

1.25

3.7

11.9

179

RAS deassertion to WR

assertion

RRH

0.25

2.6

0.5

180

CAS assertion to WR deassertion

WCH

4.2

33.3

181

RAS assertion to WR deassertion

WCR

5.5

4.2

64.6

182

WR assertion pulse width

8.5

4.5

101.8

183

WR assertion to RAS deassertion

RWL

8.75

4.3

105.1

184

WR assertion to CAS deassertion

CWL

7.75

4.3

92.6

185

Data valid to CAS assertion (write)

4.75

4.0

55.4

186

CAS assertion to data not valid (write)

3.25

4.0

36.6

187

RAS assertion to data not valid (write)

DHR

5.75

4.0

67.9

188

WR assertion to CAS assertion

WCS

5.5

4.3

64.5

189

CAS assertion to RAS assertion (refresh)

CSR

1.5

4.0

14.8

190

RAS deassertion to CAS assertion (refresh)

RPC

1.75

4.0

17.9

191

RD assertion to RAS deassertion

ROH

8.5

4.0

102.3

192

RD assertion to data valid

7.5

6.5

87.3

193

RD deassertion to data not valid

0.0

194

WR assertion to data active

0.75

1.5

7.9

195

WR deassertion to data high impedance

0.25

3.1

Notes:

The number of wait states for an out-of-page access is specified in the DCR.

The refresh period is specified in the DCR.

RD deassertion always occurs after CAS deassertion; therefore, the restricted timing is t

OFF

and not t

Either t

RCH

or t

RRH

must be satisfied for read cycles.

Table 2-12. DRAM Out-of-Page and Refresh Timings, Eight Wait States

1, 2

(Continued)

No.

Characteristics

Symbol

Expression

80 MHz

Unit

Min

Max

2-23

AC Electrical Characteristics

Table 2-13. DRAM Out-of-Page and Refresh Timings, Eleven Wait States

1, 2

No.

Characteristics

Symbol

Expression

80 MHz

100 MHz

Unit

Min

Max

Min

Max

157

Random read or write cycle time

150.0

120.0

158

RAS assertion to data valid (read)

RAC

80 MHz:

6.25

6.5

100 MHz:

6.25

7.0

71.6

55.5

159

CAS assertion to data valid (read)

CAC

80 MHz:

3.75

6.5

100 MHz:

3.75

7.0

40.4

30.5

160

Column address valid to data valid (read)

80 MHz:

4.5

6.5

100 MHz:

4.5

7.0

49.8

38.0

161

CAS deassertion to data not valid (read hold time)

OFF

0.0

162

RAS deassertion to RAS assertion

4.25

4.0

49.1

38.5

163

RAS assertion pulse width

RAS

7.75

4.0

92.9

73.5

164

CAS assertion to RAS deassertion

RSH

5.25

4.0

61.6

48.5

165

RAS assertion to CAS deassertion

CSH

6.25

4.0

74.1

58.5

166

CAS assertion pulse width

CAS

3.75

4.0

42.9

33.5

167

RAS assertion to CAS assertion

RCD

2.5

4.0

27.3

35.3

21.0

29.0

168

RAS assertion to column address valid

RAD

1.75

4.0

17.9

25.9

13.5

21.5

169

CAS deassertion to RAS assertion

CRP

5.75

4.0

67.9

53.5

170

CAS deassertion pulse width

4.25

6.0

49.1

36.5

171

Row address valid to RAS assertion

ASR

4.25

4.0

49.1

38.5

172

RAS assertion to row address not valid

RAH

1.75

4.0

17.9

13.5

173

Column address valid to CAS assertion

ASC

0.75

4.0

5.4

3.5

174

CAS assertion to column address not valid

CAH

5.25

4.0

61.6

48.5

175

RAS assertion to column address not valid

7.75

4.0

92.9

73.5

176

Column address valid to RAS deassertion

RAL

4.0

71.0

56.0

177

WR deassertion to CAS assertion

RCS

3.0

4.0

33.5

26.0

178

CAS deassertion to WR

assertion

RCH

1.75

3.7

17.9

13.8

179

RAS deassertion to WR

assertion

RRH

80 MHz:

0.25

2.6

100 MHz:

0.25

2.0

0.5

180

CAS assertion to WR deassertion

WCH

4.2

58.3

45.8

181

RAS assertion to WR deassertion

WCR

7.5

4.2

89.6

70.8

182

WR assertion pulse width

11.5

4.5

139.3

110.5

183

WR assertion to RAS deassertion

RWL

11.75

4.3

142.7

113.2

184

WR assertion to CAS deassertion

CWL

10.25

4.3

123.8

98.2

185

Data valid to CAS assertion (write)

5.75

4.0

67.9

53.5

2-24

AC Electrical Characteristics

186

CAS assertion to data not valid (write)

5.25

4.0

61.6

48.5

187

RAS assertion to data not valid (write)

DHR

7.75

4.0

92.9

73.5

188

WR assertion to CAS assertion

WCS

6.5

4.3

77.0

60.7

189

CAS assertion to RAS assertion (refresh)

CSR

1.5

4.0

14.8

11.0

190

RAS deassertion to CAS assertion (refresh)

RPC

2.75

4.0

30.4

23.5

191

RD assertion to RAS deassertion

ROH

11.5

4.0

139.8

111.0

192

RD assertion to data valid

80 MHz:

6.5

100 MHz:

7.0

118.5

93.0

193

RD deassertion to data not valid

0.0

194

WR assertion to data active

0.75

1.5

9.1

6.0

195

WR deassertion to data high impedance

0.25

3.1

2.5

Notes:

The number of wait states for an out-of-page access is specified in the DCR.

The refresh period is specified in the DCR.

RD deassertion always occurs after CAS deassertion; therefore, the restricted timing is t

OFF

and not t

Either t

RCH

or t

RRH

must be satisfied for read cycles.

Table 2-14. DRAM Out-of-Page and Refresh Timings, Fifteen Wait States

1, 2

No.

Characteristics

Symbol

Expression

80 MHz

100 MHz

Unit

Min

Max

Min

Max

157

Random read or write cycle time

200.0

160.0

158

RAS assertion to data valid (read)

RAC

80 MHz:

8.25

6.5

100 MHz:

8.25

5.7

96.6

76.8

159

CAS assertion to data valid (read)

CAC

80 MHz:

4.75

6.5

100 MHz:

4.75

5.7

52.9

41.8

160

Column address valid to data valid (read)

80 MHz:

5.5

6.5

100 MHz:

5.5

5.7

62.3

49.3

161

CAS deassertion to data not valid (read hold time)

OFF

0.0

162

RAS deassertion to RAS assertion

6.25

4.0

74.1

58.5

163

RAS assertion pulse width

RAS

9.75

4.0

117.9

93.5

164

CAS assertion to RAS deassertion

RSH

6.25

4.0

74.1

58.5

165

RAS assertion to CAS deassertion

CSH

8.25

4.0

99.1

78.5

166

CAS assertion pulse width

CAS

4.75

4.0

55.4

43.5

167

RAS assertion to CAS assertion

RCD

3.5

41.8

45.8

33.0

37.0

Table 2-13. DRAM Out-of-Page and Refresh Timings, Eleven Wait States

1, 2

(Continued)

No.

Characteristics

Symbol

Expression

80 MHz

100 MHz

Unit

Min

Max

Min

Max

2-25

AC Electrical Characteristics

168

RAS assertion to column address valid

RAD

2.75

2.0

32.4

36.4

25.5

29.5

169

CAS deassertion to RAS assertion

CRP

7.75

4.0

92.9

73.5

170

CAS deassertion pulse width

6.25

6.0

74.1

56.5

171

Row address valid to RAS assertion

ASR

6.25

4.0

74.1

58.5

172

RAS assertion to row address not valid

RAH

2.75

4.0

30.4

23.5

173

Column address valid to CAS assertion

ASC

0.75

4.0

5.4

3.5

174

CAS assertion to column address not valid

CAH

6.25

4.0

74.1

58.5

175

RAS assertion to column address not valid

9.75

4.0

117.9

93.5

176

Column address valid to RAS deassertion

RAL

4.0

83.5

66.0

177

WR deassertion to CAS assertion

RCS

3.8

58.7

46.2

178

CAS deassertion to WR

assertion

RCH

1.75

3.7

18.2

13.8

179

RAS deassertion to WR

assertion

RRH

80 MHz:

0.25

2.6

100 MHz:

0.25

2.0

0.5

180

CAS assertion to WR deassertion

WCH

4.2

70.8

55.8

181

RAS assertion to WR deassertion

WCR

9.5

4.2

114.6

90.8

182

WR assertion pulse width

15.5

4.5

189.3

150.5

183

WR assertion to RAS deassertion

RWL

15.75

4.3

192.6

153.2

184

WR assertion to CAS deassertion

CWL

14.25

4.3

173.8

138.2

185

Data valid to CAS assertion (write)

8.75

4.0

105.4

83.5

186

CAS assertion to data not valid (write)

6.25

4.0

74.1

58.5

187

RAS assertion to data not valid (write)

DHR

9.75

4.0

117.9

93.5

188

WR assertion to CAS assertion

WCS

9.5

4.3

114.5

90.7

189

CAS assertion to RAS assertion (refresh)

CSR

1.5

4.0

14.8

11.0

190

RAS deassertion to CAS assertion (refresh)

RPC

4.75

4.0

55.4

43.5

191

RD assertion to RAS deassertion

ROH

15.5

4.0

189.8

151.0

192

RD assertion to data valid

80 MHz:

6.5

100 MHz:

5.7

168.5

134.3

193

RD deassertion to data not valid

0.0

194

WR assertion to data active

0.75

1.5

9.1

6.0

195

WR deassertion to data high impedance

0.25

3.1

2.5

Notes:

The number of wait states for an out-of-page access is specified in the DCR.

The refresh period is specified in the DCR.

RD deassertion always occurs after CAS deassertion; therefore, the restricted timing is t

OFF

and not t

Either t

RCH

or t

RRH

must be satisfied for read cycles.

Table 2-14. DRAM Out-of-Page and Refresh Timings, Fifteen Wait States

1, 2

(Continued)

No.

Characteristics

Symbol

Expression

80 MHz

100 MHz

Unit

Min

Max

Min

Max

2-28

AC Electrical Characteristics

2.6.5.3 Synchronous Timings (SRAM)

Table 2-15. External Bus Synchronous Timings (SRAM Access)

No.

Characteristics

Expression

1,2

80 MHz

100 MHz

Unit

Min

Max

Min

Max

196

CLKOUT high to BS assertion

0.25

+5.2/0.5

2.6

8.3

2.0

7.7

197

CLKOUT high to BS deassertion

0.75

+4.2/1.0

8.4

13.6

6.5

11.7

198

CLKOUT high to address, and AA valid

0.25

+ 2.5

5.6

5.0

199

CLKOUT high to address, and AA invalid

0.25

0.7

2.4

1.8

200

TA valid to CLKOUT high (setup time)

5.8

4.0

201

CLKOUT high to TA invalid (hold time)

0.0

202

CLKOUT high to data out active

0.25

3.1

2.5

203

CLKOUT high to data out valid

80 MHz:

0.25

+ 4.5

100 MHz:

0.25

+ 4.0

7.6

6.5

204

CLKOUT high to data out invalid

0.25

3.1

2.5

205

CLKOUT high to data out high impedance

80 MHz:

0.25

+ 0.5

100 MHz:
0.25

3.6

2.5

206

Data in valid to CLKOUT high (setup)

5.0

4.0

207

CLKOUT high to data in invalid (hold)

0.0

208

CLKOUT high to RD assertion

maximum:

0.75

+ 2.5

10.4

11.9

6.7

10.0

ns
ns

209

CLKOUT high to RD deassertion

0.0

4.5

0.0

4.0

210

CLKOUT high to WR assertion

0.5

+ 4.3

[WS = 1 or WS

7.6

1.3

10.6

4.8

4.5

0.0

9.3

4.3

211

CLKOUT high to WR deassertion

0.0

4.3

0.0

3.8

Notes:

WS is the number of wait states specified in the BCR.

If WS > 1, WR assertion refers to the next rising edge of CLKOUT.

External bus synchronous timings should be used only for reference to the clock and

not

for relative timings.

T198 and T199 are valid for Address Trace mode if the ATE bit in the Operating Mode Register is set. Use the
status of BR (See T212) to determine whether the access referenced by A[023] is internal or external in this
mode.

2-30

AC Electrical Characteristics

2.6.5.4 Arbitration Timings

Table 2-16. Arbitration Bus Timings

No.

Characteristics

Expression

80 MHz

100 MHz

Unit

Min

Max

Min

Max

212

CLKOUT high to BR
assertion/deassertion

1.0

4.5

0.0

4.0

213

BG asserted/deasserted to CLKOUT
high (setup)

5.0

4.0

214

CLKOUT high to BG
deasserted/asserted (hold)

0.0

215

BB deassertion to CLKOUT high (input
setup)

5.0

4.0

216

CLKOUT high to BB assertion (input
hold)

0.0

217

CLKOUT high to BB assertion (output)

1.0

4.5

0.0

4.0

218

CLKOUT high to BB deassertion (output)

1.0

4.5

0.0

4.0

219

BB high to BB high impedance (output)

5.6

4.5

220

CLKOUT high to address and controls
active

0.25

3.1

2.5

221

CLKOUT high to address and controls
high impedance

0.75

9.4

7.5

222

CLKOUT high to AA active

0.25

3.1

2.5

223

CLKOUT high to AA deassertion

maximum: 0.25

+ 4.0

4.1

7.1

2.0

6.5

224

CLKOUT high to AA high impedance

0.75

9.4

7.5

Notes:

Synchronous Bus Arbitration is not recommended. Use Asynchronous mode whenever possible.

An expression is used to compute the maximum or minimum value listed, as appropriate. For timing 223, the
minimum is an absolute value.

T212 is valid for Address Trace mode when the ATE bit in the Operating Mode Register is set. BR is
deasserted for internal accesses and asserted for external accesses.

2-33

AC Electrical Characteristics

2.6.5.5 Asynchronous Bus Arbitrations Timings

The asynchronous bus arbitration is enabled by internal

inputs and synchronization circuits on

These synchronization circuits add delay from the external signal until it is exposed to internal logic. As a
result of this delay, a DSP56300 part can assume mastership and assert

, for some time after

deasserted. Timing 250 defines when

can be asserted.

Once

is asserted, there is a synchronization delay from

assertion to the time this assertion is

exposed to other DSP56300 components which are potential masters on the same bus. If

input is

asserted before that time, a situation of

asserted, and

deasserted, can cause another DSP56300

component to assume mastership at the same time. Therefore, a non-overlap period between one

input active to another

input active is required. Timing 251 ensures that such a situation is avoided.

Table 2-17. Asynchronous Bus Arbitration Timing

1,3

No.

Characteristics

Expression

80 MHz

100 MHz

Unit

Min

Max

Min

Max

250

BB assertion window from BG input deassertion

2.5

Tc + 5

251

Delay from BB assertion to BG assertion

Tc + 5

Notes:

Bit 13 in the Operating Mode Register must be set to enter Asynchronous Arbitration mode.

Asynchronous Arbitration mode is recommended for operation at 100 MHz.

If Asynchronous Arbitration mode is active, none of the timings in Table 2-16 is required.

In order to guarantee timings 250, and 251, BG inputs must be asserted to different DSP56300 devices on
the same bus in the non-overlap manner shown in Figure 2-26.

Figure 2-26. Asynchronous Bus Arbitration Timing

BG1

251

BG2

250

250+251

2-34

AC Electrical Characteristics

2.6.6 Host Interface Timing

Table 2-18. Universal Bus Mode Timing Parameters

No.

Characteristic

Expression

80 MHz

100 MHz

Unit

Min

Max

Min

Max

300

Access Cycle Time

37.5

30.0

301

HA[100], HAEN Setup to Data Strobe Assertion

5.8

4.6

302

HA[100], HAEN Valid Hold from Data Strobe Deassertion

0.0

303

HRW Setup to HDS Assertion

5.8

4.6

304

HRW Valid Hold from HDS Deassertion

0.0

305

Data Strobe Deasserted Width

4.1

3.3

306

Data Strobe Asserted Pulse Width

80 MHz: 2.5

+ 1.7

100 MHz: 2.5

+ 1.3

32.9

26.3

ns
ns

307

HBS Asserted Pulse Width

2.5

2.0

308

HBS Assertion to Data Strobe Assertion

80 MHz: T

4.9

100 MHz: T

4.0

7.6

6.0

ns
ns

309

HBS Assertion to Data Strobe Deassertion

80 MHz: 2.5

+ 2.9

100 MHz: 2.5

+ 2.3

34.1

27.3

ns
ns

310

HBS Deassertion to Data Strobe Deassertion

80 MHz: 1.5

+ 3.3

100 MHz: 1.5

+ 2.6

22.1

17.6

ns
ns

311

Data Out Valid to TA Assertion (HBS Not Used--Tied to V

)

80 MHz: 2

11.6

100 MHz: 2

9.2

13.4

10.8

ns
ns

312

Data Out Active from Read Data Strobe Assertion

1.7

1.3

313

Data Out Valid from Read Data Strobe Assertion
(No Wait States Inserted--HTA Asserted)

18.9

16.9

314

Data Out Valid Hold from Read Data Strobe Deassertion

1.7

1.3

315

Data Out High Impedance from Read Data Strobe Deassertion

12.0

9.6

316

Data In Valid Setup to Write Data Strobe Deassertion

8.3

6.6

317

Data In Valid Hold from Write Data Strobe Deassertion

0.0

318

HSAK Assertion from Data Strobe Assertion

30.0

319

HSAK Asserted Hold from Data Strobe Deassertion

2.0

320

HTA Active from Data Strobe Assertion

1,2,5

3.1

2.5

321

HTA Assertion from Data Strobe Assertion
(HBS Not Used--Tied to V

)

1,2,5

80 MHz: 2.0

+ 13.0

100 MHz: 2.0

+ 12.2

38.0

32.2

ns
ns

322

HTA Assertion from HBS Assertion

2,5

80 MHz: 2.0

+ 13.0

100 MHz: 2.0

+ 12.2

38.0

32.2

ns
ns

323

HTA Deasserted from Data Strobe Assertion

1,2,5

17.1

15.0

324

HTA Assertion to Data Strobe Deassertion

1,2

0.0

325

HTA High Impedance from Data Strobe Deassertion

1,2

15.3

12.2

326

HIRQ Asserted Pulse Width (HIRH = 0, HIRD = 1)

(LT + 1)

6.0

19.0

14.0

327

Data Strobe Deasserted Hold from HIRQ Deassertion
(HIRH = 0)

0.0

328

HIRQ Asserted Hold from Data Strobe Assertion (HIRH = 1)

1.5

18.8

15.0

2-35

AC Electrical Characteristics

329

HIRQ Deassertion from Data Strobe Assertion
(HIRH = 1, HIRD = 1)

80 MHz: 2.5

+ 24.7

100 MHz: 2.5

+ 21.5

55.9

46.5

ns
ns

330

HIRQ High Impedance from Data Strobe Assertion
(HIRH = 1, HIRD = 0)

1,6

80 MHz: 2.5

+ 24.7

100 MHz: 2.5

+ 21.5

55.9

46.5

ns
ns

331

HIRQ Active from Data Strobe Deassertion
(HIRH = 1, HIRD = 0)

2.5

31.3

25.0

332

HIRQ Deasserted Hold from Data Strobe Deassertion

2.5

31.3

25.0

333

HDRQ

Asserted Hold from Data Strobe Assertion

1.5

18.8

15.0

334

HDRQ

Deassertion from Data Strobe Assertion

80 MHz: 2.5

+ 24.7

100 MHz: 2.5

+ 21.5

55.9

46.5

ns
ns

335

HDRQ

Deasserted Hold from Data Strobe Deassertion

80 MHz: 2.5

+ 3.7

100 MHz: 2.5

+ 3.0

35.0

28.0 --

ns
ns

336

HDAK Assertion to Data Strobe Assertion

5.8

4.6

337

HDAK Asserted Hold from Data Strobe Deassertion

0.0

338

HDBEN Deasserted Hold from Data Strobe Assertion

2.5

2.0

339

HDBEN Assertion from Data Strobe Assertion

22.2

19.6

340

HDBEN Asserted Hold from Data Strobe Deassertion

2.5

2.0

341

HDBEN Deassertion from Data Strobe Deassertion

22.2

19.6

342

HDBDR High Hold from Read Data Strobe Assertion

2.5

2.0

343

HDBDR Low from Read Data Strobe Assertion

22.2

19.6

344

HDBDR Low Hold from Read Data Strobe Deassertion

2.5

2.0

345

HDBDR High from Read Data Strobe Deassertion

22.2

19.6

346

HRST Assertion to Host Port Pins High Impedance

22.2

19.6

Notes:

The Data Strobe is HRD or HWR in the Dual Data Strobe mode and HDS in the Single Data Strobe mode.

HTA, HDRQ, and HRST may be programmed as active-high or active-low. In the example timing diagrams, HDRQ and HRST
are shown as active-high and HTA is shown as active low.

The Read Data Strobe is HRD in the Dual Data Strobe mode and HDS in the Single Data Strobe mode.

The Write Data Strobe is HWR in the Dual Data Strobe mode and HDS in the Single Data Strobe mode.

HTA requires an external pull-down resistor if programmed as active high (HTAP = 0); or an external pull-up resistor if
programmed as active low (HTAP = 1). The resistor value should be consistent with the DC specifications.

HIRQ requires an external pull-up resistor if programmed as open drain (HIRD = 0). The resistor value should be consistent
with the DC specifications.

"LT" is the value of the latency timer register (CLAT) as programmed by the user during self configuration.
LT

Values are valid for V

= 3.3

0.3V

Table 2-18. Universal Bus Mode Timing Parameters (Continued)

No.

Characteristic

Expression

80 MHz

100 MHz

Unit

Min

Max

Min

Max

2-36

AC Electrical Characteristics

Table 2-19. Universal Bus Mode, Synchronous Port A Type Host Timing

No.

Characteristic

Expression

80 MHz

100 MHz

Unit

Min

Max

Min

Max

300

Access Cycle Time

37.5

30.0

301

HA[100], HAEN Setup to Data Strobe Assertion

5.8

4.6

302

HA[100], HAEN Valid Hold from Data Strobe Deassertion

0.0

305

Data Strobe Deasserted Width

4.1

3.3

307

HBS Asserted Pulse Width

2.5

2.0

308

HBS Assertion to Data Strobe Assertion

80 MHz: T

4.9

100 MHz: T

4.0

7.6

6.0

ns
ns

309

HBS Assertion to Data Strobe Deassertion

80 MHz: 2.5

+ 2.9

100 MHz: 2.5

+ 2.3

34.1

27.3

ns
ns

310

HBS Deassertion to Data Strobe Deassertion

80 MHz: 1.5

+ 3.3

100 MHz: 1.5

+ 2.6

22.1

17.6

ns
ns

312

Data Out Active from Read Data Strobe Assertion

1.7

1.3

313

Data Out Valid from Read Data Strobe Assertion
(No Wait States Inserted--HTA Asserted)

18.9

16.9

314

Data Out Valid Hold from Read Data Strobe Deassertion

1.7

1.3

315

Data Out High Impedance from Read Data Strobe Deassertion

12.0

9.6

316

Data In Valid Setup to Write Data Strobe Deassertion

8.3

6.6

317

Data In Valid Hold from Write Data Strobe Deassertion

0.0

324

HTA Assertion to Data Strobe Deassertion

1,2

0.0

325

HTA High Impedance from Data Strobe Deassertion

1,2

15.3

12.2

326

HIRQ Asserted Pulse Width (HIRH = 0, HIRD = 1)

(LT + 1)

6.0

6.5

4.0

327

Data Strobe Deasserted Hold from HIRQ Deassertion
(HIRH = 0)

0.0

328

HIRQ Asserted Hold from Data Strobe Assertion (HIRH = 1)

1.5

18.8

15.0

329

HIRQ Deassertion from Data Strobe Assertion
(HIRH = 1, HIRD = 1)

80 MHz: 2.5

+ 24.7

100 MHz: 2.5

+ 21.5

55.9

46.5

ns
ns

330

HIRQ High Impedance from Data Strobe Assertion
(HIRH = 1, HIRD = 0)

1,6

80 MHz: 2.5

+ 24.7

100 MHz: 2.5

+ 21.5

55.9

46.5

ns
ns

331

HIRQ Active from Data Strobe Deassertion
(HIRH = 1, HIRD = 0)

2.5

31.3

25.0

332

HIRQ Deasserted Hold from Data Strobe Deassertion

2.5

31.3

25.0

346

HRST Assertion to Host Port Pins High Impedance

22.2

19.6

347

HBS Assertion to CLKOUT Rising Edge

4.3

3.4

348

Data Strobe Deassertion to CLKOUT Rising Edge

7.4

5.9

Notes:

The Data Strobe is HRD or HWR in the Dual Data Strobe mode and HDS in the Single Data Strobe mode.

HTA, HDRQ, and HRST may be programmed as active-high or active-low. In the example timing diagrams, HDRQ and HRST
are shown as active-high and HTA is shown as active low.

The Read Data Strobe is HRD in the Dual Data Strobe mode and HDS in the Single Data Strobe mode.

The Write Data Strobe is HWR in the Dual Data Strobe mode and HDS in the Single Data Strobe mode.

HIRQ requires an external pull-up resistor if programmed as open drain (HIRD = 0). The resistor value should be consistent
with the DC specifications.

"LT" is the value of the latency timer register (CLAT) as programmed by the user during self configuration.

Values are valid for V

= 3.3

0.3V

2-40

AC Electrical Characteristics

Table 2-20. PCI Mode Timing Parameters

No.

Characteristic

Symbol

80 MHz

100 MHz

Unit

Min

Max

Min

Max

349

HCLK to Signal Valid Delay--Bussed Signals

VAL

2.0

11.0

2.0

11.0

350

HCLK to Signal Valid Delay--Point to Point

VAL(ptp)

2.0

12.0

2.0

12.0

351

Float to Active Delay

2.0

352

Active to Float Delay

OFF

28.0

353

Input Set Up Time to HCLK--Bussed Signals

7.0

354

Input Set Up Time to HCLK--Point to Point

SU(ptp)

10.0, 12.0

355

Input Hold Time from HCLK

0.0

356

Reset Active Time After Power Stable

RST

1.0

357

Reset Active Time After HCLK Stable

RST-CLK

100.0

358

Reset Active to Output Float Delay

RST-OFF

40.0

359

HCLK Cycle Time

CYC

30.0

360

HCLK High Time

HIGH

11.0

361

HCLK Low Time

LOW

11.0

Notes:

For standard PCI timing, see the

PCI Local Bus Specification

, Rev. 2.0, especially Chapters 3 and 4.

The HI32 supports these timings for a PCI bus operating at 33 MHz for a DSP clock frequency of 56 MHz and above. The DSP
core operating frequency should be greater than 5/3 of the PCI bus frequency to maintain proper PCI operation.

HGNT has a setup time of 10 ns. HREQ has a setup time of 12 ns.

Figure 2-36. PCI Timing

HCLK

OUTPUT

High

OUTPUT

INPUT

DELAY

359

361

349

360

351

352

355

350

353

354

Impedance

2-42

AC Electrical Characteristics

2.6.7 SCI Timing

Table 2-21. SCI Timing

No.

Characteristics

Symbol

Expression

80 MHz

100 MHz

Unit

Min

Max

Min

Max

400

Synchronous clock cycle

SCC

100.0

80.0

401

Clock low period

SCC

10.0

40.0

30.0

402

Clock high period

SCC

10.0

40.0

30.0

403

Output data setup to clock falling edge (internal
clock)

SCC

/4 + 0.5

17.0

14.3

8.0

404

Output data hold after clock rising edge (internal
clock)

SCC

0.5

18.8

15.0

405

Input data setup time before clock rising edge
(internal clock)

SCC

/4 + 0.5

+ 25.0

56.3

50.0

406

Input data not valid before clock rising edge
(internal clock)

SCC

/4 + 0.5

5.5

25.8

19.5

407

Clock falling edge to output data valid (external
clock)

32.0

408

Output data hold after clock rising edge
(external clock)

+ 8.0

20.5

18.0

409

Input data setup time before clock rising edge
(external clock)

0.0

410

Input data hold time after clock rising edge
(external clock)

9.0

411

Asynchronous clock cycle

ACC

800.0

640.0

412

Clock low period

ACC

10.0

390.0

310.0

413

Clock high period

ACC

10.0

390.0

310.0

414

Output data setup to clock rising edge (internal
clock)

ACC

30.0

370.0

290.0

415

Output data hold after clock rising edge
(internal clock)

ACC

30.0

370.0 --

290.0 --

Notes:

= 3.3 V

0.3 V; T

40°C to +100 °C, C

= 50 pF

SCC

= synchronous clock cycle time (For internal clock, t

SCC

is determined by the SCI clock control register and T

)

ACC

= asynchronous clock cycle time; value given for 1X Clock mode (For internal clock, t

ACC

is determined by the

SCI clock control register and T

)

2-44

AC Electrical Characteristics

2.6.8 ESSI0/ESSI1 Timing

Table 2-22. ESSI Timings

No.

Characteristics

4, 5, 7

Symbol

Expression

80 MHz

100 MHz

Cond-

ition

Unit

Min

Max

Min

Max

430

Clock cycle

SSICC

50.0
37.5

--
--

30.0
40.0

--
--

x ck

i ck

431

Clock high period
For internal clock
For external clock

10.0

1.5

15.0
18.8

--
--

10.0
15.0

--
--

ns
ns

432

Clock low period
For internal clock
For external clock

10.0

1.5

15.0
18.8

--
--

10.0
15.0

--
--

ns
ns

433

RXC rising edge to FSR out (bl) high

--
--

37.0
22.0

--
--

37.0
22.0

x ck

i ck a

434

RXC rising edge to FSR out (bl) low

--
--

37.0
22.0

--
--

37.0
22.0

x ck

i ck a

435

RXC rising edge to FSR out (wr) high

--
--

39.0
24.0

--
--

39.0
24.0

x ck

i ck a

436

RXC rising edge to FSR out (wr) low

--
--

39.0
24.0

--
--

39.0
24.0

x ck

i ck a

437

RXC rising edge to FSR out (wl) high

--
--

36.0
21.0

--
--

36.0
21.0

x ck

i ck a

438

RXC rising edge to FSR out (wl) low

--
--

37.0
22.0

--
--

37.0
22.0

x ck

i ck a

439

Data in setup time before RXC (SCK in
Synchronous mode) falling edge

10.0
19.0

--
--

10.0
19.0

--
--

x ck

i ck

440

Data in hold time after RXC falling edge

5.0
3.0

--
--

5.0
3.0

--
--

x ck

i ck

441

FSR input (bl, wr) high before RXC falling edge

1.0

23.0

--
--

1.0

23.0

--
--

x ck

i ck a

442

FSR input (wl) high before RXC falling edge

3.5

23.0

--
--

3.5

23.0

--
--

x ck

i ck a

443

FSR input hold time after RXC falling edge

3.0
0.0

--
--

3.0
0.0

--
--

x ck

i ck a

444

Flags input setup before RXC falling edge

5.5

19.0

--
--

5.5

19.0

--
--

x ck

i ck s

445

Flags input hold time after RXC falling edge

6.0
0.0

--
--

6.0
0.0

--
--

x ck

i ck s

446

TXC rising edge to FST out (bl) high

--
--

29.0
15.0

--
--

29.0
15.0

x ck

i ck

447

TXC rising edge to FST out (bl) low

--
--

31.0
17.0

--
--

31.0
17.0

x ck

i ck

448

TXC rising edge to FST out (wr) high

--
--

31.0
17.0

--
--

31.0
17.0

x ck

i ck

449

TXC rising edge to FST out (wr) low

--
--

33.0
19.0

--
--

33.0
19.0

x ck

i ck

450

TXC rising edge to FST out (wl) high

--
--

30.0
16.0

--
--

30.0
16.0

x ck

i ck

2-45

AC Electrical Characteristics

451

TXC rising edge to FST out (wl) low

--
--

31.0
17.0

--
--

31.0
17.0

x ck

i ck

452

TXC rising edge to data out enable from high
impedance

--
--

31.0
17.0

--
--

31.0
17.0

x ck

i ck

453

TXC rising edge to Transmitter #0 drive enable
assertion

--
--

34.0
20.0

--
--

34.0
20.0

x ck

i ck

454

TXC rising edge to data out valid

--
--

20.0
10.0

--
--

20.0
10.0

x ck

i ck

455

TXC rising edge to data out high impedance

--
--

31.0
16.0

--
--

31.0
16.0

x ck

i ck

456

TXC rising edge to Transmitter #0 drive enable
deassertion

--
--

34.0
20.0

--
--

34.0
20.0

x ck

i ck

457

FST input (bl, wr) setup time before TXC falling
edge

2.0

21.0

--
--

2.0

21.0

--
--

x ck

i ck

458

FST input (wl) to data out enable from high
impedance

27.0

459

FST input (wl) to Transmitter #0 drive enable
assertion

31.0

460

FST input (wl) setup time before TXC falling edge

2.5

21.0

--
--

2.5

21.0

--
--

x ck

i ck

461

FST input hold time after TXC falling edge

4.0
0.0

--
--

4.0
0.0

--
--

x ck

i ck

462

Flag output valid after TXC rising edge

--
--

32.0
18.0

--
--

32.0
18.0

x ck

i ck

Notes:

For the internal clock, the external clock cycle is defined by the instruction cycle time (timing 7 in Table 2-5 on page 2-6)
and the ESSI control register.

The word-relative frame sync signal waveform relative to the clock operates the same way as the bit-length frame sync
signal waveform, but spreads from one serial clock before the first bit clock (same as Bit Length Frame Sync signal), until
the one before the last bit clock of the first word in frame.

Periodically sampled and not 100 percent tested

= 3.3 V

0.3 V; T

40°C to +100 °C, C

= 50 pF

TXC (SCK Pin) = Transmit Clock
RXC (SC0 or SCK Pin) = Receive Clock
FST (SC2 Pin) = Transmit Frame Sync
FSR (SC1 or SC2 Pin) Receive Frame Sync

i ck = Internal Clock
x ck = External Clock
i ck a = Internal Clock, Asynchronous Mode

(Asynchronous implies that TXC and RXC are two different clocks)

i ck s = Internal Clock, Synchronous Mode

(Synchronous implies that TXC and RXC are the same clock)

bl = bit length
wl = word length
wr = word length relative

If the DSP core writes to the transmit register during the last cycle before causing an underrun error, the delay is 20 ns +
(0.5

Table 2-22. ESSI Timings (Continued)

No.

Characteristics

4, 5, 7

Symbol

Expression

80 MHz

100 MHz

Cond-

ition

Unit

Min

Max

Min

Max

2-48

AC Electrical Characteristics

2.6.9 Timer Timing

Table 2-23. Timer Timing

No.

Characteristics

Expression

80 MHz

100 MHz

Unit

Min

Max

Min

Max

480

TIO Low

+ 2.0

27.0

22.0

481

TIO High

+ 2.0

27.0

22.0

482

Timer setup time from TIO (Input) assertion to CLKOUT
rising edge

9.0

12.5

9.0

10.0

483

Synchronous timer delay time from CLKOUT rising edge to
the external memory access address out valid caused by
first interrupt instruction execution

10.25

+ 1.0

129.1

103.5

484

CLKOUT rising edge to TIO (Output) assertion
·

Minimum

Maximum

0.5

+ 0.5

0.5

+ 19.8

9.8

26.1

5.5

24.8

ns
ns

485

CLKOUT rising edge to TIO (Output) deassertion
·

Minimum

Maximum

0.5

+ 0.5

0.5

+ 19.8

9.8

26.1

5.5

24.8

ns
ns

Note:

= 3.3 V

0.3 V; T

40°C to +100 °C, C

= 50 pF

Figure 2-42. TIO Timer Event Input Restrictions

Figure 2-43. Timer Interrupt Generation

Figure 2-44. External Pulse Generation

TIO

481

480

CLKOUT

TIO (Input)

First Interrupt Instruction Execution

Address

482

483

CLKOUT

TIO (Output)

484

485

2-50

AC Electrical Characteristics

2.6.11 JTAG Timing

Table 2-25. JTAG Timing

No.

Characteristics

1,2

All frequencies

Unit

Min Max

500

TCK frequency of operation (1/(T

3); maximum 22 MHz)

0.0

22.0

MHz

501

TCK cycle time in Crystal mode

45.0

502

TCK clock pulse width measured at 1.5 V

20.0

503

TCK rise and fall times

0.0

3.0

504

Boundary scan input data setup time

5.0

505

Boundary scan input data hold time

24.0

506

TCK low to output data valid

0.0

40.0

507

TCK low to output high impedance

0.0

40.0

508

TMS, TDI data setup time

5.0

509

TMS, TDI data hold time

25.0

510

TCK low to TDO data valid

0.0

44.0

511

TCK low to TDO high impedance

0.0

44.0

512

TRST assert time

100.0

513

TRST setup time to TCK low

40.0

Notes:

= 3.3 V

0.3 V; T

40°C to +100 °C, C

= 50 pF

All timings apply to OnCE module data transfers because it uses the JTAG port as an interface.

Figure 2-46. Test Clock Input Timing Diagram

TCK

(Input)

501

502

503

3-2

TQFP Package Description

3.2 TQFP Package Description

Top and bottom views of the TQFP package are shown in Figure 3-1. and Figure 3-2. with their pin-outs.

Figure 3-1. DSP56301 Thin Quad Flat Pack (TQFP), Top View

I
T

SET

HC1

HCL

HRS

HRE

PAR

SER

PER

EVS

PVC

RDY

HIRDY

HIDS

HC2

HC3

157

(Top View)

Orientation Mark

105

NC
NC

HAD11
HAD10

HAD9
HAD8

HC0

HAD7
HAD6
HAD5
HAD4

GND

CCH

HAD3
HAD2
HAD1
HAD0

TIO2
TIO1
TIO0

RXD

SCLK

CCS

GND

HINTA

CCQ

GND

TXD

SC12
SC11
SC10
STD1

SCK1

SRD1
SRD0

SCK0

CCS

GND

STD0
SC00
SC01
SC02

TMS

TCK

TDI

TDO

TRST

NC
NC

NC
NC
MODB
MODA
D23
D22
D21
V

CCD

GND

D20
D19
D18
D17
D16
D15
V

CCD

GND

D14
D13
D12
D11
D10
D9
V

CCD

GND

CCQ

GND

D8
D7
D6
D5
D4
D3
V

CCD

GND

D2
D1
D0
A23
A22
V

CCA

GND

A21
A20
A19
A18
V

CCA

GND

A17
A16
NC
NC

3-3

TQFP Package Description

Figure 3-2. DSP56301 Thin Quad Flat Pack (TQFP), Bottom View

105

157

(Bottom View)

Orientation Mark

NC
NC
HAD11
HAD10
HAD9
HAD8
HC0
HAD7
HAD6
HAD5
HAD4
GND

CCH

HAD3
HAD2
HAD1
HAD0
TIO2
TIO1
TIO0
RXD
SCLK
V

CCS

GND

HINTA
V

CCQ

GND

TXD
SC12
SC11
SC10
STD1
SCK1
SRD1
SRD0
SCK0
V

CCS

GND

STD0
SC00
SC01
SC02
DE
TMS
TCK
TDI
TDO
TRST
BS
BL
NC
NC

NC
NC

MODB
MODA

D23
D22
D21

CCD

GND

D20
D19
D18
D17
D16
D15

CCD

GND

D14
D13
D12
D11
D10

CCD

GND

CCQ

GND

D8
D7
D6
D5
D4
D3

CCD

GND

D2
D1
D0

A23
A22

CCA

GND

A21
A20
A19
A18

CCA

GND

A17
A16

NC
NC

(On Top Side)

I
T

CCH

HC3

CCH

HC2

HIDS

CCQ

HIRDY

RDY

CCH

HRE

HRS

HCL

HC1

CCH

3-5

TQFP Package Description

101

MODA/IRQA

126

HAD17 or HD9

102

MODB/IRQB

127

HAD16 or HD8

GND

103

128

HC2/HBE2, HA2, or PB18

CCQ

104

129

HIDSEL or HRD/HDS

GND

105

MODC/IRQC

130

HFRAME

CCD

106

MODD/IRQD

131

CCQ

107

HAD31 or HD23

132

GND

D10

108

HAD30 or HD22

133

HIRDY, HDBDR, or PB21

D11

109

HAD29 or HD21

134

HTRDY, HDBEN, or PB20

D12

110

HAD28 or HD20

135

CCH

D13

111

CCH

136

GND

D14

112

GND

137

PVCL

GND

113

HAD27 or HD19

138

HDEVSEL, HSAK, or PB22

CCD

114

HAD26 or HD18

139

HSTOP or HWR/HRW

D15

115

HAD25 or HD17

140

HLOCK, HBS, or PB23

D16

116

HAD24 or HD16

141

HPERR or HDRQ

D17

117

HC3/HBE3 or PB19

142

HSERR or HIRQ

D18

118

HAD23 or HD15

143

GND

D19

119

HAD22 or HD14

144

CCH

D20

120

HAD21 or HD13

145

HPAR or HDAK

GND

121

HAD20 or HD12

146

HREQ or HTA

CCD

122

CCH

147

HRST or HRST

D21

123

GND

148

HCLK

D22

124

HAD19 or HD11

149

HGNT or HAEN

100

D23

125

HAD18 or HD10

150

HC1/HBE1, HA1, or PB17

Table 3-1. DSP56301 TQFP Signal Identification by Pin Number (Continued)

Pin
No.

Signal Name

Pin
No.

Signal Name

Pin
No.

Signal Name

3-6

TQFP Package Description

151

HAD15, HD7, or PB15

171

HAD2, HA5, or PB2

191

SRD0 or PC4

152

HAD14, HD6, or PB14

172

HAD1, HA4, or PB1

192

SCK0 or PC3

153

HAD13, HD5, or PB13

173

HAD0, HA3, or PB0

193

CCS

154

HAD12, HD4, or PB12

174

TIO2

194

GND

155

GND

175

TIO1

195

STD0 or PC5

156

CCH

176

TIO0

196

SC00 or PC0

157

177

RXD or PE0

197

SC01 or PC1

158

178

SCLK or PE2

198

SC02 or PC2

159

HAD11, HD3, or PB11

179

CCS

199

160

HAD10, HD2, or PB10

180

GND

200

TMS

161

HAD9, HD1, or PB9

181

HINTA

201

TCK

162

HAD8, HD0, or PB8

182

CCQ

202

TDI

163

HC0/HBE0, HA0, or PB16

183

GND

203

TDO

164

HAD7, HA10, or PB7

184

TXD or PE1

204

TRST

165

HAD6, HA9, or PB6

185

SC12 or PD2

205

166

HAD5, HA8, or PB5

186

SC11 or PD1

206

167

HAD4, HA7, or PB4

187

SC10 or PD0

207

168

GND

188

STD1 or PD5

208

169

CCH

189

SCK1 or PD3

170

HAD3, HA6, or PB3

190

SRD1 or PD4

Notes:

Signal names are based on configured functionality. Most pins supply a single signal. Some pins
provide a signal with dual functionality, such as the MODx/IRQx pins that select an operating mode
after RESET is deasserted, but act as interrupt lines during operation. Some pins have two or more
configurable functions; names assigned to these pins indicate the function for a specific configuration.
For example, Pin 165 is address/data line HAD6 in PCI bus mode, address line HA9 in non-PCI bus
mode, or GPIO line PB6 when the GPIO function is enabled for this pin.

NC stands for Not Connected. These pins are reserved for future development. Do not connect any
line, component, trace, or via to these pins.

Table 3-1. DSP56301 TQFP Signal Identification by Pin Number (Continued)

Pin
No.

Signal Name

Pin
No.

Signal Name

Pin
No.

Signal Name

3-11

TQFP Package Mechanical Drawing

3.3 TQFP Package Mechanical Drawing

Figure 3-3. DSP56301 Mechanical Information, 208-pin TQFP Package

Section AB-AB

rotated 90

clockwise

208 places

Plating

Base metal

0.08

T L-M N

104

105

156

157

208

L-M

0.2

L-M

0.2

4X 52 TIPS

Pin 1
ident

view Y

View AA

Seating

plane

208X

(2)

0.08

View AA

Gage

plane

2X R

0.25

(Z)

(W)

(K)

0.05

View Y

X= L, M or N

DIM

MIN

MAX

Millimeters

28.00 BSC

14.00 BSC

28.00 BSC

14.00 BSC

---

1.60

0.05

---

1.35

1.45

0.17

0.27

0.45

0.75

0.17

0.23

0.50 BSC

0.09

0.20

0.50 REF

0.25 BSC

0.10

0.20

30.00 BSC

15.00 BSC

0.09

0.16

30.00 REF

15.00 REF

0.20 REF

1.00 REF

0 ---

12 REF

1
2

CASE 998-01

Notes:

1. Dimensioning and tolerancing per ANSI

Y14.5M, 1982.

2. Controlling dimension: millimeter.
3. Datum plane-H- is located at bottom of

lead and is coincident with the lead

where the lead exits the plastic body at

the bottom of the parting line.

4. Datums -L-, -M-, and -N- to be

determined at datum plane -H-.

5. Dimensions S and V to be determined

at seating place -T-.

6. Dimensions A and B do not include

mold protrusion. Allowable protrusion

is 0.25 per side. Dimensions A and B

do include mold mismatch and are

determined at datum plane -H-.

7. Dimension d does not include dambar

protrusion. Dambar protrusion shall

not cause the lead width to exceed

0.35 minimum space between

protrusion and adjacent lead 0.07.

3-12

MAP-BGA Package Description

3.4 MAP-BGA Package Description

Top and bottom views of the MAP-BGA package are shown in Figure 3-4. and Figure 3-5. with their
pin-outs.

Figure 3-4. DSP56301 Molded Array Process-Ball Grid Array (MAP-BGA), Top View

CCP

CLK

OUT

Top View

RESET

BCLK

A13

GND

PCAP

A10

TDI

A17

TCK

A20

A16

A23

TMS

TDO

A21

SC00

A22

A19

STD0

GND

SC01

SC02

GND

SRD1

SCK1

GND

SRD0

SCK0

GND

STD1

SC12

GND

SC10

TXD

GND

SC11

D10

HINTA

GND

TI00

GND

SCLK

D13

D11

RXD

D14

GND

TI02

GND

D15

GND

TI01

D16

D12

HAD0

D17

GND

HAD3

GND

D19

GND

HAD1

D20

D18

HAD4

D21

HC0

HAD6

MODA

HAD2

D22

HAD7

D23

HAD10

HAD9

HAD28

HTRDY

HSTOP

PVCL

HAD5

MODB

MODC

HAD11

HAD18

HAD13

HAD12

HAD21

HAD26

HC3

HLOCK

HREQ

HC1

HAD8

MODD

HC2

HGNT

HAD14

HAD19

HAD31

HAD25

HAD22

HIDSEL

HDEV

HSERR

HRST

HAD29

HAD17

HCLK

HAD15

HAD20

HAD30

HAD24

HAD23

HAD16

HIRDY

HPERR

HPAR

HAD27

BCLK

CAS

AA1

A14

XTAL

AA2

A11

A18

EXTAL

AA0

A15

A12

AA3

GND

PINIT

TRST

SEL

FRAME

3-13

MAP-BGA Package Description

Figure 3-5. DSP56301 Molded Array Process-Ball Grid Array (MAP-BGA), Bottom View

CCP

CLK

OUT

Bottom View

RESET

BCLK

A13

GND

PCAP

A10

TDI

A17

TCK

A20

A16

A23

TMS

TDO

A21

SC00

A22

A19

STD0

GND

SC01

SC02

GND

SRD1

SCK1

GND

SRD0

SCK0

GND

STD1

SC12

GND

SC10

TXD

GND

SC11

D10

HINTA

GND

TI00

GND

SCLK

D13

D11

RXD

D14

GND

TI02

GND

D15

GND

TI01

D16

D12

HAD0

D17

GND

HAD3

GND

D19

GND

HAD1

D20

D18

HAD4

D21

HC0

HAD6

MODA

HAD2

D22

HAD7

D23

HAD10

HAD9

HAD28

HTRDY HSTOP

PVCL

HAD5

MODB

MODC

HAD11

HAD18

HAD13 HAD12

HAD21

HAD26

HC3

HLOCK HREQ

HC1

HAD8

MODD

HC2

HGNT HAD14

HAD19

HAD31

HAD25 HAD22

HIDSEL

HDEV

HSERR HRST

HAD29

HAD17

HCLK

HAD15

HAD20

HAD30

HAD24 HAD23

HAD16 HIRDY HPERR HPAR

HAD27

BLCK

CAS

AA1

A14

XTAL

AA2

A11

A18

EXTAL

AA0

A15

A12

AA3

GND

PINIT

TRST

SEL

FRAME

3-14

MAP-BGA Package Description

Table 3-3. DSP56301 MAP-BGA Signal Identification by Pin Number

Pin
No.

Signal Name

Pin
No.

Signal Name

Pin
No.

Signal Name

B12

HAD25 or HD17

HAD15, HD7, or PB15

B13

HAD29 or HD21

PVCL

HCLK

B14

HAD31 or HD23

HSTOP or HWR/HRW

HPAR or HDAK

B15

HTRDY, HDBEN, or PB20

HPERR or HDRQ

B16

HIRDY, HDBDR, or PB21

HAD8, HD0, or PB8

D10

HAD16 or HD8

HAD11, HD3, or PB11

D11

HAD17 or HD9

HAD12, HD4, or PB12

D12

HAD28 or HD20

A10

HAD20 or HD12

HAD13, HD5, or PB13

D13

MODC/IRQC

A11

HAD23 or HD15

HC1/HBE1, HA1, or PB17

D14

A12

HAD24 or HD16

HREQ or HTA

D15

MODB/IRQB

A13

HAD27 or HD19

HLOCK, HBS, or PB23

D16

D23

A14

HAD30 or HD22

HFRAME

HAD2, HA5, or PB2

A15

HAD18 or HD10

HAD4, HA7, or PB4

C10

HAD21 or HD13

HAD6, HA9, or PB6

C11

HC3/HBE3 or PB19

HC0/HBE0, HA0, or PB16

HAD14, HD6, or PB14

C12

HAD26 or HD18

HGNT or HAEN

C13

MODD/IRQD

HRST/HRST

C14

HSERR or HIRQ

C15

HDEVSEL, HSAK, or PB22

C16

HIDSEL or HRD/HDS

HAD5, HA8, or PB5

E10

HC2/HBE2, HA2, or PB18

HAD7, HA10, or PB7

E11

B10

HAD19 or HD11

HAD9, HD1, or PB9

E12

B11

HAD22 or HD14

HAD10, HD2, or PB10

E13

3-17

MAP-BGA Package Description

CAS

R13

A11

CCP

R14

A14

R15

AA2/RAS2

R16

T10

XTAL

T11

BCLK

T12

R10

RESET

T13

A10

R11

PCAP

T14

A13

R12

GND

T15

Notes:

Signal names are based on configured functionality. Most connections supply a single signal. Some
connections provide a signal with dual functionality, such as the MODx/IRQx pins that select an
operating mode after RESET is deasserted, but act as interrupt lines during operation. Some signals
have configurable polarity; these names are shown with and without overbars, such as HAS/HAS.
Some connections have two or more configurable functions; names assigned to these connections
indicate the function for a specific configuration. For example, connection N2 is data line H7 in
non-multiplexed bus mode, data/address line HAD7 in multiplexed bus mode, or GPIO line PB7 when
the GPIO function is enabled for this pin. Unlike the TQFP package, most of the GND pins are
connected internally in the center of the connection array and act as heat sink for the chip. Therefore,
except for GND

and GND

that support the PLL, other GND signals do not support individual

subsystems in the chip.

NC stands for Not Connected. The following pin groups are shorted to each other:
-- pins A2, B1, and B2
-- pins A15, B15, B16, C14, C15, C16, and D14
-- pins N3, R1, R2, and T2
-- pins N16, P13, P15, R15, R16, and T15
Do not connect any line, component, trace, or via to these pins.

Table 3-3. DSP56301 MAP-BGA Signal Identification by Pin Number (Continued)

Pin
No.

Signal Name

Pin
No.

Signal Name

Pin
No.

Signal Name

4-1

Chapter 4

Design
Considerations

4.1 Thermal Design Considerations

An estimate of the chip junction temperature, T

, in

C can be obtained from

this equation:

Equation 1:

Where:

ambient temperature °C

package junction-to-ambient thermal resistance °C/W

power dissipation in package

Historically, thermal resistance has been expressed as the sum of a
junction-to-case thermal resistance and a case-to-ambient thermal resistance,
as in this equation:

Equation 2:

Where:

package junction-to-ambient thermal resistance °C/W

package junction-to-case thermal resistance °C/W

package case-to-ambient thermal resistance °C/W

is device-related and cannot be influenced by the user. The user controls

the thermal environment to change the case-to-ambient thermal resistance,
R

. For example, the user can change the air flow around the device, add a

heat sink, change the mounting arrangement on the printed circuit board
(PCB) or otherwise change the thermal dissipation capability of the area
surrounding the device on a PCB. This model is most useful for ceramic
packages with heat sinks; some 90 percent of the heat flow is dissipated
through the case to the heat sink and out to the ambient environment. For
ceramic packages, in situations where the heat flow is split between a path to
the case and an alternate path through the PCB, analysis of the device thermal
performance may need the additional modeling capability of a system-level
thermal simulation tool.

The thermal performance of plastic packages is more dependent on the
temperature of the PCB to which the package is mounted. Again, if the
estimates obtained from R

do not satisfactorily answer whether the thermal

performance is adequate, a system-level model may be appropriate.

(

)

J A

4-2

Electrical Design Considerations

A complicating factor is the existence of three common ways to determine the junction-to-case thermal
resistance in plastic packages.

· To minimize temperature variation across the surface, the thermal resistance is measured from the

junction to the outside surface of the package (case) closest to the chip mounting area when that surface
has a proper heat sink.

· To define a value approximately equal to a junction-to-board thermal resistance, the thermal resistance

is measured from the junction to the point at which the leads attach to the case.

· If the temperature of the package case (T

) is determined by a thermocouple, thermal resistance is

computed from the value obtained by the equation (T

)/P

As noted earlier, the junction-to-case thermal resistances quoted in this data sheet are determined using
the first definition. From a practical standpoint, that value is also suitable to determine the junction
temperature from a case thermocouple reading in forced convection environments. In natural convection,
the use of the junction-to-case thermal resistance to estimate junction temperature from a thermocouple
reading on the case of the package will yield an estimate of a junction temperature slightly higher than
actual temperature. Hence, the new thermal metric, thermal characterization parameter or

, has been

defined to be (T

)/P

. This value gives a better estimate of the junction temperature in natural

convection when the surface temperature of the package is used. Remember that surface temperature
readings of packages are subject to significant errors caused by inadequate attachment of the sensor to the
surface and to errors caused by heat loss to the sensor. The recommended technique is to attach a
40-gauge thermocouple wire and bead to the top center of the package with thermally conductive epoxy.

4.2 Electrical Design Considerations

CAUTION

This device contains protective circuitry to
guard against damage due to high static
voltage or electrical fields. However, normal
precautions are advised to avoid application
of any voltages higher than maximum rated
voltages to this high-impedance circuit.
Reliability of operation is enhanced if unused
inputs are tied to an appropriate logic voltage
level (for example, either GND or V

4-3

Power Consumption Considerations

Use the following list of recommendations to ensure correct DSP operation.

· Provide a low-impedance path from the board power supply to each

pin on the DSP and from the

board ground to each

GND

pin.

· Use at least six 0.010.1

F bypass capacitors positioned as close as possible to the four sides of the

package to connect the

power source to

GND

· Ensure that capacitor leads and associated printed circuit traces that connect to the chip

and

GND

pins are less than 0.5 inch per capacitor lead.

· Use at least a four-layer PCB with two inner layers for

and

GND

· Because the DSP output signals have fast rise and fall times, PCB trace lengths should be minimal.

This recommendation particularly applies to the address and data buses as well as the

IRQA

IRQB

IRQC

IRQD

, and

pins. Maximum PCB trace lengths on the order of 6 inches are recommended.

· Consider all device loads as well as parasitic capacitance due to PCB traces when you calculate

capacitance. This is especially critical in systems with higher capacitive loads that could create higher
transient currents in the

and

GND

circuits.

· All inputs must be terminated (that is, not allowed to float) by CMOS levels except for the three pins

with internal pull-up resistors (

TRST

TMS

· Take special care to minimize noise levels on the

CCP

GND

, and

GND

pins.

· The following pins must be asserted after power-up:

RESET

and

TRST

· If multiple DSP devices are on the same board, check for cross-talk or excessive spikes on the supplies

due to synchronous operation of the devices.

RESET

must be asserted when the chip is powered up. A stable

EXTAL

signal should be supplied

before deassertion of

RESET

· At power-up, ensure that the voltage difference between the 5 V tolerant pins and the chip V

never

exceeds 3.5 V.

4.3 Power Consumption Considerations

Power dissipation is a key issue in portable DSP applications. Some of the factors affecting current
consumption are described in this section. Most of the current consumed by CMOS devices is alternating
current (ac), which is charging and discharging the capacitances of the pins and internal nodes.

Current consumption is described by this formula:

Equation 3:

Where:

C =

node/pin

capacitance

voltage swing

frequency of node/pin toggle

Equation 4:

The maximum internal current (I

CCI

max) value reflects the typical possible switching of the internal

buses on best-case operation conditions--not necessarily a real application case. The typical internal
current (I

CCItyp

) value reflects the average switching of the internal buses on typical operating conditions.

Example 4-1. Current Consumption

For a Port A address pin loaded with 50 pF capacitance, operating at 3.3 V, with a 66 MHz clock, toggling at its
maximum possible rate (33 MHz), the current consumption is expressed in Equation 4.

3.3

5.48 mA

4-4

PLL Performance Issues

Perform the following steps for applications that require very low current consumption:

Set the EBD bit when you are not accessing external memory.

Minimize external memory accesses, and use internal memory accesses.

Minimize the number of pins that are switching.

Minimize the capacitive load on the pins.

Connect the unused inputs to pull-up or pull-down resistors.

Disable unused peripherals.

Disable unused pin activity (for example, CLKOUT, XTAL).

One way to evaluate power consumption is to use a current-per-MIPS measurement methodology to
minimize specific board effects (that is, to compensate for measured board current not caused by the
DSP). A benchmark power consumption test algorithm is listed in Appendix A. Use the test algorithm,
specific test current measurements, and the following equation to derive the current-per-MIPS value.

Equation 5:

Where:

typF2

current at F2

typF1

current at F1

high frequency (any specified operating frequency)

low frequency (any specified operating frequency lower than F2)

Note:

F1 should be significantly less than F2. For example, F2 could be 66 MHz and F1 could be 33
MHz. The degree of difference between F1 and F2 determines the amount of precision with
which the current rating can be determined for an application.

4.4 PLL Performance Issues

The following explanations should be considered as general observations on expected PLL behavior.
There is no test that replicates these exact numbers. These observations were measured on a limited
number of parts and were not verified over the entire temperature and voltage ranges.

4.4.1 Phase Skew Performance

The phase skew of the PLL is defined as the time difference between the falling edges of EXTAL and
CLKOUT for a given capacitive load on CLKOUT, over the entire process, temperature and voltage
ranges. As defined in Figure 2-2, External Clock Timing, on page 2-5 for input frequencies greater than
15 MHz and the MF

4, this skew is greater than or equal to 0.0 ns and less than 1.8 ns; otherwise, this

skew is not guaranteed. However, for MF < 10 and input frequencies greater than 10 MHz, this skew is
between

1.4 ns and +3.2 ns.

4.4.2 Phase Jitter Performance

The phase jitter of the PLL is defined as the variations in the skew between the falling edges of EXTAL
and CLKOUT for a given device in specific temperature, voltage, input frequency, MF, and capacitive
load on CLKOUT. These variations are a result of the PLL locking mechanism. For input frequencies
greater than 15 MHz and MF

4, this jitter is less than

0.6 ns; otherwise, this jitter is not guaranteed.

However, for MF < 10 and input frequencies greater than 10 MHz, this jitter is less than

2 ns.

I MIPS

I MHz

typF2

typF1

(

)

(

)

A-1

Appendix A

Power
Consumption
Benchmark

The following benchmark program permits evaluation of DSP power usage in a test situation. It enables
the PLL, disables the external clock, and uses repeated multiply-accumulate (MAC) instructions with a
set of synthetic DSP application data to emulate intensive sustained DSP operation.

;**************************************************************************
;**************************************************************************
;*

;* CHECKS Typical Power Consumption

;* *
;**************************************************************************

page

200,55,0,0,0

nolist

I_VEC EQU$000000; Interrupt vectors for program debug only
START EQU$8000 ; MAIN (external) program starting address
INT_PROG EQU$100 ; INTERNAL program memory starting address
INT_XDAT EQU$0 ; INTERNAL X-data memory starting address
INT_YDAT EQU$0 ; INTERNAL Y-data memory starting address

INCLUDE "ioequ.asm"
INCLUDE "intequ.asm"

list

org

P:START

;

movep #$0123FF,x:M_BCR; BCR: Area 3 : 1 w.s (SRAM)

; Area 2 : 0 w.s (SSRAM)
; Default: 1 w.s (SRAM)
;

movep

#$0d0000,x:M_PCTL; XTAL disable

; PLL enable
; CLKOUT disable
;
;Load the program
;

move

#INT_PROG,r0

move

#PROG_START,r1

#(PROG_END-PROG_START),PLOAD_LOOP

move

p:(r1)+,x0

move

x0,p:(r0)+

nop

PLOAD_LOOP
;
; Load the X-data
;

move

#INT_XDAT,r0

move

#XDAT_START,r1

#(XDAT_END-XDAT_START),XLOAD_LOOP

move

p:(r1)+,x0

move

x0,x:(r0)+

XLOAD_LOOP
;
;Load the Y-data
;

move

#INT_YDAT,r0

move

#YDAT_START,r1

#(YDAT_END-YDAT_START),YLOAD_LOOP

move

p:(r1)+,x0

move

x0,y:(r0)+

YLOAD_LOOP
;

jmp

INT_PROG

PROG_START

move

#$0,r0

move

#$0,r4

move

#$3f,m0

move

#$3f,m4

;

A-4

Power Consumption Benchmark

;
;

EQUATES for DSP56301 I/O registers and ports

;

Reference: DSP56301 Specifications Revision 3.00

;
;

Last update:

November 15 1993

; Changes:

GPIO for ports C,D and E,

;

HI32

;

DMA status reg

;

PLL control reg

;

AAR

;

SCI registers address

;

SSI registers addr. + split TSR from SSISR

;

December 19 1993 (cosmetic - page and opt directives)

;

August 9 1994 ESSI and SCI control registers bit update

;
;**************************************************************************

page

132,55,0,0,0

opt

mex

ioequ ident 1,0

;------------------------------------------------------------------------
;
; EQUATES for I/O Port Programming
;
;------------------------------------------------------------------------

; Register Addresses

M_DATH EQU $FFFFCF ; Host port GPIO data Register
M_DIRH EQU $FFFFCE; Host port GPIO direction Register
M_PCRC EQU $FFFFBF; Port C Control Register
M_PRRC EQU $FFFFBE; Port C Direction Register
M_PDRC EQU $FFFFBD ; Port C GPIO Data Register
M_PCRD EQU $FFFFAF ; Port D Control register
M_PRRD EQU $FFFFAE ; Port D Direction Data Register
M_PDRD EQU $FFFFAD; Port D GPIO Data Register
M_PCRE EQU $FFFF9F; Port E Control register
M_PRRE EQU $FFFF9E; Port E Direction Register
M_PDRE EQU $FFFF9D; Port E Data Register
M_OGDB EQU $FFFFFC; OnCE GDB Register

;------------------------------------------------------------------------
;
; EQUATES for Host Interface
;
;------------------------------------------------------------------------

; Register Addresses

M_DTXS EQU $FFFFCD ; DSP SLAVE TRANSMIT DATA FIFO (DTXS)
M_DTXM EQU $FFFFCC; DSP MASTER TRANSMIT DATA FIFO (DTXM)
M_DRXR EQU $FFFFCB; DSP RECEIVE DATA FIFO (DRXR)
M_DPSR EQU $FFFFCA; DSP PCI STATUS REGISTER (DPSR)
M_DSR EQU $FFFFC9; DSP STATUS REGISTER (DSR)
M_DPAR EQU $FFFFC8; DSP PCI ADDRESS REGISTER (DPAR)
M_DPMC EQU $FFFFC7; DSP PCI MASTER CONTROL REGISTER (DPMC)
M_DPCR EQU $FFFFC6; DSP PCI CONTROL REGISTER (DPCR)
M_DCTR EQU $FFFFC5 ; DSP CONTROL REGISTER (DCTR)

; Host Control Register Bit Flags

M_HCIE EQU 0

; Host Command Interrupt Enable

M_STIE EQU 1

; Slave Transmit Interrupt Enable

M_SRIE EQU 2

; Slave Receive Interrupt Enable

M_HF35 EQU $38 ; Host Flags 5-3 Mask
M_HF3 EQU 3

; Host Flag 3

M_HF4 EQU 4

; Host Flag 4

M_HF5 EQU 5

; Host Flag 5

M_HINT EQU 6

; Host Interrupt A

M_HDSM EQU 13

; Host Data Strobe Mode

M_HRWP EQU 14

; Host RD/WR Polarity

M_HTAP EQU 15 ; Host Transfer Acknowledge Polarity
M_HDRP EQU 16

; Host Dma Request Polarity

M_HRSP EQU 17

; Host Reset Polarity

M_HIRP EQU 18

; Host Interrupt Request Polarity

M_HIRC EQU 19

; Host Interupt Request Control

M_HM0 EQU 20

; Host Interface Mode

M_HM1 EQU 21

; Host Interface Mode

A-5

Power Consumption Benchmark

M_HM2 EQU 22

; Host Interface Mode

M_HM EQU $700000 ; Host Interface Mode Mask

; Host PCI Control Register Bit Flags

M_PMTIE EQU 1

; PCI Master Transmit Interrupt Enable

M_PMRIE EQU 2 ; PCI Master Receive Interrupt Enable
M_PMAIE EQU 4 ; PCI Master Address Interrupt Enable
M_PPEIE EQU 5

; PCI Parity Error Interrupt Enable

M_PTAIE EQU 7

; PCI Transaction Abort Interrupt Enable

M_PTTIE EQU 9 ; PCI Transaction Termination Interrupt Enable
M_PTCIE EQU 12 ; PCI Transfer Complete Interrupt Enable
M_CLRT EQU 14

; Clear Transmitter

M_MTT EQU 15

; Master Transfer Terminate

M_SERF EQU 16

; HSERR~ Force

M_MACE EQU 18 ; Master Access Counter Enable
M_MWSD EQU 19

; Master Wait States Disable

M_RBLE EQU 20 ; Receive Buffer Lock Enable
M_IAE EQU 21

; Insert Address Enable

; Host PCI Master Control Register Bit Flags

M_ARH EQU $00ffff; DSP PCI Transaction Address (High)
M_BL EQU $3f0000; PCI Data Burst Length
M_FC EQU $c00000; Data Transfer Format Control

; Host PCI Address Register Bit Flags

M_ARL EQU $00ffff; DSP PCI Transaction Address (Low)
M_C EQU $0f0000; PCI Bus Command
M_BE EQU $f00000; PCI Byte Enables

; DSP Status Register Bit Flags

M_HCP EQU 0

; Host Command pending

M_STRQ EQU 1

; Slave Transmit Data Request

M_SRRQ EQU 2

; Slave Receive Data Request

M_HF02 EQU $38 ; Host Flag 0-2 Mask
M_HF0 EQU 3

; Host Flag 0

M_HF1 EQU 4

; Host Flag 1

M_HF2 EQU 5

; Host Flag 2

; DSP PCI Status Register Bit Flags

M_MWS EQU 0

; PCI Master Wait States

M_MTRQ EQU 1

; PCI Master Transmit Data Request

M_MRRQ EQU 2

; PCI Master Receive Data Request

M_MARQ EQU 4

; PCI Master Address Request

M_APER EQU 5 ; PCI Address Parity Error
M_DPER EQU 6 ; PCI Data Parity Error
M_MAB EQU 7 ; PCI Master Abort
M_TAB EQU 8 ; PCI Target Abort
M_TDIS EQU 9 ; PCI Target Disconnect
M_TRTY EQU 10 ; PCI Target Retry
M_TO EQU 11 ; PCI Time Out Termination
M_RDC EQU $3F0000; Remaining Data Count Mask (RDC5-RDC0)
M_RDC0 EQU 16 ; Remaining Data Count 0
M_RDC1 EQU 17 ; Remaining Data Count 1
M_RDC2 EQU 18 ; Remaining Data Count 2
M_RDC3 EQU 19 ; Remaining Data Count 3
M_RDC4 EQU 20 ; Remaining Data Count 4
M_RDC5 EQU 21 ; Remaining Data Count 5
M_HACT EQU 23 ; Hi32 Active

;------------------------------------------------------------------------
;
; EQUATES for Serial Communications Interface (SCI)
;
;------------------------------------------------------------------------

; Register Addresses

M_STXH EQU $FFFF97; SCI Transmit Data Register (high)
M_STXM EQU $FFFF96; SCI Transmit Data Register (middle)
M_STXL EQU $FFFF95; SCI Transmit Data Register (low)
M_SRXH EQU $FFFF9A; SCI Receive Data Register (high)
M_SRXM EQU $FFFF99; SCI Receive Data Register (middle)
M_SRXL EQU $FFFF98; SCI Receive Data Register (low)
M_STXA EQU $FFFF94; SCI Transmit Address Register
M_SCR EQU $FFFF9C; SCI Control Register

A-6

Power Consumption Benchmark

M_SSR EQU $FFFF93; SCI Status Register
M_SCCR EQU $FFFF9B; SCI Clock Control Register

; SCI Control Register Bit Flags

M_WDS EQU $7 ; Word Select Mask (WDS0-WDS3)
M_WDS0 EQU 0 ; Word Select 0
M_WDS1 EQU 1 ; Word Select 1
M_WDS2 EQU 2 ; Word Select 2
M_SSFTD EQU 3 ; SCI Shift Direction
M_SBK EQU 4 ; Send Break
M_WAKE EQU 5 ; Wakeup Mode Select
M_RWU EQU 6 ; Receiver Wakeup Enable
M_WOMS EQU 7 ; Wired-OR Mode Select
M_SCRE EQU 8 ; SCI Receiver Enable
M_SCTE EQU 9 ; SCI Transmitter Enable
M_ILIE EQU 10 ; Idle Line Interrupt Enable
M_SCRIE EQU 11 ; SCI Receive Interrupt Enable
M_SCTIE EQU 12 ; SCI Transmit Interrupt Enable
M_TMIE EQU 13 ; Timer Interrupt Enable
M_TIR EQU 14 ; Timer Interrupt Rate
M_SCKP EQU 15 ; SCI Clock Polarity
M_REIE EQU 16 ; SCI Error Interrupt Enable (REIE)

; SCI Status Register Bit Flags

M_TRNE EQU 0 ; Transmitter Empty
M_TDRE EQU 1 ; Transmit Data Register Empty
M_RDRF EQU 2 ; Receive Data Register Full
M_IDLE EQU 3 ; Idle Line Flag
M_OR EQU 4 ; Overrun Error Flag
M_PE EQU 5 ; Parity Error
M_FE EQU 6 ; Framing Error Flag
M_R8 EQU 7 ; Received Bit 8 (R8) Address

; SCI Clock Control Register

M_CD EQU $FFF ; Clock Divider Mask (CD0-CD11)
M_COD EQU 12 ; Clock Out Divider
M_SCP EQU 13 ; Clock Prescaler
M_RCM EQU 14 ; Receive Clock Mode Source Bit
M_TCM EQU 15 ; Transmit Clock Source Bit

;------------------------------------------------------------------------
;
; EQUATES for Synchronous Serial Interface (SSI)
;
;------------------------------------------------------------------------

;
; Register Addresses Of SSI0
M_TX00 EQU $FFFFBC; SSI0 Transmit Data Register 0
M_TX01 EQU $FFFFBB; SSIO Transmit Data Register 1
M_TX02 EQU $FFFFBA; SSIO Transmit Data Register 2
M_TSR0 EQU $FFFFB9; SSI0 Time Slot Register
M_RX0 EQU $FFFFB8; SSI0 Receive Data Register
M_SSISR0 EQU $FFFFB7; SSI0 Status Register
M_CRB0 EQU $FFFFB6; SSI0 Control Register B
M_CRA0 EQU $FFFFB5; SSI0 Control Register A
M_TSMA0 EQU $FFFFB4; SSI0 Transmit Slot Mask Register A
M_TSMB0 EQU $FFFFB3; SSI0 Transmit Slot Mask Register B
M_RSMA0 EQU $FFFFB2; SSI0 Receive Slot Mask Register A
M_RSMB0 EQU $FFFFB1; SSI0 Receive Slot Mask Register B

; Register Addresses Of SSI1
M_TX10 EQU $FFFFAC; SSI1 Transmit Data Register 0
M_TX11 EQU $FFFFAB; SSI1 Transmit Data Register 1
M_TX12 EQU $FFFFAA; SSI1 Transmit Data Register 2
M_TSR1 EQU $FFFFA9; SSI1 Time Slot Register
M_RX1 EQU $FFFFA8; SSI1 Receive Data Register
M_SSISR1 EQU $FFFFA7; SSI1 Status Register
M_CRB1 EQU $FFFFA6; SSI1 Control Register B
M_CRA1 EQU $FFFFA5; SSI1 Control Register A
M_TSMA1 EQU $FFFFA4; SSI1 Transmit Slot Mask Register A
M_TSMB1 EQU $FFFFA3; SSI1 Transmit Slot Mask Register B
M_RSMA1 EQU $FFFFA2; SSI1 Receive Slot Mask Register A
M_RSMB1 EQU $FFFFA1; SSI1 Receive Slot Mask Register B

; SSI Control Register A Bit Flags

M_PM EQU $FF ; Prescale Modulus Select Mask (PM0-PM7)

A-7

Power Consumption Benchmark

M_PSR EQU 11 ; Prescaler Range
M_DC EQU $1F000 ; Frame Rate Divider Control Mask (DC0-DC7)
M_ALC EQU 18

; Alignment Control (ALC)

M_WL EQU $380000; Word Length Control Mask (WL0-WL7)
M_SSC1 EQU 22

; Select SC1 as TR #0 drive enable (SSC1)

; SSI Control Register B Bit Flags

M_OF EQU $3

; Serial Output Flag Mask

M_OF0 EQU 0

; Serial Output Flag 0

M_OF1 EQU 1

; Serial Output Flag 1

M_SCD EQU $1C

; Serial Control Direction Mask

M_SCD0 EQU 2

; Serial Control 0 Direction

M_SCD1 EQU 3 ; Serial Control 1 Direction
M_SCD2 EQU 4 ; Serial Control 2 Direction
M_SCKD EQU 5 ; Clock Source Direction
M_SHFD EQU 6 ; Shift Direction
M_FSL EQU $180 ; Frame Sync Length Mask (FSL0-FSL1)
M_FSL0 EQU 7

; Frame Sync Length 0

M_FSL1 EQU 8

; Frame Sync Length 1

M_FSR EQU 9

; Frame Sync Relative Timing

M_FSP EQU 10

; Frame Sync Polarity

M_CKP EQU 11

; Clock Polarity

M_SYN EQU 12

; Sync/Async Control

M_MOD EQU 13

; SSI Mode Select

M_SSTE EQU $1C000; SSI Transmit enable Mask
M_SSTE2 EQU 14 ; SSI Transmit #2 Enable
M_SSTE1 EQU 15 ; SSI Transmit #1 Enable
M_SSTE0 EQU 16 ; SSI Transmit #0 Enable
M_SSRE EQU 17 ; SSI Receive Enable
M_SSTIE EQU 18 ; SSI Transmit Interrupt Enable
M_SSRIE EQU 19 ; SSI Receive Interrupt Enable
M_STLIE EQU 20 ; SSI Transmit Last Slot Interrupt Enable
M_SRLIE EQU 21 ; SSI Receive Last Slot Interrupt Enable
M_STEIE EQU 22 ; SSI Transmit Error Interrupt Enable
M_SREIE EQU 23 ; SSI Receive Error Interrupt Enable

; SSI Status Register Bit Flags

M_IF EQU $3 ; Serial Input Flag Mask
M_IF0 EQU 0 ; Serial Input Flag 0
M_IF1 EQU 1 ; Serial Input Flag 1
M_TFS EQU 2 ; Transmit Frame Sync Flag
M_RFS EQU 3 ; Receive Frame Sync Flag
M_TUE EQU 4 ; Transmitter Underrun Error FLag
M_ROE EQU 5 ; Receiver Overrun Error Flag
M_TDE EQU 6 ; Transmit Data Register Empty
M_RDF EQU 7 ; Receive Data Register Full

; SSI Transmit Slot Mask Register A

M_SSTSA EQU $FFFF ; SSI Transmit Slot Bits Mask A (TS0-TS15)

; SSI Transmit Slot Mask Register B

M_SSTSB EQU $FFFF ; SSI Transmit Slot Bits Mask B (TS16-TS31)

; SSI Receive Slot Mask Register A

M_SSRSA EQU $FFFF ; SSI Receive Slot Bits Mask A (RS0-RS15)

; SSI Receive Slot Mask Register B

M_SSRSB EQU $FFFF ; SSI Receive Slot Bits Mask B (RS16-RS31)

;------------------------------------------------------------------------
;
; EQUATES for Exception Processing
;
;------------------------------------------------------------------------

; Register Addresses

M_IPRC EQU $FFFFFF; Interrupt Priority Register Core
M_IPRP EQU $FFFFFE; Interrupt Priority Register Peripheral

; Interrupt Priority Register Core (IPRC)

A-8

Power Consumption Benchmark

M_IAL EQU $7 ; IRQA Mode Mask
M_IAL0 EQU 0 ; IRQA Mode Interrupt Priority Level (low)
M_IAL1 EQU 1 ; IRQA Mode Interrupt Priority Level (high)
M_IAL2 EQU 2 ; IRQA Mode Trigger Mode
M_IBL EQU $38 ; IRQB Mode Mask
M_IBL0 EQU 3 ; IRQB Mode Interrupt Priority Level (low)
M_IBL1 EQU 4 ; IRQB Mode Interrupt Priority Level (high)
M_IBL2 EQU 5 ; IRQB Mode Trigger Mode
M_ICL EQU $1C0 ; IRQC Mode Mask
M_ICL0 EQU 6 ; IRQC Mode Interrupt Priority Level (low)
M_ICL1 EQU 7 ; IRQC Mode Interrupt Priority Level (high)
M_ICL2 EQU 8 ; IRQC Mode Trigger Mode
M_IDL EQU $E00 ; IRQD Mode Mask
M_IDL0 EQU 9 ; IRQD Mode Interrupt Priority Level (low)
M_IDL1 EQU 10 ; IRQD Mode Interrupt Priority Level (high)
M_IDL2 EQU 11 ; IRQD Mode Trigger Mode
M_D0L EQU $3000 ; DMA0 Interrupt priority Level Mask
M_D0L0 EQU 12 ; DMA0 Interrupt Priority Level (low)
M_D0L1 EQU 13 ; DMA0 Interrupt Priority Level (high)
M_D1L EQU $C000 ; DMA1 Interrupt Priority Level Mask
M_D1L0 EQU 14 ; DMA1 Interrupt Priority Level (low)
M_D1L1 EQU 15 ; DMA1 Interrupt Priority Level (high)
M_D2L EQU $30000 ; DMA2 Interrupt priority Level Mask
M_D2L0 EQU 16 ; DMA2 Interrupt Priority Level (low)
M_D2L1 EQU 17 ; DMA2 Interrupt Priority Level (high)
M_D3L EQU $C0000 ; DMA3 Interrupt Priority Level Mask
M_D3L0 EQU 18 ; DMA3 Interrupt Priority Level (low)
M_D3L1 EQU 19 ; DMA3 Interrupt Priority Level (high)
M_D4L EQU $300000; DMA4 Interrupt priority Level Mask
M_D4L0 EQU 20 ; DMA4 Interrupt Priority Level (low)
M_D4L1 EQU 21 ; DMA4 Interrupt Priority Level (high)
M_D5L EQU $C00000; DMA5 Interrupt priority Level Mask
M_D5L0 EQU 22 ; DMA5 Interrupt Priority Level (low)
M_D5L1 EQU 23 ; DMA5 Interrupt Priority Level (high)

; Interrupt Priority Register Peripheral (IPRP)

M_HPL EQU $3 ; Host Interrupt Priority Level Mask
M_HPL0 EQU 0 ; Host Interrupt Priority Level (low)
M_HPL1 EQU 1 ; Host Interrupt Priority Level (high)
M_S0L EQU $C ; SSI0 Interrupt Priority Level Mask
M_S0L0 EQU 2 ; SSI0 Interrupt Priority Level (low)
M_S0L1 EQU 3 ; SSI0 Interrupt Priority Level (high)
M_S1L EQU $30 ; SSI1 Interrupt Priority Level Mask
M_S1L0 EQU 4 ; SSI1 Interrupt Priority Level (low)
M_S1L1 EQU 5 ; SSI1 Interrupt Priority Level (high)
M_SCL EQU $C0 ; SCI Interrupt Priority Level Mask
M_SCL0 EQU 6 ; SCI Interrupt Priority Level (low)
M_SCL1 EQU 7 ; SCI Interrupt Priority Level (high)
M_T0L EQU $300 ; TIMER Interrupt Priority Level Mask
M_T0L0 EQU 8 ; TIMER Interrupt Priority Level (low)
M_T0L1 EQU 9 ; TIMER Interrupt Priority Level (high)

;------------------------------------------------------------------------
;
; EQUATES for TIMER
;
;------------------------------------------------------------------------

; Register Addresses Of TIMER0

M_TCSR0 EQU $FFFF8F; TIMER0 Control/Status Register
M_TLR0 EQU $FFFF8E; TIMER0 Load Reg
M_TCPR0 EQU $FFFF8D; TIMER0 Compare Register
M_TCR0 EQU $FFFF8C ; TIMER0 Count Register

; Register Addresses Of TIMER1

M_TCSR1 EQU $FFFF8B; TIMER1 Control/Status Register
M_TLR1 EQU $FFFF8A; TIMER1 Load Reg
M_TCPR1 EQU $FFFF89; TIMER1 Compare Register
M_TCR1 EQU $FFFF88; TIMER1 Count Register

; Register Addresses Of TIMER2

M_TCSR2 EQU $FFFF87; TIMER2 Control/Status Register
M_TLR2 EQU $FFFF8; TIMER2 Load Reg

A-9

Power Consumption Benchmark

M_TCPR2 EQU $FFFF85; TIMER2 Compare Register
M_TCR2 EQU $FFFF84 ; TIMER2 Count Register
M_TPLR EQU $FFFF83 ; TIMER Prescaler Load Register
M_TPCR EQU $FFFF82 ; TIMER Prescalar Count Register

; Timer Control/Status Register Bit Flags

M_TE EQU 0 ; Timer Enable
M_TOIE EQU 1 ; Timer Overflow Interrupt Enable
M_TCIE EQU 2 ; Timer Compare Interrupt Enable
M_TC EQU $F0 ; Timer Control Mask (TC0-TC3)
M_INV EQU 8 ; Inverter Bit
M_TRM EQU 9 ; Timer Restart Mode
M_DIR EQU 11 ; Direction Bit
M_DI EQU 12 ; Data Input
M_DO EQU 13 ; Data Output
M_PCE EQU 15

; Prescaled Clock Enable

M_TOF EQU 20 ; Timer Overflow Flag
M_TCF EQU 21 ; Timer Compare Flag

; Timer Prescaler Register Bit Flags

M_PS EQU $600000 ; Prescaler Source Mask
M_PS0 EQU 21
M_PS1 EQU 22

;

Timer Control Bits

M_TC0 EQU 4 ; Timer Control 0
M_TC1 EQU 5 ; Timer Control 1
M_TC2 EQU 6 ; Timer Control 2
M_TC3 EQU 7 ; Timer Control 3

;------------------------------------------------------------------------
;
; EQUATES for Direct Memory Access (DMA)
;
;------------------------------------------------------------------------

; Register Addresses Of DMA
M_DSTR EQU $FFFFF4; DMA Status Register
M_DOR0 EQU $FFFFF3; DMA Offset Register 0
M_DOR1 EQU $FFFFF2; DMA Offset Register 1
M_DOR2 EQU $FFFFF1; DMA Offset Register 2
M_DOR3 EQU $FFFFF0; DMA Offset Register 3

; Register Addresses Of DMA0

M_DSR0 EQU $FFFFEF; DMA0 Source Address Register
M_DDR0 EQU $FFFFEE; DMA0 Destination Address Register
M_DCO0 EQU $FFFFED; DMA0 Counter
M_DCR0 EQU $FFFFEC; DMA0 Control Register

; Register Addresses Of DMA1

M_DSR1 EQU $FFFFEB; DMA1 Source Address Register
M_DDR1 EQU $FFFFEA; DMA1 Destination Address Register
M_DCO1 EQU $FFFFE9; DMA1 Counter
M_DCR1 EQU $FFFFE8; DMA1 Control Register

; Register Addresses Of DMA2

M_DSR2 EQU $FFFFE7; DMA2 Source Address Register
M_DDR2 EQU $FFFFE6; DMA2 Destination Address Register
M_DCO2 EQU $FFFFE5; DMA2 Counter
M_DCR2 EQU $FFFFE4; DMA2 Control Register

; Register Addresses Of DMA4

M_DSR3 EQU $FFFFE3; DMA3 Source Address Register
M_DDR3 EQU $FFFFE2; DMA3 Destination Address Register
M_DCO3 EQU $FFFFE1; DMA3 Counter
M_DCR3 EQU $FFFFE0; DMA3 Control Register

; Register Addresses Of DMA4

M_DSR4 EQU $FFFFDF; DMA4 Source Address Register
M_DDR4 EQU $FFFFDE; DMA4 Destination Address Register

A-10

Power Consumption Benchmark

M_DCO4 EQU $FFFFDD; DMA4 Counter
M_DCR4 EQU $FFFFDC; DMA4 Control Register

; Register Addresses Of DMA5

M_DSR5 EQU $FFFFDB; DMA5 Source Address Register
M_DDR5 EQU $FFFFDA; DMA5 Destination Address Register
M_DCO5 EQU $FFFFD9; DMA5 Counter
M_DCR5 EQU $FFFFD8; DMA5 Control Register

;

DMA Control Register

M_DSS EQU $3

; DMA Source Space Mask (DSS0-Dss1)

M_DSS0 EQU 0

; DMA Source Memory space 0

M_DSS1 EQU 1

; DMA Source Memory space 1

M_DDS EQU $C

; DMA Destination Space Mask (DDS-DDS1)

M_DDS0 EQU 2

; DMA Destination Memory Space 0

M_DDS1 EQU 3

; DMA Destination Memory Space 1

M_DAM EQU $3F0 ; DMA Address Mode Mask (DAM5-DAM0)
M_DAM0 EQU 4

; DMA Address Mode 0

M_DAM1 EQU 5

; DMA Address Mode 1

M_DAM2 EQU 6

; DMA Address Mode 2

M_DAM3 EQU 7

; DMA Address Mode 3

M_DAM4 EQU 8

; DMA Address Mode 4

M_DAM5 EQU 9

; DMA Address Mode 5

M_D3D EQU 10

; DMA Three Dimensional Mode

M_DRS EQU $F800; DMA Request Source Mask (DRS0-DRS4)
M_DCON EQU 16

; DMA Continuous Mode

M_DPR EQU $60000; DMA Channel Priority
M_DPR0 EQU 17

; DMA Channel Priority Level (low)

M_DPR1 EQU 18

; DMA Channel Priority Level (high)

M_DTM EQU $380000; DMA Transfer Mode Mask (DTM2-DTM0)
M_DTM0 EQU 19

; DMA Transfer Mode 0

M_DTM1 EQU 20

; DMA Transfer Mode 1

M_DTM2 EQU 21

; DMA Transfer Mode 2

M_DIE EQU 22

; DMA Interrupt Enable bit

M_DE EQU 23

; DMA Channel Enable bit

; DMA Status Register

M_DTD EQU $3F

; Channel Transfer Done Status MASK (DTD0-DTD5)

M_DTD0 EQU 0 ; DMA Channel Transfer Done Status 0
M_DTD1 EQU 1 ; DMA Channel Transfer Done Status 1
M_DTD2 EQU 2 ; DMA Channel Transfer Done Status 2
M_DTD3 EQU 3 ; DMA Channel Transfer Done Status 3
M_DTD4 EQU 4 ; DMA Channel Transfer Done Status 4
M_DTD5 EQU 5 ; DMA Channel Transfer Done Status 5
M_DACT EQU 8

; DMA Active State

M_DCH EQU $E00 ; DMA Active Channel Mask (DCH0-DCH2)
M_DCH0 EQU 9

; DMA Active Channel 0

M_DCH1 EQU 10

; DMA Active Channel 1

M_DCH2 EQU 11

; DMA Active Channel 2

;------------------------------------------------------------------------
;
; EQUATES for Phase Lock Loop (PLL)
;
;------------------------------------------------------------------------

; Register Addresses Of PLL

M_PCTL EQU $FFFFFD; PLL Control Register

; PLL Control Register

M_MF EQU $FFF ; Multiplication Factor Bits Mask (MF0-MF11)
M_DF EQU $7000 ; Division Factor Bits Mask (DF0-DF2)
M_XTLR EQU 15 ; XTAL Range select bit
M_XTLD EQU 16 ; XTAL Disable Bit
M_PSTP EQU 17 ; STOP Processing State Bit
M_PEN EQU 18 ; PLL Enable Bit
M_PCOD EQU 19 ; PLL Clock Output Disable Bit
M_PD EQU $F00000; PreDivider Factor Bits Mask (PD0-PD3)

;------------------------------------------------------------------------
;
; EQUATES for BIU
;
;------------------------------------------------------------------------

A-11

Power Consumption Benchmark

; Register Addresses Of BIU

M_BCR EQU $FFFFFB; Bus Control Register
M_DCR EQU $FFFFFA; DRAM Control Register
M_AAR0 EQU $FFFFF9; Address Attribute Register 0
M_AAR1 EQU $FFFFF8; Address Attribute Register 1
M_AAR2 EQU $FFFFF7; Address Attribute Register 2
M_AAR3 EQU $FFFFF6; Address Attribute Register 3
M_IDR EQU $FFFFF5; ID Register

; Bus Control Register

M_BA0W EQU $1F ; Area 0 Wait Control Mask (BA0W0-BA0W4)
M_BA1W EQU $3E0 ; Area 1 Wait Control Mask (BA1W0-BA14)
M_BA2W EQU $1C00 ; Area 2 Wait Control Mask (BA2W0-BA2W2)
M_BA3W EQU $E000 ; Area 3 Wait Control Mask (BA3W0-BA3W3)
M_BDFW EQU $1F0000; Default Area Wait Control Mask (BDFW0-BDFW4)
M_BBS EQU 21 ; Bus State
M_BLH EQU 22 ; Bus Lock Hold
M_BRH EQU 23 ; Bus Request Hold

; DRAM Control Register

M_BCW EQU $3 ; In Page Wait States Bits Mask (BCW0-BCW1)
M_BRW EQU $C ; Out Of Page Wait States Bits Mask (BRW0-BRW1)
M_BPS EQU $300 ; DRAM Page Size Bits Mask (BPS0-BPS1)
M_BPLE EQU 11 ; Page Logic Enable
M_BME EQU 12 ; Mastership Enable
M_BRE EQU 13 ; Refresh Enable
M_BSTR EQU 14 ; Software Triggered Refresh
M_BRF EQU $7F8000; Refresh Rate Bits Mask (BRF0-BRF7)
M_BRP EQU 23 ; Refresh prescaler

; Address Attribute Registers

M_BAT EQU $3 ; External Access Type and Pin Definition Bits Mask (BAT0-BAT1)
M_BAAP EQU 2 ; Address Attribute Pin Polarity
M_BPEN EQU 3 ; Program Space Enable
M_BXEN EQU 4 ; X Data Space Enable
M_BYEN EQU 5 ; Y Data Space Enable
M_BAM EQU 6 ; Address Muxing
M_BPAC EQU 7

; Packing Enable

M_BNC EQU $F00 ; Number of Address Bits to Compare Mask (BNC0-BNC3)
M_BAC EQU $FFF000; Address to Compare Bits Mask (BAC0-BAC11)

; control and status bits in SR

M_CP EQU $c00000 ; mask for CORE-DMA priority bits in SR
M_CA EQU 0 ; Carry
M_V EQU 1 ; Overflow
M_Z EQU 2 ; Zero
M_N EQU 3 ; Negative
M_U EQU 4 ; Unnormalized
M_E EQU 5 ; Extension
M_L EQU 6 ; Limit
M_S EQU 7 ; Scaling Bit
M_I0 EQU 8 ; Interupt Mask Bit 0
M_I1 EQU 9 ; Interupt Mask Bit 1
M_S0 EQU 10 ; Scaling Mode Bit 0
M_S1 EQU 11 ; Scaling Mode Bit 1
M_SC EQU 13 ; Sixteen_Bit Compatibility
M_DM EQU 14 ; Double Precision Multiply
M_LF EQU 15 ; DO-Loop Flag
M_FV EQU 16 ; DO-Forever Flag
M_SA EQU 17 ; Sixteen-Bit Arithmetic
M_CE EQU 19 ; Instruction Cache Enable
M_SM EQU 20 ; Arithmetic Saturation
M_RM EQU 21 ; Rounding Mode
M_CP0 EQU22 ; bit 0 of priority bits in SR
M_CP1 EQU 23 ; bit 1 of priority bits in SR

; control and status bits in OMR
M_CDP EQU$300 ; mask for CORE-DMA priority bits in OMR
M_MA EQU 0 ; Operating Mode A
M_MB EQU 1 ; Operating Mode B
M_MC EQU 2 ; Operating Mode C
M_MD EQU 3 ; Operating Mode D
M_EBD EQU 4 ; External Bus Disable bit in OMR
M_SD EQU 6 ; Stop Delay

A-12

Power Consumption Benchmark

M_CDP0 EQU 8 ; bit 0 of priority bits in OMR
M_CDP1 EQU 9 ; bit 1 of priority bits in OMR
M_BEN EQU 10 ; Burst Enable
M_TAS EQU 11 ; TA Synchronize Select
M_BRT EQU 12 ; Bus Release Timing
M_XYS EQU 16 ; Stack Extension space select bit in OMR.
M_EUN EQU 17 ; Extensed stack UNderflow flag in OMR.
M_EOV EQU 18 ; Extended stack OVerflow flag in OMR.
M_WRP EQU 19 ; Extended WRaP flag in OMR.
M_SEN EQU 20 ; Stack Extension Enable bit in OMR.
;*************************************************************************
;
; EQUATES for DSP56301 interrupts
; Reference: DSP56301 Specifications Revision 3.00
;
; Last update: November 15 1993 (Debug request & HI32 interrupts)
; December 19 1993 (cosmetic - page and opt directives)
;

August 16 1994 (change interrupt addresses to be

;

relative to I_VEC)

;
;*************************************************************************

page

132,55,0,0,0

opt

mex

intequ ident 1,0

@DEF(I_VEC)

;leave user definition as is.
else

I_VEC

equ

endif

;------------------------------------------------------------------------
; Non-Maskable interrupts
;------------------------------------------------------------------------
I_RESET EQU I_VEC+$00 ; Hardware RESET
I_STACK EQU I_VEC+$02 ; Stack Error
I_ILL EQU I_VEC+$04 ; Illegal Instruction
I_DBG EQU I_VEC+$06 ; Debug Request
I_TRAP EQU I_VEC+$08 ; Trap
I_NMI EQU I_VEC+$0A ; Non Maskable Interrupt

;------------------------------------------------------------------------
; Interrupt Request Pins
;------------------------------------------------------------------------
I_IRQA EQU I_VEC+$10 ; IRQA
I_IRQB EQU I_VEC+$12 ; IRQB
I_IRQC EQU I_VEC+$14 ; IRQC
I_IRQD EQU I_VEC+$16 ; IRQD

;------------------------------------------------------------------------
; DMA Interrupts
;------------------------------------------------------------------------
I_DMA0 EQU I_VEC+$18 ; DMA Channel 0
I_DMA1 EQU I_VEC+$1A ; DMA Channel 1
I_DMA2 EQU I_VEC+$1C ; DMA Channel 2
I_DMA3 EQU I_VEC+$1E ; DMA Channel 3
I_DMA4 EQU I_VEC+$20 ; DMA Channel 4
I_DMA5 EQU I_VEC+$22 ; DMA Channel 5

;------------------------------------------------------------------------
; Timer Interrupts
;------------------------------------------------------------------------
I_TIM0C EQU I_VEC+$24 ; TIMER 0 compare
I_TIM0OF EQU I_VEC+$26 ; TIMER 0 overflow
I_TIM1C EQU I_VEC+$28 ; TIMER 1 compare
I_TIM1OF EQU I_VEC+$2A ; TIMER 1 overflow
I_TIM2C EQU I_VEC+$2C ; TIMER 2 compare
I_TIM2OF EQU I_VEC+$2E ; TIMER 2 overflow

;------------------------------------------------------------------------
; ESSI Interrupts
;------------------------------------------------------------------------
I_SI0RD EQU I_VEC+$30 ; ESSI0 Receive Data
I_SI0RDE EQU I_VEC+$32 ; ESSI0 Receive Data With Exception Status
I_SI0RLS EQU I_VEC+$34 ; ESSI0 Receive last slot
I_SI0TD EQU I_VEC+$36 ; ESSI0 Transmit data
I_SI0TDE EQU I_VEC+$38 ; ESSI0 Transmit Data With Exception Status

A-13

Power Consumption Benchmark

I_SI0TLS EQU I_VEC+$3A ; ESSI0 Transmit last slot
I_SI1RD EQU I_VEC+$40 ; ESSI1 Receive Data
I_SI1RDE EQU I_VEC+$42 ; ESSI1 Receive Data With Exception Status
I_SI1RLS EQU I_VEC+$44 ; ESSI1 Receive last slot
I_SI1TD EQU I_VEC+$46 ; ESSI1 Transmit data
I_SI1TDE EQU I_VEC+$48 ; ESSI1 Transmit Data With Exception Status
I_SI1TLS EQU I_VEC+$4A ; ESSI1 Transmit last slot

;------------------------------------------------------------------------
; SCI Interrupts
;------------------------------------------------------------------------
I_SCIRD EQU I_VEC+$50 ; SCI Receive Data
I_SCIRDE EQU I_VEC+$52 ; SCI Receive Data With Exception Status
I_SCITD EQU I_VEC+$54 ; SCI Transmit Data
I_SCIIL EQU I_VEC+$56 ; SCI Idle Line
I_SCITM EQU I_VEC+$58 ; SCI Timer

;------------------------------------------------------------------------
; HOST Interrupts
;------------------------------------------------------------------------
I_HPTT EQU I_VEC+$60 ; Host PCI Transaction Termination
I_HPTA EQU I_VEC+$62 ; Host PCI Transaction Abort
I_HPPE EQU I_VEC+$64 ; Host PCI Parity Error
I_HPTC EQU I_VEC+$66 ; Host PCI Transfer Complete
I_HPMR EQU I_VEC+$68 ; Host PCI Master Receive
I_HSR EQU I_VEC+$6A ; Host Slave Receive
I_HPMT EQU I_VEC+$6C ; Host PCI Master Transmit
I_HST EQU I_VEC+$6E ; Host Slave Transmit
I_HPMA EQU I_VEC+$70 ; Host PCI Master Address
I_HCNMI EQU I_VEC+$72 ; Host Command/Host NMI (Default)

;------------------------------------------------------------------------
; INTERRUPT ENDING ADDRESS
;------------------------------------------------------------------------
I_INTEND EQU I_VEC+$FF ; last address of interrupt vector space

Index

Index-1

ac electrical characteristics 2-4
address bus 1-1
Address Trace mode 2-28

2-30

applications iv
arbitration bus timings 2-30

benchmark test algorithm A-1
block diagram i
bootstrap ROM iii
Boundary Scan (JTAG Port) timing diagram 2-51
bus

acquisition timings 2-31
control 1-1
external address 1-6
external data 1-6
release timings 2-31

2-32

clock 1-1

1-5

external 2-4
internal 2-4
operation 2-6

crystal oscillator circuits 2-5

data bus 1-1
data memory expansion iv
dc electrical characteristics 2-3
Debug support iii
design considerations

electrical 4-2

4-3

PLL 4-4

4-5

power consumption 4-3
thermal 4-1

documentation list iv
DRAM

out of page

read access 2-26
wait states selection guide 2-21
write access 2-27

out of page and refresh timings

11 wait states 2-23
15 wait states 2-24
8 wait states 2-21

Page mode

read accesses 2-20
wait states selection guide 2-16
write accesses 2-20

Page mode timings

2 wait states 2-17
3 wait states 2-18
4 wait states 2-19

refresh access 2-27

DRAM controller iv
drawing

mechanical information 3-11

3-23

pins

bottom view 3-3
top view 3-2

3-12

DSP56300

Family Manual iv

DSP56301

block diagram i
Technical Data iv
User's Manual iv

electrical

design considerations 4-2

4-3

Enhanced Synchronous Serial Interface (ESSI) iii

1-1

1-19

1-20

1-21

1-22

ESSI 1-2

receiver timing 2-47
timing 2-44
transmitter timing 2-46

external address bus 1-6
external bus control 1-6

1-7

1-8

external bus synchronous timings (SRAM

access) 2-28

external clock operation 2-4
external data bus 1-6
external interrupt timing (negative

edge-triggered) 2-11

external level-sensitive fast interrupt timing 2-10
external memory access (DMA Source)

timing 2-12

External Memory Expansion Port 1-6

2-13

functional groups 1-2
functional signal groups 1-1

General-Purpose Input/Output (GPIO) iii
GPIO 1-24

Timers 1-2
timing 2-49

ground 1-1

1-4

PLL 1-4

Index

Index-2

Host Interface (HI08) 1-1
Host Interface (HI32) iii

1-2

1-11

1-12

PCI 1-2
timing

PCI mode 2-40
Universal Bus mode 2-34

I/O access

2-37

host port

configuration 1-12
usage considerations 1-11

information sources iv
instruction cache iii
internal clocks 2-4
interrupt and mode control 1-1

1-9

1-10

interrupt control 1-9

1-10

interrupt timing 2-7

external level-sensitive fast 2-10
external negative edge-triggered 2-11
synchronous from Wait state 2-11

JTAG iii

1-25

JTAG Port

reset timing diagram 2-51
timing 2-50

2-51

JTAG/OnCE port 1-1

1-2

MAP-BGA 3-1
maximum ratings 2-1

2-2

mechanical information

drawing 3-11

3-23

memory expansion port iii
mode control 1-9

1-10

Mode select timing 2-7

off-chip memory iii
OnCE module iii

1-2

1-25

Debug request 2-52
timing 2-52

on-chip DRAM controller iv
On-Chip Emulation module iii
on-chip memory iii
operating mode select timing 2-11

package

208-pin TQFP 3-1
252-pin MAP-BGA 3-1
TQFP description 3-2

Phase Lock Loop 2-6
Phase-Lock Loop (PLL) 1-1

design considerations 4-4

4-5

performance issues 4-4

4-5

pins

drawing

bottom view 3-3
top view 3-2

3-12

PLL 1-5

2-6

Characteristics 2-6

Port A 1-1

1-6

Port B 1-1

GPIO 1-3

Port C 1-1

1-2

1-19

1-20

Port D 1-1

1-2

1-21

1-22

Port E 1-1

1-23

power 1-1

1-4

power consumption

design considerations 4-3

power consumption benchmark test A-1
power management iv
program memory expansion iv
program RAM iii

recovery from Stop state using

IRQA

2-12

RESET 1-11
Reset timing 2-7

2-9

synchronous 2-10

ROM, bootstrap iii

SCI 1-2

Asynchronous mode timing 2-43
Synchronous mode timing 2-43
timing 2-42

Serial Communication Interface (SCI) iii

1-1

Serial Communications Interface (SCI) 1-23
signal groupings 1-1
signals 1-1

functional grouping 1-2

SRAM

Access 2-28
read access 2-15
read and write accesses 2-13
support iv

DSP56301/D

HOW TO REACH US:

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P.O. Box 5405, Denver, Colorado 80217
1-303-675-2140 or 1-800-441-2447

JAPAN:

Motorola Japan Ltd.; SPS, Technical Information Center,
3-20-1, Minami-Azabu Minato-ku, Tokyo 106-8573 Japan
81-3-3440-3569

ASIA/PACIFIC:

Motorola Semiconductors H.K. Ltd.; Silicon Harbour
Centre, 2 Dai King Street, Tai Po Industrial Estate,
Tai Po, N.T., Hong Kong
852-26668334

TECHNICAL INFORMATION CENTER:

1-800-521-6274

HOME PAGE:

http://www.motorola.com/semiconductors

Information in this document is provided solely to enable system and software implementers to use

Motorola products. There are no express or implied copyright licenses granted hereunder to design or

fabricate any integrated circuits or integrated circuits based on the information in this document.

Motorola reserves the right to make changes without further notice to any products herein. Motorola

makes no warranty, representation or guarantee regarding the suitability of its products for any

particular purpose, nor does Motorola assume any liability arising out of the application or use of any

product or circuit, and specifically disclaims any and all liability, including without limitation

consequential or incidental damages. "Typical" parameters which may be provided in Motorola data

sheets and/or specifications can and do vary in different applications and actual performance may

vary over time. All operating parameters, including "Typicals" must be validated for each customer

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Ordering Information

Consult a Motorola Semiconductor sales office or authorized distributor to determine product availability and place an order.

Part

Supply

Voltage

Package Type

Pin

Count

Core

Frequency

(MHz)

Order Number

DSP56301

3 V

Thin Quad Flat Pack (TQFP)

208

DSP56301PW80

100

DSP56301PW100

Molded Array Process-Ball Grid Array (MAP-BGA)

252

DSP56301VF80

100

DSP56301VF100

Document Outline

Ð­Ð»ÐµÐºÑ‚Ñ€Ð¾Ð½Ð½Ñ‹Ð¹ ÐºÐ¾Ð¼Ð¿Ð¾Ð½ÐµÐ½Ñ‚: DSP56301PW80

Document Outline

ÐÐ»ÐµÐºÑ‚Ñ€Ð¾Ð½Ð½Ñ‹Ð¹ ÐºÐ¾Ð¼Ð¿Ð¾Ð½ÐµÐ½Ñ‚: DSP56301PW80