Document Outline

DSP56309
- 24-Bit Digital Signal Processor Users Manual
Table of contents
List of Figures
List of Tables
- Section 1
DSP56309 Overview
Signal/Connection Descriptions
Memory Configuration
Core Configuration
General-Purpose I/O
Host Interface (HI08)
Enhanced Synchronous Serial Interface (ESSI)
Serial Communication Interface (SCI)
Triple Timer Module
On-Chip Emulation Module
JTAG Port
Bootstrap Programs
- Appendix B
Equates
DSP56309 BSDL Listing
- appendix D
Programming Reference

MOTOROLA

DSP56309UM/D iii

TABLE OF CONTENTS

SECTION

DSP56309 OVERVIEW . . . . . . . . . . . . . . . . . . . . . . 1-1

1.1

INTRODUCTION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-3

1.2

MANUAL ORGANIZATION . . . . . . . . . . . . . . . . . . . . . . . . . . 1-3

1.3

MANUAL CONVENTIONS . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-5

1.4

DSP56309 FEATURES . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-6

1.5

DSP56309 CORE DESCRIPTION . . . . . . . . . . . . . . . . . . . . . 1-7

1.5.1

General Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-7

1.5.2

Hardware Debugging Support . . . . . . . . . . . . . . . . . . . . . . 1-7

1.5.3

Reduced Power Dissipation. . . . . . . . . . . . . . . . . . . . . . . . 1-7

1.6

DSP56300 CORE FUNCTIONAL BLOCKS . . . . . . . . . . . . . . 1-8

1.6.1

Data ALU . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-8

1.6.1.1

Data ALU Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-8

1.6.1.2

Multiplier-Accumulator (MAC) . . . . . . . . . . . . . . . . . . . . 1-9

1.6.2

Address Generation Unit (AGU) . . . . . . . . . . . . . . . . . . . . 1-9

1.6.3

Program Control Unit (PCU) . . . . . . . . . . . . . . . . . . . . . . 1-10

1.6.4

PLL and Clock Oscillator . . . . . . . . . . . . . . . . . . . . . . . . . 1-11

1.6.5

JTAG TAP and OnCE Module . . . . . . . . . . . . . . . . . . . . . 1-11

1.6.6

On-Chip Memory . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-12

1.6.7

Off-Chip Memory Expansion . . . . . . . . . . . . . . . . . . . . . . 1-12

1.7

INTERNAL BUSES . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-13

1.8

DSP56309 BLOCK DIAGRAM . . . . . . . . . . . . . . . . . . . . . . . 1-14

1.9

DIRECT MEMORY ACCESS (DMA) . . . . . . . . . . . . . . . . . . 1-15

1.10

DSP56309 ARCHITECTURE OVERVIEW . . . . . . . . . . . . . 1-15

1.10.1

GPIO Functionality. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-15

1.10.2

Host Interface (HI08) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-16

1.10.3

Enhanced Synchronous Serial Interface (ESSI) . . . . . . . 1-16

1.10.4

Serial Communications Interface (SCI) . . . . . . . . . . . . . . 1-16

1.10.5

Timer Module . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-17

SECTION

SIGNAL/CONNECTION DESCRIPTIONS. . . . . . . . 2-1

2.1

SIGNAL GROUPINGS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-3

2.2

POWER . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-5

r
e

s
c

l
e

i
c

t
o

r
,

I

Freescale Semiconductor, Inc.

For More Information On This Product,

Go to: www.freescale.com

.
.

DSP56309UM/D MOTOROLA

2.3

GROUND. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-6

2.4

CLOCK . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-7

2.5

PHASE-LOCKED LOOP (PLL) . . . . . . . . . . . . . . . . . . . . . . . 2-8

2.6

EXTERNAL MEMORY EXPANSION PORT (PORT A). . . . . 2-9

2.6.1

External Address Bus . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-9

2.6.2

External Data Bus . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-10

2.6.3

External Bus Control . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-10

2.7

INTERRUPT AND MODE CONTROL . . . . . . . . . . . . . . . . . 2-14

2.8

HOST INTERFACE (HI08) . . . . . . . . . . . . . . . . . . . . . . . . . 2-16

2.8.1

Host Port Usage Considerations. . . . . . . . . . . . . . . . . . . 2-16

2.8.2

Host Port Configuration. . . . . . . . . . . . . . . . . . . . . . . . . . 2-17

2.9

ENHANCED SYNCHRONOUS SERIAL INTERFACE . . . . 2-24

2.9.1

ESSI0 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-24

2.9.2

ESSI1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-27

2.10

SERIAL COMMUNICATION INTERFACE (SCI) . . . . . . . . . 2-32

2.11

TIMERS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-33

2.12

ONCE/JTAG INTERFACE. . . . . . . . . . . . . . . . . . . . . . . . . . 2-35

SECTION

MEMORY CONFIGURATION . . . . . . . . . . . . . . . . . 3-1

3.1

MEMORY SPACES . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-3

3.1.1

Program Memory Space . . . . . . . . . . . . . . . . . . . . . . . . . . 3-3

3.1.2

Data Memory Spaces . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-3

3.1.2.1

X Data Memory Space . . . . . . . . . . . . . . . . . . . . . . . . . 3-4

3.1.2.2

Y Data Memory Space . . . . . . . . . . . . . . . . . . . . . . . . . 3-4

3.1.3

Memory Space Configuration . . . . . . . . . . . . . . . . . . . . . . 3-5

3.2

RAM CONFIGURATION. . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-5

3.2.1

On-Chip Program Memory (Program RAM) . . . . . . . . . . . 3-6

3.2.2

On-Chip X Data Memory (X Data RAM) . . . . . . . . . . . . . . 3-6

3.2.3

On-Chip Y Data Memory (Y Data RAM) . . . . . . . . . . . . . . 3-7

3.2.4

Bootstrap ROM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-7

3.3

MEMORY CONFIGURATIONS . . . . . . . . . . . . . . . . . . . . . . . 3-7

3.3.1

Memory Space Configurations . . . . . . . . . . . . . . . . . . . . . 3-7

3.3.2

RAM Configurations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-8

3.4

MEMORY MAPS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-9

3.5

INTERNAL I/O MEMORY MAP . . . . . . . . . . . . . . . . . . . . . . 3-18

r
e

s
c

l
e

i
c

t
o

r
,

I

Freescale Semiconductor, Inc.

For More Information On This Product,

Go to: www.freescale.com

.
.

MOTOROLA

DSP56309UM/D v

SECTION

CORE CONFIGURATION . . . . . . . . . . . . . . . . . . . . 4-1

4.1

INTRODUCTION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-3

4.2

OPERATING MODES . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-3

4.3

BOOTSTRAP PROGRAM. . . . . . . . . . . . . . . . . . . . . . . . . . . 4-4

4.3.1

Mode 0: Expanded Mode. . . . . . . . . . . . . . . . . . . . . . . . . . 4-6

4.3.2

Modes 1 to 7: Reserved. . . . . . . . . . . . . . . . . . . . . . . . . . . 4-6

4.3.3

Mode 8: Expanded Mode. . . . . . . . . . . . . . . . . . . . . . . . . . 4-6

4.3.4

Mode 9: Boot from Byte-Wide External Memory . . . . . . . . 4-7

4.3.5

Mode A: Boot from SCI . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-7

4.3.6

Mode B: Reserved . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-7

4.3.7

Modes C, D, E, F: Boot from HI08 . . . . . . . . . . . . . . . . . . . 4-8

4.3.7.1

Mode C: In ISA/DSP5630X Mode (8-Bit Bus) . . . . . . . 4-8

4.3.7.2

Mode D: In HC11 Non-multiplexed Mode . . . . . . . . . . 4-8

4.3.7.3

Mode E: In 8051 Multiplexed Bus Mode . . . . . . . . . . . 4-9

4.3.7.4

Mode F: In 68302/68360 Bus Mode . . . . . . . . . . . . . . . 4-9

4.4

INTERRUPT SOURCES AND PRIORITIES . . . . . . . . . . . . . 4-9

4.4.1

Interrupt Sources . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-9

4.4.2

Interrupt Priority Levels . . . . . . . . . . . . . . . . . . . . . . . . . . 4-12

4.4.3

Interrupt Source Priorities Within an IPL . . . . . . . . . . . . . 4-14

4.5

DMA REQUEST SOURCES . . . . . . . . . . . . . . . . . . . . . . . . 4-16

4.6

OPERATING MODE REGISTER (OMR) . . . . . . . . . . . . . . . 4-17

4.7

PLL CONTROL REGISTER . . . . . . . . . . . . . . . . . . . . . . . . . 4-18

4.7.1

PCTL PLL Multiplication Factor Bits 0Ð11 . . . . . . . . . . . . 4-18

4.7.2

PCTL XTAL Disable Bit (XTLD) Bit 16. . . . . . . . . . . . . . . 4-18

4.7.3

PCTL Predivider Factor Bits (PD0ÐPD3) Bits 20Ð23 . . . . 4-18

4.8

DEVICE IDENTIFICATION REGISTER (IDR) . . . . . . . . . . . 4-18

4.9

AA CONTROL REGISTERS (AAR0ÐAAR3) . . . . . . . . . . . . 4-19

4.10

JTAG BOUNDARY SCAN REGISTER (BSR) . . . . . . . . . . . 4-20

SECTION

GENERAL-PURPOSE I/O . . . . . . . . . . . . . . . . . . . . 5-1

5.1

INTRODUCTION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-3

5.2

PROGRAMMING MODEL . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-3

5.2.1

Port B Signals and Registers . . . . . . . . . . . . . . . . . . . . . . . 5-3

5.2.2

Port C Signals and Registers. . . . . . . . . . . . . . . . . . . . . . . 5-3

5.2.3

Port D Signals and Registers. . . . . . . . . . . . . . . . . . . . . . . 5-4

5.2.4

Port E Signals and Registers . . . . . . . . . . . . . . . . . . . . . . . 5-4

r
e

s
c

l
e

i
c

t
o

r
,

I

Freescale Semiconductor, Inc.

For More Information On This Product,

Go to: www.freescale.com

.
.

DSP56309UM/D MOTOROLA

5.2.5

Triple Timer Signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-4

SECTION

HOST INTERFACE (HI08) . . . . . . . . . . . . . . . . . . . 6-1

6.1

INTRODUCTION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-3

6.2

HI08 FEATURES . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-3

6.2.1

Host to DSP Core Interface. . . . . . . . . . . . . . . . . . . . . . . . 6-3

6.2.2

HI08-to-Host Processor Interface . . . . . . . . . . . . . . . . . . . 6-4

6.3

HI08 HOST PORT SIGNALS. . . . . . . . . . . . . . . . . . . . . . . . . 6-6

6.4

HI08 BLOCK DIAGRAM . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-7

6.5

HI08 DSP SIDE PROGRAMMERÕS MODEL. . . . . . . . . . . . . 6-8

6.5.1

Host Receive Data Register (HRX). . . . . . . . . . . . . . . . . . 6-8

6.5.2

Host Transmit Data Register (HTX) . . . . . . . . . . . . . . . . . 6-9

6.5.3

Host Control Register (HCR). . . . . . . . . . . . . . . . . . . . . . . 6-9

6.5.3.1

HCR Host Receive Interrupt Enable (HRIE) Bit 0 . . . 6-10

6.5.3.2

HCR Host Transmit Interrupt Enable (HTIE) Bit 1 . . . 6-10

6.5.3.3

HCR Host Command Interrupt Enable (HCIE) Bit 2 . . 6-10

6.5.3.4

HCR Host Flags 2,3 (HF[3:2]) Bits 3, 4 . . . . . . . . . . . 6-10

6.5.3.5

HCR Reserved Bits 5-15 . . . . . . . . . . . . . . . . . . . . . . 6-10

6.5.4

Host Status Register (HSR) . . . . . . . . . . . . . . . . . . . . . . 6-11

6.5.4.1

HSR Host Receive Data Full (HRDF) Bit 0 . . . . . . . . 6-11

6.5.4.2

HSR Host Transmit Data Empty (HTDE) Bit 1 . . . . . . 6-11

6.5.4.3

HSR Host Command Pending (HCP) Bit 2 . . . . . . . . 6-11

6.5.4.4

HSR Host Flags 0, 1 (HF[1:0]) Bits 3, 4 . . . . . . . . . . . 6-11

6.5.4.5

HSR Reserved Bits 5-15 . . . . . . . . . . . . . . . . . . . . . . 6-11

6.5.5

Host Base Address Register (HBAR) . . . . . . . . . . . . . . . 6-12

6.5.5.1

HBAR Base Address (BA[10:3]) Bits 0-7 . . . . . . . . . . 6-12

6.5.5.2

HBAR Reserved Bits 8-15 . . . . . . . . . . . . . . . . . . . . . 6-12

6.5.6

Host Port Control Register (HPCR). . . . . . . . . . . . . . . . . 6-12

6.5.6.1

HPCR Host GPIO Port Enable (HGEN) Bit 0 . . . . . . . 6-13

6.5.6.2

HPCR Host Address Line 8 Enable (HA8EN) Bit 1 . . 6-13

6.5.6.3

HPCR Host Address Line 9 Enable (HA9EN) Bit 2 . . 6-13

6.5.6.4

HPCR Host Chip Select Enable (HCSEN) Bit 3 . . . . . 6-13

6.5.6.5

HPCR Host Request Enable (HREN) Bit 4 . . . . . . . . 6-14

6.5.6.6

HPCR Host Acknowledge Enable (HAEN) Bit 5. . . . . 6-14

6.5.6.7

HPCR Host Enable (HEN) Bit 6 . . . . . . . . . . . . . . . . . 6-14

6.5.6.8

HPCR Reserved Bit 7. . . . . . . . . . . . . . . . . . . . . . . . . 6-14

r
e

s
c

l
e

i
c

t
o

r
,

I

Freescale Semiconductor, Inc.

For More Information On This Product,

Go to: www.freescale.com

.
.

MOTOROLA

DSP56309UM/D vii

6.5.6.9

HPCR Host Request Open Drain (HROD) Bit 8 . . . . . 6-14

6.5.6.10

HPCR Host Data Strobe Polarity (HDSP) Bit 9 . . . . . . 6-14

6.5.6.11

HPCR Host Address Strobe Polarity (HASP) Bit 10 . . 6-15

6.5.6.12

HPCR Host Multiplexed Bus (HMUX) Bit 11 . . . . . . . . 6-15

6.5.6.13

HPCR Host Dual Data Strobe (HDDS) Bit 12 . . . . . . . 6-15

6.5.6.14

HPCR Host Chip Select Polarity (HCSP) Bit 13 . . . . . 6-16

6.5.6.15

HPCR Host Request Polarity (HRP) Bit 14 . . . . . . . . . 6-16

6.5.6.16

HPCR Host Acknowledge Polarity (HAP) Bit 15 . . . . . 6-16

6.5.7

Host Data Direction Register (HDDR) . . . . . . . . . . . . . . . 6-17

6.5.8

Host Data Register (HDR) . . . . . . . . . . . . . . . . . . . . . . . . 6-17

6.5.9

DSP Side Registers After Reset . . . . . . . . . . . . . . . . . . . 6-18

6.5.10

Host Interface DSP Core Interrupts . . . . . . . . . . . . . . . . . 6-19

6.6

HI08-EXTERNAL HOST PROGRAMMERÕS MODEL . . . . . 6-20

6.6.1

Interface Control Register (ICR) . . . . . . . . . . . . . . . . . . . 6-22

6.6.1.1

ICR Receive Request Enable (RREQ) Bit 0 . . . . . . . . 6-23

6.6.1.2

ICR Transmit Request Enable (TREQ) Bit 1 . . . . . . . . 6-23

6.6.1.3

ICR Double Host Request (HDRQ) Bit 2. . . . . . . . . . . 6-23

6.6.1.4

ICR Host Flag 0 (HF0) Bit 3 . . . . . . . . . . . . . . . . . . . . 6-24

6.6.1.5

ICR Host Flag 1 (HF1) Bit 4 . . . . . . . . . . . . . . . . . . . . 6-24

6.6.1.6

ICR Host Little Endian (HLEND) Bit 5 . . . . . . . . . . . . . 6-24

6.6.1.7

ICR Reserved Bit 6 . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-24

6.6.1.8

ICR Initialize Bit (INIT) Bit 7 . . . . . . . . . . . . . . . . . . . . 6-24

6.6.2

Command Vector Register (CVR) . . . . . . . . . . . . . . . . . . 6-25

6.6.2.1

CVR Host Vector (HV[6:0]) Bits 0Ð6 . . . . . . . . . . . . . . 6-25

6.6.2.2

CVR Host Command Bit (HC) Bit 7. . . . . . . . . . . . . . . 6-26

6.6.3

Interface Status Register (ISR) . . . . . . . . . . . . . . . . . . . . 6-26

6.6.3.1

ISR Receive Data Register Full (RXDF) Bit 0 . . . . . . . 6-26

6.6.3.2

ISR Transmit Data Register Empty (TXDE) Bit 1 . . . . 6-27

6.6.3.3

ISR Transmitter Ready (TRDY) Bit 2 . . . . . . . . . . . . . 6-27

6.6.3.4

ISR Host Flag 2 (HF2) Bit 3 . . . . . . . . . . . . . . . . . . . . 6-27

6.6.3.5

ISR Host Flag 3 (HF3) Bit 4 . . . . . . . . . . . . . . . . . . . . 6-27

6.6.3.6

ISR Reserved Bits 5, 6 . . . . . . . . . . . . . . . . . . . . . . . . 6-27

6.6.3.7

ISR Host Request (HREQ) Bit 7 . . . . . . . . . . . . . . . . . 6-27

6.6.4

Interrupt Vector Register (IVR) . . . . . . . . . . . . . . . . . . . . 6-28

6.6.5

Receive Byte Registers (RXH: RXM: RXL) . . . . . . . . . . . 6-28

6.6.6

Transmit Byte Registers (TXH:TXM:TXL) . . . . . . . . . . . . 6-29

r
e

s
c

l
e

i
c

t
o

r
,

I

Freescale Semiconductor, Inc.

For More Information On This Product,

Go to: www.freescale.com

.
.

viii

DSP56309UM/D MOTOROLA

6.6.7

Host Side Registers After Reset . . . . . . . . . . . . . . . . . . . 6-30

6.6.8

General-Purpose I/O . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-30

6.7

SERVICING THE HOST INTERFACE . . . . . . . . . . . . . . . . 6-31

6.7.1

HI08 Host Processor Data Transfer . . . . . . . . . . . . . . . . 6-31

6.7.2

Polling . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-31

6.7.3

Servicing Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-32

6.8

HI08 PROGRAMMING MODEL QUICK REFERENCE. . . . 6-34

SECTION

ENHANCED SYNCHRONOUS SERIAL INTERFACE (ESSI)
7-1

7.1

INTRODUCTION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-3

7.2

ENHANCEMENTS TO THE ESSI . . . . . . . . . . . . . . . . . . . . . 7-3

7.3

ESSI DATA AND CONTROL SIGNALS . . . . . . . . . . . . . . . . 7-4

7.3.1

Serial Transmit Data (STD) Signal . . . . . . . . . . . . . . . . . . 7-4

7.3.2

Serial Receive Data Signal (SRD) . . . . . . . . . . . . . . . . . . 7-4

7.3.3

Serial Clock (SCK) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-5

7.3.4

Serial Control Signal (SC0) . . . . . . . . . . . . . . . . . . . . . . . . 7-6

7.3.5

Serial Control Signal (SC1) . . . . . . . . . . . . . . . . . . . . . . . . 7-7

7.3.6

Serial Control Signal (SC2) . . . . . . . . . . . . . . . . . . . . . . . . 7-8

7.4

ESSI PROGRAMMING MODEL . . . . . . . . . . . . . . . . . . . . . . 7-8

7.4.1

ESSI Control Register A (CRA). . . . . . . . . . . . . . . . . . . . 7-11

7.4.1.1

CRA Prescale Modulus Select PM[7:0] Bits 7Ð0 . . . . 7-11

7.4.1.2

CRA Reserved Bits 8Ð10 . . . . . . . . . . . . . . . . . . . . . . 7-11

7.4.1.3

CRA Prescaler Range (PSR) Bit 11 . . . . . . . . . . . . . . 7-11

7.4.1.4

CRA Frame Rate Divider Control DC[4:0] Bits 16Ð12 7-12

7.4.1.5

CRA Reserved Bit 17 . . . . . . . . . . . . . . . . . . . . . . . . . 7-13

7.4.1.6

CRA Alignment Control (ALC) Bit 18 . . . . . . . . . . . . . 7-13

7.4.1.7

CRA Word-length Control (WL[2:0]) Bits 21Ð19 . . . . . 7-14

7.4.1.8

CRA Select SC1 (SSC1) Bit 22 . . . . . . . . . . . . . . . . . 7-14

7.4.1.9

CRA Reserved Bit 23 . . . . . . . . . . . . . . . . . . . . . . . . . 7-14

7.4.2

ESSI Control Register B (CRB). . . . . . . . . . . . . . . . . . . . 7-15

7.4.2.1

CRB Serial Output Flags (OF0, OF1) Bits 0, 1. . . . . . 7-15

7.4.2.1.1

CRB Serial Output Flag 0 (OF0) Bit 0 . . . . . . . . . . 7-15

7.4.2.1.2

CRB Serial Output Flag 1 (OF1) Bit 1 . . . . . . . . . . 7-16

7.4.2.2

CRB Serial Control Direction 0 (SCD0) Bit 2 . . . . . . . 7-16

7.4.2.3

CRB Serial Control Direction 1 (SCD1) Bit 3 . . . . . . . 7-16

r
e

s
c

l
e

i
c

t
o

r
,

I

Freescale Semiconductor, Inc.

For More Information On This Product,

Go to: www.freescale.com

.
.

MOTOROLA

DSP56309UM/D ix

7.4.2.4

CRB Serial Control Direction 2 (SCD2) Bit 4 . . . . . . . 7-16

7.4.2.5

CRB Clock Source Direction (SCKD) Bit 5 . . . . . . . . . 7-16

7.4.2.6

CRB Shift Direction (SHFD) Bit 6 . . . . . . . . . . . . . . . . 7-17

7.4.2.7

CRB Frame Sync Length FSL[1:0] Bits 7 and 8 . . . . . 7-17

7.4.2.8

CRB Frame Sync Relative Timing (FSR) Bit 9 . . . . . . 7-17

7.4.2.9

CRB Frame Sync Polarity (FSP) Bit 10. . . . . . . . . . . . 7-17

7.4.2.10

CRB Clock Polarity (CKP) Bit 11. . . . . . . . . . . . . . . . . 7-18

7.4.2.11

CRB Synchronous /Asynchronous (SYN) Bit 12. . . . . 7-18

7.4.2.12

CRB ESSI Mode Select (MOD) Bit 13 . . . . . . . . . . . . 7-20

7.4.2.13

Enabling, Disabling ESSI Data Transmission . . . . . . . 7-22

7.4.2.14

CRB ESSI Transmit 2 Enable (TE2) Bit 14 . . . . . . . . . 7-22

7.4.2.15

CRB ESSI Transmit 1 Enable (TE1) Bit 15 . . . . . . . . . 7-23

7.4.2.16

CRB ESSI Transmit 0 Enable (TE0) Bit 16 . . . . . . . . . 7-24

7.4.2.17

CRB ESSI Receive Enable (RE) Bit 17. . . . . . . . . . . . 7-26

7.4.2.18

CRB ESSI Transmit Interrupt Enable (TIE) Bit 18. . . . 7-26

7.4.2.19

CRB ESSI Receive Interrupt Enable (RIE) Bit 19 . . . . 7-26

7.4.2.20

Transmit Last Slot Interrupt Enable (TLIE) Bit 20 . . . . 7-26

7.4.2.21

Receive Last Slot Interrupt Enable (RLIE) Bit 21 . . . . 7-27

7.4.2.22

Transmit Exception Interrupt Enable (TEIE) Bit 22 . . . 7-27

7.4.2.23

Receive Exception Interrupt Enable (REIE) Bit 23 . . . 7-27

7.4.3

ESSI Status Register (SSISR) . . . . . . . . . . . . . . . . . . . . . 7-27

7.4.3.1

SSISR Serial Input Flag 0 (IF0) Bit 0 . . . . . . . . . . . . . 7-28

7.4.3.2

SSISR Serial Input Flag 1 (IF1) Bit 1 . . . . . . . . . . . . . 7-28

7.4.3.3

SSISR Transmit Frame Sync Flag (TFS) Bit 2 . . . . . . 7-28

7.4.3.4

SSISR Receive Frame Sync Flag (RFS) Bit 3 . . . . . . 7-28

7.4.3.5

SSISR Transmitter Underrun Error Flag (TUE) Bit 4 . 7-29

7.4.3.6

SSISR Receiver Overrun Error Flag (ROE) Bit 5 . . . . 7-29

7.4.3.7

ESSI Transmit Data Register Empty (TDE) Bit 6 . . . . 7-29

7.4.3.8

ESSI Receive Data Register Full (RDF) Bit 7 . . . . . . . 7-30

7.4.4

ESSI Receive Shift Register . . . . . . . . . . . . . . . . . . . . . . 7-33

7.4.5

ESSI Receive Data Register (RX) . . . . . . . . . . . . . . . . . . 7-33

7.4.6

ESSI Transmit Shift Registers . . . . . . . . . . . . . . . . . . . . . 7-33

7.4.7

ESSI Transmit Data Registers (TX0-2) . . . . . . . . . . . . . . 7-34

7.4.8

ESSI Time Slot Register (TSR) . . . . . . . . . . . . . . . . . . . . 7-34

7.4.9

Transmit Slot Mask Registers (TSMA, TSMB) . . . . . . . . 7-34

7.4.10

Receive Slot Mask Registers (RSMA, RSMB). . . . . . . . . 7-35

r
e

s
c

l
e

i
c

t
o

r
,

I

Freescale Semiconductor, Inc.

For More Information On This Product,

Go to: www.freescale.com

.
.

DSP56309UM/D MOTOROLA

7.5

OPERATING MODES . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-36

7.5.1

ESSI After Reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-36

7.5.2

ESSI Initialization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-36

7.5.3

ESSI Exceptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-37

7.5.4

Operating Modes: Normal, Network, and On-Demand . . 7-40

7.5.4.1

Normal/Network/On-Demand Mode Selection . . . . . . 7-40

7.5.4.2

Synchronous/Asynchronous Operating Modes . . . . . 7-40

7.5.4.3

Frame Sync Selection . . . . . . . . . . . . . . . . . . . . . . . . 7-41

7.5.4.3.1

Frame Sync Signal Format . . . . . . . . . . . . . . . . . . 7-41

7.5.4.3.2

Frame Sync Length for Multiple Devices . . . . . . . . 7-41

7.5.4.3.3

Word-Length Frame Sync and Data-Word Timing 7-41

7.5.4.3.4

Frame Sync Polarity . . . . . . . . . . . . . . . . . . . . . . . 7-42

7.5.4.4

Byte Format (LSB/MSB) for the Transmitter . . . . . . . 7-42

7.5.5

Flags . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-42

7.6

GPIO SIGNALS AND REGISTERS. . . . . . . . . . . . . . . . . . . 7-43

7.6.1

Port Control Register (PCR) . . . . . . . . . . . . . . . . . . . . . . 7-43

7.6.2

Port Direction Register (PRR) . . . . . . . . . . . . . . . . . . . . . 7-44

7.6.3

Port Data Register (PDR) . . . . . . . . . . . . . . . . . . . . . . . . 7-45

SECTION

SERIAL COMMUNICATION INTERFACE (SCI) . . 8-1

8.1

INTRODUCTION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8-3

8.2

SCI I/O SIGNALS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8-3

8.2.1

Receive Data (RXD) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8-4

8.2.2

Transmit Data (TXD) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8-4

8.2.3

SCI Serial Clock (SCLK) . . . . . . . . . . . . . . . . . . . . . . . . . . 8-4

8.3

SCI PROGRAMMING MODEL . . . . . . . . . . . . . . . . . . . . . . . 8-4

8.3.1

SCI Control Register (SCR) . . . . . . . . . . . . . . . . . . . . . . . 8-8

8.3.1.1

SCR Word Select (WDS[0:2]) Bits 0Ð2 . . . . . . . . . . . . 8-8

8.3.1.2

SCR SCI Shift Direction (SSFTD) Bit 3 . . . . . . . . . . . . 8-9

8.3.1.3

SCR Send Break (SBK) Bit 4 . . . . . . . . . . . . . . . . . . . . 8-9

8.3.1.4

SCR Wakeup Mode Select (WAKE) Bit 5 . . . . . . . . . . 8-9

8.3.1.5

SCR Receiver Wakeup Enable (RWU) Bit 6 . . . . . . . . 8-9

8.3.1.6

SCR Wired-OR Mode Select (WOMS) Bit 7. . . . . . . . 8-10

8.3.1.7

SCR Receiver Enable (RE) Bit 8 . . . . . . . . . . . . . . . . 8-10

8.3.1.8

SCR Transmitter Enable (TE) Bit 9 . . . . . . . . . . . . . . 8-10

8.3.1.9

SCR Idle Line Interrupt Enable (ILIE) Bit 10. . . . . . . . 8-11

r
e

s
c

l
e

i
c

t
o

r
,

I

Freescale Semiconductor, Inc.

For More Information On This Product,

Go to: www.freescale.com

.
.

MOTOROLA

DSP56309UM/D xi

8.3.1.10

SCR SCI Receive Interrupt Enable (RIE) Bit 11 . . . . . 8-11

8.3.1.11

SCR SCI Transmit Interrupt Enable (TIE) Bit 12 . . . . . 8-12

8.3.1.12

SCR Timer Interrupt Enable (TMIE) Bit 13 . . . . . . . . . 8-12

8.3.1.13

SCR Timer Interrupt Rate (STIR) Bit 14 . . . . . . . . . . . 8-12

8.3.1.14

SCR SCI Clock Polarity (SCKP) Bit 15 . . . . . . . . . . . . 8-12

8.3.1.15

Receive with Exception Interrupt Enable (REIE) Bit 168-13

8.3.2

SCI Status Register (SSR) . . . . . . . . . . . . . . . . . . . . . . . 8-13

8.3.2.1

SSR Transmitter Empty (TRNE) Bit 0 . . . . . . . . . . . . . 8-13

8.3.2.2

SSR Transmit Data Register Empty (TDRE) Bit 1 . . . 8-13

8.3.2.3

SSR Receive Data Register Full (RDRF) Bit 2 . . . . . . 8-14

8.3.2.4

SSR Idle Line Flag (IDLE) Bit 3. . . . . . . . . . . . . . . . . . 8-14

8.3.2.5

SSR Overrun Error Flag (OR) Bit 4 . . . . . . . . . . . . . . . 8-14

8.3.2.6

SSR Parity Error (PE) Bit 5 . . . . . . . . . . . . . . . . . . . . . 8-14

8.3.2.7

SSR Framing Error Flag (FE) Bit 6 . . . . . . . . . . . . . . . 8-15

8.3.2.8

SSR Received Bit 8 (R8) Address Bit 7 . . . . . . . . . . . 8-15

8.3.3

SCI Clock Control Register (SCCR) . . . . . . . . . . . . . . . . 8-15

8.3.3.1

SCCR Clock Divider (CD[11:0]) Bits 11Ð0 . . . . . . . . . 8-16

8.3.3.2

SCCR Clock Out Divider (COD) Bit 12 . . . . . . . . . . . . 8-16

8.3.3.3

SCCR SCI Clock Prescaler (SCP) Bit 13 . . . . . . . . . . 8-17

8.3.3.4

SCCR Receive Clock Mode Source (RCM) Bit 14 . . . 8-17

8.3.3.5

SCCR Transmit Clock Source Bit (TCM) Bit 15 . . . . . 8-18

8.3.4

SCI Data Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8-18

8.3.4.1

SCI Receive Registers (SRX) . . . . . . . . . . . . . . . . . . . 8-19

8.3.4.2

SCI Transmit Registers . . . . . . . . . . . . . . . . . . . . . . . . 8-20

8.4

OPERATING MODES . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8-21

8.4.1

SCI After Reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8-22

8.4.2

SCI Initialization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8-24

8.4.3

SCI Initialization Example . . . . . . . . . . . . . . . . . . . . . . . . 8-25

8.4.4

Preamble, Break, and Data Transmission Priority . . . . . . 8-26

8.4.5

SCI Exceptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8-26

8.5

GPIO SIGNALS AND REGISTERS . . . . . . . . . . . . . . . . . . . 8-27

8.5.1

Port E Control Register (PCRE) . . . . . . . . . . . . . . . . . . . 8-27

8.5.2

Port E Direction Register (PRRE) . . . . . . . . . . . . . . . . . . 8-27

8.5.3

Port E Data Register (PDRE) . . . . . . . . . . . . . . . . . . . . . 8-28

r
e

s
c

l
e

i
c

t
o

r
,

I

Freescale Semiconductor, Inc.

For More Information On This Product,

Go to: www.freescale.com

.
.

xii

DSP56309UM/D MOTOROLA

SECTION

TRIPLE TIMER MODULE . . . . . . . . . . . . . . . . . . . . 9-1

9.1

INTRODUCTION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9-3

9.2

TRIPLE TIMER MODULE ARCHITECTURE . . . . . . . . . . . . 9-3

9.2.1

Triple Timer Module Block Diagram . . . . . . . . . . . . . . . . . 9-3

9.2.2

Timer Block Diagram. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9-4

9.3

TRIPLE TIMER MODULE PROGRAMMING MODEL. . . . . . 9-5

9.3.1

Prescaler Counter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9-7

9.3.2

Timer Prescaler Load Register (TPLR). . . . . . . . . . . . . . . 9-7

9.3.2.1

TPLR Prescaler Preload Value (PL[20:0]) Bits 20-0 . . 9-7

9.3.2.2

TPLR Prescaler Source (PS[1:0]) Bits 22-21 . . . . . . . . 9-7

9.3.2.3

TPLR Reserved Bit 23 . . . . . . . . . . . . . . . . . . . . . . . . . 9-8

9.3.3

Timer Prescaler Count Register (TPCR). . . . . . . . . . . . . . 9-8

9.3.3.1

TPCR Prescaler Counter Value (PC[20:0]) Bits 20-0 . . 9-9

9.3.3.2

TPCR Reserved Bits 23-21 . . . . . . . . . . . . . . . . . . . . . 9-9

9.3.4

Timer Control/Status Register (TCSR) . . . . . . . . . . . . . . . 9-9

9.3.4.1

Timer Enable (TE) Bit 0 . . . . . . . . . . . . . . . . . . . . . . . . 9-9

9.3.4.2

Timer Overflow Interrupt Enable (TOIE) Bit 1 . . . . . . . 9-9

9.3.4.3

Timer Compare Interrupt Enable (TCIE) Bit 2 . . . . . . 9-10

9.3.4.4

Timer Control (TC[3:0]) Bits 4-7 . . . . . . . . . . . . . . . . . 9-10

9.3.4.5

Inverter (INV) Bit 8 . . . . . . . . . . . . . . . . . . . . . . . . . . . 9-11

9.3.4.6

Timer Reload Mode (TRM) Bit 9 . . . . . . . . . . . . . . . . 9-13

9.3.4.7

Direction (DIR) Bit 11 . . . . . . . . . . . . . . . . . . . . . . . . . 9-14

9.3.4.8

Data Input (DI) Bit 12 . . . . . . . . . . . . . . . . . . . . . . . . . 9-14

9.3.4.9

Data Output (DO) Bit 13 . . . . . . . . . . . . . . . . . . . . . . . 9-14

9.3.4.10

Prescaler Clock Enable (PCE) Bit 15 . . . . . . . . . . . . . 9-14

9.3.4.11

Timer Overflow Flag (TOF) Bit 20 . . . . . . . . . . . . . . . 9-14

9.3.4.12

Timer Compare Flag (TCF) Bit 21 . . . . . . . . . . . . . . . 9-15

9.3.4.13

TCSR Reserved Bits 3, 10, 14, 16-19, 22, 23 . . . . . . 9-15

9.3.5

Timer Load Register (TLR) . . . . . . . . . . . . . . . . . . . . . . . 9-15

9.3.6

Timer Compare Register (TCPR) . . . . . . . . . . . . . . . . . . 9-16

9.3.7

Timer Count Register (TCR) . . . . . . . . . . . . . . . . . . . . . . 9-16

9.4

TIMER OPERATIONAL MODES. . . . . . . . . . . . . . . . . . . . . 9-16

9.4.1

Timing Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9-17

9.4.1.1

Timer GPIO (Mode 0) . . . . . . . . . . . . . . . . . . . . . . . . . 9-17

9.4.1.2

Timer Pulse (Mode 1) . . . . . . . . . . . . . . . . . . . . . . . . . 9-18

9.4.1.3

Timer Toggle (Mode 2) . . . . . . . . . . . . . . . . . . . . . . . . 9-19

r
e

s
c

l
e

i
c

t
o

r
,

I

Freescale Semiconductor, Inc.

For More Information On This Product,

Go to: www.freescale.com

.
.

MOTOROLA

DSP56309UM/D xiii

9.4.1.4

Timer Event Counter (Mode 3) . . . . . . . . . . . . . . . . . . 9-20

9.4.2

Signal Measurement Modes . . . . . . . . . . . . . . . . . . . . . . 9-20

9.4.2.1

Measurement Accuracy . . . . . . . . . . . . . . . . . . . . . . . 9-21

9.4.2.2

Measurement Input Width (Mode 4) . . . . . . . . . . . . . . 9-21

9.4.2.3

Measurement Input Period (Mode 5) . . . . . . . . . . . . . 9-22

9.4.2.4

Measurement Capture (Mode 6) . . . . . . . . . . . . . . . . . 9-23

9.4.3

Pulse Width Modulation (PWM, Mode 7) . . . . . . . . . . . . . 9-24

9.4.4

Watchdog Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9-25

9.4.4.1

Watchdog Pulse (Mode 9). . . . . . . . . . . . . . . . . . . . . . 9-25

9.4.4.2

Watchdog Toggle (Mode 10). . . . . . . . . . . . . . . . . . . . 9-26

9.4.5

Reserved Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9-27

9.4.6

Special Cases . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9-27

9.4.6.1

Timer Behavior during Wait. . . . . . . . . . . . . . . . . . . . . 9-27

9.4.6.2

Timer Behavior during Stop . . . . . . . . . . . . . . . . . . . . 9-27

9.4.7

DMA Trigger . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9-27

SECTION

ON-CHIP EMULATION MODULE . . . . . . . . . . . . . 10-1

10.1

INTRODUCTION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10-3

10.2

ONCE MODULE SIGNALS . . . . . . . . . . . . . . . . . . . . . . . . . 10-3

10.3

DEBUG EVENT (DE) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10-4

10.4

ONCE CONTROLLER . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10-4

10.4.1

OnCE Command Register (OCR) . . . . . . . . . . . . . . . . . . 10-5

10.4.1.1

10.4.1.2

Exit Command (EX) Bit 5 . . . . . . . . . . . . . . . . . . . . . . 10-5

10.4.1.3

GO Command (GO) Bit 6 . . . . . . . . . . . . . . . . . . . . . . 10-6

10.4.1.4

Read/Write Command (R/W) Bit 7 . . . . . . . . . . . . . . . 10-6

10.4.2

OnCE Decoder (ODEC). . . . . . . . . . . . . . . . . . . . . . . . . . 10-8

10.4.3

OnCE Status and Control Register (OSCR) . . . . . . . . . . 10-8

10.4.3.1

Trace Mode Enable (TME) Bit 0 . . . . . . . . . . . . . . . . . 10-8

10.4.3.2

Interrupt Mode Enable (IME) Bit 1. . . . . . . . . . . . . . . . 10-8

10.4.3.3

Software Debug Occurrence (SWO) Bit 2. . . . . . . . . . 10-8

10.4.3.4

Memory Breakpoint Occurrence (MBO) Bit 3 . . . . . . . 10-8

10.4.3.5

Trace Occurrence (TO) Bit 4 . . . . . . . . . . . . . . . . . . . . 10-9

10.4.3.6

Reserved OCSR Bit 5 . . . . . . . . . . . . . . . . . . . . . . . . . 10-9

10.4.3.7

Core Status (OS0, OS1) Bits 6-7 . . . . . . . . . . . . . . . . 10-9

10.4.3.8

Reserved Bits 8-23 . . . . . . . . . . . . . . . . . . . . . . . . . . . 10-9

r
e

s
c

l
e

i
c

t
o

r
,

I

Freescale Semiconductor, Inc.

For More Information On This Product,

Go to: www.freescale.com

.
.

xiv

DSP56309UM/D MOTOROLA

10.5

ONCE MEMORY BREAKPOINT LOGIC. . . . . . . . . . . . . . . 10-9

10.5.1

OnCE Memory Address Latch (OMAL). . . . . . . . . . . . . 10-11

10.5.2

OnCE Memory Limit Register 0 (OMLR0). . . . . . . . . . . 10-11

10.5.3

OnCE Memory Address Comparator 0 (OMAC0) . . . . . 10-11

10.5.4

OnCE Memory Limit Register 1 (OMLR1). . . . . . . . . . . 10-11

10.5.5

OnCE Memory Address Comparator 1 (OMAC1) . . . . . 10-11

10.5.6

OnCE Breakpoint Control Register (OBCR) . . . . . . . . . 10-12

10.5.6.1

Memory Breakpoint Select (MBS0ÐMBS1) . . . . . . . 10-12

10.5.6.2

Breakpoint 0 Read/Write Select (RW00ÐRW01) . . . 10-12

10.5.6.3

Breakpoint 0 Condition Code Select (CC00ÐCC01). 10-13

10.5.6.4

Breakpoint 1 Read/Write Select (RW10ÐRW11) . . . 10-13

10.5.6.5

Breakpoint 1 Condition Code Select (CC10ÐCC11). 10-14

10.5.6.6

Breakpoint 0 and 1 Event Select (BT0ÐBT1) . . . . . . 10-14

10.5.6.7

OnCE Memory Breakpoint Counter (OMBC) . . . . . . 10-14

10.5.6.8

Reserved Bits 12-15 . . . . . . . . . . . . . . . . . . . . . . . . . 10-15

10.6

ONCE TRACE LOGIC . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10-15

10.7

METHODS OF ENTERING DEBUG MODE . . . . . . . . . . . 10-16

10.7.1

External Debug Request During RESET Assertion . . . 10-16

10.7.2

External Debug Request During Normal Activity . . . . . 10-16

10.7.3

Executing the JTAG DEBUG_REQUEST Instruction . . 10-17

10.7.4

External Debug Request During Stop . . . . . . . . . . . . . . 10-17

10.7.5

External Debug Request During Wait . . . . . . . . . . . . . . 10-17

10.7.6

Software Request During Normal Activity . . . . . . . . . . . 10-18

10.7.7

Enabling Trace Mode . . . . . . . . . . . . . . . . . . . . . . . . . . 10-18

10.7.8

Enabling Memory Breakpoints . . . . . . . . . . . . . . . . . . . 10-18

10.8

PIPELINE INFORMATION AND OGDB REGISTER. . . . . 10-18

10.8.1

OnCE PDB Register (OPDBR) . . . . . . . . . . . . . . . . . . . 10-19

10.8.2

OnCE PIL Register (OPILR) . . . . . . . . . . . . . . . . . . . . . 10-19

10.8.3

OnCE GDB Register (OGDBR). . . . . . . . . . . . . . . . . . . 10-20

10.9

DEBUGGING RESOURCES . . . . . . . . . . . . . . . . . . . . . . . 10-20

10.9.1

OnCE PAB Register for Fetch (OPABFR) . . . . . . . . . . 10-20

10.9.2

PAB Register for Decode (OPABDR) . . . . . . . . . . . . . . 10-20

10.9.3

OnCE PAB Register for Execute (OPABEX) . . . . . . . . 10-20

10.9.4

Trace Buffer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10-21

10.10

SERIAL PROTOCOL DESCRIPTION . . . . . . . . . . . . . . . . 10-22

10.11

TARGET SITE DEBUG SYSTEM REQUIREMENTS . . . . 10-23

r
e

s
c

l
e

i
c

t
o

r
,

I

Freescale Semiconductor, Inc.

For More Information On This Product,

Go to: www.freescale.com

.
.

MOTOROLA

DSP56309UM/D xv

10.12

ONCE MODULE EXAMPLES . . . . . . . . . . . . . . . . . . . . . . 10-23

10.12.1

Checking Whether the Chip Has Entered Debug Mode 10-24

10.12.2

Polling the JTAG Instruction Shift Register . . . . . . . . . . 10-24

10.12.3

Saving Pipeline Information . . . . . . . . . . . . . . . . . . . . . . 10-25

10.12.4

Reading the Trace Buffer. . . . . . . . . . . . . . . . . . . . . . . . 10-25

10.12.5

Displaying a Specified Register . . . . . . . . . . . . . . . . . . . 10-26

10.12.6

Displaying X Memory Area Starting at Address $xxxx . 10-26

10.12.7

Returning from Debug to Normal Mode (Same Program)10-28

10.12.8

Returning from Debug to Normal Mode (New Program) 10-28

10.13

JTAG PORT/ONCE MODULE INTERACTION . . . . . . . . . 10-29

SECTION

JTAG PORT . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11-1

11.1

INTRODUCTION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11-3

11.2

JTAG SIGNALS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11-4

11.2.1

Test Clock (TCK) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11-5

11.2.2

Test Mode Select (TMS) . . . . . . . . . . . . . . . . . . . . . . . . . 11-5

11.2.3

Test Data Input (TDI) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11-5

11.2.4

Test Data Output (TDO) . . . . . . . . . . . . . . . . . . . . . . . . . 11-5

11.2.5

Test Reset (TRST). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11-5

11.3

TAP CONTROLLER . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11-6

11.3.1

Boundary Scan Register (BSR) . . . . . . . . . . . . . . . . . . . . 11-7

11.3.2

Instruction Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11-7

11.3.2.1

EXTEST (B[3:0] = 0000) . . . . . . . . . . . . . . . . . . . . . . . 11-8

11.3.2.2

SAMPLE/PRELOAD (B[3:0] = 0001). . . . . . . . . . . . . . 11-9

11.3.2.3

IDCODE (B[3:0] = 0010) . . . . . . . . . . . . . . . . . . . . . . . 11-9

11.3.2.4

CLAMP (B[3:0] = 0011) . . . . . . . . . . . . . . . . . . . . . . . 11-10

11.3.2.5

HI-Z (B[3:0] = 0100) . . . . . . . . . . . . . . . . . . . . . . . . . 11-10

11.3.2.6

ENABLE_ONCE(B[3:0] = 0110) . . . . . . . . . . . . . . . . 11-11

11.3.2.7

DEBUG_REQUEST(B[3:0] = 0111) . . . . . . . . . . . . . 11-11

11.3.2.8

BYPASS (B[3:0] = 1111) . . . . . . . . . . . . . . . . . . . . . 11-11

11.4

DSP56300 RESTRICTIONS . . . . . . . . . . . . . . . . . . . . . . . 11-12

11.5

DSP56309 BOUNDARY SCAN REGISTER . . . . . . . . . . . 11-13

r
e

s
c

l
e

i
c

t
o

r
,

I

Freescale Semiconductor, Inc.

For More Information On This Product,

Go to: www.freescale.com

.
.

xvi

DSP56309UM/D MOTOROLA

APPENDIX A

BOOTSTRAP PROGRAMS . . . . . . . . . . . . . . . . . . A-1

APPENDIX B

EQUATES . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . B-1

B.1

I/O EQUATES . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . B-3

B.2

HOST INTERFACE (HI08) EQUATES . . . . . . . . . . . . . . . . . B-3

B.3

SCI EQUATES. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . B-4

B.4

ESSI EQUATES . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . B-5

B.5

EXCEPTION PROCESSING EQUATES . . . . . . . . . . . . . . . B-7

B.6

TIMER MODULE EQUATES . . . . . . . . . . . . . . . . . . . . . . . . B-9

B.7

DIRECT MEMORY ACCESS (DMA) EQUATES . . . . . . . . B-10

B.8

PHASE-LOCKED LOOP (PLL) EQUATES . . . . . . . . . . . . . B-12

B.9

BUS INTERFACE UNIT (BIU) EQUATES . . . . . . . . . . . . . B-13

B.10

INTERRUPT EQUATES . . . . . . . . . . . . . . . . . . . . . . . . . . . B-15

APPENDIX C

DSP56309 BSDL LISTING . . . . . . . . . . . . . . . . . . . C-1

APPENDIX D

PROGRAMMING REFERENCE . . . . . . . . . . . . . . . D-1

D.1

INTRODUCTION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . D-3

D.1.1

Peripheral Addresses . . . . . . . . . . . . . . . . . . . . . . . . . . . . D-3

D.1.2

Interrupt Addresses. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . D-3

D.1.3

Interrupt Priorities . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . D-3

D.1.4

Programming Sheets . . . . . . . . . . . . . . . . . . . . . . . . . . . . D-3

D.2

INTERNAL I/O MEMORY MAP . . . . . . . . . . . . . . . . . . . . . . . D-4

D.3

INTERRUPT ADDRESSES AND SOURCES . . . . . . . . . . . D-11

D.4

INTERRUPT PRIORITIES. . . . . . . . . . . . . . . . . . . . . . . . . . D-13

r
e

s
c

l
e

i
c

t
o

r
,

I

Freescale Semiconductor, Inc.

For More Information On This Product,

Go to: www.freescale.com

.
.

xviii

DSP56309UM/D MOTOROLA

Figure 6-4

Host Base Address Register (HBAR) (X:$FFFFC5). . . . . . . . . . 6-12

Figure 6-5

Self Chip Select Logic . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-12

Figure 6-6

Host Port Control Register (HPCR) (X:$FFFFC4) . . . . . . . . . . . 6-13

Figure 6-7

Single Strobe Bus. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-15

Figure 6-8

Dual Strobe Bus . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-16

Figure 6-9

Host Data Direction Register (HDDR) (X:$FFFFC8) . . . . . . . . . 6-17

Figure 6-10

Host Data Register (HDR) (X:$FFFFC9) . . . . . . . . . . . . . . . . . . 6-17

Figure 6-11

HSR-HCR Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-20

Figure 6-12

Interface Control Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-22

Figure 6-13

Command Vector Register (CVR) . . . . . . . . . . . . . . . . . . . . . . . 6-25

Figure 6-14

Interface Status Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-26

Figure 6-15

Interrupt Vector Register (IVR). . . . . . . . . . . . . . . . . . . . . . . . . . 6-28

Figure 6-16

HI08 Host Request Structure . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-33

Figure 7-1

ESSI Block Diagram. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-5

Figure 7-2

ESSI Control Register A (CRA) . . . . . . . . . . . . . . . . . . . . . . . . . . 7-9

Figure 7-3

ESSI Control Register B (CRB) . . . . . . . . . . . . . . . . . . . . . . . . . . 7-9

Figure 7-4

ESSI Status Register (SSISR) . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-9

Figure 7-5

ESSI Transmit Slot Mask Register A (TSMA) . . . . . . . . . . . . . . 7-10

Figure 7-6

ESSI Transmit Slot Mask Register B (TSMB) . . . . . . . . . . . . . . 7-10

Figure 7-7

ESSI Receive Slot Mask Register A (RSMA). . . . . . . . . . . . . . . 7-10

Figure 7-8

ESSI Receive Slot Mask Register B (RSMB). . . . . . . . . . . . . . . 7-10

Figure 7-9

ESSI Clock Generator Functional Block Diagram . . . . . . . . . . . 7-12

r
e

s
c

l
e

i
c

t
o

r
,

I

Freescale Semiconductor, Inc.

For More Information On This Product,

Go to: www.freescale.com

.
.

MOTOROLA

DSP56309UM/D xix

Figure 7-10

ESSI Frame Sync Generator Functional Block Diagram. . . . . . 7-13

Figure 7-11

CRB FSL0 and FSL1 Bit Operation (FSR = 0) . . . . . . . . . . . . . 7-19

Figure 7-12

CRB SYN Bit Operation. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-20

Figure 7-13

CRB MOD Bit Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-21

Figure 7-14

Normal Mode, External Frame Sync (8 Bit, 1 Word in Frame) . 7-22

Figure 7-15

Network Mode, External Frame Sync (8 Bit, 2 Words in Frame) 7-23

Figure 7-16

ESSI Data Path Programming Model (SHFD = 0). . . . . . . . . . . 7-31

Figure 7-17

ESSI Data Path Programming Model (SHFD = 1). . . . . . . . . . . 7-32

Figure 7-18

Port Control Register (PCR) (PCRC X:$FFFFBF). . . . . . . . . . . 7-44

Figure 7-19

Port Direction Register (PRR)(PRRC X:$FFFFBE). . . . . . . . . . 7-44

Figure 7-20

Port Data Register (PDR) (PDRC X:$FFFFBD) . . . . . . . . . . . . 7-45

Figure 8-1

SCI Control Register (SCR). . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8-5

Figure 8-2

SCI Status Register (SSR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8-5

Figure 8-3

SCI Clock Control Register (SCCR) . . . . . . . . . . . . . . . . . . . . . . 8-5

Figure 8-4

SCI Data Word Formats . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8-6

Figure 8-5

16 x Serial Clock . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8-16

Figure 8-6

SCI Baud Rate Generator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8-18

Figure 8-7

SCI Programming Model Data Registers . . . . . . . . . . . . . . . . . 8-19

Figure 8-8

Port E Control Register (PCRE) . . . . . . . . . . . . . . . . . . . . . . . . 8-27

Figure 8-9

Port E Direction Register (PRRE) . . . . . . . . . . . . . . . . . . . . . . . 8-28

Figure 8-10

Port E Data Register (PDRE) . . . . . . . . . . . . . . . . . . . . . . . . . . 8-29

Figure 9-1

Triple Timer Module Block Diagram . . . . . . . . . . . . . . . . . . . . . . 9-4

r
e

s
c

l
e

i
c

t
o

r
,

I

Freescale Semiconductor, Inc.

For More Information On This Product,

Go to: www.freescale.com

.
.

DSP56309UM/D MOTOROLA

Figure 9-2

Timer Module Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9-5

Figure 9-3

Timer Module ProgrammerÕs Model . . . . . . . . . . . . . . . . . . . . . . . 9-6

Figure 9-4

Timer Prescaler Load Register (TPLR) . . . . . . . . . . . . . . . . . . . . 9-7

Figure 9-5

Timer Prescaler Count Register (TPCR) . . . . . . . . . . . . . . . . . . . 9-8

Figure 9-6

Timer Control/Status Register . . . . . . . . . . . . . . . . . . . . . . . . . . . 9-9

Figure 10-1

OnCE Module Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . 10-3

Figure 10-2

OnCE Module Multiprocessor Configuration . . . . . . . . . . . . . . . 10-4

Figure 10-3

OnCE Controller Block Diagram. . . . . . . . . . . . . . . . . . . . . . . . . 10-5

Figure 10-4

OnCE Command Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10-5

Figure 10-5

OnCE Status and Control Register (OSCR). . . . . . . . . . . . . . . . 10-8

Figure 10-6

OnCE Memory Breakpoint Logic 0. . . . . . . . . . . . . . . . . . . . . . 10-10

Figure 10-7

OnCE Breakpoint Control Register (OBCR). . . . . . . . . . . . . . . 10-12

Figure 10-8

OnCE Trace Logic Block Diagram . . . . . . . . . . . . . . . . . . . . . . 10-15

Figure 10-9

OnCE Pipeline Information and GDB Registers . . . . . . . . . . . 10-19

Figure 10-10

OnCE Trace Buffer. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10-22

Figure 11-1

TAP Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11-4

Figure 11-2

TAP Controller State Machine . . . . . . . . . . . . . . . . . . . . . . . . . . 11-6

Figure 11-3

JTAG Instruction Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11-7

Figure 11-4

JTAG ID Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11-9

Figure 11-5

Bypass Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11-11

Figure D-1

Status Register (SR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . D-15

Figure D-2

Operating Mode Register (OMR) . . . . . . . . . . . . . . . . . . . . . . . . D-16

r
e

s
c

l
e

i
c

t
o

r
,

I

Freescale Semiconductor, Inc.

For More Information On This Product,

Go to: www.freescale.com

.
.

MOTOROLA

DSP56309UM/D xxi

Figure D-3

Interrupt Priority RegisterÐCore (IPRÐC). . . . . . . . . . . . . . . . . . D-17

Figure D-4

Interrupt Priority Register Ð Peripherals (IPRÐP). . . . . . . . . . . . D-18

Figure D-5

Phase-Locked Loop Control Register (PCTL) . . . . . . . . . . . . . . D-19

Figure D-6

Host Receive and Host Transmit Data Registers . . . . . . . . . . . D-20

Figure D-7

Host Control and Host Status Registers . . . . . . . . . . . . . . . . . . D-21

Figure D-8

Host Base Address and Host Port Control Registers . . . . . . . . D-22

Figure D-9

Interrupt Control and Interrupt Status Registers . . . . . . . . . . . . D-23

Figure D-10

Interrupt Vector and Command Vector Registers . . . . . . . . . . . D-24

Figure D-11

Host Receive and Host Transmit Data Registers . . . . . . . . . . . D-25

Figure D-12

ESSI Control Register A (CRA) . . . . . . . . . . . . . . . . . . . . . . . . . D-26

Figure D-13

ESSI Control Register B (CRB) . . . . . . . . . . . . . . . . . . . . . . . . . D-27

Figure D-14

ESSI Status Register (SSISR). . . . . . . . . . . . . . . . . . . . . . . . . . D-28

Figure D-15

ESSR Transmit and Receive Slot Mask Registers (TSM, RSM) D-29

Figure D-16

SCI Control Register (SCR). . . . . . . . . . . . . . . . . . . . . . . . . . . . D-30

Figure D-17

SCI Status and Clock Control Registers (SSR, SCCR). . . . . . . D-31

Figure D-18

SCI Receive and Transmit Data Registers (SRX, TRX) . . . . . . D-32

Figure D-19

Timer Prescaler Load/Count Register (TPLR, TPCR). . . . . . . . D-33

Figure D-20

Timer Control/Status Register (TCSR) . . . . . . . . . . . . . . . . . . . D-34

Figure D-21

Timer Load, Compare, Count Registers (TLR, TCPR, TCR) . . D-35

Figure D-22

Host Data Direction and Host Data Registers (HDDR, HDR) . . D-36

Figure D-23

Port C Registers (PCRC, PRRC, PDRC) . . . . . . . . . . . . . . . . . D-37

Figure D-24

Port D Registers (PCRD, PRRD, PDRD) . . . . . . . . . . . . . . . . . D-38

r
e

s
c

l
e

i
c

t
o

r
,

I

Freescale Semiconductor, Inc.

For More Information On This Product,

Go to: www.freescale.com

.
.

MOTOROLA

DSP56309UM/D xxiii

LIST OF TABLES

Table 1-1

High True/Low True Signal Conventions . . . . . . . . . . . . . . . . . . 1-5

Table 1-2

On Chip Memory . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-12

Table 2-1

DSP56309 Functional Signal Groupings . . . . . . . . . . . . . . . . . . 2-3

Table 2-2

Power Inputs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-5

Table 2-3

Grounds . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-6

Table 2-4

Clock Signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-7

Table 2-5

Phase-Locked Loop Signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-8

Table 2-6

External Address Bus Signals . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-9

Table 2-7

External Data Bus Signals. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-10

Table 2-8

External Bus Control Signals . . . . . . . . . . . . . . . . . . . . . . . . . . 2-10

Table 2-9

Interrupt and Mode Control . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-14

Table 2-10

Host Port Usage Considerations . . . . . . . . . . . . . . . . . . . . . . . 2-17

Table 2-11

Host Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-18

Table 2-12

Enhanced Synchronous Serial Interface 0 (ESSI0) . . . . . . . . . 2-24

Table 2-13

Enhanced Synchronous Serial Interface 1 (ESSI1) . . . . . . . . . 2-28

Table 2-14

Serial Communication Interface (SCI) . . . . . . . . . . . . . . . . . . . 2-32

Table 2-15

Triple Timer Signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-34

Table 2-16

OnCE/JTAG Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-35

Table 3-1

Memory Space Configuration Bit Settings for the DSP56309 . . . 3-5

r
e

s
c

l
e

i
c

t
o

r
,

I

Freescale Semiconductor, Inc.

For More Information On This Product,

Go to: www.freescale.com

.
.

xxiv

DSP56309UM/D MOTOROLA

Table 3-2

RAM Configuration Bit Settings for the DSP56309 . . . . . . . . . . . 3-5

Table 3-3

Memory Space Configurations for the DSP56309 . . . . . . . . . . . . 3-7

Table 3-4

RAM Configurations for the DSP56309 . . . . . . . . . . . . . . . . . . . . 3-8

Table 3-5

Memory Locations for Program RAM and Instruction Cache . . . . 3-8

Table 3-6

Memory Locations for Data RAM . . . . . . . . . . . . . . . . . . . . . . . . . 3-9

Table 4-1

DSP56309 Operating Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-4

Table 4-2

Interrupt Sources . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-10

Table 4-3

Interrupt Priority Level Bits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-12

Table 4-4

Interrupt Source Priorities within an IPL . . . . . . . . . . . . . . . . . . 4-14

Table 4-5

DMA Request Sources . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-16

Table 6-1

HI08 Signal Definitions for Various Operational Modes . . . . . . . . 6-6

Table 6-2

HI08 Data Strobe Signals. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-6

Table 6-3

HI08 Host Request Signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-6

Table 6-4

Host Command Interrupt Priority List . . . . . . . . . . . . . . . . . . . . . 6-10

Table 6-5

HDR and HDDR Functionality . . . . . . . . . . . . . . . . . . . . . . . . . 6-18

Table 6-6

DSP Side Registers after Reset . . . . . . . . . . . . . . . . . . . . . . . . . 6-19

Table 6-7

Host Side Register Map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-22

Table 6-8

TREQ and RREQ modes (HDRQ = 0) . . . . . . . . . . . . . . . . . . . . 6-23

Table 6-9

TREQ and RREQ modes (HDRQ = 1) . . . . . . . . . . . . . . . . . . . . 6-23

Table 6-10

INIT Command Effects . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-25

Table 6-11

HREQ and HDRQ Settings . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-28

Table 6-12

Host Side Registers After Reset. . . . . . . . . . . . . . . . . . . . . . . . . 6-30

r
e

s
c

l
e

i
c

t
o

r
,

I

Freescale Semiconductor, Inc.

For More Information On This Product,

Go to: www.freescale.com

.
.

MOTOROLA

DSP56309UM/D xxv

Table 6-13

HI08 Programming Model . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-34

Table 7-1

ESSI Clock Sources . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-8

Table 7-2

ESSI Word Length Selection . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-14

Table 7-3

FSL1 and FSL0 Encoding . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-17

Table 7-4

Mode and Signal Definition Table . . . . . . . . . . . . . . . . . . . . . . 7-24

Table 7-5

Port Control Register and Port Direction Register Bits . . . . . . . 7-45

Table 8-1

Word Formats . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8-8

Table 8-2

TCM and RCM Bit Configuration . . . . . . . . . . . . . . . . . . . . . . . 8-17

Table 8-3

SCI Registers after Reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8-23

Table 8-4

Port Control Register and Port Direction Register Bits . . . . . . . 8-28

Table 9-1

Prescaler Source Selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9-8

Table 9-2

Timer Control Bits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9-10

Table 9-3

Inverter (INV) Bit Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . 9-12

Table 10-1

EX Bit Definition. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10-6

Table 10-2

GO Bit Definition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10-6

Table 10-3

R/W Bit Definition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10-6

Table 10-4

OnCE Register Select Encoding . . . . . . . . . . . . . . . . . . . . . . . 10-6

Table 10-5

Core Status Bits Description . . . . . . . . . . . . . . . . . . . . . . . . . . . 10-9

Table 10-6

Memory Breakpoint 0 and 1 Select Table . . . . . . . . . . . . . . . . 10-12

Table 10-7

Breakpoint 0 Read/Write Select Table . . . . . . . . . . . . . . . . . . 10-13

Table 10-8

Breakpoint 0 Condition Select Table . . . . . . . . . . . . . . . . . . . 10-13

Table 10-9

Breakpoint 1 Read/Write Select Table . . . . . . . . . . . . . . . . . . 10-13

r
e

s
c

l
e

i
c

t
o

r
,

I

Freescale Semiconductor, Inc.

For More Information On This Product,

Go to: www.freescale.com

.
.

DSP56309 Overview

Manual Conventions

MOTOROLA

DSP56309UM/D 1-5

1.3

MANUAL CONVENTIONS

This manual uses the following conventions:

¥ Bits within registers are always listed from most significant bit (MSB) to least

significant bit (LSB).

¥ Bits within a register are indicated AA[n:m], n>m, when more than one bit is

involved in a description. For purposes of description, the bits are presented as if
they are contiguous within a register. However, this is not always the case. Refer
to the programming model diagrams or to the programmerÕs sheets to see the
exact location of bits within a register.

¥ When a bit is described as Òset,Ó its value is 1. When a bit is described as

Òcleared,Ó its value is 0.

¥ The word ÒassertÓ means that a high true (active high) signal is pulled high to

or that a low true (active low) signal is pulled low to ground. The word

ÒdeassertÓ means that a high true signal is pulled low to ground or that a low true
signal is pulled high to V

. See

Table 1-1

¥ Pins or signals that are asserted low (made active when pulled to ground)

Ð In text, have an overbar. For example, RESET is asserted low.

Ð In code examples, have a tilde in front of their names. In

Example 1-1

, line 3

refers to the SS0 signal (shown as

~SS0

Table 1-1

High True/Low True Signal Conventions

Signal/Symbol

Logic State

Signal State

Voltage

True

Asserted

Ground

False

Deasserted

True

Asserted

False

Deasserted

Ground

PIN is a generic term for any pin on the chip.

Ground is an acceptable low voltage level. See the
appropriate data sheet for the range of acceptable low
voltage levels (typically a TTL logic low).

is an acceptable high voltage level. See the

appropriate data sheet for the range of acceptable high
voltage levels (typically a TTL logic high).

r
e

s
c

l
e

i
c

t
o

r
,

I

Freescale Semiconductor, Inc.

For More Information On This Product,

Go to: www.freescale.com

.
.

1-6

DSP56309UM/D MOTOROLA

DSP56309 Overview

DSP56309 Features

¥ Sets of signals are indicated by the first and last signals in the set, for instance

HA1ÐHA8.

¥ Code examples are displayed in a monospaced font, as shown in Example 1-1.

¥ Hex values are indicated with a dollar sign ($) preceding the hex value. For

example, $FFFFFF is the X memory address for the core interrupt priority register
(IPR-C).

¥ The word ÔresetÕ is used in four different contexts in this manual:

Ð the reset signal, written as RESET;

Ð the reset instruction, written as RESET;

Ð the reset operating state, written as Reset; and

Ð the reset function, written as reset.

1.4

DSP56309 FEATURES

The DSP56309 is a member of the DSP56300 family of programmable CMOS DSPs. The
DSP56309 uses the DSP56300 core, a high-performance engine with a single clock cycle
per instruction. The DSP56300 core provides up to twice the performance of Motorola's
popular DSP56000 core family, while retaining code compatibility.

The DSP56300 core family offers a new level of performance in speed and power
provided by its rich instruction set and low-power dissipation, enabling a new
generation of wireless, telecommunications, and multimedia products. The DSP56300
core is composed of the data arithmetic logic unit (Data ALU), address generation unit
(AGU), program controller (PC), instruction cache controller, bus interface unit, direct
memory access (DMA) controller, On-Chip Emulation (OnCE) module, and a PLL-based
clock oscillator. Significant architectural enhancements to the DSP56300 core family
include a barrel shifter, 24-bit addressing, an instruction cache, and DMA.

The DSP56300 core family members contain the DSP56300 core and additional modules.
The modules are chosen from a library of standard pre-designed elements, such as
memories and peripherals. New modules can be added to the library to meet customer

Example 1-1

Sample Code Listing

BFSET

#$0007,X:PCC; Configure:

line 1

; MISO0, MOSI0, SCK0 for SPI master

line 2

; ~SS0 as PC3 for GPIO

line 3

r
e

s
c

l
e

i
c

t
o

r
,

I

Freescale Semiconductor, Inc.

For More Information On This Product,

Go to: www.freescale.com

.
.

DSP56309 Overview

DSP56300 Core Functional Blocks

MOTOROLA

DSP56309UM/D 1-9

All the Data ALU operations are performed in two clock cycles in pipeline fashion so
that a new instruction can be initiated in every clock, yielding an effective execution rate
of one instruction per clock cycle. The destination of every arithmetic operation can be
used as a source operand for the immediately following operation without penalty.

1.6.1.2

Multiplier-Accumulator (MAC)

The MAC unit comprises the main arithmetic processing unit of the DSP56300 core and
performs all of the calculations on data operands. For arithmetic instructions, the unit
accepts as many as three input operands and outputs one 56-bit result of the following
form, Extension:Most Significant Product:Least Significant Product (EXT:MSP:LSP).

The multiplier executes 24-bit

´ 24-bit, parallel, fractional multiplies between

twos-complement signed, unsigned, or mixed operands. The 48-bit product is
right-justified and added to the 56-bit contents of either the A or B accumulator. A 56-bit
result can be stored as a 24-bit operand. The LSP can either be truncated or rounded into
the MSP. Rounding is performed if specified.

1.6.2

Address Generation Unit (AGU)

The AGU performs the effective address calculations using integer arithmetic necessary
to address data operands in memory and contains the registers that generate the
addresses. It implements four types of arithmetic: linear, modulo, multiple wrap-around
modulo, and reverse-carry. The AGU operates in parallel with other chip resources to
minimize address-generation overhead.

The AGU is divided into two halves, each with its own address arithmetic logic unit
(Address ALU). Each Address ALU has four sets of register triplets, and each register
triplet is composed of an address register, an offset register, and a modifier register. The
two Address ALUs are identical. Each contains a 16-bit full adder (called an offset
adder).

A second full adder (called a modulo adder) adds the summed result of the first full
adder to a modulo value that is stored in its respective modifier register. A third full
adder (called a reverse-carry adder) is also provided.

The offset adder and the reverse-carry adder are in parallel and share common inputs.
The only difference between them is that they carry propagates in opposite directions.
Test logic determines which of the three summed results of the full adders is output.

Each Address ALU can update one address register from its respective address register
file during one instruction cycle. The contents of the associated modifier register

r
e

s
c

l
e

i
c

t
o

r
,

I

Freescale Semiconductor, Inc.

For More Information On This Product,

Go to: www.freescale.com

.
.

DSP56309 Overview

DSP56300 Core Functional Blocks

MOTOROLA

DSP56309UM/D 1-11

¥ SPÑstack pointer

¥ OMRÑoperating mode register

¥ SCÑstack counter register

The PCU also includes a hardware system stack (SS).

1.6.4

PLL and Clock Oscillator

The clock generator in the DSP56300 core is composed of two main blocks: the PLL,
which performs clock input division, frequency multiplication, and skew elimination;
and the clock generator (CLKGEN), which performs low-power division and clock pulse
generation.

¥ Allows change of low-power divide factor (DF) without loss of lock

¥ Output clock with skew elimination

The PLL allows the processor to operate at a high internal clock frequency using a
low-frequency clock input, a feature that offers two immediate benefits:

¥ A lower-frequency clock input reduces the overall electromagnetic interference

generated by a system.

¥ The ability to oscillate at different frequencies reduces costs by eliminating the

need to add additional oscillators to a system.

1.6.5

JTAG TAP and OnCE Module

The DSP56300 core provides a dedicated user-accessible Test Access Port (TAP) that is
fully compatible with the IEEE 1149.1 Standard Test Access Port and Boundary Scan
Architecture. Problems associated with testing high density circuit boards have led to
development of this standard under the sponsorship of the Test Technology Committee
of IEEE and the Joint Test Action Group (JTAG). The DSP56300 core implementation
supports circuit-board test strategies based on this standard.

The test logic includes a TAP consisting of four dedicated signals, a 16-state controller,
and three test data registers. A boundary scan register links all device signals into a
single shift register. The test logic, implemented utilizing static logic design, is
independent of the device system logic. More information on the JTAG port is provided
in Section 11ÑJTAG Port

r
e

s
c

l
e

i
c

t
o

r
,

I

Freescale Semiconductor, Inc.

For More Information On This Product,

Go to: www.freescale.com

.
.

1-12

DSP56309UM/D MOTOROLA

DSP56309 Overview

DSP56300 Core Functional Blocks

The OnCE module provides a means of interacting with the DSP56300 core and its
peripherals non-intrusively so that a user can examine registers, memory, or on-chip
peripherals. This facilitates hardware and software development on the DSP56300 core
processor. OnCE module functions are provided through the JTAG TAP signals. More
information about the OnCE module is provided in Section 10ÑOn-Chip Emulation
Module

1.6.6

On-Chip Memory

The memory space of the DSP56300 core is partitioned into program memory space,
X data memory space, and Y data memory space. The data memory space is divided into
X data memory and Y data memory in order to work with the two Address ALUs and to
feed two operands simultaneously to the Data ALU. Memory space includes internal
RAM and ROM and can be expanded off-chip under software control. More information
about the internal memory is provided in Section 3ÑMemory Configuration.

Program RAM, instruction cache, X data RAM, and Y data RAM size are programmable,
as indicated in Table 1-2.

Table 1-2

On Chip Memory

There is an on-chip 192 x 24-bit bootstrap ROM.

1.6.7

Off-Chip Memory Expansion

Memory can be expanded off-chip to do the following:

¥ Data memory expansion to two 256K

´ 24-bit word memory spaces (or up to two

´ 24-bit word memory spaces by using the address attribute AA0ÐAA3 signals)

¥ Program memory expansion to one 256K

´ 24-bit words memory space (or up to

one

4 M

´ 24-bit word memory space by using the address attribute AA0ÐAA3 signals)

Additional features of off-chip memory include the following:

Instruction

Cache

Switch

Mode

Program RAM

Size

Instruction

Cache Size

X Data RAM

Size

Y Data RAM

Size

disabled

20K

´ 24-bit

enabled

disabled

19K

´ 24-bit

disabled

enabled

24K

´ 24-bit

enabled

23K

´ 24-bit

r
e

s
c

l
e

i
c

t
o

r
,

I

Freescale Semiconductor, Inc.

For More Information On This Product,

Go to: www.freescale.com

.
.

DSP56309 Overview

Direct Memory Access (DMA)

MOTOROLA

DSP56309UM/D 1-15

1.9

DIRECT MEMORY ACCESS (DMA)

The DMA block has the following features:

¥ Six DMA channels supporting internal and external accesses

¥ One-, two-, and three-dimensional transfers (including circular buffering)

¥ End-of-block-transfer interrupts

¥ Triggering from interrupt lines, all peripherals, and DMA channels

1.10

DSP56309 ARCHITECTURE OVERVIEW

The DSP56309 performs a wide variety of fixed-point digital signal processing functions.
In addition to the core features previously discussed, the DSP56309 provides the
following peripherals:

¥ Enhanced DSP56000-like 8-bit parallel host interface (HI08) supports a variety of

buses (e.g., industry standard architecture) and provides glueless connection to a
number of industry standard microcomputers, microprocessors, and DSPs

¥ Two enhanced synchronous serial interfaces (ESSI0 and ESSI1), each with one

receiver and three transmitters (allows six-channel home theater)

¥ Serial communications interface (SCI) with baud rate generator

¥ Triple timer module

¥ Up to 34 programmable general purpose input/output (GPIO) pins, depending

on which peripherals are enabled

1.10.1

GPIO Functionality

The GPIO port consists of as many as thirty-four programmable signals, all of which are
also used by the peripherals (HI08, ESSI, SCI, and timer). There are no dedicated GPIO
signals. Peripheral pins are configured as GPIO inputs after any reset. (Data in the port
data register is not affected by a reset.) The GPIO functionality for each peripheral is
controlled by three memory-mapped registers per peripheral. The techniques for
register programming for all GPIO functionality is very similar between these interfaces.

r
e

s
c

l
e

i
c

t
o

r
,

I

Freescale Semiconductor, Inc.

For More Information On This Product,

Go to: www.freescale.com

.
.

1-16

DSP56309UM/D MOTOROLA

DSP56309 Overview

DSP56309 Architecture Overview

1.10.2

Host Interface (HI08)

The HI08 is a byte-wide, full-duplex, double-buffered, parallel port that can connect
directly to the data bus of a host processor. The HI08 supports a variety of buses and
connects to a number of industry-standard DSPs, microcomputers, and microprocessors
without requiring additional logic.

The DSP core treats the HI08 as a memory-mapped peripheral occupying eight 24-bit
words in data memory space. The DSP can use the HI08 as a memory-mapped
peripheral, using either standard polled or interrupt programming techniques. Separate
transmit and receive data registers are double-buffered to allow the DSP and host
processor to transfer data efficiently at high speed. Memory mapping allows DSP core
communication with the HI08 registers using standard instructions and addressing
modes.

1.10.3

Enhanced Synchronous Serial Interface (ESSI)

On the DSP56309 are two independent and identical ESSIs. Each ESSI has a full-duplex
serial port for communication with a variety of serial devices, including one or more
industry-standard codecs, other DSPs, microprocessors, and peripherals that implement
the Motorola SPI. The ESSI consists of independent transmitter and receiver sections and
a common ESSI clock generator.

The capabilities of the ESSI include the following:

¥ Independent (asynchronous) or shared (synchronous) transmit and receive

sections with separate or shared internal/external clocks and frame syncs

¥ Normal mode operation using frame sync

¥ Network mode operation with as many as 32 time slots

¥ Programmable word length (8, 12, or 16 bits)

¥ Program options for frame synchronization and clock generation

¥ One receiver and three transmitters per ESSI allows six-channel home theater

1.10.4

Serial Communications Interface (SCI)

The DSP56309Õs SCI provides a full-duplex port for serial communication with other
DSPs, microprocessors, or peripherals such as modems. The SCI interfaces without

r
e

s
c

l
e

i
c

t
o

r
,

I

Freescale Semiconductor, Inc.

For More Information On This Product,

Go to: www.freescale.com

.
.

DSP56309 Overview

DSP56309 Architecture Overview

MOTOROLA

DSP56309UM/D 1-17

additional logic to peripherals that use TTL-level signals. With a small amount of
additional logic, the SCI can connect to peripheral interfaces that have non-TTL level
signals, such as the RS-232C, RS-422, etc.

(

up to 8.25 Mbps for a

66 MHz clock). The asynchronous protocols supported by the SCI include a multidrop
mode for master/slave operation with wakeup on idle line and wakeup on address bit
capability. This mode allows the DSP56309 to share a single serial line efficiently with
other peripherals.

The SCI consists of separate transmit and receive sections that can operate
asynchronously with respect to each other. A programmable baud-rate generator
provides the transmit and receive clocks. An enable vector and an interrupt vector have
been included so that the baud-rate generator can function as a general purpose timer
when it is not being used by the SCI or when the interrupt timing is the same as that
used by the SCI.

1.10.5

Timer Module

The triple timer module is composed of a common 21-bit prescaler and three
independent and identical general-purpose 24-bit timer/event counters, each with its
own memory-mapped register set.

Each timer has a single signal that can function as a GPIO signal or as a timer signal.
Each timer can use internal or external clocking and can interrupt the DSP after a
specified number of events (clocks) or can signal an external device after counting
internal events. Each timer connects to the external world through one bidirectional
signal. When this signal is configured as an input, the timer can function as an external
event counter or measures external pulse width/signal period. When the signal is used
as an output, the timer can function as either a timer, a watchdog, or a Pulse Width
Modulator (PWM).

r
e

s
c

l
e

i
c

t
o

r
,

I

Freescale Semiconductor, Inc.

For More Information On This Product,

Go to: www.freescale.com

.
.

2-4

DSP56309UM/D MOTOROLA

Signal/Connection Descriptions

Signal Groupings

Figure 2-1

Signals Identified by Functional Group

DSP56309

Timers

OnCE/JTAG

PLL
Core Logic
I/O
Address Bus
Data Bus
Bus Control
HI08
ESSI/SCI/Timer

A0ÐA17

D0ÐD23

TCK
TDI
TDO
TMS
TRST
DE

CLKOUT

PCAP

After

Reset

NMI

CCP

CCQL

CCQH

CCA

CCD

CCC

CCH

CCS

Serial Communications Interface (SCI)

GND

4
4

MODA
MODB
MODC
MODD
RESET

Non-Multiplexed
Bus
H0ÐH7
HA0
HA1
HA2
HCS/HCS
Single DS
HRW
HDS/HDS
Single HR
HREQ/HREQ
HACK/HACK

RXD

TXD
SCLK

SC00ÐSC02
SCK0
SRD0
STD0

TIO0
TIO1
TIO2

EXTAL

XTAL

SC10ÐSC12
SCK1
SRD1
STD1

Multiplexed
Bus
HAD0ÐHAD7
HAS/HAS
HA8
HA9
HA10
Double DS
HRD/HRD
HWR/HWR
Double HR
HTRQ/HTRQ
HRRQ/HRRQ

Port B
GPIO
PB0ÐPB7
PB8
PB9
PB10
PB13

PB11
PB12

PB14
PB15

Port E GPIO

PE0

PE1
PE2

Port C GPIO
PC0ÐPC2
PC3
PC4
PC5

Port D GPIO
PD0ÐPD2
PD3
PD4
PD5

GPIO
TIO0
TIO1
TIO2

Port A

AA0601

Notes:

The HI08 port supports a non-multiplexed or a multiplexed bus, single or double Data Strobe (DS), and single or
double Host Request (HR) configurations. Since each of these modes is configured independently, any combination
of these modes is possible. These HI08 signals can also be configured alternately as GPIO signals (PB0ÐPB15).
Signals with dual designations (e.g., HAS/HAS) have configurable polarity.

The ESSI0, ESSI1, and SCI signals are multiplexed with the Port C GPIO signals (PC0ÐPC5), Port D GPIO signals
(PD0ÐPD5), and Port E GPIO signals (PE0ÐPE2), respectively.

TIO0ÐTIO2 can be configured as GPIO signals.

IRQA
IRQB
IRQC
IRQD

PINIT

RESET

During Reset

After Reset

Reset

During

Power Inputs

Host Interface (H108)

Enhanced Synchronous Serial Interface (ESSI0)

Clock

EXTERNAL MEMORY INTERFACE

PLL
PLL
Internal Logic
Address Bus
Data Bus
Bus Control
HI08
ESSI/SCI/Timer

AA0ÐAA3/

RAS0ÐRAS3

CAS

BCLK
BCLK

Enhanced Synchronous Serial Interface (ESSI1)

Port C

Port D

Port E

Port B

Grounds

PLL

r
e

s
c

l
e

i
c

t
o

r
,

I

Freescale Semiconductor, Inc.

For More Information On This Product,

Go to: www.freescale.com

.
.

Signal/Connection Descriptions

Power

MOTOROLA

DSP56309UM/D 2-5

2.2

POWER

Power input descriptions for the DSP56309 are listed in Table 2-2.

Table 2-2

Power Inputs

Power Name

Description

CCP

PLL Power

ÑV

CCP

is power dedicated for phase-locked loop (PLL) use.

The voltage should be well regulated, and the input should be provided
with an extremely low impedance path to the V

power rail. V

CCP

should be bypassed to GND

by a stabilizing capacitor located as close

as possible to the chip package. There is one V

CCP

input.

CCQL

(4)

Quiet Core (Low) Power

ÑV

CCQL

is an isolated power for the core

processing logic. This input must be isolated externally from all other
chip power inputs. The user must provide adequate external decoupling
capacitors. There are four V

CCQL

inputs.

CCQH

(3)

Quiet External (High) Power

ÑV

CCQH

is a quiet power source for I/O

lines. This input must be tied externally to all other chip power inputs,
except V

CCQL

. The user must provide adequate external decoupling

capacitors. There are three V

CCQH

inputs.

CCA

(3)

Address Bus Power

ÑV

CCA

is an isolated power for sections of the

address bus I/O drivers. This input must be tied externally to all other
chip power inputs except V

CCQL

. The user must provide adequate

external decoupling capacitors. There are three V

CCA

inputs.

CCD

(4)

Data Bus Power

ÑV

CCD

is an isolated power for sections of the data bus

I/O drivers. This input must be tied externally to all other chip power
inputs. The user must provide adequate external decoupling capacitors.
There are four V

CCD

inputs.

CCC

(2)

Bus Control Power

ÑV

CCC

is an isolated power for the bus control I/O

drivers. This input must be tied externally to all other chip power inputs
except V

CCQL

. The user must provide adequate external decoupling

capacitors. There are two V

CCC

inputs.

CCH

Host Power

ÑV

CCH

is an isolated power for the HI08 I/O drivers. This

input must be tied externally to all other chip power inputs except
V

CCQL

. The user must provide adequate external decoupling capacitors.

There is one V

CCH

input.

r
e

s
c

l
e

i
c

t
o

r
,

I

Freescale Semiconductor, Inc.

For More Information On This Product,

Go to: www.freescale.com

.
.

2-6

DSP56309UM/D MOTOROLA

Signal/Connection Descriptions

Ground

2.3

GROUND

Ground descriptions for the DSP56309 are listed in Table 2-3.

CCS

(2)

ESSI, SCI, and Timer Power

ÑV

CCS

is an isolated power for the ESSI,

SCI, and timer I/O drivers. This input must be tied externally to all
other chip power inputs except V

CCQL

. The user must provide adequate

external decoupling capacitors. There are two V

CCS

inputs.

Note:

These designations are package-dependent. Some packages connect all V

inputs except V

CCP

each other internally. On those packages, all power input, except V

CCP

, are labeled V

. The number

of connections indicated in this table are minimum values; the total V

connections are

package-dependent.

Table 2-3

Grounds

Ground Name

Description

GND

PLL Ground

ÑGND

is a ground dedicated for PLL use. The connection

should be provided with an extremely low-impedance path to ground.
V

CCP

should be bypassed to GND

by a 0.47

mF capacitor located as

close as possible to the chip package. There is one GND

connection.

GND

PLL Ground 1

ÑGND

is a ground dedicated for PLL use. The

connection should be provided with an extremely low-impedance path
to ground. There is one GND

connection.

GND

(4)

Quiet Ground

ÑGND

is an isolated ground for the internal processing

logic. This connection must be tied externally to all other chip ground
connections. The user must provide adequate external decoupling
capacitors. There are four GND

connections.

GND

(4)

Address Bus Ground

ÑGND

is an isolated ground for sections of the

address bus I/O drivers. This connection must be tied externally to all
other chip ground connections. The user must provide adequate
external decoupling capacitors. There are four GND

connections.

Table 2-2

Power Inputs (Continued)

Power Name

Description

r
e

s
c

l
e

i
c

t
o

r
,

I

Freescale Semiconductor, Inc.

For More Information On This Product,

Go to: www.freescale.com

.
.

Signal/Connection Descriptions

Clock

MOTOROLA

DSP56309UM/D 2-7

2.4

CLOCK

Clock Signal descriptions for the DSP56309 are listed in Table 2-4.

GND

(4)

Data Bus Ground

ÑGND

is an isolated ground for sections of the data

bus I/O drivers. This connection must be tied externally to all other chip
ground connections. The user must provide adequate external
decoupling capacitors. There are four GND

connections.

GND

(2)

Bus Control Ground

ÑGND

is an isolated ground for the bus control

I/O drivers. This connection must be tied externally to all other chip
ground connections. The user must provide adequate external
decoupling capacitors. There are two GND

connections.

GND

Host Ground

ÑGND

is an isolated ground for the HI08 I/O drivers.

This connection must be tied externally to all other chip ground
connections. The user must provide adequate external decoupling
capacitors. There is one GND

connection.

GND

(2)

ESSI, SCI, and Timer Ground

ÑGND

is an isolated ground for the

ESSI, SCI, and timer I/O drivers. This connection must be tied externally
to all other chip ground connections. The user must provide adequate
external decoupling capacitors. There are two GND

connections.

Note:

These designations are package-dependent. Some packages connect all GND inputs, except GND

and GND

, to each other internally. On those packages, all ground connections, except GND

and

GND

, are labeled GND. The number of connections indicated in this table are minimum values; the

total GND connections are package-dependent.

Table 2-4

Clock Signals

Signal

Name

Type

State

During

Reset

Signal Description

EXTAL

Input

External Clock/Crystal Input

ÑEXTAL interfaces the

internal crystal oscillator input to an external crystal
or an external clock.

Table 2-3

Grounds (Continued)

Ground Name

Description

r
e

s
c

l
e

i
c

t
o

r
,

I

Freescale Semiconductor, Inc.

For More Information On This Product,

Go to: www.freescale.com

.
.

Signal/Connection Descriptions

External Memory Expansion Port (Port A)

MOTOROLA

DSP56309UM/D 2-13

Input/
Output

Input

Bus Busy

ÑBB is a bidirectional active-low

input/output and must be asserted and deasserted
synchronous to CLKOUT. BB indicates that the bus
is active. Only after BB is deasserted can the pending
bus master become the bus master (and then assert
the signal again). The bus master can keep BB
asserted after ceasing bus activity regardless of
whether BR is asserted or deasserted. This is called
Òbus parkingÓ and allows the current bus master to
reuse the bus without rearbitration until another
device requires the bus. The deassertion of BB is
done by an Òactive pull-upÓ method (i.e., BB is
driven high and then released and held high by an
external pull-up resistor).

BB requires an external pull-up resistor.

CAS

Output

Tri-stated

Column Address Strobe

ÑWhen the DSP is the bus

master, CAS is an active-low output used by DRAM
to strobe the column address. Otherwise, if the Bus
Mastership Enable (BME) bit in the DRAM Control
Register is cleared, the signal is tri-stated.

BCLK

Output

Tri-stated

Bus Clock

ÑWhen the DSP is the bus master, BCLK

is an active-high output. BCLK is active as a
sampling signal when the program address tracing
mode is enabled (by setting the ATE bit in the OMR).
When BCLK is active and synchronized to CLKOUT
by the internal PLL, BCLK precedes CLKOUT by 1/4
of a clock cycle. The BCLK rising edge can be used to
sample the internal program memory access on the
A0ÐA23 address lines.

BCLK

Output

Tri-stated

Bus Clock Not

ÑWhen the DSP is the bus master,

BCLK is an active-low output and is the inverse of
the BCLK signal. Otherwise, the signal is tri-stated.

Table 2-8

External Bus Control Signals (Continued)

Signal

Name

Type

State

During

Reset

Signal Description

r
e

s
c

l
e

i
c

t
o

r
,

I

Freescale Semiconductor, Inc.

For More Information On This Product,

Go to: www.freescale.com

.
.

2-14

DSP56309UM/D MOTOROLA

Signal/Connection Descriptions

Interrupt and Mode Control

2.7

INTERRUPT AND MODE CONTROL

The interrupt and mode control signals select the chipÕs operating mode as it comes out
of hardware reset. After RESET is deasserted, these inputs are hardware interrupt
request lines.

Table 2-9

Interrupt and Mode Control

Signal Name

Type

State

During

Reset

Signal Description

RESET

Input

ResetÑ

RESET is an active-low, Schmitt-trigger

input. Deassertion of RESET is internally
synchronized to the clock out (CLKOUT). When
asserted, the chip is placed in the Reset state and
the internal phase generator is reset. The
Schmitt-trigger input allows a slowly rising input
(such as a capacitor charging) to reset the chip
reliably. If RESET is deasserted synchronous to
CLKOUT, exact start-up timing is guaranteed,
allowing multiple processors to start
synchronously and operate together in lock-step.
When the RESET signal is deasserted, the initial
chip operating mode is latched from the MODA,
MODB, MODC, and MODD inputs. The RESET
signal must be asserted after power up.

MODA

IRQA

Input

Mode Select A

ÑMODA is an active-low

Schmitt-trigger input, internally synchronized to
CLKOUT. MODA, MODB, MODC, and MODD
select one of 16 initial chip operating modes,
latched into the OMR when the RESET signal is
deasserted.

External Interrupt Request AÑAfter reset, this
signal becomes a level-sensitive or
negative-edge-triggered, maskable interrupt
request input during normal instruction
processing. If IRQA is asserted synchronous to
CLKOUT, multiple processors can be
resynchronized using the WAIT instruction and
asserting IRQA to exit the wait state. If the
processor is in the stop standby state and IRQA is
asserted, the processor exits the stop state.

r
e

s
c

l
e

i
c

t
o

r
,

I

Freescale Semiconductor, Inc.

For More Information On This Product,

Go to: www.freescale.com

.
.

3-4

DSP56309UM/D MOTOROLA

Memory Configuration

Memory Spaces

DSP56309 to feed two operands to the Data ALU simultaneously, enabling it to perform
a multiply-accumulate operation in one clock cycle.

X and Y data memory are identical in structure and functionality except for the upper
128 words of each space. The upper 128 words of X data memory are reserved for
internal I/O. We recommend that the programmer reserve the upper 128 words of Y
data memory for external I/O. (For further information, see Section 3.1.2.1 X Data
Memory Space

and Section 3.1.2.2 Y Data Memory Space.)

X and Y data memory space each consist of the following:

¥ Internal data memory (X data RAM and Y data RAM, the default size of each is

7K, but they can be switched to 5K each)

¥ (Optionally) Off-chip memory expansion (up to 16 M in the 24-bit address mode

and 64K in the 16-bit address mode)

3.1.2.1

X Data Memory Space

The on-chip peripheral registers and some of the DSP56309 core registers occupy the top
128 locations of X data memory ($FFFF80Ð$FFFFFF in the 24-bit Address mode or
$FF80Ð$FFFF in the 16-bit Address mode). This area is called X-I/O space, and it can be
accessed by MOVE and MOVEP instructions and by bit oriented instructions (BCHG,
BCLR, BSET, BTST, BRCLR, BRSET, BSCLR, BSSET, JCLR, JSET, JSCLR, and JSSET). For
a listing of the contents of this area, see the programming sheets in
Appendix DÑProgramming Reference

The X memory space at locations $FF0000 to $FFEFFF is reserved and should not be
accessed by the programmer.

3.1.2.2

Y Data Memory Space

The off-chip peripheral registers should be mapped into the top 128 locations of Y data
memory ($FFFF80Ð$FFFFFF in the 24-bit address mode or $FF80Ð$FFFF in the 16-bit
address mode) to take advantage of the move peripheral data (MOVEP) instruction and
the bit oriented instructions (BCHG, BCLR, BSET, BTST, BRCLR, BRSET, BSCLR, BSSET,
JCLR, JSET, JSCLR, and JSSET).

The Y memory space at locations $FF0000 to $FFEFFF is reserved and should not be
accessed by the programmer.

r
e

s
c

l
e

i
c

t
o

r
,

I

Freescale Semiconductor, Inc.

For More Information On This Product,

Go to: www.freescale.com

.
.

3-6

DSP56309UM/D MOTOROLA

Memory Configuration

RAM Configuration

Memory maps for the different configurations are shown in Figure 3-1 through
Figure 3-8

Note:

The MS bit cannot be changed when CE is set. The instruction cache occupies

the top 1K of what would otherwise be Program RAM; if you switch memory
into or out of Program RAM when the cache is enabled, the switch causes
conflicts. To change the MS bit when CE is set, do the following:

1. Clear CE.

2. Change MS.

3. Set CE.

3.2.1

On-Chip Program Memory (Program RAM)

The on-chip Program RAM consists of 24-bit wide, high-speed, internal Static RAM
occupying the lowest 20K (default), 23K, 24K, or 19K locations in the program memory
space (depending on the settings of the MS and CE bits). The Program RAM default
organization is 80 banks of 256 24-bit words (20K). The upper eight banks of both X data
RAM and Y data RAM can be configured as Program RAM by setting the MS bit. When
the CE is set, the upper 1K of Program RAM is used as an internal Instruction Cache.

CAUTION

While the contents of Program RAM are unaffected by toggling the
MS bit, the location of program data placed in the Program
RAM/Instruction Cache area changes after the MS bit is toggled, since
the cache always occupies the top-most 1K Program RAM addresses.
To preserve program data integrity, do not set or clear the MS bit
when the CE bit is set. See Section 3.2 on page 3-5 for the correct
procedure.

3.2.2

On-Chip X Data Memory (X Data RAM)

The on-chip X data RAM consists of 24-bit wide, high-speed, internal Static RAM
occupying the lowest 7K (default) or 5K locations in the X memory space. The size of the
X data RAM depends on the setting of the MS bit (default: MS is cleared). The X data
RAM default organization is 28 banks of 256 (7K) 24-bit words. Eight banks of RAM can
be switched from the X data RAM to the Program RAM by setting the MS bit (leaving 5K
of X data RAM).

r
e

s
c

l
e

i
c

t
o

r
,

I

Freescale Semiconductor, Inc.

For More Information On This Product,

Go to: www.freescale.com

.
.

Core Configuration

Bootstrap Program

MOTOROLA

DSP56309UM/D 4-5

On exiting the reset state, the DSP56309 does the following:

1. Samples the MODA, MODB, MODC, and MODD signal lines.

2. Loads their values into bits MA, MB, MC, and MD in the OMR.

The contents of the MA, MB, MC, and MD bits determine which bootstrap mode the
DSP56309 enters:

1. If MA, MB, MC, and MD are all cleared (Bootstrap mode 0), the program bypasses

the bootstrap ROM, and the DSP56309 starts loading instructions from external
program memory location $C00000.

2. If MA, MB, and MC are cleared and MD is set (Bootstrap mode 8), the program

bypasses the bootstrap ROM, and the DSP56309 starts loading in instruction
values from external program memory location $008000.

3. Otherwise (Bootstrap modes 1Ð7), the DSP56309 jumps to the bootstrap program

entry point at $FF0000.

If the bootstrap program is loading via the host interface (HI08), setting the HF0 bit in
the host status register (HSR) causes the DSP56309 to stop loading and begin executing
the loaded program at the specified start address.

See Table 4-1 for a tabular description of the mode bit settings for the operating modes.

The bootstrap program options (except modes 0 and 8) can be invoked at any time by
setting the MA, MB, MC, and MD bits in the OMR and jumping to the bootstrap
program entry point, $FF0000. Software can directly set the mode selection bits in the
OMR.

Bootstrap modes 0 and 8 are the normal functioning modes for the DSP56309. Bootstrap
modes 1Ð7 are the bootstrap modes proper.

Bootstrap modes 9, A, C, D, E, F select different, specific devices for loading the
bootstrap source. In those bootstrap modes, the bootstrap program expects the following
data sequence when downloading the user program through an external port:

1. Three bytes defining the number of (24-bit) program words to be loaded

2. Three bytes defining the (24-bit) start address to which the user program loads in

the DSP56309 program memory

3. The user program (three bytes for each 24-bit program word)

r
e

s
c

l
e

i
c

t
o

r
,

I

Freescale Semiconductor, Inc.

For More Information On This Product,

Go to: www.freescale.com

.
.

Core Configuration

Interrupt Sources and Priorities

MOTOROLA

DSP56309UM/D 4-9

4.3.7.3

Mode E: In 8051 Multiplexed Bus Mode

In mode E: boot from HI08 in 8051 multiplexed bus mode, the bootstrap program sets
the host interface to interface with the Intel

8051 bus.

If the host processor sets host flag 0 (HF0) in the HCR while writing the initialization
program, the bootstrap program stops loading instructions, jumps to the starting
address specified, and executes the loaded program.

4.3.7.4

Mode F: In 68302/68360 Bus Mode

In mode F: boot from HI08 in 68302/68360 Bus mode, the bootstrap program sets the
host interface to interface with the Motorola 68302 or 68360 bus.

4.4

INTERRUPT SOURCES AND PRIORITIES

DSP56309 interrupt handling, like that of all DSP56300 family members, has been
optimized for DSP applications. Refer to Section 7 of the DSP56300

Family Manual.

The

interrupt table is located in the 256 locations of program memory to which the vector
base address (VBA) register in the program control unit (PCU) points.

4.4.1

Interrupt Sources

Each interrupt is allocated two instructions in the table, so there are 128 table entries for
interrupt handling. Table 4-2 shows the table entry address for each interrupt source.

Mode

MODD

MODC

MODB

MODA

Reset

Vector

Description

$FF0000

HI08 Bootstrap in 8051
multiplexed bus

Mode

MODD

MODC

MODB

MODA

Reset

Vector

Description

$FF0000

HI08 Bootstrap in 68302 bus

r
e

s
c

l
e

i
c

t
o

r
,

I

Freescale Semiconductor, Inc.

For More Information On This Product,

Go to: www.freescale.com

.
.

General-Purpose I/O

Introduction

MOTOROLA

DSP56309UM/D 5-3

5.1

INTRODUCTION

The DSP56309 provides thirty-four bidirectional signals that can be configured as GPIO
signals or as dedicated peripheral signals. No dedicated GPIO signals are provided. All
of these signals are GPIO by default after reset. The control register settings of the
DSP56309Õs peripherals determine whether these signals function as GPIO or as
dedicated peripheral signals. This section describes how signals can function as GPIO.

5.2

PROGRAMMING MODEL

Section 2ÑSignal/Connection Descriptions

of this manual documents the special uses

of these signals in detail. There are five groups of these signals. They can be controlled
separately or as groups. The groups include the following signals:

¥ Port B: sixteen GPIO signals (shared with the HI08 signals)

¥ Port C: six GPIO signals (shared with the ESSI0 signals)

¥ Port D: six GPIO signals (shared with the ESSI1 signals)

¥ Port E: three GPIO signals (shared with the SCI signals)

¥ Timers: three GPIO signals (shared with the Triple Timer signals)

5.2.1

Port B Signals and Registers

Each of the 16 Port B signals not used as a HI08 signal can be configured as a GPIO
signal. The GPIO functionality of Port B is controlled by three registers: host control
register (HCR), host port GPIO data register (HDR), and host port GPIO direction
register (HDDR). These registers are documented in Section 6ÑHost Interface (HI08) of
this manual.

5.2.2

Port C Signals and Registers

Each of the six Port C signals not used as an ESSI0 signal can be configured as a GPIO
signal. The GPIO functionality of Port C is controlled by three registers: Port C control
register (PCRC), Port C direction register (PRRC), and Port C data register (PDRC).
These registers are documented in Section 7ÑEnhanced Synchronous Serial Interface
(ESSI)

of this manual.

r
e

s
c

l
e

i
c

t
o

r
,

I

Freescale Semiconductor, Inc.

For More Information On This Product,

Go to: www.freescale.com

.
.

6-8

DSP56309UM/D MOTOROLA

Host Interface (HI08)

HI08 DSP Side ProgrammerÕs Model

6.5

HI08 DSP SIDE PROGRAMMERÕS MODEL

The DSP56309 core treats the HI08 as a memory-mapped peripheral occupying eight
24-bit words in X data memory space. The DSP treats the HI08 as a normal
memory-mapped peripheral, employing either standard polled or interrupt-driven
programming techniques. Separate transmit and receive data registers are
double-buffered to allow the DSP and host processor to transfer data efficiently at high
speed. Direct memory mapping allows the DSP56309 core to communicate with the HI08
registers using standard instructions and addressing modes. In addition, the MOVEP
instruction allows direct data transfers between DSP56309 internal memory and the
HI08 registers or vice versa.

There are two kinds of host processor registers, data and control, with eight registers in
all. All eight registers can be accessed by the DSP core but not by the external host.

Data registers are 24-bit registers used for high-speed data transfer to and from the DSP.

¥ Host data receive register (HRX)

¥ Host data transmit register (HTX)

The DSP side control registers are 16-bit registers that control DSP functions. The eight
MSBs in the DSP side control registers are read by the DSP56309 as 0. Those registers are
as follows:

¥ Host control register (HCR)

¥ Host status register (HSR)

¥ Host base address register (HBAR)

¥ Host port control register (HPCR)

¥ Host GPIO data direction register (HDDR)

¥ Host GPIO data register (HDR)

Both hardware RESET signals and software RESET instructions disable the HI08. After
reset, the HI08 signals are configured to GPIO and disconnected from the DSP56309 core
(i.e., the signals are left floating).

6.5.1

Host Receive Data Register (HRX)

The HRX register handles host-to-DSP data transfers. The DSP56309 views it as a 24-bit
read-only register. Its address is X:$FFFFC6. It is loaded with 24-bit data from the

r
e

s
c

l
e

i
c

t
o

r
,

I

Freescale Semiconductor, Inc.

For More Information On This Product,

Go to: www.freescale.com

.
.

Host Interface (HI08)

HI08 DSP Side ProgrammerÕs Model

MOTOROLA

DSP56309UM/D 6-9

transmit data registers (TXH:TXM:TXL on the host side) when both the hostÕs transmit
data register empty (ISR:TXDE) bit and the DSPÕs host receive data full (HSR:HRDF) bits
are cleared. The transfer operation sets both the TXDE and HRDF bits. When the HRDF
bit is set, the HRX register contains valid data. The DSP56309 sets the HRIE bit (HCR, bit
0) to cause a host receive data interrupt when HRDF is set. When the DSP56309 reads the
HRX register, the HRDF bit is cleared.

6.5.2

Host Transmit Data Register (HTX)

The HTX register handles for DSP-to-host data transfers. The DSP56309 views it as a
24-bit write-only register. Its address is X:$FFFFC7. Writing to the HTX register clears
the DSPÕs host transfer data empty (HSR:HTDE) bit. The contents of the HTX register are
transferred as 24-bit data to the receive byte registers (RXH:RXM:RXL) when both the
HTDE and the hostÕs receive data full (ISR:RXDF) bits are cleared. This transfer
operation sets the HTDE and RXDF bits. The DSP56309 sets the HTIE bit to cause a host
transmit data interrupt when HTDE is set. To prevent the previous data from being
overwritten, data should not be written to the HTX until the HTDE bit is set.

Note:

During data writes to a peripheral device, there is a two-cycle pipeline delay

until any status bits affected by this operation are updated. If you read any of
those status bits within the next two cycles, the bit does not reflect its current
status. See the DSP56300 Family Manual, Appendix B, Polling a Peripheral
Device for Write

for further details.

6.5.3

Host Control Register (HCR)

The HCR is a 16-bit, read/write control register by which the DSP core controls the HI08
operating mode. Initialization values for HCR bits are documented in
Section 6.5.9ÑDSP Side Registers After Reset

. Reserved bits are read as 0 and should

be written with 0 for future compatibility.

HF3 HF2 HCIE HTIE HRIE

ÑReserved bit, read as 0, should be written with 0 for future compatibility.

AA0658

Figure 6-2

Host Control Register (HCR) (X:$FFFFC2)

r
e

s
c

l
e

i
c

t
o

r
,

I

Freescale Semiconductor, Inc.

For More Information On This Product,

Go to: www.freescale.com

.
.

6-10

DSP56309UM/D MOTOROLA

Host Interface (HI08)

HI08 DSP Side ProgrammerÕs Model

6.5.3.1

HCR Host Receive Interrupt Enable (HRIE) Bit 0

The HRIE bit generates a host receive data interrupt request if the host receive data full
(HRDF) bit in the host status register (HSR, Bit 0), is set. The HRDF bit is set when data is
written to the HRX. If HRIE is cleared, HRDF interrupts are disabled.

6.5.3.2

HCR Host Transmit Interrupt Enable (HTIE) Bit 1

The HTIE bit generates a host transmit data interrupt request if the host transmit data
empty (HTDE) bit in the HSR is set. The HTDE bit is set when data is read from the HTX.
If HTIE is cleared, HTDE interrupts are disabled.

6.5.3.3

HCR Host Command Interrupt Enable (HCIE) Bit 2

The HCIE bit generates a host command interrupt request if the host command pending
(HCP) status bit in the HSR is set. If HCIE is cleared, HCP interrupts are disabled. The
interrupt address is determined by the host command vector register (CVR).

Note:

If more than one interrupt request source is asserted and enabled (e.g., HRDF

is set, HCP is set, HRIE is set, and HCIE is set), the HI08 generates interrupt
requests according to priorities shown in Table 6-4.

6.5.3.4

HCR Host Flags 2,3 (HF[3:2]) Bits 3, 4

HF[3:2] bits are general-purpose flags for DSP-to-host communication. The DSP core sets
and clears them. The values of HF[3:2] are reflected in the interface status register (ISR);
that is, if they are modified by the DSP software, the host processor can read the
modified values by reading the ISR.

These two flags can be used individually or as encoded pairs in a simple DSP-to-host
communication protocol, implemented in both the DSP and the host processor software.

6.5.3.5

HCR Reserved Bits 5-15

These bits are reserved. They are read as 0 and should be written with 0.

Table 6-4

Host Command Interrupt Priority List

Priority

Interrupt Source

Highest

Host Command (HCP = 1)

Transmit Data (HTDE = 1)

Lowest

Receive Data (HRDF = 1)

r
e

s
c

l
e

i
c

t
o

r
,

I

Freescale Semiconductor, Inc.

For More Information On This Product,

Go to: www.freescale.com

.
.

Host Interface (HI08)

HI08 DSP Side ProgrammerÕs Model

MOTOROLA

DSP56309UM/D 6-11

6.5.4

Host Status Register (HSR)

The HSR is a 16-bit, read-only status register by which the DSP reads the HI08 status and
flags. The host processor cannot access it directly. Reserved bits are read as 0 and should
be written with 0. The initialization values for the HSR bits are described in
Section 6.5.9ÑDSP Side Registers After Reset

on page 6-18.

6.5.4.1

HSR Host Receive Data Full (HRDF) Bit 0

The HRDF bit indicates that the host receive data register (HRX) contains data from the
host processor. HRDF is set when data is transferred from the TXH:TXM:TXL registers
to the HRX register. If HRDF is set, the HI08 generates a receive data full DMA request.
HRDF is cleared when the DSP core reads the HRX. HRDF is also cleared when the host
processor uses the initialize function.

6.5.4.2

HSR Host Transmit Data Empty (HTDE) Bit 1

The HTDE bit indicates that the host transmit data register (HTX) is empty and can be
written by the DSP core. HTDE is set when the HTX register is transferred to the
RXH:RXM:RXL registers. HTDE is also set when the host processor uses the initialize
function. If HTDE is set, the HI08 generates a transmit data full DMA request. HTDE is
cleared when HTX is written by the DSP core.

6.5.4.3

HSR Host Command Pending (HCP) Bit 2

The HCP bit indicates that the host has set the HC bit and that a host command interrupt
is pending. The HCP bit reflects the status of the HC bit in the CVR. HC and HCP are
cleared by the HI08 hardware when the interrupt request is serviced by the DSP core. If
the host clears HC, HCP is also cleared.

6.5.4.4

HSR Host Flags 0, 1 (HF[1:0]) Bits 3, 4

HF[1:0] bits are used as general-purpose flags for host-to-DSP communication. HF[1:0]
can be set or cleared by the host. These bits reflect the status of host flags HF[1:0] in the
ICR on the host side. They can be used individually or as encoded pairs in a simple
host-to-DSP communication protocol implemented in both the DSP and the host
processor software.

6.5.4.5

HSR Reserved Bits 5-15

These bits are reserved. They are read as 0 and should be written with 0.

HF1

HF0

HCP

HTDE HRDF

ÑReserved bit, read as 0, should be written with 0 for future compatibility.

AA0659

Figure 6-3

Host Status Register (HSR) (X:$FFFFC3)

r
e

s
c

l
e

i
c

t
o

r
,

I

Freescale Semiconductor, Inc.

For More Information On This Product,

Go to: www.freescale.com

.
.

Host Interface (HI08)

HI08 DSP Side ProgrammerÕs Model

MOTOROLA

DSP56309UM/D 6-13

Note:

To assure proper operation of the DSP56309, the HPCR bits HAP, HRP, HCSP,

HDDS, HMUX, HASP, HDSP, HROD, HAEN, and HREN should be changed
only if HEN is cleared.

To assure proper operation of the DSP56309, the HPCR bits HAP, HRP, HCSP,
HDDS, HMUX, HASP, HDSP, HROD, HAEN, HREN, HCSEN, HA9EN, and
HA8EN should not be set when HEN is set or simultaneously with setting
HEN.

6.5.6.1

HPCR Host GPIO Port Enable (HGEN) Bit 0

If HGEN is set, signals configured as GPIO are enabled. If this bit is cleared, signals
configured as GPIO are disconnected; outputs are high impedance, and inputs are
electrically disconnected. Signals configured as HI08 are not affected by the value of
HGEN.

6.5.6.2

HPCR Host Address Line 8 Enable (HA8EN) Bit 1

If HA8EN is set and the HI08 is in multiplexed bus mode, then HA8/A1 acts as host
address line 8 (HA8). If this bit is cleared and the HI08 is in multiplexed bus mode, then
HA8/HA1 acts as a GPIO signal according to the value of the HDDR and HDR.

Note:

HA8EN is ignored when the HI08 is not in the multiplexed bus mode (HMUX

is cleared).

6.5.6.3

HPCR Host Address Line 9 Enable (HA9EN) Bit 2

If HA9EN is set and the HI08 is in multiplexed bus mode, then HA9/HA2 acts as host
address line 9 (HA9). If this bit is cleared, and the HI08 is in multiplexed bus mode, then
HA9/HA2 is configured as a GPIO signal according to the value of the HDDR and HDR.

Note:

HA9EN is ignored when the HI08 is not in the multiplexed bus mode (HMUX

is cleared).

6.5.6.4

HPCR Host Chip Select Enable (HCSEN) Bit 3

If the HCSEN bit is set, then HCS/HA10 is used as host chip select (HCS) in the
non-multiplexed bus mode (HMUX is cleared), and as host address line 10 (HA10) in the
multiplexed bus mode (HMUX is set). If this bit is cleared, then HCS/HA10 is
configured as a GPIO signal according to the value of the HDDR and HDR.

HAP

HRP

HCSP HDDS HMUX HASP HDSP HROD

HEN

HAEN HREN HCSEN HA9EN HA8EN HGEN

ÑReserved bit, read as 0, should be written with 0 for future compatibility.

AA0660

Figure 6-6

Host Port Control Register (HPCR) (X:$FFFFC4)

r
e

s
c

l
e

i
c

t
o

r
,

I

Freescale Semiconductor, Inc.

For More Information On This Product,

Go to: www.freescale.com

.
.

6-14

DSP56309UM/D MOTOROLA

Host Interface (HI08)

HI08 DSP Side ProgrammerÕs Model

6.5.6.5

HPCR Host Request Enable (HREN) Bit 4

The HREN bit controls the host request signals. If HREN is set and the HI08 is in the
single host request mode (HDRQ is cleared in the host interface control register (ICR)),
HREQ/HTRQ is configured as the host request (HREQ) output. If HREN is cleared,
HREQ/HTRQ and HACK/HRRQ are configured as GPIO signals according to the value
of the HDDR and HDR.

If HREN is set in the double host request mode (HDRQ is set in the ICR), HREQ/HTRQ
is configured as the host transmit request (HTRQ) output and HACK/HRRQ as the host
receive request (HRRQ) output. If HREN is cleared, HREQ/HTRQ and HACK/HRRQ
are configured as GPIO signals according to the value of the HDDR and HDR.

6.5.6.6

HPCR Host Acknowledge Enable (HAEN) Bit 5

The HAEN bit controls the HACK signal. In the single host request mode (HDRQ is
cleared in the ICR), if HAEN and HREN are both set, HACK/HRRQ is configured as the
host acknowledge (HACK) input. If HAEN or HREN is cleared, HACK/HRRQ is
configured as a GPIO signal according to the value of the HDDR and HDR. In the double
host request mode (HDRQ is set in the ICR), HAEN is ignored.

6.5.6.7

HPCR Host Enable (HEN) Bit 6

If HEN is set, the HI08 operates as the host interface. If HEN is cleared, the HI08 is not
active, and all the HI08 signals are configured as GPIO signals according to the value of
the HDDR and HDR.

6.5.6.8

HPCR Reserved Bit 7

This bit is reserved. It is read as 0 and should be written as 0.

6.5.6.9

HPCR Host Request Open Drain (HROD) Bit 8

The HROD bit controls the output drive of the host request signals. In the single host
request mode (HDRQ is cleared in ICR), if HROD is cleared and host requests are
enabled (HREN is set and HEN is set in HPCR), the HREQ signal is always driven by the
HI08. If HROD is set and host requests are enabled, the HREQ signal is an open drain
output. In the double host request mode (HDRQ is set in the ICR), if HROD is cleared
and host requests are enabled (HREN is set and HEN is set in the HPCR), the HTRQ and
HRRQ signals are always driven. If HROD is set and host requests are enabled, the
HTRQ and HRRQ signals are open drain outputs.

6.5.6.10

HPCR Host Data Strobe Polarity (HDSP) Bit 9

If HDSP is cleared, the data strobe signals are configured as active low inputs, and data
is transferred when the data strobe is low. If HDSP is set, the data strobe signals are
configured as active high inputs, and data is transferred when the data strobe is high.
The data strobe signals are either HDS by itself or both HRD and HWR together.

r
e

s
c

l
e

i
c

t
o

r
,

I

Freescale Semiconductor, Inc.

For More Information On This Product,

Go to: www.freescale.com

.
.

Host Interface (HI08)

HI08-External Host ProgrammerÕs Model

MOTOROLA

DSP56309UM/D 6-21

The CVR is a special command register by which the host processor issues commands to
the DSP56309. Only the host processor can access this register.

Host processors can use standard host processor instructions (e.g., byte move) and
addressing modes to communicate with the HI08 registers. The HI08 registers are
aligned so that 8-bit host processors can use 8/16/24-bit load and store instructions for
data transfers. The HREQ/HTRQ and HACK/HRRQ handshake flags are provided for
polled or interrupt-driven data transfers with the host processor. Because of the speed of
the DSP56309 interrupt response, most host microprocessors can load or store data at
their maximum programmed I/O instruction rate without testing the handshake flags
for each transfer. If full handshake is not needed, the host processor can treat the
DSP56309 as a fast device, and data can be transferred between the host processor and
the DSP56309 at the fastest host processor data rate.

One of the most innovative features of the host interface is the host command feature.
With this feature, the host processor can issue vectored interrupt requests to the
DSP56309. The host can select any of 128 DSP interrupt routines for execution by writing
a vector address register in the HI08. This flexibility allows the host processor to execute
up to 128 pre-programmed functions inside the DSP56309. For example, use of the
DSP56309 host interrupts can allow the host processor to read or write DSP registers (X,
Y, or program memory locations), force interrupt handlers (e.g., SSI, SCI, IRQA, IRQB
interrupt routines), and perform control and debugging operations.

Note:

When the DSP enters stop mode, the HI08 signals are electrically disconnected

internally, thus disabling the HI08 until the core leaves stop mode. While the
HI08 configuration remains unchanged in stop mode, the core cannot be
restarted via the HI08 interface.

Do not issue a STOP command to the DSP via the HI08 unless some other
mechanism for exiting stop mode is provided.

r
e

s
c

l
e

i
c

t
o

r
,

I

Freescale Semiconductor, Inc.

For More Information On This Product,

Go to: www.freescale.com

.
.

Host Interface (HI08)

HI08-External Host ProgrammerÕs Model

MOTOROLA

DSP56309UM/D 6-25

The t

Òype of initialization done when the INIT bit is set depends on the state of TREQ

and RREQ in the HI08. The INIT command, which is local to the HI08, can conveniently
configure the HI08 into the desired data transfer mode. The effect of the INIT command
is described in Table 6-10. When the host sets the INIT bit, the HI08 hardware executes
the INIT command. The interface hardware clears the INIT bit after the command has
been executed.

6.6.2

Command Vector Register (CVR)

The host processor uses the CVR to cause the DSP56309 to execute an interrupt. The host
command feature is independent of any of the data transfer mechanisms in the HI08. It
can cause any of the 128 possible interrupt routines in the DSP core to be executed. This
register is illustrated in Figure 6-13.

6.6.2.1

CVR Host Vector (HV[6:0]) Bits 0Ð6

The seven HV bits select the host command interrupt address to be used by the host
command interrupt logic. When the host command interrupt is recognized by the DSP
interrupt control logic, the address of the interrupt routine taken is 2

´ HV. The host can

write HC and HV in the same write cycle.

The host processor can select any of the 128 possible interrupt routine starting addresses
in the DSP by writing the interrupt routine address divided by two into the HV bits. This
means that the host processor can force any of the existing interrupt handlers (SSI, SCI,

Table 6-10

INIT Command Effects

TREQ

RREQ

After INIT Execution

Transfer Direction

Initialized

INIT = 0

None

INIT = 0; RXDF = 0; HTDE = 1

DSP to Host

INIT = 0; TXDE = 1; HRDF = 0

Host to DSP

INIT = 0; RXDF = 0; HTDE = 1; TXDE = 1;

HRDF = 0

Host to/from DSP

HV6

HV5

HV4

HV3

HV2

HV1

HV0

AA0669

Figure 6-13

Command Vector Register (CVR)

r
e

s
c

l
e

i
c

t
o

r
,

I

Freescale Semiconductor, Inc.

For More Information On This Product,

Go to: www.freescale.com

.
.

6-26

DSP56309UM/D MOTOROLA

Host Interface (HI08)

HI08-External Host ProgrammerÕs Model

IRQA, IRQB, etc.) and can use any of the reserved or otherwise unused addresses
(provided they have been pre-programmed in the DSP). HV is set to $32 (vector location
$0064) by a hardware RESET signal, software RESET instruction, individual reset, or a
STOP instruction.

6.6.2.2

CVR Host Command Bit (HC) Bit 7

The host processor uses the HC bit to handshake the execution of host command
interrupts. Normally, the host processor sets HC to request a host command interrupt
from the DSP56309. When the DSP56309 acknowledges the host command interrupt, the
HI08 hardware clears the HC bit. The host processor can read the state of HC to
determine when the host command has been accepted. After setting HC, the host must
not write to the CVR again until the HI08 hardware clears HC. Setting the HC bit causes
host command pending (HCP) to be set in the HSR. The host can write to the HC and HV
bits in the same write cycle.

6.6.3

Interface Status Register (ISR)

The interface status register (ISR) is an 8-bit, read-only status register used by the host
processor to interrogate the status and flags of the HI08. The host processor can write to
this address without affecting the internal state of the HI08. The DSP core cannot access
the ISR. The ISR bits are described in the following paragraphs. This register is
illustrated in Figure 6-14.

6.6.3.1

ISR Receive Data Register Full (RXDF) Bit 0

The RXDF bit indicates that the receive byte registers (RXH:RXM:RXL) contain data
from the DSP56309 and can be read by the host processor. RXDF is set when the HTX is
transferred to the receive byte registers. RXDF is cleared when the receive data (RXL or
RXH according to HLEND bit) register is read by the host processor. RXDF can be
cleared by the host processor using the initialize function. RXDF can assert the external
HREQ signal if the RREQ bit is set. Regardless of whether the RXDF interrupt is enabled,
RXDF indicates whether the RX registers are full and data can be latched out so that the
host processor can use polling techniques.

HREQ

HF3

HF2

TRDY

TXDE

RXDF

ÑReserved bit. Read as 0. Should be written with 0, for future compatibility.

AA0670

Figure 6-14

Interface Status Register

r
e

s
c

l
e

i
c

t
o

r
,

I

Freescale Semiconductor, Inc.

For More Information On This Product,

Go to: www.freescale.com

.
.

Host Interface (HI08)

HI08-External Host ProgrammerÕs Model

MOTOROLA

DSP56309UM/D 6-27

6.6.3.2

ISR Transmit Data Register Empty (TXDE) Bit 1

The TXDE bit indicates that the transmit byte registers (TXH:TXM:TXL) are empty and
can be written by the host processor. TXDE is set when the contents of the transmit byte
registers are transferred to the HRX register. TXDE is cleared when the transmit (TXL or
TXH according to HLEND bit) register is written by the host processor. The host
processor can set TXDE using the initialize function. TXDE can assert the external HTRQ
signal if the TREQ bit is set. Regardless of whether the TXDE interrupt is enabled, TXDE
indicates whether the TX registers are full and data can be latched in so that the host
processor can use polling techniques.

6.6.3.3

ISR Transmitter Ready (TRDY) Bit 2

The TRDY status bit indicates that TXH:TXM:TXL, and the HRX registers are empty.

TRDY = TXDE

and

HRDF

If TRDY is set, the data that the host processor writes to TXH:TXM:TXL is immediately
transferred to the DSP side of the HI08. This feature has many applications. For example,
if the host processor issues a host command which causes the DSP56309 to read the
HRX, the host processor can be guaranteed that the data it just transferred to the HI08 is
that being received by the DSP56309.

6.6.3.4

ISR Host Flag 2 (HF2) Bit 3

HF2 indicates the state of host flag 2 in the HCR on the DSP side. HF2 can be changed
only by the DSP56309, as documented in Section 6.5.3.4ÑHCR Host Flags 2,3 (HF[3:2])
Bits 3, 4

on page 6-10.

6.6.3.5

ISR Host Flag 3 (HF3) Bit 4

HF3 indicates the state of Host Flag 3 in the HCR on the DSP side. HF3 can be changed
only by the DSP56309, as documented in Section 6.5.3.4ÑHCR Host Flags 2,3 (HF[3:2])
Bits 3, 4

on page 6-10.

6.6.3.6

ISR Reserved

Bits 5, 6

These bits are reserved. They are read as 0 and should be written with 0.

6.6.3.7

ISR Host Request (HREQ) Bit 7

HREQ indicates the status of the external transmit and receive request output signals
(HTRQ and HRRQ) if HDRQ is set. If HDRQ is cleared, it indicates the status of the
external host request output signal (HREQ). Table 6-11 shows possible settings of
HRDQ and HDEQ and their effects.

r
e

s
c

l
e

i
c

t
o

r
,

I

Freescale Semiconductor, Inc.

For More Information On This Product,

Go to: www.freescale.com

.
.

6-28

DSP56309UM/D MOTOROLA

Host Interface (HI08)

HI08-External Host ProgrammerÕs Model

Table 6-11

HREQ and HDRQ Settings

The HREQ is set from either or both of two conditionsÑeither the receive byte registers
are full or the transmit byte registers are empty. These conditions are indicated by the
ISR RXDF and TXDE status bits, respectively. If the interrupt source has been enabled by
the associated request enable bit in the ICR, HREQ is set if one or more of the two
enabled interrupt sources is set.

6.6.4

Interrupt Vector Register (IVR)

The IVR is an 8-bit, read/write register which typically contains the interrupt vector
number used with MC68000 family processor vectored interrupts. Only the host
processor can read and write this register. The contents of the IVR are placed on the host
data bus, H[7:0], when both the HREQ and HACK signals are asserted. The contents of
this register are initialized to $0F by a hardware RESET signal or software RESET
instruction. This value corresponds to the uninitialized interrupt vector in the MC68000
family. This register is illustrated in Figure 6-15.

6.6.5

Receive Byte Registers (RXH: RXM: RXL)

The receive byte registers are viewed by the host processor as three 8-bit, read-only
registers. These registers are the receive high register (RXH), the receive middle register
(RXM), and the receive low register (RXL). They receive data from the high, middle, and

HDRQ

HREQ

Effect

HREQ is cleared; no host processor interrupts are requested.

HREQ is set; an interrupt is requested.

HTRQ and HRRQ are cleared, no host processor interrupts are
requested.

HTRQ or HRRQ are set; an interrupt is requested.

IV7

IV6

IV5

IV4

IV3

IV2

IV1

IV0

AA0671

Figure 6-15

Interrupt Vector Register (IVR)

r
e

s
c

l
e

i
c

t
o

r
,

I

Freescale Semiconductor, Inc.

For More Information On This Product,

Go to: www.freescale.com

.
.

Host Interface (HI08)

HI08-External Host ProgrammerÕs Model

MOTOROLA

DSP56309UM/D 6-29

low bytes, respectively, of the HTX register and are selected by the external host address
inputs (HA[2:0]) during a host processor read operation.

The memory address of the receive byte registers is set by the HLEND bit in the ICR. If
the HLEND bit is set, the RXH is located at address $7, RXM at $6, and RXL at $5. If the
HLEND bit is cleared, the RXH is located at address $5, RXM at $6, and RXL at $7.

When data is written to the receive byte register at host address $7, the receive data
register full (RXDF) bit is set. The host processor can program the RREQ bit to assert the
external HREQ signal when RXDF is set. This indicates that the HI08 has a full word
(either 8, 16, or 24 bits) for the host processor. The host processor can program the RREQ
bit to assert the external HREQ signal when RXDF is set. Asserting the HREQ signal
informs the host processor that the receive byte registers have data to be read. When the
host reads the receive byte register at host address $7, the RXDF bit is cleared.

6.6.6

Transmit Byte Registers (TXH:TXM:TXL)

The host processor views the transmit byte registers as three 8-bit, write-only registers.
These registers are the transmit high register (TXH), the transmit middle register (TXM),
and the transmit low register (TXL). These registers send data to the high, middle, and
low bytes, respectively, of the HRX register and are selected by the external host address
inputs, HA[2:0], during a host processor write operation.

If the HLEND bit in the ICR is set, the TXH register is located at address $7, the TXM
register at $6 and the TXL register at $5. If the HLEND bit in the ICR is cleared, the TXH
register is located at address $5, the TXM register at $6, and the TXL register at $7.

Data is written into the transmit byte registers when the transmit data register empty
(TXDE) bit is set. The host processor programs the TREQ bit to assert the external
HREQ/HTRQ signal when TXDE is set. This informs the host processor that the
transmit byte registers are empty. Writing to the data register at host address $7 clears
the TXDE bit. The contents of the transmit byte registers are transferred as 24-bit data to
the HRX register when both the TXDE and the HRDF bit are cleared. This transfer
operation sets TXDE and HRDF.

Note:

When data is written to a peripheral device, there is a two-cycle pipeline delay

for further details.

r
e

s
c

l
e

i
c

t
o

r
,

I

Freescale Semiconductor, Inc.

For More Information On This Product,

Go to: www.freescale.com

.
.

Host Interface (HI08)

Servicing the Host Interface

MOTOROLA

DSP56309UM/D 6-31

connected to the HI08 may need external pull-up/pull-down resistors until the signals
are configured for operation. The registers cleared are the HPCR, HDDR, and HDR.
Selection between GPIO and HI08 is made by clearing HPCR bits 6 through 1 for GPIO
or setting these bits for HI08 functionality. If the HI08 is in GPIO mode, the HDDR
configures each corresponding signal in the HDR as an input signal if the HDDR bit is
cleared or as an output signal if the HDDR bit is set. (See Section 6.5.7ÑHost Data
Direction Register (HDDR)

on page 6-17 and Section 6.5.8ÑHost Data Register (HDR)

also on page 6-17.)

6.7

SERVICING THE HOST INTERFACE

The HI08 can be serviced by using one of the following protocols:

¥ Polling

¥ Interrupts

The host processor writes to the appropriate HI08 register to reset the control bits and
configure the HI08 for proper operation.

6.7.1

HI08 Host Processor Data Transfer

To the host processor, the HI08 looks like a contiguous block of Static RAM. To transfer
data between itself and the HI08, the host processor performs the following steps:

1. asserts the HI08 address to select the register to be read or written

2. selects the direction of the data transfer

(If it is writing, the host processor sources the data on the bus.)

3. strobes the data transfer

6.7.2

Polling

In polling mode, the HREQ/HTRQ signal is not connected to the host processor and
HACK must be deasserted to insure IVR data is not being driven on H[7:0] when other
registers are being polled. (If the HACK function is not needed, the HACK signal can be
configured as a GPIO signal, as documented in Section 6.5.6ÑHost Port Control
Register (HPCR)

on page 6-12.)

r
e

s
c

l
e

i
c

t
o

r
,

I

Freescale Semiconductor, Inc.

For More Information On This Product,

Go to: www.freescale.com

.
.

6-32

DSP56309UM/D MOTOROLA

Host Interface (HI08)

Servicing the Host Interface

The host processor first performs a data read transfer to read the ISR, as in Figure 6-16.
This convention allows the host processor to assess the status of the HI08 and perform
the appropriate actions.

Generally, after the appropriate data transfer has been made, the corresponding status
bit is updated to reflect the transfer.

¥ If RXDF is set, the receive data register is full, and the host processor can perform

a data read.

¥ If TXDE is set, the transmit data register is empty, and the host processor can

perform a data write.

¥ If TRDY is set, the transmit data register is empty. This implies that the receive

data register on the DSP side is also empty. Data written by the host processor to
the HI08 is transferred directly to the DSP side.

¥ If (HF2 and HF3)

0, depending on how the host flags have been used, this may

indicate that an application-specific state within the DSP56309 has been reached.
Intervention by the host processor may be required.

¥ If HREQ is set, the HREQ/TRQ signal has been asserted, and the DSP56309 is

requesting the attention of the host processor. One of the previous four conditions
exists.

After the appropriate data transfer has been made, the corresponding status bit is
updated to reflect the transfer.

If the host processor has issued a command to the DSP56309 by writing to the CVR and
setting the HC bit, it can read the HC bit in the CVR to determine whether the command
has been accepted by the interrupt controller in the DSP core. When the command has
been accepted for execution, the HC bit is cleared by the interrupt controller in the DSP
core.

6.7.3

Servicing Interrupts

If either HREQ/HTRQ or the HRRQ signal or both are connected to the host processorÕs
interrupt input, the HI08 can request service from the host processor by asserting one of
these signals. The HREQ/HTRQ and/or the HRRQ signal is asserted when TXDE is set
and/or RXDF is set and the corresponding enable bit (TREQ or RREQ, respectively) is
set. This situation appears in Figure 6-16.

r
e

s
c

l
e

i
c

t
o

r
,

I

Freescale Semiconductor, Inc.

For More Information On This Product,

Go to: www.freescale.com

.
.

Enhanced Synchronous Serial Interface (ESSI)

Introduction

MOTOROLA

DSP56309UM/D 7-3

7.1

INTRODUCTION

The Enhanced Synchronous Serial Interface (ESSI) provides a full-duplex serial port for
serial communication with a variety of serial devices, including one or more
industry-standard codecs, other DSPs, microprocessors, and peripherals that implement
the Motorola Serial Peripheral Interface (SPI). The ESSI consists of independent
transmitter and receiver sections and a common ESSI clock generator.

There are two independent and identical ESSIs in the DSP56309: ESSI0 and ESSI1. For
the sake of simplicity, a single generic ESSI is described.

The ESSI block diagram appears in Figure 7-1 on page 7-5. This interface is synchronous
because all serial transfers are synchronized to a clock.

Note:

This should not be confused with the asynchronous mode of the ESSI, in

which separate clocks are used for the receiver and transmitter. In this mode,
the ESSI is still a synchronous device, because all transfers are synchronized to
these clocks.

Additional synchronization signals are used to delineate the word frames. Normal mode
is used to transfer data at a periodic rate, one word per period. Network mode is similar
in that it is also intended for periodic transfers; however, it supports up to 32 words
(time slots) per period. Network mode can be used to build time division multiplexed
(TDM) networks. In contrast, on-demand mode is intended for non-periodic transfers of
data. This mode can be used to transfer data serially at high speed when the data become
available. This mode offers a subset of the SPI protocol.

Since each ESSI unit can be configured with one receiver and three transmitters, the two
units can be used together for surround sound applications (which need two digital
input channels and six digital output channels).

7.2

ENHANCEMENTS TO THE ESSI

The synchronous serial interface (SSI) used in the DSP56000 family has been enhanced in
the following ways to make the ESSI:

¥ Network enhancements

Ð Time slot mask registers (receive and transmit) added

Ð End-of-frame interrupt added

Ð Drive enable signal added (to be used with transmitter 0)

r
e

s
c

l
e

i
c

t
o

r
,

I

Freescale Semiconductor, Inc.

For More Information On This Product,

Go to: www.freescale.com

.
.

7-6

DSP56309UM/D MOTOROLA

Enhanced Synchronous Serial Interface (ESSI)

ESSI Data and Control Signals

modes; see Table 7-1 on page 7-8. SCK can be programmed as a GPIO signal (P3) when
the ESSI SCK function is not being used.

Notes:

Although an external serial clock can be independent of and asynchronous

to the DSP system clock, the external ESSI clock frequency must not exceed
F

core

/3, and each ESSI phase must exceed the minimum of 1.5 CLKOUT

cycles.

The internally sourced ESSI clock frequency must not exceed F

core

/4.

7.3.4

Serial Control Signal (SC0)

SC00 is a serial control signal for ESSI0, and SC10 is a serial control signal for ESSI1. They
are referred to collectively as SC0.

The function of this signal is determined by selecting either synchronous or
asynchronous mode; see Table 7-4 on page 7-24. In asynchronous mode, this signal is
used for the receive clock I/O. In synchronous mode, this signal is used as the
transmitter data out signal for transmit shift register 1 or for serial flag I/O. A typical
application of serial flag I/O would be multiple device selection for addressing in codec
systems.

If SC0 is configured as a serial flag signal, its direction is determined by the serial control
direction 0 (SCD0) bit in the ESSI control register B (CRB). When configured as an
output, its value is determined by the value of the serial output flag 0 (OF0) bit in the
CRB. When configured as an input, SC0 controls the state of serial input flag 0 (IF0) bit in
the ESSI status register (SSISR).

When SC0 is configured as a transmit data signal, it is always an output signal
regardless of the SCD0 bit value. SC0 is fully synchronized with the other transmit data
signals (STD and SC1).

In asynchronous mode, SC0 is configured as the receive clock. The direction of the SC0
in this mode is also determined by SCD0.

SC0 can be programmed as a GPIO signal (P0) when the ESSI SC0 function is not being
used.

Note:

The ESSI can operate with more than one active transmitter only in

synchronous mode.

r
e

s
c

l
e

i
c

t
o

r
,

I

Freescale Semiconductor, Inc.

For More Information On This Product,

Go to: www.freescale.com

.
.

Enhanced Synchronous Serial Interface (ESSI)

ESSI Data and Control Signals

MOTOROLA

DSP56309UM/D 7-7

7.3.5

Serial Control Signal (SC1)

SC01 is a serial control signal for ESSI0, and SC11 is a serial control signal for ESSI1. They
are referred to collectively as SC1.

The function of this signal is determined by selecting either synchronous or
asynchronous mode; see Table 7-4 on page 7-24. In asynchronous mode (such as a single
codec with asynchronous transmit and receive), SC1 is the receiver frame sync I/O. In
synchronous mode, SC1 is used for the transmitter data out signal of transmit shift
register TX2, for the drive enable transmitter 0 signal, or for serial flag SC1.

When used as a serial flag signal, SC1 operates like the previously described SC0. SC0
and SC1 are independent flags but can be used together for multiple serial device
selection. SC0 and SC1 can be used unencoded to select up to two codecs or can be
decoded externally to select up to four codecs.

If SC1 is configured as a serial flag signal, its direction is determined by the SCD1 bit in
the CRB. When configured as an output, its value is determined by the value of the serial
output flag1 (OF1) bit in the CRB. When configured as an input, SC0 controls the stated
serial input flag 1 (IF1) bits in SSISR.

When SC1 is configured as a transmit data signal, it is always an output signal
regardless of the SCD1 bit value. As an output, it is fully synchronized with the other
ESSI transmit data signals (STD and SC0).

In asynchronous mode, SC1 is configured as the receive frame sync. The direction of SC1
in this mode is determined by SCD1.

SC1 can be programmed as a GPIO signal (P1) when the ESSI SC1 function is not being
used.

Table 7-1

summarizes ESSI clock sources, whether synchronous or asynchronous, and

shows the bit settings for the signals involved.

r
e

s
c

l
e

i
c

t
o

r
,

I

Freescale Semiconductor, Inc.

For More Information On This Product,

Go to: www.freescale.com

.
.

Enhanced Synchronous Serial Interface (ESSI)

ESSI Programming Model

MOTOROLA

DSP56309UM/D 7-11

7.4.1

ESSI Control Register A (CRA)

The ESSI control register A (CRA) is one of two 24-bit, read/write control registers used
to direct the operation of the ESSI. The CRA controls the ESSI clock generator bit and
frame sync rates, word length, and number of words per frame for the serial data. The
CRA control bits are described in the following paragraphs; see also Figure 7-2 on
page 7-9.

7.4.1.1

CRA Prescale Modulus Select PM[7:0] Bits 7Ð0

The PM[7:0] bits specify the divide ratio of the prescale divider in the ESSI clock
generator. A divide ratio from 1 to 256 (PM = $0 to $FF) can be selected. The bit clock
output is available at the transmit clock signal (SCK) and/or the receive clock (SC0)
signal of the DSP. The bit clock output is also available internally for use as the bit clock
to shift the transmit and receive shift registers. The ESSI clock generator functional
diagram is shown in Figure 7-9. F

core

is the DSP56309 core clock frequency (the same

frequency as the CLKOUT signal, when that signal is enabled). Careful choice of the
crystal oscillator frequency and the prescaler modulus allows generation of the
industry-standard codec master clock frequencies of 2.048 MHz, 1.544 MHz, and
1.536 MHz. Both the hardware RESET signal and the software RESET instruction clear

PM[7:0].

7.4.1.2

CRA Reserved Bits 8Ð10

These bits are reserved. They are read as 0 and should be written with 0.

7.4.1.3

CRA Prescaler Range (PSR) Bit 11

The PSR controls a fixed divide-by-eight prescaler in series with the variable prescaler.
This bit is used to extend the range of the prescaler for those cases where a slower bit
clock is desired. When PSR is set, the fixed prescaler is bypassed. When PSR is cleared,
the fixed divide-by-eight prescaler is operational; see Figure 7-9 on page 7-12.

Note:

This definition is reversed from that of the 560xx SSI.

The maximum allowed internally generated bit clock frequency is the internal DSP56309
clock frequency divided by 4; the minimum possible internally generated bit clock
frequency is the DSP56309 internal clock frequency divided by 4096. Both the hardware
RESET signal and the software RESET instruction clear PSR.

r
e

s
c

l
e

i
c

t
o

r
,

I

Freescale Semiconductor, Inc.

For More Information On This Product,

Go to: www.freescale.com

.
.

7-12

DSP56309UM/D MOTOROLA

Enhanced Synchronous Serial Interface (ESSI)

ESSI Programming Model

Note:

The combination PSR = 1 and PM[7:0] = $00 (dividing F

core

by 2) can cause

synchronization problems and should not be used.

7.4.1.4

CRA Frame Rate Divider Control DC[4:0] Bits 16Ð12

The values of the DC[4:0] bits control the divide ratio for the programmable frame rate
dividers used to generate the frame clocks. In network mode, this ratio can be
interpreted as the number of words per frame minus one. In normal mode, this ratio
determines the word transfer rate.

The divide ratio can range from 1 to 32 (DC = 00000 to 11111) for normal mode and 2 to
32 (DC = 00001 to 11111) for network mode. A divide ratio of one (DC = 00000) in
network mode is a special case known as on-demand mode. In normal mode, a divide
ratio of one (DC = 00000) provides continuous periodic data word transfers. A bit-length
frame sync must be used in this case and is selected by setting the FSL[1:0] bits in the
CRA to (01). Both the hardware RESET signal and the software RESET instruction clear
DC[4:0].

The ESSI frame sync generator functional diagram is shown in Figure 7-10.

Figure 7-9

ESSI Clock Generator Functional Block Diagram

SCn0

SCKn

CRB(SCD0)

CRB(SCKD)

CRB(SYN) = 1

SCD0 = 0

RCLOCK

TCLOCK

Internal Bit Clock

SYN = 1

CRA(WL2:0)

RX Shift Register

TX Shift Register

/1 or /8

/1 to /256

CORE

RX
Word
Clock

SYN = 0

SCD0 = 1

Note: 1. F

CORE

is the DSP56300 Core internal

clock frequency.

2. ESSI internal clock range:

min = F

OSC

/4096

max = F

OSC

3. ÔnÕ in signal name is ESSI # (0 or 1)

AA0679

Sync:

TX #1, or

Async:

RX clk

Sync:

TX/RX clk

Async:

TX clk

255

CRA(PSR)

CRA(PM7:0)

/8, /12, /16, /24, /32

4,5

Flag0 Out

(Sync Mode)

CRB(OF0)

CRB(TE1)

TX #1

Flag0 In

(Sync Mode)

SSISR(IF0)

SYN = 0

/8, /12, /16, /24, /32

4,5

CRA(WL2:0)

TX
Word
Clock

Flag0

(Opposite

from SSI)

r
e

s
c

l
e

i
c

t
o

r
,

I

Freescale Semiconductor, Inc.

For More Information On This Product,

Go to: www.freescale.com

.
.

Enhanced Synchronous Serial Interface (ESSI)

ESSI Programming Model

MOTOROLA

DSP56309UM/D 7-13

7.4.1.5

CRA Reserved Bit 17

This bit is reserved. It is read as 0 and should be written with 0.

7.4.1.6

CRA Alignment Control (ALC) Bit 18

The ESSI is designed for 24-bit fractional data. Shorter data words are left aligned to the
MSB, Bit 23. For applications that use 16 bit fractional data, shorter data words are left
aligned to bit 15. The ALC bit supports shorter data words. If ALC is set, received words
are left aligned to bit 15 in the receive shift register. Transmitted words must be left
aligned to bit 15 in the transmit shift register. If the ALC bit is cleared, received words
are left aligned to bit 23 in the receive shift register. Transmitted words must be left
aligned to bit 23 in the transmit shift register. The ALC bit is cleared by either a
hardware RESET signal or a software RESET instruction.

Note:

If the ALC bit is set, only 8-, 12-, or 16-bit words should be used. The use of

24- or 32-bit words leads to unpredictable results.

Figure 7-10

ESSI Frame Sync Generator Functional Block Diagram

Frame Sync

Transmit

Frame Sync

Receive

RX Word

Clock

TX Word

Clock

CRA(DC4:0)

Receive

Control Logic

Transmit

Control Logic

Sync

Type

Sync

Type

CRB(SYN) = 0

SYN = 1

Internal Rx Frame Sync

CRB(SCD1) = 1

SYN = 1

SCD1 = 0

SYN = 0

CRB(SCD1)

Internal TX Frame Sync

AA0680

SCn1

/1 to /32

CRB(FSL1)

CRB(FSL1:0)

CRA(DC4:0)

/1 to /32

SCn2

CRB(SCD2)

Flag1 Out,

(Sync Mode)

CRB(OF1)

CRB(TE2)

TX #2,

or drive enb.

CRA(SSC1)

Flag1 In

SSISR(IF1)

(Sync Mode)

CRB(FSR)

Sync:

TX #2,

Async:

RX F.S.

Flag1, or
drive enb.

Sync:

TX/RX F.S.

Async:

TX F.S.

CRB(FSR)

These signals are
identical in sync mode.

r
e

s
c

l
e

i
c

t
o

r
,

I

Freescale Semiconductor, Inc.

For More Information On This Product,

Go to: www.freescale.com

.
.

Enhanced Synchronous Serial Interface (ESSI)

ESSI Programming Model

MOTOROLA

DSP56309UM/D 7-15

7.4.2

ESSI Control Register B (CRB)

The CRB is one of two 24-bit, read/write control registers used to direct the operation of
the ESSI; see Figure 7-3 on page 7-9. CRB controls the ESSI multifunction signals,
SC[2:0], which can be used as clock inputs or outputs, frame synchronization signals,
transmit data signals, or serial I/O flag signals.

The serial output flag control bits and the direction control bits for the serial control
signals are in the ESSI CRB. Interrupt enable bits for the receiver and the transmitter are
also in the CRB. The bit setting of the CRB also determines how many transmitters are
enabled (0, 1, 2, or 3 transmitters can be enabled). The CRB settings also determine the
ESSI operating mode.

Either a hardware RESET signal or a software RESET instruction clears all the bits in the
CRB.

The relationship between the ESSI signals SC[2:0], SCK, and the CRB bits is summarized
in Table 7-4 on page 7-24. The ESSI CRB bits are described in the following paragraphs.

7.4.2.1

CRB Serial Output Flags (OF0, OF1) Bits 0, 1

The ESSI has two serial output flag bits, OF1 and OF0. The normal sequence for setting
output flags when transmitting data (by transmitter 0 through the STD signal only)
consists of these steps:

1. Wait for TDE (TX0 empty) to be set.

2. Write the flags.

3. Write the transmit data to the TX register.

Bits OF0 and OF1 are double-buffered so that the flag states appear on the signals when
the TX data is transferred to the transmit shift register. The flag bits values are
synchronized with the data transfer.

Note:

The timing of the optional serial output signals SC[2:0] is controlled by the

frame timing and is not affected by the settings of TE2, TE1, TE0, or the receive
enable (RE) bit of the CRB.

7.4.2.1.1

CRB Serial Output Flag 0 (OF0) Bit 0

When the ESSI is in synchronous mode and transmitter 1 is disabled (TE1 = 0), the SC0
signal is configured as ESSI flag 0. If the serial control direction bit (SCD0) is set, the SC0
signal is an output. Data present in bit OF0 is written to SC0 at the beginning of the
frame in normal mode or at the beginning of the next time slot in network mode.

r
e

s
c

l
e

i
c

t
o

r
,

I

Freescale Semiconductor, Inc.

For More Information On This Product,

Go to: www.freescale.com

.
.

7-16

DSP56309UM/D MOTOROLA

Enhanced Synchronous Serial Interface (ESSI)

ESSI Programming Model

Bit OF0 is cleared by a hardware RESET signal or by a software RESET instruction.

7.4.2.1.2

CRB Serial Output Flag 1 (OF1) Bit 1

When the ESSI is in synchronous mode and transmitter 2 is disabled (TE2 = 0), the SC1
signal is configured as ESSI flag 1. If the serial control direction bit (SCD1) is set, the SC1
signal is an output. Data present in bit OF1 is written to SC1 at the beginning of the
frame in normal mode or at the beginning of the next time slot in network mode.

Bit OF1 is cleared by a hardware RESET signal or by a software RESET instruction.

7.4.2.2

CRB Serial Control Direction 0 (SCD0) Bit 2

In synchronous mode (SYN = 1) when transmitter 1 is disabled (TE1 = 0), or in
asynchronous mode (SYN = 0), SCD0 controls the direction of the SC0 I/O signal. When
SCD0 is set, SC0 is an output; when SCD0 is cleared, SC0 is an input.

When TE1 is set, the value of SCD0 is ignored, and the SC0 signal is always an output.

Bit SCD0 is cleared by a hardware RESET signal or by a software RESET instruction.

7.4.2.3

CRB Serial Control Direction 1 (SCD1) Bit 3

In synchronous mode (SYN = 1) when transmitter 2 is disabled (TE2 = 0), or in
asynchronous mode (SYN = 0), SCD1 controls the direction of the SC1 I/O signal. When
SCD1 is set, SC1 is an output; when SCD1 is cleared, SC1 is an input.

When TE2 is set, the value of SCD1 is ignored, and the SC1 signal is always an output.
Bit SCD1 is cleared by a hardware RESET signal or by a software RESET instruction.

7.4.2.4

CRB Serial Control Direction 2 (SCD2) Bit 4

SCD2 controls the direction of the SC2 I/O signal. When SCD2 is set, SC2 is an output;
when SCD2 is cleared, SC2 is an input. SCD2 is cleared by a hardware RESET signal or
by a software RESET instruction.

7.4.2.5

CRB Clock Source Direction (SCKD) Bit 5

SCKD selects the source of the clock signal. If SCKD is set and the ESSI is in synchronous
mode, the internal clock is the source of the clock signal used for all the transmit shift
registers and the receive shift register. If SCKD is set and the ESSI is in asynchronous
mode, the internal clock source becomes the bit clock for the transmit shift register and
word length divider. The internal clock is output on the SCK signal.

When SCKD is cleared, the external clock source is selected. The internal clock generator
is disconnected from the SCK signal, and an external clock source can drive this signal.

Either a hardware RESET signal or a software RESET instruction clears SCKD.

r
e

s
c

l
e

i
c

t
o

r
,

I

Freescale Semiconductor, Inc.

For More Information On This Product,

Go to: www.freescale.com

.
.

Enhanced Synchronous Serial Interface (ESSI)

ESSI Programming Model

MOTOROLA

DSP56309UM/D 7-17

7.4.2.6

CRB Shift Direction (SHFD) Bit 6

The setting of the SHFD bit determines the shift direction of the transmit or receive shift
register. If SHFD is set, data is shifted out with the LSB first. If SHFD is cleared, data is
shifted out MSB first; see Figure 7-16 on page 7-31 and Figure 7-17 on page 7-32.
Received data is shifted in LSB first when SHFD is set or MSB first when SHFD is
cleared.

Either a hardware RESET signal or a software RESET instruction clears SHFD.

7.4.2.7

CRB Frame Sync Length FSL[1:0] Bits 7 and 8

These bits select the length of frame sync to be generated or recognized; see Figure 7-11
on page 7-19, Figure 7-14 on page 7-22, and Figure 7-15 on page 7-23. The values of
FSL[1:0] are documented in Table 7-3.

The word length is defined by WL[2:0].

Either a hardware RESET signal or a software RESET instruction clears FSL[1:0].

7.4.2.8

CRB Frame Sync Relative Timing (FSR) Bit 9

The FSR bit determines the relative timing of the receive and transmit frame sync signal
in reference to the serial data lines, for word length frame sync only. When FSR is
cleared, the word length frame sync occurs together with the first bit of the data word of
the first slot. When FSR is set, the word length frame sync occurs one serial clock cycle
earlier (i.e., simultaneously with the last bit of the previous data word).

Either a hardware RESET signal or a software RESET instruction clears FSR.

7.4.2.9

CRB Frame Sync Polarity (FSP) Bit 10

The FSP bit determines the polarity of the receive and transmit frame sync signals. When
FSP is cleared, the frame sync signal polarity is positive (i.e., the frame start is indicated

Table 7-3

FSL1 and FSL0 Encoding

FSL1

FSL0

Frame Sync Length

word

bit

word

r
e

s
c

l
e

i
c

t
o

r
,

I

Freescale Semiconductor, Inc.

For More Information On This Product,

Go to: www.freescale.com

.
.

7-22

DSP56309UM/D MOTOROLA

Enhanced Synchronous Serial Interface (ESSI)

ESSI Programming Model

7.4.2.13

Enabling, Disabling ESSI Data Transmission

The ESSI has three transmit enable bits (TE[2:0]), one for each data transmitter. The
process of transmitting data from TX1 and TX2 is the same. TX0 can also operate in
asynchronous mode. The normal transmit enable sequence is to write data to one or
more transmit data registers (or the time slot register (TSR)) before setting the TE bit. The
normal transmit disable sequence is to clear the TE, transmit interrupt enable (TIE), and
transmit exception interrupt enable (TEIE) bits after the transmit data empty (TDE) bit is
set. In network mode, clearing the appropriate TE bit and setting it again disables the
corresponding transmitter (0, 1, or 2) after transmission of the current data word. The
transmitter remains disabled until the beginning of the next frame. During that time
period, the corresponding SC (or STD in the case of TX0) signal remains in the
high-impedance state.

7.4.2.14

CRB ESSI Transmit 2 Enable (TE2) Bit 14

The TE2 bit enables the transfer of data from TX2 to transmit shift register 2. TE2 is
functional only when the ESSI is in synchronous mode and is ignored when the ESSI is
in asynchronous mode.

When TE2 is set and a frame sync is detected, transmitter 2 is enabled for that frame.

When TE2 is cleared, transmitter 2 is disabled after completing transmission of data
currently in the ESSI transmit shift register. Any data present in TX2 is not transmitted. If
TE2 is cleared, data can be written to TX2; the TDE bit is cleared, but data is not
transferred to transmit shift register 2.

Figure 7-14

Normal Mode, External Frame Sync (8 Bit, 1 Word in Frame)

Frame SYNC

(FSL0 = 0, FSL1 = 0)

Frame SYNC

(FSL0 = 0, FSL1 = 1)

Data Out

Flags

Slot 0

Wait

AA0684

r
e

s
c

l
e

i
c

t
o

r
,

I

Freescale Semiconductor, Inc.

For More Information On This Product,

Go to: www.freescale.com

.
.

7-24

DSP56309UM/D MOTOROLA

Enhanced Synchronous Serial Interface (ESSI)

ESSI Programming Model

The TE1 bit is cleared by either a hardware RESET signal or a software RESET
instruction.

Note:

The setting of the TE1 bit does not affect the generation of frame sync or

output flags.

7.4.2.16

CRB ESSI Transmit 0 Enable (TE0) Bit 16

The TE0 bit enables the transfer of data from TX0 to transmit shift register 0. TE0 is
functional when the ESSI is in either synchronous or asynchronous mode.

When TE0 is set and a frame sync is detected, the transmitter 0 is enabled for that frame.

When TE0 is cleared, transmitter 0 is disabled after completing transmission of data
currently in the ESSI transmit shift register. The STD output is tri-stated, and any data
present in TX0 is not transmitted (i.e., data can be written to TX0 with TE0 cleared; the
TDE bit is cleared, but data is not transferred to the transmit shift register 0).

The TE0 bit is cleared by either a hardware RESET signal or a software RESET
instruction.

The transmit enable sequence for on-demand mode can be the same as for normal mode,
or TE0 can be left enabled.

Note:

Transmitter 0 is the only transmitter that can operate in asynchronous mode

(SYN = 0). TE0 does not affect the generation of frame sync or output flags.

Table 7-4

summarizes the preceding sections; it shows possible settings of control bits

and their associated signals.

Table 7-4

Mode and Signal Definition Table

Control Bits

ESSI Signals

SYN

TE0

TE1

TE2

SC0

SC1

SC2

SCK

STD

SRD

RXC

FSR

FST

TXC

TD0

RXC

FSR

FST

TXC

TD0

r
e

s
c

l
e

i
c

t
o

r
,

I

Freescale Semiconductor, Inc.

For More Information On This Product,

Go to: www.freescale.com

.
.

7-26

DSP56309UM/D MOTOROLA

Enhanced Synchronous Serial Interface (ESSI)

ESSI Programming Model

7.4.2.17

CRB ESSI Receive Enable (RE) Bit 17

When the RE bit is set, the receive portion of the ESSI is enabled. When this bit is cleared,
the receiver is disabled by inhibiting data transfer into RX. If data is being received while
this bit is cleared, the remainder of the word is shifted in and transferred to the ESSI
receive data register.

RE must be set in both the normal and on-demand modes for the ESSI to receive data. In
network mode, clearing RE and setting it again disables the receiver after reception of
the current data word. The receiver remains disabled until the beginning of the next data
frame.

RE is cleared by either a hardware RESET signal or a software RESET instruction.

Note:

The setting of the RE bit does not affect the generation of a frame sync.

7.4.2.18

CRB ESSI Transmit Interrupt Enable (TIE) Bit 18

Setting the TIE bit enables a DSP transmit interrupt, which is generated when both the
TIE and the TDE bits in the ESSI status register are set. When TIE is cleared, the transmit
interrupt is disabled. The use of the transmit interrupt is described in Section 7.5.3.
Writing data to the data registers of the enabled transmitters or to the TSR clears TDE
and also clears the interrupt. Transmit interrupts with exception conditions have higher
priority than normal transmit data interrupts. If the transmitter underrun error (TUE) bit
is set, signaling that an exception has occurred, and the TEIE bit is set, the ESSI requests
an SSI transmit data with exception interrupt from the interrupt controller.

TIE is cleared by either a hardware RESET signal or a software RESET instruction.

7.4.2.19

CRB ESSI Receive Interrupt Enable (RIE) Bit 19

Setting the RIE enables a DSP receive data interrupt, which is generated when both the
RIE and receive data register full (RDF) bit in the SSISR are set. When RIE is cleared, this
interrupt is disabled. The use of the receive interrupt is described in Section 7.5.3.
Reading the receive data register clears RDF and the pending interrupt. Receive
interrupts with exception have higher priority than normal receive data interrupts. If the
receiver overrun error (ROE) bit is set, signaling that an exception has occurred, and the
REIE bit is set, the ESSI requests an SSI receive data with exception interrupt from the
interrupt controller.

RIE is cleared by either a hardware RESET signal or a software RESET instruction.

7.4.2.20

Transmit Last Slot Interrupt Enable (TLIE) Bit 20

Setting the TLIE bit enables an interrupt at the beginning of the last slot of a frame when
the ESSI is in network mode. When TLIE is set, the DSP is interrupted at the start of the
last slot in a frame regardless of the transmit mask register setting. When TLIE is cleared,

r
e

s
c

l
e

i
c

t
o

r
,

I

Freescale Semiconductor, Inc.

For More Information On This Product,

Go to: www.freescale.com

.
.

Enhanced Synchronous Serial Interface (ESSI)

ESSI Programming Model

MOTOROLA

DSP56309UM/D 7-27

the transmit last slot interrupt is disabled. The use of the transmit last slot interrupt is
described in Section 7.5.3ÑESSI Exceptions.

TLIE is cleared by either a hardware RESET signal or a software RESET instruction. TLIE
is disabled when the ESSI is in on-demand mode (DC = $0).

7.4.2.21

Receive Last Slot Interrupt Enable (RLIE) Bit 21

Setting the RLIE bit enables an interrupt after the last slot of a frame ends when the ESSI
is in network mode. When RLIE is set, the DSP is interrupted after the last slot in a frame
ends regardless of the receive mask register setting. When RLIE is cleared, the receive
last slot interrupt is disabled. The use of the receive last slot interrupt is described in
Section 7.5.3ÑESSI Exceptions

RLIE is cleared by either a hardware RESET signal or a software RESET instruction.
RLIE is disabled when the ESSI is in on-demand mode (DC = $0).

7.4.2.22

Transmit Exception Interrupt Enable (TEIE) Bit 22

When the TEIE bit is set, the DSP is interrupted when both TDE and TUE in the ESSI
Status Register are set. When TEIE is cleared, this interrupt is disabled. The use of the
transmit interrupt is described in Section 7.5.3ÑESSI Exceptions. Reading the status
register, followed by writing to all the data registers of the enabled transmitters, clears
both TUE and the pending interrupt.

TEIE is cleared by either a hardware RESET signal or a software RESET instruction.

7.4.2.23

Receive Exception Interrupt Enable (REIE) Bit 23

When the REIE bit is set, the DSP is interrupted when both RDF and ROE in the ESSI
status register are set. When REIE is cleared, this interrupt is disabled. The use of the
receive interrupt is described in Section 7.5.3ÑESSI Exceptions. Reading the status
register followed by reading the receive data register clears both ROE and the pending
interrupt.

REIE is cleared by either a hardware RESET signal or a software RESET instruction.

7.4.3

ESSI Status Register (SSISR)

The SSISR (in Figure 7-4 on page 7-9) is a 24-bit, read-only status register used by the
DSP to read the status and serial input flags of the ESSI. The SSISR bits are documented
in the following paragraphs.

r
e

s
c

l
e

i
c

t
o

r
,

I

Freescale Semiconductor, Inc.

For More Information On This Product,

Go to: www.freescale.com

.
.

7-28

DSP56309UM/D MOTOROLA

Enhanced Synchronous Serial Interface (ESSI)

ESSI Programming Model

7.4.3.1

SSISR Serial Input Flag 0 (IF0) Bit 0

The IF0 bit is enabled only when SC0 is an input flag and synchronous mode is selected
(i.e., when the SYN bit is set, and the TE1 and SCD0 bits are cleared).

The ESSI latches data present on the SC0 signal during reception of the first received bit
after the frame sync is detected. The IF0 bit is updated with this data when the data in
the receive shift register is transferred into the receive data register.

If it is not enabled, the IF0 bit is cleared.

A hardware RESET signal, software RESET instruction, ESSI individual reset, or STOP
instruction clears the IF0 bit.

7.4.3.2

SSISR Serial Input Flag 1 (IF1) Bit 1

The IF1 bit is enabled only when SC1 is an input flag and synchronous mode is selected,
the SYN bit is set, and the TE2 and SCD1 bits are cleared.

The ESSI latches data present on the SC1 signal during reception of the first received bit
after the frame sync is detected. The IF1 bit is updated with this data when the data in
the receive shift register is transferred into the receive data register.

If it is not enabled, the IF1 bit is cleared.

A hardware RESET signal, software RESET instruction, ESSI individual reset, or STOP
instruction clears the IF1 bit.

7.4.3.3

SSISR Transmit Frame Sync Flag (TFS) Bit 2

When set, TFS indicates that a transmit frame sync occurred in the current time slot. TFS
is set at the start of the first time slot in the frame and cleared during all other time slots.
If the transmitter is enabled, data written to a transmit data register during the time slot
when TFS is set is transmitted (in network mode) during the second time slot in the
frame. TFS is useful in network mode to identify the start of a frame. TFS is valid only if
at least one transmitter is enabled (TE0, TE1 or TE2 are set).

A hardware RESET signal, software RESET instruction, ESSI individual reset, or STOP
instruction clears TFS.

Note:

In normal mode, TFS is always read as 1 when transmitting data because there

is only one time slot per frame, the Ôframe syncÕ time slot.

7.4.3.4

SSISR Receive Frame Sync Flag (RFS) Bit 3

When set, the RFS bit indicates that a receive frame sync occurred during the reception
of a word in the serial receive data register. This means that the data word is from the

r
e

s
c

l
e

i
c

t
o

r
,

I

Freescale Semiconductor, Inc.

For More Information On This Product,

Go to: www.freescale.com

.
.

Enhanced Synchronous Serial Interface (ESSI)

ESSI Programming Model

MOTOROLA

DSP56309UM/D 7-29

first time slot in the frame. When the RFS bit is cleared and a word is received, it
indicates (only in Network mode) that the frame sync did not occur during reception of
that word. RFS is valid only if the receiver is enabled (i.e., the RE bit is set).

A hardware RESET signal, software RESET instruction, ESSI individual reset, or STOP
instruction clears RFS.

Note:

In normal mode, RFS is always read as 1 when reading data because there is

only one time slot per frame, the frame sync time slot.

7.4.3.5

SSISR Transmitter Underrun Error Flag (TUE) Bit 4

The TUE bit is set when at least one of the enabled serial transmit shift registers is empty
(no new data to be transmitted) and a transmit time slot occurs. When a transmit
underrun error occurs, the previous data (which is still present in the TX registers that
were not written) is retransmitted. In normal mode, there is only one transmit time slot
per frame. In network mode, there can be up to thirty-two transmit time slots per frame.
If the TEIE bit is set, a DSP transmit underrun error interrupt request is issued when the
TUE bit is set.

A hardware RESET signal, software RESET instruction, ESSI individual reset, or STOP
instruction clears TUE. TUE can also be cleared by first reading the SSISR with the TUE
bit set, then writing to all the enabled transmit data registers or to the TSR.

7.4.3.6

SSISR Receiver Overrun Error Flag (ROE) Bit 5

The ROE bit is set when the serial receive shift register is filled and ready to transfer to
the receive data register (RX), but RX is already full (i.e., the RDF bit is set). If the REIE
bit is set, a DSP receiver overrun error interrupt request is issued when the ROE bit is set.

A hardware RESET signal, software RESET instruction, ESSI individual reset, or STOP
instruction clears ROE. ROE can also be cleared by reading the SSISR with the ROE bit
set and then reading the RX.

7.4.3.7

ESSI Transmit Data Register Empty (TDE) Bit 6

The TDE bit is set when the contents of the transmit data register of every enabled
transmitter are transferred to the transmit shift register. It is also set for a TSR disabled
time slot period in network mode (as if data were being transmitted after the TSR was
written). When set, the TDE bit indicates that data should be written to all the TX
registers of the enabled transmitters or to the TSR. The TDE bit is cleared when the
DSP56309 writes to all the transmit data registers of the enabled transmitters or when the
DSP writes to the TSR to disable transmission of the next time slot. If the TIE bit is set, a
DSP transmit data interrupt request is issued when TDE is set. A hardware RESET
signal, software RESET instruction, ESSI individual reset, or STOP instruction clears the
TDE bit.

r
e

s
c

l
e

i
c

t
o

r
,

I

Freescale Semiconductor, Inc.

For More Information On This Product,

Go to: www.freescale.com

.
.

Enhanced Synchronous Serial Interface (ESSI)

ESSI Programming Model

MOTOROLA

DSP56309UM/D 7-33

7.4.4

ESSI Receive Shift Register

The 24-bit receive shift register (in Figure 7-16 on page 7-31 and Figure 7-17 on
page 7-32) receives the incoming data from the serial receive data signal. Data is shifted
in by the selected (internal/external) bit clock when the associated frame sync I/O is
asserted. It is assumed that data is received MSB first if SHFD is cleared and LSB first if
SHFD is set. Data is transferred to the ESSI receive data register after 8, 12, 16, 24, or 32
serial clock cycles are counted, depending on the word-length control bits in the CRA.

7.4.5

ESSI Receive Data Register (RX)

The receive data register (RX) is a 24-bit, read-only register that accepts data from the
receive shift register as it becomes full; see Figure 7-16 on page 7-31 and Figure 7-17 on
page 7-32. The data read is aligned according to the value of the ALC bit. When the ALC
bit is cleared, the MSB is bit 23 and the least significant byte is unused. When the ALC bit
is set, the MSB is bit 15 and the most significant byte is unused. Unused bits are read as
0s. If the associated interrupt is enabled, the DSP is interrupted whenever the RX register
becomes full.

7.4.6

ESSI Transmit Shift Registers

The three 24-bit transmit shift registers contain the data being transmitted; see
Figure 7-16

on page 7-31 and Figure 7-17 on page 7-32. Data is shifted out to the serial

transmit data signals by the selected (internal/external) bit clock when the associated
frame sync I/O is asserted. The word-length control bits in the CRA determine the
number of bits that must be shifted out before the shift registers are considered empty
and can be written to again. Depending on the setting of the CRA, the number of bits to
be shifted out can be 8, 12, 16, 24, or 32 bits.

The data transmitted is aligned according to the value of the ALC bit. When the ALC bit
is cleared, the MSB is bit 23 and the least significant byte is unused. When ALC is set, the
MSB is bit 15 and the most significant byte is unused. Unused bits are read as 0s. Data is
shifted out of these registers MSB first if the SHFD bit is cleared and LSB first if the
SHFD bit is set.

r
e

s
c

l
e

i
c

t
o

r
,

I

Freescale Semiconductor, Inc.

For More Information On This Product,

Go to: www.freescale.com

.
.

7-34

DSP56309UM/D MOTOROLA

Enhanced Synchronous Serial Interface (ESSI)

ESSI Programming Model

7.4.7

ESSI Transmit Data Registers (TX0-2)

TX20, TX10, and TX00 are transmit data registers for ESSI0. TX21, TX11, and TX01 are
transmit data registers for ESSI1. TX20 and TX21 are known as TX2. TX10 and TX11 are
known as TX1. TX00 and TX01 are known as TX0.

TX2, TX1, and TX0 are 24-bit, write-only registers. Data to be transmitted is written into
these registers and automatically transferred to the transmit shift registers; see
Figure 7-16

on page 7-31 and Figure 7-17 on page 7-32. The data transmitted (8, 12, 16, or

24 bits) is aligned according to the value of the ALC bit. When the ALC bit is cleared, the
MSB is Bit 23. When ALC is set, the MSB is Bit 15. If the transmit data register empty
interrupt has been enabled, the DSP is interrupted whenever a transmit data register
becomes empty.

Note:

When data is written to a peripheral device, there is a two cycle pipeline delay

for further details.

7.4.8

ESSI Time Slot Register (TSR)

TSR is effectively a write-only null data register that is used to prevent data transmission
in the current transmit time slot. For the purposes of timing, TSR is a write-only register
that behaves like an alternative transmit data register, except that, rather than
transmitting data, the transmit data signals of all the enabled transmitters are in the
high-impedance state for the current time slot.

7.4.9

Transmit Slot Mask Registers (TSMA, TSMB)

The transmit slot mask Registers are two 16-bit, read/write registers. When the TSMA or
TSMB is read to the internal data bus, the register contents occupy the two low-order
bytes of the data bus, and the high-order byte is zero-filled. In network mode, these
registers are used by the transmitter(s) to determine what action to take in the current
transmission slot. Depending on the setting of the bits, the transmitter(s) either tri-state
the transmitter(s) data signal(s) or transmit a data word and generate a transmitter
empty condition.

r
e

s
c

l
e

i
c

t
o

r
,

I

Freescale Semiconductor, Inc.

For More Information On This Product,

Go to: www.freescale.com

.
.

Enhanced Synchronous Serial Interface (ESSI)

ESSI Programming Model

MOTOROLA

DSP56309UM/D 7-35

TSMA and TSMB (in Figure 7-16 on page 7-31 and Figure 7-17 on page 7-32) can be seen
as a single 32-bit register, TSM. Bit n in TSM (TSn) is an enable/disable control bit for
transmission in slot number N. When TSn is cleared, all the transmit data signals of the
enabled transmitters are tri-stated during transmit time slot number N. The data is still
transferred from the enabled transmit data register(s) to the transmit shift register.
However, the TDE and the TUE flags are not set. This means that during a disabled slot,
no transmitter empty interrupt is generated. The DSP is interrupted only for enabled
slots. Data written to the transmit data register when servicing the transmitter empty
interrupt request is transmitted in the next enabled transmit time slot.

When TSn is set, the transmit sequence proceeds normally. Data is transferred from the
TX register to the shift register during slot number N and the TDE flag is set.

Using the TSM slot mask does not conflict with using the TSR. Even if a slot is enabled in
the TSM, you can write to the TSR to tri-state the signals of the enabled transmitters
during the next transmission slot. Setting the bits in the TSM affects the next frame
transmission. The frame currently being transmitted is not affected by the new TSM
setting. If the TSM is read, it shows the current setting.

After a hardware RESET signal or software RESET instruction, the TSM register is reset
to $FFFFFFFF; this setting enables all thirty-two slots for data transmission.

7.4.10

Receive Slot Mask Registers (RSMA, RSMB)

The receive slot mask registers are two 16-bit, read/write registers. In network mode,
these registers are used by the receiver(s) to determine what action to take in the current
time slot. Depending on the setting of the bits, the receiver(s) either tri-state the
receiver(s) data signal(s) or receive a data word and generate a receiver full condition.

RSMA and RSMB (in Figure 7-16 on page 7-31 and Figure 7-17 on page 7-32) can be seen
as one 32-bit register, RSM. Bit n in RSM (RSn) is an enable/disable control bit for time
slot number N. When RSn is cleared, all the data signals of the enabled receivers are
tri-stated during time slot number N. Data is transferred from the receive data register(s)
to the receive shift register(s) and the RDF and ROE flags are not set. During a disabled
slot, no receiver full interrupt is generated. The DSP is interrupted only for enabled slots.

When RSn is set, the receive sequence proceeds normally. Data is received during slot
number N, and the RDF flag is set.

Setting the bits in the RSM affects the next frame transmission. The frame currently
being transmitted is not affected by the new RSM setting. If the RSM is read, it shows the
current setting.

r
e

s
c

l
e

i
c

t
o

r
,

I

Freescale Semiconductor, Inc.

For More Information On This Product,

Go to: www.freescale.com

.
.

7-36

DSP56309UM/D MOTOROLA

Enhanced Synchronous Serial Interface (ESSI)

Operating Modes

When the RSMA or RSMB register are read by the internal data bus, the register contents
occupy the two low-order bytes of the data bus, and the high-order byte is zero-filled.

After a hardware RESET signal or a software RESET instruction, the RSM register is reset
to $FFFFFFFF; this setting enables all thirty-two time slots for data transmission.

7.5

OPERATING MODES

The ESSI operating modes are selected by the ESSI control registers (CRA and CRB). The
operating modes are described in the following paragraphs.

7.5.1

ESSI After Reset

A hardware RESET signal or software RESET instruction clears the port control register
and the port direction control register. This situation configures all the ESSI signals as
GPIO. The ESSI is in the reset state while all ESSI signals are programmed as GPIO; the
ESSI is active only if at least one of the ESSI I/O signals is programmed as an ESSI signal.

7.5.2

ESSI Initialization

To initialize the ESSI, do the following:

1. Send a reset: a hardware RESET signal, software RESET instruction, ESSI

individual reset, or STOP instruction.

2. Program the ESSI control and time slot registers.

3. Write data to all the enabled transmitters.

4. Configure at least one signal as an ESSI signal.

5. If an external frame sync is used, from the moment the ESSI is activated, at least

five serial clocks are needed before the first external frame sync is supplied.
Otherwise, improper operation can result.

Clearing the PC[5:0] bits in the GPIO PCR during program execution causes the ESSI to
stop serial activity and enter the individual reset state. All status bits of the interface are
set to their reset state. The contents of CRA and CRB are not affected. The ESSI
individual reset allows a program to reset each interface separately from the other

r
e

s
c

l
e

i
c

t
o

r
,

I

Freescale Semiconductor, Inc.

For More Information On This Product,

Go to: www.freescale.com

.
.

Enhanced Synchronous Serial Interface (ESSI)

Operating Modes

MOTOROLA

DSP56309UM/D 7-37

internal peripherals. During ESSI individual reset, internal DMA accesses to the data
registers of the ESSI are not valid and data read is undefined.

To insure proper operation of the ESSI, use an ESSI individual reset when changing the
ESSI control registers (except for bits TEIE, REIE, TLIE, RLIE, TIE, RIE, TE2, TE1, TE0,
and RE).

Here is an example of initializing the ESSI.

1. Put the ESSI in its individual reset state by clearing the PCR bits.

2. Configure the control registers (CRA, CRB) to set the operating mode. Disable the

transmitters and receiver by clearing the TE[2:0] and RE bits. Set the interrupt
enable bits for the operating mode chosen.

3. Enable the ESSI by setting the PCR bits to activate the input/output signals to be

used.

4. Write initial data to the transmitters that are used during operation. This step is

needed even if DMA is used to service the transmitters.

5. Enable the transmitters and receiver to be used.

Now the ESSI can be serviced by polling, interrupts, or DMA.

Once the ESSI has been enabled (Step 3), operation starts as follows:

¥ For internally generated clock and frame sync, these signals start activity

immediately after the ESSI is enabled.

¥ Data is received by the ESSI after the occurrence of a frame sync signal (either

internally or externally generated) only when the receive enable (RE) bit is set.

¥ Data is transmitted after the occurrence of a frame sync signal (either internally or

externally generated) only when the transmitter enable (TE[2:0]) bit is set.

7.5.3

ESSI Exceptions

The ESSI can generate six different exceptions. They are discussed in the following
paragraphs (ordered from the highest to the lowest exception priority):

1. ESSI receive data with exception status:

Occurs when the receive exception interrupt is enabled, the receive data register
is full, and a receiver overrun error has occurred. This exception sets the ROE bit.
The ROE bit is cleared by first reading the SSISR and then reading RX.

r
e

s
c

l
e

i
c

t
o

r
,

I

Freescale Semiconductor, Inc.

For More Information On This Product,

Go to: www.freescale.com

.
.

7-38

DSP56309UM/D MOTOROLA

Enhanced Synchronous Serial Interface (ESSI)

Operating Modes

2. ESSI receive data:

Occurs when the receive interrupt is enabled, the receive data register is full, and
no receive error conditions exist. Reading RX clears the pending interrupt. This
error-free interrupt can use a fast interrupt service routine for minimum
overhead.

3. ESSI receive last slot interrupt:

Occurs when the ESSI is in network mode and the last slot of the frame has ended.
This interrupt is generated regardless of the receive mask register setting. The
receive last slot interrupt can be used to signal that the receive mask slot register
can be reset, the DMA channels can be reconfigured, and data memory pointers
can be reassigned. Using the receive last slot interrupt guarantees that the
previous frame was serviced with the previous setting and the new frame is
serviced with the new setting without synchronization problems.

Note:

The maximum time it takes to service a receive last slot interrupt should not

exceed N Ð 1 ESSI bits service time (where N is the number of bits the ESSI can
transmit per time slot).

4. ESSI transmit data with exception status:

Occurs when the transmit exception interrupt is enabled, at least one transmit
data register of the enabled transmitters is empty, and a transmitter underrun
error has occurred. This exception sets the TUE bit. The TUE bit is cleared by first
reading the SSISR and then writing to all the transmit data registers of the enabled
transmitters or by writing to the TSR to clear the pending interrupt.

5. ESSI transmit last slot interrupt:

Occurs when the ESSI is in network mode at the start of the last slot of the frame.
This exception occurs regardless of the transmit mask register setting. The
transmit last slot interrupt can be used to signal that the transmit mask slot
register can be reset, the DMA channels can be reconfigured, and data memory
pointers can be reassigned. Using the transmit last slot interrupt guarantees that
the previous frame was serviced with the previous setting, and the new frame is
serviced with the new setting without synchronization problems.

Note:

The maximum transmit last slot interrupt service time should not exceed

N Ð 1 ESSI bits service time (where N is the number of bits in a slot).

6. ESSI transmit data:

Occurs when the transmit interrupt is enabled, at least one of the enabled transmit
data registers is empty, and no transmitter error conditions exist. Writing to all
the enabled TX registers or to the TSR clears this interrupt. This error-free
interrupt can use a fast interrupt service routine for minimum overhead (if no
more than two transmitters are used).

To configure an ESSI exception, perform the following steps:

r
e

s
c

l
e

i
c

t
o

r
,

I

Freescale Semiconductor, Inc.

For More Information On This Product,

Go to: www.freescale.com

.
.

Enhanced Synchronous Serial Interface (ESSI)

Operating Modes

MOTOROLA

DSP56309UM/D 7-39

1. Configure interrupt service routine (ISR)

a. Load vector base address register.

VBA (b23:8)

b. Define I_VEC to be equal to the VBA value (if that is nonzero). If it is defined,

I_VEC must be defined for the assembler before the interrupt equate file is
included.

c. Load the exception vector table entry: two-word fast interrupt or

jump/branch to subroutine (long interrupt).

p:I_SI0TD

2. Configure interrupt trigger/preload transmit data

a. Enable and prioritize overall peripheral interrupt functionality.

IPRP (S0L1:0)

b. Enable peripheral and associated signals.

PCRC (PC5:0)

c. Write data to all enabled transmit registers.

TX00

d. Enable peripheral interrupt-generating function.

CRB (TE0)

e. Enable specific peripheral interrupt.

CRB0 (TIE)

f. Unmask interrupts at global level.

SR (I1:0)

Notes:

The example material to the right of the steps above shows register settings

for configuring an ESSI0 transmit interrupt using transmitter 0.

The order of the steps is optional except that the interrupt trigger

configuration must not be completed until the ISR configuration has been
completed. Since 2d can cause an immediate transmit without generating
an interrupt, perform the transmit data preload in 2c before 2d to insure
valid data is sent in the first transmission.

After the first transmit, subsequent transmit values are typically loaded

into TXnn by the ISR (one value per register per interrupt). Therefore, if N
items are to be sent from a particular TXnn, the ISR will need to load the
transmit register (N Ð 1) times.

Steps d and e can be performed using a single instruction.

If an interrupt trigger event occurs at a time when not all interrupt trigger

configuration steps have been performed, the event is ignored forever (the
event is not queued in this case).

If interrupts derived from the core or other peripherals need to be enabled

at the same time as ESSI interrupts, step f should be done last.

r
e

s
c

l
e

i
c

t
o

r
,

I

Freescale Semiconductor, Inc.

For More Information On This Product,

Go to: www.freescale.com

.
.

7-40

DSP56309UM/D MOTOROLA

Enhanced Synchronous Serial Interface (ESSI)

Operating Modes

7.5.4

Operating Modes: Normal, Network, and On-Demand

The ESSI has three basic operating modes and several data/operation formats. These
modes can be programmed using the ESSI control registers. The data/operation formats
available to the ESSI are selected by setting or clearing control bits in the CRA and CRB.
These control bits are WL[2:1], MOD, SYN, FSL[1:0], FSR, FSP, CKP, and SHFD.

7.5.4.1

Normal/Network/On-Demand Mode Selection

To select normal mode (or network mode), clear (or set) the MOD bit in the CRB. In
normal mode, the ESSI sends or receives one data word per frame (per enabled receiver
or transmitter). In network mode, two to thirty-two time slots per frame can be selected.
During each frame, zero to thirty-two data words can be received or transmitted (from
each enabled receiver or transmitter). In either case, the transfers are periodic.

Normal mode is typically used to transfer data to or from a single device. Network mode
is typically used in TDM networks of codecs or DSPs with multiple words per frame.

Network mode has a sub-mode called on-demand mode. Setting the MOD bit in the CRB
for network mode, and setting the frame rate divider to 0 (DC = $00000) selects the
on-demand mode. This sub-mode does not generate a periodic frame sync. A frame sync
pulse is generated only when data is available to transmit. The frame sync signal
indicates the first time slot in the frame. The on-demand mode requires that the transmit
frame sync be internal (output) and the receive frame sync be external (input). For
simplex operation, synchronous mode could be used; however, for full-duplex
operation, asynchronous mode must be used. Data transmission that is data driven is
enabled by writing data into each TX. Although the ESSI is double-buffered, only one
word can be written to each TX, even if the transmit shift register is empty. The receive
and transmit interrupts function normally, using TDE and RDF; however, transmit
underruns are impossible for Ôon- demandÕ transmission and are disabled. This mode is
useful for interfacing to codecs requiring a continuous clock.

7.5.4.2

Synchronous/Asynchronous Operating Modes

The transmit and receive sections of the ESSI interface can be synchronous or
asynchronous. The transmitter and receiver use common clock and synchronization
signals in synchronous mode; they use separate clock and sync signals in asynchronous
mode. The SYN bit in CRB selects synchronous or asynchronous operation. When the
SYN bit is cleared, the ESSI TX and RX clocks and frame sync sources are independent. If
the SYN bit is set, the ESSI TX and RX clocks and frame sync are driven by the same
source (either external or internal). Since the ESSI is designed to operate either
synchronously or asynchronously, separate receive and transmit interrupts are
provided.

r
e

s
c

l
e

i
c

t
o

r
,

I

Freescale Semiconductor, Inc.

For More Information On This Product,

Go to: www.freescale.com

.
.

Enhanced Synchronous Serial Interface (ESSI)

Operating Modes

MOTOROLA

DSP56309UM/D 7-41

Transmitter 1 and transmitter 2 operate only in synchronous mode. Data clock and
frame sync signals can be generated internally by the DSP or can be obtained from
external sources. If clocks are internally generated, the ESSI clock generator derives bit
clock and frame sync signals from the DSP internal system clock. The ESSI clock
generator consists of a selectable fixed prescaler with a programmable prescaler for bit
rate clock generation and a programmable frame-rate divider with a word-length
divider for frame-rate sync-signal generation.

7.5.4.3

Frame Sync Selection

The transmitter and receiver can operate independently. The transmitter can have either
a bit-long or word-long frame-sync signal format, and the receiver can have the same or
another format. The selection is made by programming FSL[1:0], FSR, and FSP bits in the
CRB.

7.5.4.3.1

Frame Sync Signal Format

FSL1 controls the frame-sync signal format.

¥ If the FSL1 bit is cleared, the RX frame sync is asserted during the entire data

transfer period. This frame sync length is compatible with Motorola codecs, serial
peripherals that conform to the Motorola SPI, serial A/D and D/A converters,
shift registers, and telecommunication pulse code modulation (PCM) serial I/O.

¥ If the FSL1 bit is set, the RX frame sync pulses active for one bit clock immediately

before the data transfer period. This frame sync length is compatible with Intel
and National components, codecs, and telecommunication PCM serial I/O.

7.5.4.3.2

Frame Sync Length for Multiple Devices

The ability to mix frame sync lengths is useful in configuring systems in which data is
received from one type of device (e.g., codec) and transmitted to a different type of
device. FSL0 controls whether RX and TX have the same frame sync length.

¥ If the FSL0 bit is cleared, both RX and TX have the same frame sync length.

¥ If the FSL0 bit is set, RX and TX have different frame sync lengths.

FSL0 is ignored when the SYN bit is set.

7.5.4.3.3

Word-Length Frame Sync and Data-Word Timing

The FSR bit controls the relative timing of the word-length frame sync relative to the
data word timing.

¥ When the FSR bit is cleared, the word length frame sync is generated (or

expected) with the first bit of the data word.

r
e

s
c

l
e

i
c

t
o

r
,

I

Freescale Semiconductor, Inc.

For More Information On This Product,

Go to: www.freescale.com

.
.

7-42

DSP56309UM/D MOTOROLA

Enhanced Synchronous Serial Interface (ESSI)

Operating Modes

¥ When the FSR bit is set, the word length frame sync is generated (or expected)

with the last bit of the previous word.

FSR is ignored when a bit length frame sync is selected.

7.5.4.3.4

Frame Sync Polarity

The FSP bit controls the polarity of the frame sync.

¥ When the FSP bit is cleared, the polarity of the frame sync is positive (i.e., the

frame sync signal is asserted high). The ESSI synchronizes on the leading edge of
the frame sync signal.

¥ When the FSP bit is set, the polarity of the frame sync is negative (i.e., the frame

sync is asserted low). The ESSI synchronizes on the trailing edge of the frame sync
signal.

The ESSI receiver looks for a receive frame sync edge (leading edge if FSP is cleared,
trailing edge if FSP is set) only when the previous frame is completed. If the frame sync
is asserted before the frame is completed (or before the last bit of the frame is received in
the case of a bit frame sync or a word length frame sync with FSR set), the current frame
sync is not recognized, and the receiver is internally disabled until the next frame sync.

Frames do not have to be adjacent, that is, a new frame sync does not have to follow
immediately the previous frame. Gaps of arbitrary periods can occur between frames.
All the enabled transmitters are tri-stated during these gaps.

7.5.4.4

Byte Format (LSB/MSB) for the Transmitter

Some devices, such as codecs, require a MSB-first data format. Other devices, such as
those that use the AES-EBU digital audio format, require the LSB first. To be compatible
with all formats, the shift registers in the ESSI are bidirectional. The MSB/LSB selection
is made by programming the SHFD bit in the CRB.

¥ If the SHFD bit is cleared, data is shifted into the receive shift register MSB first

and shifted out of the transmit shift register MSB first.

¥ If the SHFD bit is set, data is shifted into the receive shift register LSB first and

shifted out of the transmit shift register LSB first.

7.5.5

Flags

Two ESSI signals (SC[1:0]) are available for use as serial I/O flags. Their operation is
controlled by the SYN, SCD[1:0], SSC1, and TE[2:1] bits in the CRB/CRA.The control bits
OF[1:0] and status bits IF[1:0] are double-buffered to/from SC[1:0]. Double-buffering the
flags keeps the flags in sync with TX and RX.

r
e

s
c

l
e

i
c

t
o

r
,

I

Freescale Semiconductor, Inc.

For More Information On This Product,

Go to: www.freescale.com

.
.

Enhanced Synchronous Serial Interface (ESSI)

GPIO Signals and Registers

MOTOROLA

DSP56309UM/D 7-43

The SC[1:0] flags are available in synchronous mode only. Each flag can be separately
programmed.

Flag SC0 is enabled when transmitter 1 is disabled (TE1 = 0). The flagÕs direction is
selected by the SCD0 bit. When SCD0 is set, SC0 is configured as output. When SCD0 is
cleared, SC0 is configured as input.

Similarly, the SC1 flag is enabled when transmitter 2 is disabled (TE2 = 0) and the SC1
signal is not configured as transmitter drive enable (Bit SSC1 = 0). SC1Õs direction is
selected by the SCD1 bit. When SCD1 is set, SC1 is an output flag. When SCD1 is cleared,
SC1 is an input flag.

When programmed as input flags, the value of the SC[1:0] bits are latched at the same
time as the first bit of the receive data word is sampled. Once the input has been latched,
the signal on the input flag signal (SC0 and SC1) can change without affecting the input
flag. The value of SC[1:0] does not change until the first bit of the next data word is
received. When the received data word is latched by RX, the latched values of SC[1:0] are
latched by the respective SSISR IF[1:0] bits and can be read by software.

When programed as output flags, the value of the SC[1:0] bits is taken from the value of
the OF[1:0] bits. The value of the OF[1:0] bits is latched when the contents of TX are
transferred to the transmit shift register. The value on SC[1:0] is stable from the time the
first bit of the transmit data word is transmitted until the first bit of the next transmit
data word is transmitted. The OF[1:0] values can be set directly by software. This allows
the DSP56309 to control data transmission by indirectly controlling the value of the
SC[1:0] flags.

7.6

GPIO SIGNALS AND REGISTERS

The GPIO functionality of an ESSI port (C, D) is controlled by three registers: port
control register (PCRC, PCRD), port direction register (PRRC, PRRD) and port data
register (PDRC, PDRD).

7.6.1

Port Control Register (PCR)

The read/write, 24-bit PCR controls the functionality of the ESSI GPIO signals. Each of
PC[5:0] bits controls the functionality of the corresponding port signal. When a PC[i] bit
is set, the corresponding port signal is configured as a ESSI signal. When a PC[i] bit is
cleared, the corresponding port signal is configured as a GPIO signal. Either a hardware

r
e

s
c

l
e

i
c

t
o

r
,

I

Freescale Semiconductor, Inc.

For More Information On This Product,

Go to: www.freescale.com

.
.

Serial Communication Interface (SCI)

Introduction

MOTOROLA

DSP56309UM/D 8-3

8.1

INTRODUCTION

The DSP56309 serial communication interface (SCI) provides a full-duplex port for serial
communication to other DSPs, microprocessors, or peripherals such as modems. The SCI
interfaces without additional logic to peripherals that use TTL-level signals. With a small
amount of additional logic, the SCI can connect to peripheral interfaces that have
non-TTL level signals, such as the RS232C, RS422, etc.

This interface uses three dedicated signals: transmit data (TXD), receive data (RXD), and
SCI serial clock (SCLK). It supports industry-standard asynchronous bit rates and
protocols, as well as high-speed synchronous data transmission. The asynchronous
protocols supported by the SCI include a multidrop mode for master/slave operation
with wakeup on idle line and wakeup on address bit capability. This mode allows the
DSP56309 to share a single serial line efficiently with other peripherals.

The SCI consists of separate transmit and receive sections that can operate
asynchronously with respect to each other. A programmable baud-rate generator
provides the transmit and receive clocks. An enable vector and an interrupt vector have
been included so that the baud-rate generator can function as a general purpose timer
when it is not being used by the SCI, or when the interrupt timing is the same as that
used by the SCI.

8.2

SCI I/O SIGNALS

Each of the three SCI signals (RXD, TXD, and SCLK) can be configured as either a GPIO
signal or as a specific SCI signal. Each signal is independent of the others. For example, if
only the TXD signal is needed, the RXD and SCLK signals can be programmed for GPIO.
However, at least one of the three signals must be selected as an SCI signal to release the
SCI from reset.

SCI interrupts can be enabled by programming the SCI control registers before any of
the SCI signals are programmed as SCI functions. In this case, only one transmit
interrupt can be generated because the transmit data register is empty. The timer and
timer interrupt operate regardless of how the SCI pins are configuredÑeither as SCI or
GPIO.

r
e

s
c

l
e

i
c

t
o

r
,

I

Freescale Semiconductor, Inc.

For More Information On This Product,

Go to: www.freescale.com

.
.

8-8

DSP56309UM/D MOTOROLA

Serial Communication Interface (SCI)

SCI Programming Model

8.3.1

SCI Control Register (SCR)

The SCR is a 24-bit, read/write register that controls the serial interface operation.
Seventeen of the twenty-four bits are currently defined. Each bit is described in the
following paragraphs.

8.3.1.1

SCR Word Select (WDS[0:2]) Bits 0Ð2

The word select WDS[0:2] bits select the format of transmitted and received data. Format
modes are listed in Table 8-1 below and shown in Figure 8-4 on page 8-6.

Asynchronous modes are compatible with most UART-type serial devices and support
standard RS232C communication links. Multidrop asynchronous mode is compatible
with the MC68681 DUART, the M68HC11 SCI interface, and the Intel 8051 serial
interface. Synchronous data mode is essentially a high-speed shift register used for I/O
expansion and stream-mode channel interfaces. A gated transmit and receive clock
compatible with the Intel 8051 serial interface mode 0 makes it possible for you to
synchronize data.

When odd parity is selected, the transmitter counts the number of 1s in the data word. If
the total is not an odd number, the parity bit is set, thus producing an odd number. If the
receiver counts an even number of 1s, an error in transmission has occurred. When even
parity is selected, an even number must result from the calculation performed at both
ends of the line, or an error in transmission has occurred.

Table 8-1

Word Formats

WDS2

WDS1

WDS0

Mode

Word Formats

8-bit synchronous data (shift register mode)

Reserved

10-bit asynchronous (1 start, 8 data, 1 stop)

Reserved

11-bit asynchronous
(1 start, 8 data, 1 even parity, 1 stop)

11-bit asynchronous
(1 start, 8 data, 1 odd parity, 1 stop)

11-bit multidrop asynchronous
(1 start, 8 data, 1 data type, 1 stop)

Reserved

r
e

s
c

l
e

i
c

t
o

r
,

I

Freescale Semiconductor, Inc.

For More Information On This Product,

Go to: www.freescale.com

.
.

Serial Communication Interface (SCI)

SCI Programming Model

MOTOROLA

DSP56309UM/D 8-9

The word select bits are cleared by either a hardware RESET signal or a software RESET
instruction.

8.3.1.2

SCR SCI Shift Direction (SSFTD) Bit 3

The SSFTD bit determines the order in which the SCI data shift registers shift data in or
out: MSB first when set, LSB first when cleared. The parity and data type bits do not
change their position in the frame; they remain adjacent to the stop bit. SSFTD is cleared
by either a hardware RESET signal or a software RESET instruction.

8.3.1.3

SCR Send Break (SBK) Bit 4

A break is an all-zero word frameÑa start bit 0, characters of all 0s (including any
parity), and a stop bit 0 (i.e., ten or eleven 0s, depending on the mode selected). If SBK is
set and then cleared, the transmitter completes transmission of the current frame, sends
ten or eleven 0s (depending on WDS mode), and reverts to idle or sending data. If SBK
remains set, the transmitter continually sends whole frames of 0s (ten or eleven bits with
no stop bit). At the completion of the break code, the transmitter sends at least one high
(set) bit before transmitting any data to guarantee recognition of a valid start bit. Break
can be used to signal an unusual condition, message, etc. by forcing a frame error, which
is caused by a missing stop bit. Either a hardware RESET signal or a software RESET
instruction clears SBK.

8.3.1.4

SCR Wakeup Mode Select (WAKE) Bit 5

When WAKE is cleared, the wakeup on idle line mode is selected. In the wakeup on idle
line mode, the SCI receiver is reenabled by an idle string of at least ten or eleven
(depending on WDS mode) consecutive 1s. The transmitterÕs software must provide this
idle string between consecutive messages. The idle string cannot occur within a valid
message because each word frame contains a start bit that is 0.

When WAKE is set, the wakeup on address bit mode is selected. In the wakeup on
address bit mode, the SCI receiver is reenabled when the last (eighth or ninth) data bit
received in a character (frame) is 1. The ninth data bit is the address bit (R8) in the 11-bit
multidrop mode; the eighth data bit is the address bit in the 10-bit asynchronous and
11-bit asynchronous with parity modes. Thus, the received character is an address that
has to be processed by all sleeping processorsÑthat is, each processor has to compare
the received character with its own address and decide whether to receive or ignore all
following characters. Either a hardware RESET signal or a software RESET instruction
clears WAKE.

8.3.1.5

SCR Receiver Wakeup Enable (RWU) Bit 6

When RWU is set and the SCI is in an asynchronous mode, the wakeup function is
enabledÑthat is, the SCI is asleep, and can be awakened by the event defined by the
WAKE bit. In the sleep state, all interrupts and all receive flags except IDLE are disabled.

r
e

s
c

l
e

i
c

t
o

r
,

I

Freescale Semiconductor, Inc.

For More Information On This Product,

Go to: www.freescale.com

.
.

8-10

DSP56309UM/D MOTOROLA

Serial Communication Interface (SCI)

SCI Programming Model

When the receiver wakes up, RWU is cleared by the wakeup hardware. The
programmer can also clear the RWU bit to wake up the receiver.

RWU can be used by the programmer to ignore messages that are for other devices on a
multidrop serial network. Wakeup on idle line (WAKE is cleared) or wakeup on address
bit (WAKE is set) must be chosen.

1. When WAKE is cleared and RWU is set, the receiver does not respond to data on

the data line until an idle line is detected.

2. When WAKE is set and RWU is set, the receiver does not respond to data on the

data line until a data frame with the address bit set is detected.

When the receiver wakes up, the RWU bit is cleared, and the first frame of data is
received. If interrupts are enabled, the CPU is interrupted and the interrupt routine
reads the message header to determine if the message is intended for this DSP.

1. If the message is for this DSP, the message is received, and RWU is set to wait for

the next message.

2. If the message is not for this DSP, the DSP immediately sets RWU. Setting RWU

causes the DSP to ignore the remainder of the message and wait for the next
message.

Either a hardware RESET signal or a software RESET instruction clears RWU. RWU is
ignored in synchronous mode.

8.3.1.6

SCR Wired-OR Mode Select (WOMS) Bit 7

When the WOMS bit is set, the SCI TXD driver is programmed to function as an
open-drain output and can be wired together with other TXD signals in an appropriate
bus configuration, such as a master-slave multidrop configuration. An external pullup
resistor is required on the bus. When the WOMS is cleared, the TXD signal uses an active
internal pullup. Either a hardware RESET signal or a software RESET instruction clears
WOMS.

8.3.1.7

SCR Receiver Enable (RE) Bit 8

When RE is set, the receiver is enabled. When RE is cleared, the receiver is disabled, and
data transfer from the receive shift register to the receive data register (SRX) is inhibited.
If RE is cleared while a character is being received, the reception of the character is
completed before the receiver is disabled. RE does not inhibit RDRF or receive
interrupts. Either a hardware RESET signal or a software RESET instruction clears RE.

8.3.1.8

SCR Transmitter Enable (TE) Bit 9

When TE is set, the transmitter is enabled. When TE is cleared, the transmitter completes
transmission of data in the SCI Transmit Data Shift Register, then the serial output is

r
e

s
c

l
e

i
c

t
o

r
,

I

Freescale Semiconductor, Inc.

For More Information On This Product,

Go to: www.freescale.com

.
.

Serial Communication Interface (SCI)

SCI Programming Model

MOTOROLA

DSP56309UM/D 8-11

forced high (i.e., idle). Data present in the SCI transmit data register (STX) is not
transmitted. STX can be written and TDRE cleared, but the data is not transferred into
the shift register. TE does not inhibit TDRE or transmit interrupts. Either a hardware
RESET signal or a software RESET instruction clears TE.

Setting TE causes the transmitter to send a preamble of ten or eleven consecutive 1s
(depending on WDS). This procedure gives the programmer a convenient way to insure
that the line goes idle before starting a new message. To force this separation of
messages by the minimum idle line time, the following sequence is recommended:

1. Write the last byte of the first message to STX.

2. Wait for TDRE to go high, indicating the last byte has been transferred to the

transmit shift register.

3. Clear TE and set TE. This queues an idle line preamble to follow immediately the

transmission of the last character of the message (including the stop bit).

4. Write the first byte of the second message to STX.

In this sequence, if the first byte of the second message is not transferred to STX prior to
the finish of the preamble transmission, the transmit data line marks idle until STX is
finally written.

8.3.1.9

SCR Idle Line Interrupt Enable (ILIE) Bit 10

When ILIE is set, the SCI interrupt occurs when IDLE (SCI status register bit 3) is set.
When ILIE is cleared, the IDLE interrupt is disabled. Either a hardware RESET signal or
a software RESET instruction clears ILIE.

An internal flag, the shift register idle interrupt (SRIINT) flag, is the interrupt request to
the interrupt controller. SRIINT is not directly accessible to the user.

When a valid start bit has been received, an idle interrupt is generated if both IDLE and
ILIE are set. The idle interrupt acknowledge from the interrupt controller clears this
interrupt request. The idle interrupt is not asserted again until at least one character has
been received. The results are as follows:

1. The IDLE bit shows the real status of the receive line at all times.

2. An idle interrupt is generated once for each idle state, no matter how long the idle

state lasts.

8.3.1.10

SCR SCI Receive Interrupt Enable (RIE) Bit 11

The RIE bit is set to enable the SCI Receive Data interrupt. If RIE is cleared, the Receive
Data interrupt is disabled, and then the RDRF bit in the SCI Status Register must be

r
e

s
c

l
e

i
c

t
o

r
,

I

Freescale Semiconductor, Inc.

For More Information On This Product,

Go to: www.freescale.com

.
.

8-12

DSP56309UM/D MOTOROLA

Serial Communication Interface (SCI)

SCI Programming Model

polled to determine if the receive data register is full. If both RIE and RDRF are set, the
SCI requests an SCI receive data interrupt from the interrupt controller.

Receive interrupts with exception have higher priority than normal receive data
interrupts. Therefore, if an exception occurs (i.e., if PE, FE, or OR are set) and REIE is set,
the SCI requests an SCI receive data with exception interrupt from the interrupt
controller. Either a hardware RESET signal or a software RESET instruction clears RIE.

8.3.1.11

SCR SCI Transmit Interrupt Enable (TIE) Bit 12

The TIE bit is set to enable the SCI transmit data interrupt. If TIE is cleared, transmit data
interrupts are disabled, and the transmit data register empty (TDRE) bit in the SCI status
register must be polled to determine if the transmit data register is empty. If both TIE
and TDRE are set, the SCI requests an SCI transmit data interrupt from the interrupt
controller. Either a hardware RESET signal or a software RESET instruction clears TIE.

8.3.1.12

SCR Timer Interrupt Enable (TMIE) Bit 13

The TMIE bit is set to enable the SCI timer interrupt. If TMIE is set, timer interrupt
requests are sent to the interrupt controller at the rate set by the SCI clock register. The
timer interrupt is automatically cleared by the timer interrupt acknowledge from the
interrupt controller. This feature allows DSP programmers to use the SCI baud rate
generator as a simple periodic interrupt generator if the SCI is not in use, if external
clocks are used for the SCI, or if periodic interrupts are needed at the SCI baud rate. The
SCI internal clock is divided by 16 (to match the 1

SCI baud rate) for timer interrupt

generation. This timer does not require that any SCI signals be configured for SCI use to
operate. Either a hardware RESET signal or a software RESET instruction clears TMIE.

8.3.1.13

SCR Timer Interrupt Rate (STIR) Bit 14

The STIR bit controls a divide-by-32 in the SCI Timer interrupt generator. When STIR is
cleared, the divide-by-32 is inserted in the chain. When STIR is set, the divide-by-32 is
bypassed, thereby increasing timer resolution by a factor of 32. Either a hardware RESET
signal or a software RESET instruction clears this bit. To insure proper operation of the
timer, STIR must not be changed during timer operation (i.e., if TMIE = 1).

8.3.1.14

SCR SCI Clock Polarity (SCKP) Bit 15

The SCKP bit controls the clock polarity sourced or received on the clock signal (SCLK),
eliminating the need for an external inverter. When SCKP is cleared, the clock polarity is
positive. When SCKP is set, the clock polarity is negative. In synchronous mode, positive
polarity means that the clock is normally positive and transitions negative during valid
data. Negative polarity means that the clock is normally negative and transitions
positive during valid data. In asynchronous mode, positive polarity means that the
rising edge of the clock occurs in the center of the period that data is valid. Negative
polarity means that the falling edge of the clock occurs during the center of the period

r
e

s
c

l
e

i
c

t
o

r
,

I

Freescale Semiconductor, Inc.

For More Information On This Product,

Go to: www.freescale.com

.
.

Serial Communication Interface (SCI)

SCI Programming Model

MOTOROLA

DSP56309UM/D 8-13

that data is valid. Either a hardware RESET signal or a software RESET instruction clears
SCKP.

8.3.1.15

Receive with Exception Interrupt Enable (REIE) Bit 16

The REIE bit is set to enable the SCI receive data with exception interrupt. If REIE is
cleared, the receive data with exception interrupt is disabled. If both REIE and RDRF are
set, and PE, FE, and OR are not all cleared, the SCI requests an SCI receive data with
exception interrupt from the interrupt controller. Either a hardware RESET signal or a
software RESET instruction clears REIE.

8.3.2

SCI Status Register (SSR)

The SSR is a 24-bit, read-only register used by the DSP to determine the status of the SCI.
The status bits are described in the following paragraphs.

8.3.2.1

SSR Transmitter Empty (TRNE) Bit 0

The TRNE flag bit is set when both the transmit shift register and transmit data register
(STX) are empty to indicate that there is no data in the transmitter. When TRNE is set,
data written to one of the three STX locations or to the transmit data address register
(STXA) is transferred to the transmit shift register and is the first data transmitted. TRNE
is cleared when TDRE is cleared by writing data into the STX or the STXA, or when an
idle, preamble, or break is transmitted. This bit, when set, indicates that the transmitter
is empty; therefore, the data written to STX or STXA is transmitted next. That is, there is
no word in the transmit shift register presently being transmitted. This procedure is
useful when initiating the transfer of a message (i.e., a string of characters). TRNE is set
by a hardware RESET signal, software RESET instruction, SCI individual reset, or STOP
instruction.

8.3.2.2

SSR Transmit Data Register Empty (TDRE) Bit 1

The TDRE flag bit is set when the SCI transmit data register is empty. When TDRE is set,
new data can be written to one of the SCI transmit data registers (STX) or the transmit
data address register (STXA). TDRE is cleared when the SCI transmit data register is
written. TDRE is set by the hardware RESET signal, software RESET instruction, SCI
individual reset, or STOP instruction.

In synchronous mode, when using the internal SCI clock, there is a delay of up to 5.5
serial clock cycles between the time that STX is written until TDRE is set, indicating the
data has been transferred from the STX to the transmit shift register. There is a 2 to
4 serial clock cycle delay between writing STX and loading the transmit shift register; in
addition, TDRE is set in the middle of transmitting the second bit. When using an
external serial transmit clock, if the clock stops, the SCI transmitter stops. TDRE is not set

r
e

s
c

l
e

i
c

t
o

r
,

I

Freescale Semiconductor, Inc.

For More Information On This Product,

Go to: www.freescale.com

.
.

8-14

DSP56309UM/D MOTOROLA

Serial Communication Interface (SCI)

SCI Programming Model

until the middle of the second bit transmitted after the external clock starts. Gating the
external clock off after the first bit has been transmitted delays TDRE indefinitely.

In asynchronous mode, the TDRE flag is not set immediately after a word is transferred
from the STX or STXA to the transmit shift register nor when the word first begins to be
shifted out. TDRE is set two cycles of the 16

clock after the start bitÑ that is, two

clock cycles into the transmission time of the first data bit.

8.3.2.3

SSR Receive Data Register Full (RDRF) Bit 2

The RDRF bit is set when a valid character is transferred to the SCI Receive Data Register
from the SCI receive shift register (regardless of the error bits condition). RDRF is
cleared when the SCI receive data register is read or by a hardware RESET signal,
software RESET instruction, SCI individual reset, or STOP instruction.

8.3.2.4

SSR Idle Line Flag (IDLE) Bit 3

IDLE is set when 10 (or 11) consecutive 1s are received. IDLE is cleared by a start-bit
detection. The IDLE status bit represents the status of the receive line. The transition of
IDLE from 0 to 1 can cause an IDLE interrupt (ILIE). IDLE is cleared by a hardware
RESET signal, software RESET instruction, SCI individual reset, or STOP instruction.

8.3.2.5

SSR Overrun Error Flag (OR) Bit 4

The OR flag bit is set when a byte is ready to be transferred from the receive shift register
to the receive data register (SRX) that is already full (RDRF = 1). The receive shift register
data is not transferred to the SRX. The OR flag indicates that character(s) in the received
data stream may have been lost. The only valid data is located in the SRX. OR is cleared
when the SCI Status Register is read, followed by a read of SRX. The OR bit clears the FE
and PE bitsÑthat is, an overrun error has higher priority than FE or PE. OR is cleared by
a hardware RESET signal, software RESET instruction, SCI individual reset, or STOP
instruction.

8.3.2.6

SSR Parity Error (PE) Bit 5

In the 11-bit asynchronous modes, the PE bit is set when an incorrect parity bit has been
detected in the received character. It is set simultaneously with RDRF for the byte which
contains the parity errorÑthat is, when the received word is transferred to the SRX. If PE
is set, further data transfer into the SRX is not inhibited. PE is cleared when the SCI
status register is read, followed by a read of SRX. PE is also cleared by a hardware
RESET signal, software RESET instruction, SCI individual reset, or STOP instruction. In
10-bit asynchronous mode, 11-bit multidrop mode, and 8-bit synchronous mode, the PE
bit is always cleared since there is no parity bit in these modes. If the byte received
causes both parity and overrun errors, the SCI receiver recognizes only the overrun
error.

r
e

s
c

l
e

i
c

t
o

r
,

I

Freescale Semiconductor, Inc.

For More Information On This Product,

Go to: www.freescale.com

.
.

Serial Communication Interface (SCI)

SCI Programming Model

MOTOROLA

DSP56309UM/D 8-15

8.3.2.7

SSR Framing Error Flag (FE) Bit 6

The FE bit is set in asynchronous modes when no stop bit is detected in the data string
received. FE and RDRE are set simultaneously when the received word is transferred to
the SRX. However, the FE flag inhibits further transfer of data into the SRX until it is
cleared. FE is cleared when the SCI status register is read followed by reading the SRX. A
hardware RESET signal, software RESET instruction, SCI individual reset, or STOP
instruction also clears FE. In 8-bit synchronous mode, FE is always cleared. If the byte
received causes both framing and overrun errors, the SCI receiver recognizes only the
overrun error.

8.3.2.8

SSR Received Bit 8 (R8) Address Bit 7

In 11-bit asynchronous multidrop mode, the R8 bit is used to indicate whether the
received byte is an address or data. R8 is set for addresses and is cleared for data. R8 is
not affected by reading the SRX or SCI status register. A hardware RESET signal,
software RESET instruction, SCI individual reset, or STOP instruction also clears R8.

8.3.3

SCI Clock Control Register (SCCR)

The SCCR is a 24-bit, read/write register that controls the selection of the clock modes
and baud rates for the transmit and receive sections of the SCI interface. The control bits
are described in the following paragraphs. The SCCR is cleared by a hardware RESET
signal. The basic features of the clock generator (as in Figure 8-5 on page 8-16 and
Figure 8-6

on page 8-18) are these:

¥ The SCI logic always uses a 16

internal clock in asynchronous modes and

always uses a 2

internal clock in synchronous mode. The maximum internal

clock available to the SCI peripheral block is the oscillator frequency divided by 4.

¥ The 16

clock is necessary for asynchronous modes to synchronize the SCI to the

incoming data, as in Figure 8-5.

¥ For asynchronous modes, the user must provide a 16

clock to use an external

baud rate generator (i.e., SCLK input).

¥ For asynchronous modes, the user can select either 1

or 16

for the output clock

when using internal TX and RX clocks (TCM = 0 and RCM = 0).

¥ When SCKP is cleared, the transmitted data on the TXD signal changes on the

negative edge of the 1

serial clock and is stable on the positive edge. When

SCKP is set, the data changes on the positive edge and is stable on the negative
edge.

¥ The received data on the RXD signal is sampled on the positive edge (if SCKP = 0)

or on the negative edge (if SCKP = 1) of the 1

serial clock.

r
e

s
c

l
e

i
c

t
o

r
,

I

Freescale Semiconductor, Inc.

For More Information On This Product,

Go to: www.freescale.com

.
.

Serial Communication Interface (SCI)

SCI Programming Model

MOTOROLA

DSP56309UM/D 8-19

8.3.4.1

SCI Receive Registers (SRX)

Data bits received on the RXD signal are shifted into the SCI receive shift register. When
a complete word has been received, the data portion of the word is transferred to the
byte-wide SRX. This process converts the serial data to parallel data and provides
double-buffering. Double-buffering provides flexibility to the programmer and
increased throughput since the programmer can save (and process) the previous word
while the current word is being received.

The SRX can be read at three locations as SRXL, SRXM, and SRXH. When SRXL is read,
the contents of the SRX are placed in the lower byte of the data bus and the remaining
bits on the data bus are read as 0s. Similarly, when SRXM is read, the contents of SRX are
placed in the middle byte of the bus, and when SRXH is read, the contents of SRX are
placed in the high byte with the remaining bits read as 0s. Mapping SRX as described
allows three bytes to be efficiently packed into one 24-bit word by ORing three data
bytes read from the three addresses.

Figure 8-7

SCI Programming Model Data Registers

SRX

RXD

SCI Receive Data Shift Register

Note: 1. SRX is the same register decoded at three different addresses.

STX

TXD

SCI Transmit Data Shift Register

Note: 1. Bytes are masked on the fly.

2. STX is the same register decoded at four different addresses.

STXA

(a) Receive Data Register

(b) Transmit Data Register

AA0694

SCI Receive Data Register High (Read Only)

SCI Receive Data Register Middle (Read Only)

SCI Receive Data Register Low (Read Only)

SCI Transmit Data Register High (Write Only)

SCI Transmit Data Register Middle (Write Only)

SCI Transmit Data Register Low (Write Only)

SCI Transmit Data Address Register (Write Only)

r
e

s
c

l
e

i
c

t
o

r
,

I

Freescale Semiconductor, Inc.

For More Information On This Product,

Go to: www.freescale.com

.
.

8-20

DSP56309UM/D MOTOROLA

Serial Communication Interface (SCI)

SCI Programming Model

The length and format of the serial word are defined by the WDS0, WDS1, and WDS2
control bits in the SCR. The clock source is defined by the receive clock mode (RCM)
select bit in the SCR.

In synchronous mode, the start bit, the eight data bits, the address/data indicator bit
and/or the parity bit, and the stop bit are received in that order. Data bits are sent LSB
first if SSFTD is cleared, and MSB first if SSFTD is set. In synchronous mode, the
synchronization is provided by gating the clock.

In either synchronous or asynchronous mode, when a complete word has been clocked
in, the contents of the shift register can be transferred to the SRX and the flags; RDRF, FE,
PE, and OR are changed appropriately. Because the operation of the receive shift register
is transparent to the DSP, the contents of this register are not directly accessible to the
programmer.

8.3.4.2

SCI Transmit Registers

The transmit data register is a one byte-wide register mapped into four addresses as
STXL, STXM, STXH, and STXA. In asynchronous mode, when data is to be transmitted,
STXL, STXM, and STXH are used. When STXL is written, the low byte on the data bus is
transferred to the STX. When STXM is written, the middle byte is transferred to the STX.
When STXH is written, the high byte is transferred to the STX. This structure makes it
easy for the programmer to unpack the bytes in a 24-bit word for transmission. TDXA
should be written in the 11-bit asynchronous multidrop mode when the data is an
address and it is desired that the ninth bit (the address bit) be set. When STXA is written,
the data from the low byte on the data bus is stored in it. The address data bit is cleared
in the 11-bit asynchronous multidrop mode when any of STXL, STXM or STXH is
written. When either STX (STXL, STXM, or STXH) or STXA is written, TDRE is cleared.

The transfer from either STX or STXA to the transmit shift register occurs automatically,
but not immediately, when the last bit from the previous word has been shifted out; that
is, the transmit shift register is empty. Like the receiver, the transmitter is
double-buffered. However, a 2 to 4 serial clock cycle delay occurs between when the
data is transferred from either STX or STXA to the transmit shift register and when the
first bit appears on the TXD signal. (A serial clock cycle is the time required to transmit
one data bit). The transmit shift register is not directly addressable, and a dedicated flag
for this register does not exist. Because of this fact and the 2 to 4 cycle delay, two bytes
cannot be written consecutively to STX or STXA without polling, as the second byte
might overwrite the first byte. The TDRE flag should always be polled prior to writing
STX or STXA to prevent overruns unless transmit interrupts have been enabled. Either
STX or STXA is usually written as part of the interrupt service routine. An interrupt is
generated only if TDRE is set. The transmit shift register is indirectly visible via the
TRNE bit in the SSR.

r
e

s
c

l
e

i
c

t
o

r
,

I

Freescale Semiconductor, Inc.

For More Information On This Product,

Go to: www.freescale.com

.
.

Serial Communication Interface (SCI)

Operating Modes

MOTOROLA

DSP56309UM/D 8-21

In synchronous mode, data is synchronized with the transmit clock, which can have
either an internal or external source, as defined by the TCM bit in the SCCR. The length
and format of the serial word is defined by the WDS0, WDS1, and WDS2 control bits in
the SCR. In asynchronous modes, the start bit, the eight data bits (with the LSB first if
SSFTD = 0 and the MSB first if SSFTD = 1), the address/data indicator bit or parity bit,
and the stop bit are transmitted in that order.

The data to be transmitted can be written to any one of the three STX addresses. If SCKP
is set and SSHTD is set, the SCI synchronous mode is equivalent to the SSI operation in
the 8-bit data on-demand mode.

Note:

When writing data to a peripheral device, there is a two cycle pipeline delay

for further details.

8.4

OPERATING MODES

The operating modes for the DSP56309 SCI are these:

¥ 8-bit synchronous (shift register mode)

¥ 10-bit asynchronous (1 start, 8 data, 1 stop)

¥ 11-bit asynchronous (1 start, 8 data, 1 even parity, 1 stop)

¥ 11-bit asynchronous (1 start, 8 data, 1 odd parity, 1 stop)

¥ 11-bit multidrop asynchronous (1 start, 8 data, 1 data type, 1 stop)

This mode is used for master/slave operation with wakeup on idle line and
wakeup on address bit capability. It allows the DSP56309 to share a single serial
line efficiently with other peripherals.

These modes are selected using the WD[0:2] bits in the SCR.

The synchronous data mode is essentially a high-speed shift register used for I/O
expansion and stream-mode channel interfaces. Data synchronization is accomplished
by the use of a gated transmit and receive clock that is compatible with the Intel

8051

serial interface mode 0.

Asynchronous modes are compatible with most UART-type serial devices. Standard
RS232C communication links are supported by these modes.

r
e

s
c

l
e

i
c

t
o

r
,

I

Freescale Semiconductor, Inc.

For More Information On This Product,

Go to: www.freescale.com

.
.

Serial Communication Interface (SCI)

Operating Modes

MOTOROLA

DSP56309UM/D 8-25

If interrupts are to be used, the signals must be selected, and interrupts must be enabled
and unmasked before the SCI can operate. The order does not matter; any one of these
three requirements for interrupts can be used to enable the SCI.

Synchronous applications usually require exact frequencies, which require that the
crystal frequency be chosen carefully. An alternative to selecting the system clock to
accommodate the SCI requirements is to provide an external clock to the SCI.

8.4.3

SCI Initialization Example

One way to initialize the SCI is described here as an example.

1. The SCI should be in its individual reset state (PCR = $0).

2. Configure the control registers (SCR, SCCR) according to the operating mode, but

do not enable either transmitter (TE = 0) or receiver (RE = 0).

It is possible to set the interrupt enable bits that would be in use during the
operation (no interrupt occurs).

3. Enable the SCI by setting the PCR bits according to which signals will be in use

during operation.

4. If transmit interrupt is not used, write data to the transmitter.

If transmitter interrupt enable is set, an interrupt is issued and the interrupt
handler should write data into the transmitter.

SCI transmit request is serviced by DMA channel if it is programmed to service
the SCI transmitter.

5. Enable transmitters (TE = 1) and receiver (RE = 1), according to usage.

Operation starts as follows:

¥ For an internally generated clock, the SCLK signal starts operation immediately

after the SCI is enabled (Step 3 above) for asynchronous modes. In synchronous
mode, the SCLK signal is active only while transmitting (gated clock).

¥ Data is received only when the receiver is enabled (RE = 1) and after the

occurrence of the SCI receive sequence on the RXD signal, as defined by the
operating mode (i.e., idle line sequence).

¥ Data is transmitted only after the transmitter is enabled (TE = 1), and after

transmitting the initialization sequence depending on the operating mode.

r
e

s
c

l
e

i
c

t
o

r
,

I

Freescale Semiconductor, Inc.

For More Information On This Product,

Go to: www.freescale.com

.
.

8-26

DSP56309UM/D MOTOROLA

Serial Communication Interface (SCI)

Operating Modes

8.4.4

Preamble, Break, and Data Transmission Priority

Two or three transmission commands can be set simultaneously:

1. A preamble (TE is set.)

2. A break (SBK is set or is cleared.)

3. There is data for transmission (TDRE is cleared.)

After the current character transmission, if two or more of these commands are set, the
transmitter executes them in the following order:

1. Preamble

2. Break

3. Data

8.4.5

SCI Exceptions

The SCI can cause five different exceptions in the DSP. These exceptions are as follows
(ordered from the highest to the lowest priority):

1. SCI receive data with exception status is caused by receive data register full with

a receiver error (parity, framing, or overrun error). Clearing the pending interrupt
is done by reading the SCI status register, followed by a read of SRX. A long
interrupt service routine should be used to handle the error condition. This
interrupt is enabled by SCR bit 16 (REIE).

2. SCI receive data is caused by receive data register full. Reading SRX clears the

pending interrupt. This error-free interrupt can use a fast interrupt service routine
for minimum overhead. This interrupt is enabled by SCR bit 11 (RIE).

3. SCI transmit data is caused by transmit data register empty. Writing STX clears

the pending interrupt. This error-free interrupt can use a fast interrupt service
routine for minimum overhead. This interrupt is enabled by SCR bit 12 (TIE).

4. SCI idle line is caused by the receive line entering the idle state (10 or 11 bits of

1s). This interrupt is latched and then automatically reset when the interrupt is
accepted. This interrupt is enabled by SCR bit 10 (ILIE).

5. SCI timer is caused by the baud rate counter reaching zero. This interrupt is

automatically reset when the interrupt is accepted. This interrupt is enabled by
SCR bit 13 (TMIE).

r
e

s
c

l
e

i
c

t
o

r
,

I

Freescale Semiconductor, Inc.

For More Information On This Product,

Go to: www.freescale.com

.
.

Triple Timer Module

Introduction

MOTOROLA

DSP56309UM/D 9-3

9.1

INTRODUCTION

This section describes the internal triple timer module in the DSP56309. Each timer has a
single signal that can be used as a GPIO signal or as a timer signal. These three timers
can be used to generate timed pulses or as pulse width modulators. They can also be
used as an event counter, to capture an event, or to measure the width or period of a
signal.

9.2

TRIPLE TIMER MODULE ARCHITECTURE

The timer module is composed of a common 21-bit prescaler and three independent and
identical general purpose 24-bit timer/event counters, each having its own register set.
Each timer can use internal or external clocking and can interrupt the DSP56309 after a
specified number of events (clocks) or can signal an external device after counting
internal events. Each timer can also be used to trigger DMA transfers after a specified
number of events (clocks) has occurred. Each timer connects to the external world
through one bidirectional signal, designated TIO0ÐTIO2 for Timers 0Ð2, respectively.

When the TIO signal is configured as input, the timer functions as an external event
counter or measures external pulse width/signal period. When the TIO signal is used as
output, the timer functions as a timer, a watchdog timer, or a pulse width modulator.
When the TIO signal is not used by the timer, it can be used as a GPIO signal (also called
TIO0ÐTIO2).

9.2.1

Triple Timer Module Block Diagram

Figure 9-1

shows a block diagram of the triple timer module. This module includes a

24-bit timer prescaler load register (TPLR), a 24-bit timer prescaler count register
(TPCR), a 21-bit prescaler clock counter, and three timers. Each of the three timers can
use the prescaler clock as its clock source.

r
e

s
c

l
e

i
c

t
o

r
,

I

Freescale Semiconductor, Inc.

For More Information On This Product,

Go to: www.freescale.com

.
.

Triple Timer Module

Triple Timer Module Programming Model

MOTOROLA

DSP56309UM/D 9-7

9.3.1

Prescaler Counter

The prescaler counter is a 21-bit counter that is decremented on the rising edge of the
prescaler input clock. The counter is enabled when at least one of the three timers is
enabled (i.e., one or more of the timer enable (TE) bits are set) and is using the prescaler
output as its source (i.e., one or more of the PCE bits are set).

9.3.2

Timer Prescaler Load Register (TPLR)

The TPLR is a 24-bit, read/write register that controls the prescaler divide factor (i. e.,
the number that the prescaler counter loads and begins counting from) and the source
for the prescaler input clock. The control bits are shown below in Figure 9-4.

9.3.2.1

TPLR Prescaler Preload Value (PL[20:0]) Bits 20-0

These 21 bits contain the prescaler preload value. This value is loaded into the prescaler
counter when the counter value reaches 0, or the counter switches state from disabled to
enabled.

If PL[20:0] = N, then the prescaler counts N + 1 source clock cycles before generating a
prescaler clock pulse. Therefore, the prescaler divide factor = (preload value) + 1.

The PL[20:0] bits are cleared by a hardware RESET signal or a software RESET
instruction.

9.3.2.2

TPLR Prescaler Source (PS[1:0]) Bits 22-21

The two PS bits control the source of the prescaler clock. Table 9-1 summarizes PS bit
functionality. The prescalerÕs use of a TIO signal is not affected by the TCSR settings of
the timer corresponding to the TIO signal being used.

PS1

PS0

PL20

PL19

PL18

PL17

PL16

PL15

PL14

PL13

PL12

PL11

PL10

PL9

PL8

PL7

PL6

PL5

PL4

PL3

PL2

PL1

PL0

Ñ reserved, read as 0, should be written with 0 for future compatibility

Figure 9-4

Timer Prescaler Load Register (TPLR)

r
e

s
c

l
e

i
c

t
o

r
,

I

Freescale Semiconductor, Inc.

For More Information On This Product,

Go to: www.freescale.com

.
.

Triple Timer Module

Triple Timer Module Programming Model

MOTOROLA

DSP56309UM/D 9-9

9.3.3.1

TPCR Prescaler Counter Value (PC[20:0]) Bits 20-0

These 21 bits contain the current value of the prescaler counter.

9.3.3.2

TPCR Reserved Bits 23-21

These reserved bits are read as 0 and should be written with 0 for future compatibility.

9.3.4

Timer Control/Status Register (TCSR)

The TCSR is a 24-bit, read/write register controlling the timer and reflecting its status.
The register bits are shown in Figure 9-6. The control and status bits are documented in
Table 9-2

on page 9-10.

9.3.4.1

Timer Enable (TE) Bit 0

The TE bit is used to enable or disable the timer. Setting TE enables the timer and clears
the timer counter. The counter starts counting according to the mode selected by the
timer control (TC[3:0]) bit values.

Clearing the TE bit disables the timer. The TE bit is cleared by a hardware RESET signal
or a software RESET instruction.

Note:

When all three timers are disabled and the signals are not in GPIO mode, all

three TIO signals are tri-stated. To prevent undesired spikes on the TIO
signals when switching from tri-state into active state, these signals should be
tied to the high or low signal state by the use of pull-up or pull-down resistors.

9.3.4.2

Timer Overflow Interrupt Enable (TOIE) Bit 1

The TOIE bit is used to enable the timer overflow interrupts. Setting TOIE enables
overflow interrupt generation. The timer counter can hold a maximum value of
$FFFFFF. When the counter value is at the maximum value and a new event causes the
counter to be incremented to $000000, the timer generates an overflow interrupt.

TCF

TOF

PCE

DIR

TRM

INV

TC3

TC2

TC1

TC0

TCIE

TOIE

Ñ reserved, read as 0, should be written with 0 for future compatibility

Figure 9-6

Timer Control/Status Register

r
e

s
c

l
e

i
c

t
o

r
,

I

Freescale Semiconductor, Inc.

For More Information On This Product,

Go to: www.freescale.com

.
.

9-10

DSP56309UM/D MOTOROLA

Triple Timer Module

Triple Timer Module Programming Model

Clearing the TOIE bit disables overflow interrupt generation. The TOIE bit is cleared by
a hardware RESET signal or a software RESET instruction.

9.3.4.3

Timer Compare Interrupt Enable (TCIE) Bit 2

The TCIE bit is used to enable or disable the timer compare interrupts. Setting TCIE
enables the compare interrupts. In the timer, pulse width modulation (PWM), or
watchdog modes, a compare interrupt is generated after the counter value matches the
value of the TCPR. The counter starts counting up from the number loaded from the
TLR and if the TCPR value is N, an interrupt occurs after (N Ð M + 1) events, where M is
the value of TLR.

Clearing the TCIE bit disables the compare interrupts. The TCIE bit is cleared by a
hardware RESET signal or a software RESET instruction.

9.3.4.4

Timer Control (TC[3:0]) Bits 4-7

The four TC bits control the source of the timer clock, the behavior of the TIO signal, and
timer mode. Table 9-2 summarizes the TC bit functionality. There is a detailed
description of the timer operating modes in Section 9.4ÑTimer Operational Modes.

The TC bits are cleared by a hardware RESET signal or a software RESET instruction.

Note:

If the clock is external, the counter is incremented by the transitions on the

TIO signal. The external clock is internally synchronized to the internal clock,
and its frequency should be lower than the internal operating frequency
divided by 4 (CLK/4).

Note:

To insure proper operation, the TC[3:0] bits should be changed only when the

timer is disabled (i.e., when the TE bit in the TCSR has been cleared).

Table 9-2

Timer Control Bits

Bit Settings

Mode Characteristics

TC3

TC2

TC1

TC0

Mode

Number

Mode Function

TIO

Clock

Timer and GPIO

GPIO

Internal

Timer Pulse

Output

Internal

Timer Toggle

Output

Internal

Event Counter

Input

External

r
e

s
c

l
e

i
c

t
o

r
,

I

Freescale Semiconductor, Inc.

For More Information On This Product,

Go to: www.freescale.com

.
.

Triple Timer Module

Triple Timer Module Programming Model

MOTOROLA

DSP56309UM/D 9-13

The INV bit is cleared by a hardware RESET signal or a software RESET instruction.

The INV bit affects both the timer and GPIO modes. To insure correct operation, this bit
should be changed only when one or both of the following conditions is true:

¥ The timer has been disabled by clearing the TE bit in the TCSR.

¥ The timer is in GPIO mode.

The INV bit does not affect the polarity of the prescaler source when the TIO is used as
input to the prescaler.

9.3.4.6

Timer Reload Mode (TRM) Bit 9

The TRM bit controls the counter preload operation.

In timer (0Ð3) and watchdog (9Ð10) modes, the counter is preloaded with the TLR value
after the TE bit is set and the first internal or external clock signal is received. If the TRM
bit is set, the counter is reloaded each time after it reaches the value contained by the
TCR. In PWM mode (7), the counter is reloaded each time counter overflow occurs. In
measurement (4Ð5) modes, if the TRM and the TE bits are set, the counter is preloaded
with the TLR value on each appropriate edge of the input signal.

If the TRM bit is cleared, the counter operates as a free running counter and is
incremented on each incoming event. The TRM bit is cleared by a hardware RESET
signal or a software RESET instruction.

Pulse generated
by the timer has
positive

polarity

Pulse generated by
the timer has
negative

polarity

Pulse generated
by the timer has
positive

polarity

Pulse generated by
the timer has
negative

polarity

Pulse generated
by the timer has
positive

polarity.

Pulse generated by
the timer has
negative

polarity

Table 9-3

Inverter (INV) Bit Operation (Continued)

Mode

TIO Programmed as Input

TIO Programmed as Output

INV = 0

INV = 1

INV = 0

INV = 1

r
e

s
c

l
e

i
c

t
o

r
,

I

Freescale Semiconductor, Inc.

For More Information On This Product,

Go to: www.freescale.com

.
.

9-14

DSP56309UM/D MOTOROLA

Triple Timer Module

Triple Timer Module Programming Model

9.3.4.7

Direction (DIR) Bit 11

The DIR bit determines the behavior of the TIO signal when it is used as a GPIO signal.
When the DIR bit is set, the TIO signal is an output; when the DIR bit is cleared, the TIO
signal is an input. The TIO signal can be used as a GPIO signal only when all of the
TC[3:0] bits are cleared. If any of the TC[3:0] bits are set, then the GPIO function is
disabled and the DIR bit has no effect.

The DIR bit is cleared by a hardware RESET signal or a software RESET instruction.

9.3.4.8

Data Input (DI) Bit 12

The DI bit reflects the value of the TIO signal. If the INV bit is set, the value of the TIO
signal is inverted before it is written to the DI bit. If the INV bit is cleared, the value of
the TIO signal is written directly to the DI bit.

DI is cleared by a hardware RESET signal or a software RESET instruction.

9.3.4.9

Data Output (DO) Bit 13

The DO bit is the source of the TIO value when it is a data output signal. The TIO signal
is data output when GPIO mode is enabled and DIR is set. A value written to the DO bit
is written to the TIO signal. If the INV bit is set, the value of the DO bit is inverted when
written to the TIO signal. When the INV bit is cleared, the value of the DO bit is written
directly to the TIO signal. When GPIO mode is disabled, writing the DO bit has no effect.

The DO bit is cleared by a hardware RESET signal or a software RESET instruction.

9.3.4.10

Prescaler Clock Enable (PCE) Bit 15

The PCE bit is used to select the prescaler clock as the timer source clock. When the PCE
bit is cleared, the timer uses either an internal (CLK/2) signal or an external (TIO) signal
as its source clock. When the PCE bit is set, the prescaler output is used as the timer
source clock for the counter regardless of the timer operating mode. To insure proper
operation, the PCE bit should be changed only when the timer is disabled (when the TE
bit is cleared). Which source clock is used for the prescaler is determined by the PS[1:0]
bits of the TPLR. A timer can be clocked by a prescaler clock that is derived from the TIO
of another timer.

9.3.4.11

Timer Overflow Flag (TOF) Bit 20

The TOF bit is set to indicate that counter overflow has occurred. This bit is cleared by
writing a 1 to the TOF bit. Writing a 0 to the TOF bit has no effect. The bit is also cleared
when the timer overflow interrupt is serviced.

The TOF bit is cleared by a hardware RESET signal, a software RESET instruction, the
STOP instruction, or by clearing the TE bit to disable the timer.

r
e

s
c

l
e

i
c

t
o

r
,

I

Freescale Semiconductor, Inc.

For More Information On This Product,

Go to: www.freescale.com

.
.

Triple Timer Module

Triple Timer Module Programming Model

MOTOROLA

DSP56309UM/D 9-15

9.3.4.12

Timer Compare Flag (TCF) Bit 21

The TCF bit is set to indicate that the event count is complete. In the timer, PWM, and
watchdog modes, the TCF bit is set when (N Ð M + 1) events have been counted. (N is the
value in the compare register and M is the TLR value.) In measurement modes, the TCF
bit is set when the measurement is completed.

Writing a 1 into the TCF bit clears this bit. Writing a 0 into the TCF bit has no effect. The
bit is also cleared when the timer compare interrupt is serviced.

The TCF bit is cleared by a hardware RESET signal, a software RESET instruction, the
STOP instruction, or by clearing the TE bit to disable the timer.

Note:

The TOF and TCF bits are cleared by writing a 1 to the specific bit. In order to

insure that only the desired bit is cleared, do not use the BSET command. The
proper way to clear these bits is to write (using a MOVEP instruction) a 1 to
the flag to be cleared and a 0 to the other flag.

9.3.4.13

TCSR Reserved Bits 3, 10, 14, 16-19, 22, 23

These reserved bits are read as 0 and should be written with 0 for future compatibility.

9.3.5

Timer Load Register (TLR)

The TLR is a 24-bit, write-only register. In all modes, the counter is preloaded with the
TLR value after the TE bit in the TCSR is set and a first event occurs.

¥ In timer modes, if the timer reload mode (TRM) bit in the TCSR is set, the counter

is reloaded each time after it has reached the value contained by the timer
compare register (TCPR) and the new event occurs.

¥ In measurement modes, if the TRM bit in the TCSR is set and the TE bit in the

TCSR is set, the counter is reloaded with the value in the TLR on each appropriate
edge of the input signal.

¥ In PWM modes, if the TRM bit in the TCSR is set, the counter is reloaded each

time after it has overflowed and the new event occurs.

¥ In watchdog modes, if the TRM bit in the TCSR is set, the counter is reloaded each

time after it has reached the value contained by the TCPR and the new event
occurs. In this mode, the counter is also reloaded whenever the TLR is written
with a new value while the TE bit in the TCSR is set.

¥ In all modes, if the TRM bit in the TCSR is cleared (TRM = 0), the counter operates

as a free-running counter.

r
e

s
c

l
e

i
c

t
o

r
,

I

Freescale Semiconductor, Inc.

For More Information On This Product,

Go to: www.freescale.com

.
.

9-18

DSP56309UM/D MOTOROLA

Triple Timer Module

Timer Operational Modes

is reloaded with the TLR value at the next timer clock and the count is resumed. If the
TRM bit is cleared, the counter continues to be incremented on each timer clock signal.

This process is repeated until the timer is disabled (i.e., TE is cleared).

If the counter overflows, the TOF bit is set, and if TOIE is set, an overflow interrupt is
generated.

The counter contents can be read at any time by reading the TCR.

9.4.1.2

Timer Pulse (Mode 1)

In this mode, the timer generates an external pulse on its TIO signal when the timer
count reaches a pre-set value.

Set the TE bit to clear the counter and enable the timer. The value to which the timer is to
count is loaded into the TCPR. The counter is loaded with the TLR value when the first
timer clock signal is received. The TIO signal is loaded with the value of the INV bit. The
timer clock signal can be taken from either the DSP56309 clock divided by two (CLK/2)
or from the prescaler clock output. Each subsequent clock signal increments the counter.

When the counter matches the TCPR value, the TCF bit in TCSR is set and a compare
interrupt is generated if the TCIE bit is set. The polarity of the TIO signal is inverted for
one timer clock period.

If the TRM bit is set, the counter is loaded with the TLR value on the next timer clock and
the count is resumed. If the TRM bit is cleared, the counter continues to be incremented
on each timer clock.

This process is repeated until the TE bit is cleared (disabling the timer). The counter
contents can be read at any time by reading TCR.

The value of the TLR sets the delay between starting the timer and the generation of the
output pulse. To generate successive output pulses with a delay of X clocks between
signals, the TLR value should be set to X/2 and the TRM bit should be set.

This process is repeated until the timer is disabled (i.e., TE is cleared).

Bit Settings

Mode Characteristics

TC3

TC2

TC1

TC0

TIO

Clock

Function

Name

Output

Internal

Timer

Pulse

r
e

s
c

l
e

i
c

t
o

r
,

I

Freescale Semiconductor, Inc.

For More Information On This Product,

Go to: www.freescale.com

.
.

Triple Timer Module

Timer Operational Modes

MOTOROLA

DSP56309UM/D 9-19

If the counter overflows, the TOF bit is set, and if TOIE is set, an overflow interrupt is
generated.

The counter contents can be read at any time by reading the TCR.

9.4.1.3

Timer Toggle (Mode 2)

In this mode, the timer periodically toggles the polarity of the TIO signal.

Set the TE bit in the TCR to clear the counter and enable the timer. The value to which
the timer is to count is loaded into the TPCR. The counter is loaded with the TLR value
when the first timer clock signal is received. The TIO signal is loaded with the value of
the INV bit. The timer clock signal can be taken from either the DSP56309 clock divided
by two (CLK/2) or from the prescaler clock output. Each subsequent clock signal
increments the counter.

When the counter value matches the value in the TCPR, the polarity of the TIO output
signal is inverted. The TCF bit in the TCSR is set and a compare interrupt is generated if
the TCIE bit is set.

If the TRM bit is set, the counter is loaded with the value of the TLR when the next timer
clock is received, and the count is resumed. If the TRM bit is cleared, the counter
continues to be incremented on each timer clock.

This process is repeated until the TE bit is cleared, disabling the timer. The counter
contents can be read at any time by reading the TCR.

The TLR value in the TCPR sets the delay between starting the timer and toggling the
TIO signal. To generate output signals with a delay of X clock cycles between toggles,
the TLR value should be set to X/2, and the TRM bit should be set.

This process is repeated until the timer is disabled (i.e., TE is cleared). If the counter
overflows, the TOF bit is set, and if TOIE is set, an overflow interrupt is generated.

The counter contents can be read at any time by reading the TCR.

Bit Settings

Mode Characteristics

TC3

TC2

TC1

TC0

TIO

Clock

Function

Name

Output

Internal

Timer

Toggle

r
e

s
c

l
e

i
c

t
o

r
,

I

Freescale Semiconductor, Inc.

For More Information On This Product,

Go to: www.freescale.com

.
.

9-20

DSP56309UM/D MOTOROLA

Triple Timer Module

Timer Operational Modes

9.4.1.4

Timer Event Counter (Mode 3)

In this mode, the timer counts external events and issues an interrupt when a preset
number of events is counted.

Set the TE bit to clear the counter and enable the timer. The value to which the timer is to
count is loaded into the TPCR. The counter is loaded with the TLR value when the first
timer clock signal is received. The timer clock signal can be taken from either the TIO
input signal or the prescaler clock output. Each subsequent clock signal increments the
counter. If an external clock is used, it must be internally synchronized to the internal
clock, and its frequency must be less than the DSP56309 internal operating frequency
divided by 4.

The value of the INV bit in the TCSR determines whether low-to-high (0 to 1) transitions
or high-to-low (1 to 0) transitions increment the counter. If the INV bit is set, high-to-low
transitions increment the counter. If the INV bit is cleared, low-to-high transitions
increment the counter.

When the counter matches the value contained in the TCPR, the TCF bit in the TCSR is
set, and a compare interrupt is generated if the TCIE bit is set. If the TRM bit is set, the
counter is loaded with the value of the TLR when the next timer clock is received, and
the count is resumed. If the TRM bit is cleared, the counter continues to be incremented
on each timer clock.

This process is repeated until the timer is disabled (i.e., TE is cleared). If the counter
overflows, the TOF bit is set, and if TOIE is set, an overflow interrupt is generated.

The counter contents can be read at any time by reading the TCR.

9.4.2

Signal Measurement Modes

The following Signal Measurement modes are provided:

¥ Measurement input width

Bit Settings

Mode Characteristics

TC3

TC2

TC1

TC0

TIO

Clock

Function

Name

Input

External

Timer

Event Counter

r
e

s
c

l
e

i
c

t
o

r
,

I

Freescale Semiconductor, Inc.

For More Information On This Product,

Go to: www.freescale.com

.
.

Triple Timer Module

Timer Operational Modes

MOTOROLA

DSP56309UM/D 9-21

¥ Measurement input period

¥ Measurement capture

9.4.2.1

Measurement Accuracy

The external signal is synchronized with the internal clock used to increment the
counter. This synchronization process can cause the number of clocks measured for the
selected signal value to vary from the actual signal value by plus or minus one counter
clock cycle.

9.4.2.2

Measurement Input Width (Mode 4)

In this mode, the timer counts the number of clocks that occur between opposite edges of
an input signal.

Set the TE bit to clear the counter and enable the timer. Load the timerÕs count value into
the TLR. After the first appropriate transition (as determined by the INV bit) occurs on
the TIO input signal, the counter is loaded with the TLR value on the first timer clock
signal received either from the DSP56309 clock divided by two (CLK/2) or from the
prescaler clock input. Each subsequent clock signal increments the counter.

If the INV bit is set, the timer starts on the first high-to-low (1 to 0) signal transition on
the TIO signal. If the INV bit is cleared, the timer starts on the first low-to-high
(0 to 1) transition on the TIO signal.

When the first transition opposite in polarity to the INV bit setting occurs on the TIO
signal, the counter stops. The TCF bit in the TCSR is set and a compare interrupt is
generated if the TCIE bit is set. The value of the counter (which measures the width of
the TIO pulse) is loaded into the TCR. The TCR can be read to determine the external
signal pulse width.

If the TRM bit is set, the counter is loaded with the TLR value on the first timer clock
received following the next valid transition occurring on the TIO input signal and the
count is resumed. If the TRM bit is cleared, the counter continues to be incremented on
each timer clock.

Bit Settings

Mode Characteristics

TC3

TC2

TC1

TC0

Mode

Name

Function

TIO

Clock

Input Width

Measurement

Input

Internal

r
e

s
c

l
e

i
c

t
o

r
,

I

Freescale Semiconductor, Inc.

For More Information On This Product,

Go to: www.freescale.com

.
.

9-22

DSP56309UM/D MOTOROLA

Triple Timer Module

Timer Operational Modes

This process is repeated until the timer is disabled (i.e., TE is cleared). If the counter
overflows, the TOF bit is set, and if TOIE is set, an overflow interrupt is generated. The
counter contents can be read at any time by reading the TCR.

9.4.2.3

Measurement Input Period (Mode 5)

In this mode, the timer counts the period between the reception of signal edges of the
same polarity across the TIO signal.

Set the TE bit to clear the counter and enable the timer. The value to which the timer is to
count is loaded into the TLR. The value of the INV bit determines whether the period is
measured between consecutive low-to-high (0 to 1) transitions of TIO or between
consecutive high-to-low (1 to 0) transitions of TIO. If INV is set, high-to-low signal
transitions are selected. If INV is cleared, low-to-high signal transitions are selected.

After the first appropriate transition occurs on the TIO input signal, the counter is
loaded with the TLR value on the first timer clock signal received from either the
DSP56309 clock divided by two (CLK/2) or the prescaler clock output. Each subsequent
clock signal increments the counter.

On the next signal transition of the same polarity that occurs on TIO, the TCF bit in the
TCSR is set and a compare interrupt is generated if the TCIE bit is set. The contents of the
counter are loaded into the TCR. The TCR then contains the value of the time that
elapsed between the two signal transitions on the TIO signal.

After the second signal transition, if the TRM bit is set, the TE bit is set to clear the
counter and enable the timer. The counter is loaded with the TLR value on the first timer
clock signal. Each subsequent clock signal increments the counter.

After the second signal transition, if the TRM bit is set, the TE bit is set to clear if the TRM
bit is cleared, the counter continues to be incremented on each timer clock. This process
is repeated until the timer is disabled (i.e., TE is cleared). If the counter overflows, the
TOF bit is set, and if TOIE is set, an overflow interrupt is generated. The counter contents
can be read at any time by reading the TCR.

Bit Settings

Mode Characteristics

TC3

TC2

TC1

TC0

Mode

Name

Function

TIO

Clock

Input Period

Measurement

Input

Internal

r
e

s
c

l
e

i
c

t
o

r
,

I

Freescale Semiconductor, Inc.

For More Information On This Product,

Go to: www.freescale.com

.
.

9-24

DSP56309UM/D MOTOROLA

Triple Timer Module

Timer Operational Modes

9.4.3

Pulse Width Modulation (PWM, Mode 7)

In this mode, the timer generates periodic pulses of a preset width.

Set the TE bit to clear the counter and enable the timer. The value to which the timer is to
count is loaded into the TPCR. When first timer clock is received from either the
DSP56309 internal clock divided by two (CLK/2) or the prescaler clock output, the
counter is loaded with the TLR value. Each subsequent timer clock increments the
counter.

When the counter equals the value in the TCPR, the TIO output signal is toggled and the
TCF bit in the TCSR is set. The contents of the counter are placed into the TCR. If the
TCIE bit is set, a compare interrupt is generated. The counter continues to be
incremented on each timer clock.

If counter overflow has occurred, the TIO output signal is toggled, the TOF bit in TCSR
is set, and an overflow interrupt is generated if the TOIE bit is set. If the TRM bit is set,
the counter is loaded with the TLR value on the next timer clock and the count is
resumed. If the TRM bit is cleared, the counter continues to be incremented on each
timer clock.

This process is repeated until the timer is disabled by clearing the TE bit.

TIO signal polarity is determined by the value of the INV bit. When the counter is
started by setting the TE bit, the TIO signal assumes the value of the INV bit. On each
subsequent toggling of the TIO signal, the polarity of the TIO signal is reversed. For
example, if the INV bit is set, the TIO signal generates the following signal: 1010. If the
INV bit is cleared, the TIO signal generates the following signal: 0101.

The counter contents can be read at any time by reading the TCR.

The value of the TLR determines the output period ($FFFFFF

- TLR + 1). The timer

counter increments the initial TLR value and toggles the TIO signal when the counter
value exceeds $FFFFFF.

Bit Settings

Mode Characteristics

TC3

TC2

TC1

TC0

Mode

Name

Function

TIO

Clock

Pulse Width

Modulation

PWM

Output

Internal

r
e

s
c

l
e

i
c

t
o

r
,

I

Freescale Semiconductor, Inc.

For More Information On This Product,

Go to: www.freescale.com

.
.

9-26

DSP56309UM/D MOTOROLA

Triple Timer Module

Timer Operational Modes

If the counter overflows, the TOF bit is set, and if TOIE is set, an overflow interrupt is
generated. At the same time, a pulse is output on the TIO signal with a pulse width equal
to the timer clock period. The pulse polarity is determined by the value of the INV bit. If
the INV bit is set, the pulse polarity is high (logical 1). If the INV bit is cleared, the pulse
polarity is low (logical 0).

The counter contents can be read at any time by reading the TCR. The counter is
reloaded whenever the TLR is written with a new value while the TE bit is set.

Note:

In this mode, internal logic preserves the TIO value and direction for an

additional 2.5 internal clock cycles after a DSP56309 hardware RESET signal is
asserted. This insures that a valid RESET signal is generated when the TIO
signal is used to reset the DSP56309.

9.4.4.2

Watchdog Toggle (Mode 10)

In this mode, the timer toggles an external signal after preset period.

Set the TE bit to clear the counter and enable the timer. The value to which the timer is to
count is loaded into the TPCR. The counter is loaded with the TLR value on the first
timer clock received from either the DSP56309 internal clock divided by two (CLK/2) or
the prescaler clock output. Each subsequent timer clock increments the counter. The TIO
signal is set to the value of the INV bit.

When the counter equals the value in the TCPR, the TCF bit in the TCSR is set, and a
compare interrupt is generated if the TCIE bit is also set. If the TRM bit is set, the counter
is loaded with the TLR value on the next timer clock and the count is resumed. If the
TRM bit is cleared, the counter continues to be incremented on each subsequent timer
clock.

When counter overflow has occurred, the polarity of the TIO output signal is inverted,
the TOF bit in the TCSR is set, and an overflow interrupt is generated if the TOIE bit is
also set. The TIO polarity is determined by the INV bit.

The counter is reloaded whenever the TLR is written with a new value while the TE bit is
set. This process is repeated until the timer is disabled by clearing the TE bit. The counter
contents can be read at any time by reading the TCR register.

Bit Settings

Mode Characteristics

TC3

TC2

TC1

TC0

Mode

NAME

Function

TIO

Clock

Toggle

Watchdog

Output

Internal

r
e

s
c

l
e

i
c

t
o

r
,

I

Freescale Semiconductor, Inc.

For More Information On This Product,

Go to: www.freescale.com

.
.

10-8

DSP56309UM/D MOTOROLA

On-Chip Emulation Module

OnCE Controller

10.4.2

OnCE Decoder (ODEC)

The ODEC supervises the entire OnCE module activity. It receives as input the 8-bit
command from the OCR, a signal from JTAG Controller (indicating that 8 or 24 bits have
been received and update of the selected data register must be performed), and a signal
indicating that the core was halted. The ODEC generates all the strobes required for
reading and writing the selected OnCE registers.

10.4.3

OnCE Status and Control Register (OSCR)

The OSCR is a 24-bit register used to enable trace mode and to indicate the cause of
entering debug mode. The control bits are read/write while the status bits are read-only.
The OSCR bits are cleared by a hardware RESET signal. The OSCR is shown in
Figure 10-5

10.4.3.1

Trace Mode Enable (TME) Bit 0

The TME control bit, when set, enables trace mode.

10.4.3.2

Interrupt Mode Enable (IME) Bit 1

The IME control bit, when set, causes the chip to execute a vectored interrupt to the
address VBA:$06 instead of entering debug mode.

10.4.3.3

Software Debug Occurrence (SWO) Bit 2

The SWO bit is a read-only status bit that is set when debug mode is entered because of
the execution of the DEBUG or DEBUGcc instruction with condition true. This bit is
cleared when leaving debug mode.

10.4.3.4

Memory Breakpoint Occurrence (MBO) Bit 3

The MBO bit is a read-only status bit that is set when debug mode is entered because a
memory breakpoint has been encountered. This bit is cleared when leaving debug mode.

Figure 10-5

OnCE Status and Control Register (OSCR)

OnCE Status and

Control Register

Read/Write

OS1 OS0

TO MBO SWO IME TME

Indicates reserved bits, written as 0 for future compatibility

AA0705

r
e

s
c

l
e

i
c

t
o

r
,

I

Freescale Semiconductor, Inc.

For More Information On This Product,

Go to: www.freescale.com

.
.

On-Chip Emulation Module

OnCE Memory Breakpoint Logic

MOTOROLA

DSP56309UM/D 10-9

10.4.3.5

Trace Occurrence (TO) Bit 4

The TO bit is a read-only status bit that is set when debug mode is entered when the
trace counter is zero while trace mode is enabled. This bit is cleared when leaving debug
mode.

10.4.3.6

Reserved OCSR Bit 5

Bit 5 is reserved for future use. It is read as 0 and should be written with 0 for future
compatibility.

10.4.3.7

Core Status (OS0, OS1) Bits 6-7

The OS0, OS1 bits are read-only status bits that provide core status information. By
examining the status bits, the user can determine whether the chip has entered debug
mode. Examining SWO, MBO, and TO identifies the cause of entering debug mode. The
user can also examine these bits and determine the cause why the chip has not entered
debug mode after debug event (DE) assertion or as a result of the execution of the JTAG
debug request instruction (core waiting for the bus, STOP or WAIT instruction, etc.).
These bits are also reflected in the JTAG instruction shift register, which allows the
polling of the core status information at the JTAG level. This is useful when the
DSP56300 core executes the STOP instruction (and therefore there are no clocks) to allow
the reading of OSCR. See Table 10-5 for the definition of the OS0ÐOS1 bits.

10.4.3.8

Reserved Bits 8-23

Bits 8Ð23 are reserved for future use. They are read as 0 and should be written with 0 for
future compatibility.

10.5

OnCE MEMORY BREAKPOINT LOGIC

Memory breakpoints can be set on program memory or data memory locations. In
addition, the breakpoint does not have to be in a specific memory address, but within an
approximate address range where the program may be executing. This significantly
increases the programmerÕs ability to monitor what the program is doing in real time.

Table 10-5

Core Status Bits Description

OS1

OS0

Description

DSP56300 core is executing instructions

DSP56300 core is in wait or stop

DSP56300 core is waiting for bus

DSP56300 core is in debug mode

r
e

s
c

l
e

i
c

t
o

r
,

I

Freescale Semiconductor, Inc.

For More Information On This Product,

Go to: www.freescale.com

.
.

10-14

DSP56309UM/D MOTOROLA

On-Chip Emulation Module

OnCE Memory Breakpoint Logic

10.5.6.5

Breakpoint 1 Condition Code Select (CC10ÐCC11)
Bits 8Ð9

The CC10ÐCC11 bits define the condition of the comparison between the current
memory address (OMAL0) and the OnCE Memory Limit Register 1 (OMLR1). See
Table 10-10

for the definition of the CC10ÐCC11 bits.

10.5.6.6

Breakpoint 0 and 1 Event Select (BT0ÐBT1)
Bits 10Ð11

The BT0ÐBT1 bits define the sequence between breakpoint 0 and 1. If the condition
defined by BT0ÐBT1 is met, then the OnCE Breakpoint Counter (OMBC) is decremented.
See Table 10-11 for the definition of the BT0ÐBT1 bits.

10.5.6.7

OnCE Memory Breakpoint Counter (OMBC)

The OMBC is a 16-bit counter that is loaded with a value equal to the number of times
minus one that a memory access event should occur before a memory breakpoint is
declared. The memory access event is specified by the OBCR and by the memory limit
registers. On each occurrence of the memory access event, the breakpoint counter is
decremented. When the counter reaches 0 and a new occurrence takes place, the chip
enters debug mode. The OMBC can be read or written through the JTAG port. Every
time that the limit register is changed or a different breakpoint event is selected in the
OBCR, the breakpoint counter must be written afterwards. This insures that the OnCE

Table 10-10

Breakpoint 1 Condition Select Table

CC11

CC10

Description

Breakpoint on not equal

Breakpoint on equal

Breakpoint on less than

Breakpoint on greater than

Table 10-11

Breakpoint 0 and 1 Event Select Table

BT1

BT0

Description

Breakpoint 0 and Breakpoint 1

Breakpoint 0 or Breakpoint 1

Breakpoint 1 after Breakpoint 0

Breakpoint 0 after Breakpoint 1

r
e

s
c

l
e

i
c

t
o

r
,

I

Freescale Semiconductor, Inc.

For More Information On This Product,

Go to: www.freescale.com

.
.

10-16

DSP56309UM/D MOTOROLA

On-Chip Emulation Module

Methods of Entering Debug Mode

OSCR, and the DSP56300 core exits debug mode by executing the appropriate command
issued by the external command controller.

Upon exiting debug mode, the counter is decremented after each execution of an
instruction. Interrupts are serviceable then. Moreover, all executed instructions,
including fast interrupt services and the execution of each repeated instruction, cause
the OTC to be decremented. Upon decrementing to 0, the DSP56300 core reenters debug
mode, the trace occurrence bit (TO) in the OSCR register is set, the core status bits
OS[1:0] are set to 11, and the DE signal is asserted to indicate that the DSP56300 core has
entered debug mode and is requesting service.

The OnCE Trace Counter (OTC) is a 16-bit counter that can be read or written through
the JTAG port. If N instructions are to be executed before entering debug mode, the OTC
should be loaded with N Ð 1. The OTC is cleared by a hardware RESET signal.

10.7

METHODS OF ENTERING DEBUG MODE

Entering debug mode is acknowledged by the chip by setting the core status bits OS1
and OS0 and asserting the DE line. This informs the external command controller that
the chip has entered debug mode and is waiting for commands. The DSP56300 core can
disable the OnCE module if the ROM Security option is implemented. If the ROM
security is implemented, the OnCE module remains inactive until a write operation to
the OGDBR is executed by the DSP56300 core.

10.7.1

External Debug Request During RESET Assertion

Holding the DE line asserted during the assertion of RESET causes the chip to enter
debug mode. After receiving the acknowledge, the external command controller must
negate the DE line before sending the first command.

Note:

In this case, the chip does not execute any instruction before entering debug

mode.

10.7.2

External Debug Request During Normal Activity

Holding the DE line asserted during normal chip activity causes the chip to finish the
execution of the current instruction and then enter Debug mode. After receiving the
acknowledge, the external command controller must negate the DE line before sending

r
e

s
c

l
e

i
c

t
o

r
,

I

Freescale Semiconductor, Inc.

For More Information On This Product,

Go to: www.freescale.com

.
.

On-Chip Emulation Module

Methods of Entering Debug Mode

MOTOROLA

DSP56309UM/D 10-17

the first command. This process is the same for any newly fetched instruction, including
instructions fetched by the interrupt processing or instructions that will be aborted by
the interrupt processing.

Note:

In this case the chip completes the execution of the current instruction and

stops after the newly fetched instruction enters the instruction latch.

10.7.3

Executing the JTAG DEBUG_REQUEST Instruction

Executing the JTAG instruction DEBUG_REQUEST asserts an internal debug request
signal. Consequently, the chip finishes the execution of the current instruction and stops
after the newly fetched instruction enters the instruction latch. After entering debug
mode, the core status bits OS1 and OS0 are set and the DE line is asserted, thus
acknowledging the external command controller that debug mode has been entered.

10.7.4

External Debug Request During Stop

Executing the JTAG instruction DEBUG_REQUEST (or asserting DE) while the chip is in
the stop state (i. e., has executed a STOP instruction) causes the chip to exit the stop state
and enter debug mode. After receiving the acknowledge, the external command
controller must negate DE before sending the first command.

Note:

In this case, the chip completes the execution of the STOP instruction and halts

after the next instruction enters the instruction latch.

10.7.5

External Debug Request During Wait

Executing the JTAG instruction DEBUG_REQUEST (or asserting DE) while the chip is in
the wait state (i. e., has executed a WAIT instruction) causes the chip to exit the wait state
and enter debug mode. After receiving the acknowledge, the external command
controller must negate DE before sending the first command.

Note:

In this case, the chip completes the execution of the WAIT instruction and

halts after the next instruction enters the instruction latch.

r
e

s
c

l
e

i
c

t
o

r
,

I

Freescale Semiconductor, Inc.

For More Information On This Product,

Go to: www.freescale.com

.
.

10-18

DSP56309UM/D MOTOROLA

On-Chip Emulation Module

Pipeline Information and OGDB Register

10.7.6

Software Request During Normal Activity

Upon executing the DSP56300 core instruction DEBUG (or DEBUGcc when the specified
condition is true), the chip enters debug mode after the instruction following the DEBUG
instruction has entered the instruction latch.

10.7.7

Enabling Trace Mode

When Trace mode is enabled and the OTC is greater than zero, the OTC is decremented
after each instruction execution. Execution of an instruction when the value in the OTC
is 0 causes the chip to enter debug mode after completing the execution of the
instruction. Only instructions actually executed cause the OTC to decrement. An aborted
instruction does not decrement the OTC and does not cause the chip to enter debug
mode.

10.7.8

Enabling Memory Breakpoints

When the memory breakpoint mechanism is enabled with a breakpoint counter value of
0, the chip enters debug mode after completing the execution of the instruction that
caused the memory breakpoint to occur. In case of breakpoints on executed program
memory fetches, the breakpoint is acknowledged immediately after the execution of the
fetched instruction. In case of breakpoints on accesses to X, Y or program memory spaces
by MOVE instructions, the breakpoint is acknowledged after the completion of the
instruction following the instruction that accessed the specified address.

10.8

PIPELINE INFORMATION AND OGDB REGISTER

To restore the pipeline and to resume normal chip activity upon returning from debug
mode, a number of on-chip registers store the chip pipeline status. Figure 10-9 shows the
block diagram of the pipeline information registers, with the exception of the PAB
registers, which appear in Figure 10-10 on page 10-22.

r
e

s
c

l
e

i
c

t
o

r
,

I

Freescale Semiconductor, Inc.

For More Information On This Product,

Go to: www.freescale.com

.
.

10-20

DSP56309UM/D MOTOROLA

On-Chip Emulation Module

Debugging Resources

10.8.3

OnCE GDB Register (OGDBR)

The OGDBR is a 16-bit latch that can only be read through the JTAG port. The OGDBR is
not actually required for restoring the pipeline status but is required as a means of
passing information between the chip and the external command controller. The
OGDBR is mapped on the X internal I/O space at address $FFFC. Whenever the external
command controller needs the contents of a register or memory location, it forces the
chip to execute an instruction that brings that information to the OGDBR. Then the
contents of the OGDBR are delivered serially to the external command controller by the
command READ GDB REGISTER.

10.9

DEBUGGING RESOURCES

To ease debugging activity and keep track of program flow, the DSP56300 core provides
a number of on-chip dedicated resources. There are three read-only PAB registers that
give pipeline information when debug mode is entered, and a trace buffer that stores the
address of the last instruction that was executed, as well as the addresses of the last 12
change-of-flow instructions.

10.9.1

OnCE PAB Register for Fetch (OPABFR)

The OPABFR is a 16-bit register that stores the address of the last instruction whose fetch
was started before debug mode was entered. The OPABFR can only be read through the
JTAG port. This register is not affected by the operations performed during debug mode.

10.9.2

PAB Register for Decode (OPABDR)

The OPABDR is a 16-bit register that stores the address of the instruction currently on
the PDB. This is the instruction whose fetch was completed before the chip has entered
debug mode. The OPABDR can only be read through the JTAG port. This register is not
affected by the operations performed during debug mode.

10.9.3

OnCE PAB Register for Execute (OPABEX)

The OPABEX is a 16-bit register that stores the address of the instruction currently in the
instruction latch. This is the instruction that would have been decoded and executed if

r
e

s
c

l
e

i
c

t
o

r
,

I

Freescale Semiconductor, Inc.

For More Information On This Product,

Go to: www.freescale.com

.
.

On-Chip Emulation Module

Debugging Resources

MOTOROLA

DSP56309UM/D 10-21

the chip would not have entered debug mode. The OPABEX register can only be read
through the JTAG port. This register is not affected by the operations performed during
debug mode.

10.9.4

Trace Buffer

The trace buffer stores the addresses of the last 12 change-of-flow instructions that were
executed, as well as the address of the last executed instruction. The trace buffer is
implemented as a circular buffer containing 12 17-bit registers and one 4-bit counter. All
the registers have the same address, but any read access to the trace buffer address
causes the counter to increment, thus pointing to the next trace buffer register. The
registers are serially available to the external command controller through their common
trace buffer address. Figure 10-10 on page 10-22 shows the block diagram of the trace
buffer. The trace buffer is not affected by the operations performed during debug mode
except for the trace buffer pointer increment when reading the trace buffer. When
entering debug mode, the trace buffer counter is pointing to the trace buffer register
containing the address of the last executed instructions. The first trace buffer read
obtains the oldest address and the following trace buffer reads get the other addresses
from the oldest to the newest, in order of execution.

Notes:

To insure trace buffer coherence, a complete set of 12 reads of the Trace

buffer must be performed. This is necessary due to the fact that each read
increments the trace buffer pointer, thus pointing to the next location.
After 12 reads, the pointer indicates the same location as before starting the
read procedure.

On any change of flow instruction, the trace buffer stores both the address

of the change of flow instruction, as well as the address of the target of the
change of flow instruction. In the case of conditional change of flows, the
address of the change of flow instruction is always stored (regardless of the
fact that the change of flow is true or false), but if the conditional change of
flow is false (i.e., not taken) the address of the target is not stored. In order
to facilitate the program trace reconstruction, every trace buffer location
has an additional Ôinvalid bitÕ (bit 24). If a conditional change of flow
instruction has a Ôcondition falseÕ, the invalid bit is set, thus marking this
instruction as not taken. Therefore, it is imperative to read 17 bits of data
when reading the 12 trace buffer registers. Since data is read LSB first, the
invalid bit is the first bit to be read.

r
e

s
c

l
e

i
c

t
o

r
,

I

Freescale Semiconductor, Inc.

For More Information On This Product,

Go to: www.freescale.com

.
.

On-Chip Emulation Module

Target Site Debug System Requirements

MOTOROLA

DSP56309UM/D 10-23

on the DE line indicating that the chip has entered debug mode. Optionally the external
command controller can poll the OS1 and OS0 bits in the JTAG instruction shift register.
The external command controller communicates with the chip by sending 8-bit
commands that can be accompanied by 24 bits of data. Both commands and data are sent
or received LSB first. After sending a command, the external command controller should
wait for the DSP56300 core chip to acknowledge execution of the command. The external
command controller can send a new command only after the chip has acknowledged
execution of the previous command.

The OnCE commands are classified as follows:

¥ Read commands (when the chip delivers the required data)

¥ Write commands (when the chip receives data and writes the data in one of the

OnCE registers)

¥ Commands that do not have data transfers associated with them

The commands are 8 bits long. The command formats are shown in Figure 10-4
on page 10-5.

10.11 TARGET SITE DEBUG SYSTEM REQUIREMENTS

A typical debug environment consists of a target system where the DSP56300 core-based
device resides in the user defined hardware. The JTAG port interfaces to the external
command controller over a 8-wire link consisting of the five JTAG port wires, one OnCE
module wire, a ground, and a reset wire. The reset wire is optional and is only used to
reset the DSP56300 core-based device and its associated circuitry.

The external command controller acts as the medium between the DSP56300 core target
system and a host computer. The external command controller circuit acts as a JTAG
port driver and host computer command interpreter. The controller issues commands
based on the host computer inputs from a user interface program that communicates
with the user.

10.12 OnCE MODULE EXAMPLES

Following are some examples of debugging procedures. All these examples assume that
the DSP is the only device in the JTAG chain. If there is more than one device in the chain
(additional DSPs or other devices), the other devices can be forced to execute the JTAG
BYPASS instruction such as their effect in the serial stream will be one bit per additional

r
e

s
c

l
e

i
c

t
o

r
,

I

Freescale Semiconductor, Inc.

For More Information On This Product,

Go to: www.freescale.com

.
.

On-Chip Emulation Module

OnCE Module Examples

MOTOROLA

DSP56309UM/D 10-25

10.12.3

Saving Pipeline Information

The debugging activity is accomplished by means of DSP56300 core instructions
supplied from the external command controller. Therefore, the current state of the
DSP56300 core pipeline must be saved prior to starting the debug activity and the state
must be restored prior to returning to normal mode. Here is the description of the save
procedure (it assumes that ENABLE_ONCE has been executed and Debug mode has
been entered and verified, as described in Section 10.12.1ÑChecking Whether the Chip
Has Entered Debug Mode

1. Select shift-DR. Shift in the ÒRead PDBÓ. Pass through update-DR.

2. Select shift-DR. Shift out the 24 bit OPDB register. Pass through update-DR.

3. Select shift-DR. Shift in the ÒRead PILÓ. Pass through update-DR.

4. Select shift-DR. Shift out the 24 bit OPILR register. Pass through update-DR.

Note that there is no need to verify acknowledge between steps 1 and 2, as well as 3 and
4, because completion is guaranteed by design.

10.12.4

Reading the Trace Buffer

An optional step during debugging activity is reading the information associated with
the trace buffer in order to enable an external program to reconstruct the full trace of the
executed program. In the following description of the read trace buffer procedure, it is
assumed that all actions described in Saving Pipeline Information have been executed.

1. Select shift-DR. Shift in the ÒRead PABFRÓ. Pass through update-DR.

2. Select shift-DR. Shift out the 16 bit OPABFR register. Pass through update-DR.

3. Select shift-DR. Shift in the ÒRead PABDRÓ. Pass through update-DR.

4. Select shift-DR. Shift out the 16 bit OPABDR register. Pass through update-DR.

5. Select shift-DR. Shift in the ÒRead PABEXÓ. Pass through update-DR.

6. Select shift-DR. Shift out the 16 bit OPABEX register. Pass through update-DR.

7. Select shift-DR. Shift in the ÒRead FIFOÓ. Pass through update-DR.

8. Select shift-DR. Shift out the 17 bit FIFO register. Pass through update-DR.

9. Repeat steps 7 and 8 for the entire FIFO (12 times).

r
e

s
c

l
e

i
c

t
o

r
,

I

Freescale Semiconductor, Inc.

For More Information On This Product,

Go to: www.freescale.com

.
.

10-26

DSP56309UM/D MOTOROLA

On-Chip Emulation Module

OnCE Module Examples

Note:

The user must read the entire FIFO, since each read increments the FIFO

pointer, thus pointing to the next FIFO location. At the end of this procedure,
the FIFO pointer points back to the beginning of the FIFO.

The information that has been read by the external command controller now contains
the address of the newly fetched instruction, the address of the instruction currently on
the PDB, the address of the instruction currently on the instruction latch, as well as the
addresses of the last 12 instructions that have been executed and are change of flow. A
user program can now reconstruct the flow of a full trace based on this information and
on the original source code of the currently running program.

10.12.5

Displaying a Specified Register

To display a specified register, the DSP56300 must be in debug mode and all actions
described in Section 10.12.3ÑSaving Pipeline Information have been executed. The
sequence of actions is as follows:

1. Select shift-DR. Shift in the ÒWrite PDB with GO no-EXÓ. Pass through

update-DR.

2. Select shift-DR. Shift in the 24-bit opcode: ÒMOVE reg, X:OGDBÓ. Pass through

update-DR to actually write OPDBR and thus begin executing the MOVE
instruction.

3. Wait for DSP to reenter debug mode (wait for DE or poll core status).

4. Select shift-DR and shift in ÒREAD GDB REGISTERÓ. Pass through update-DR.

This step selects OGDBR as the data register for the read.

5. Select shift-DR. Shift out the OGDBR contents. Pass through update-DR. Wait for

next command.

10.12.6

Displaying X Memory Area Starting at Address $xxxx

The DSP56309 must be in debug mode and all actions described in
Section 10.12.3ÑSaving Pipeline Information

must have been executed. Since R0 is

used as pointer for the memory, R0 is saved first. The sequence of actions is as follows:

1. Select shift-DR. Shift in the ÒWrite PDB with GO no-EXÓ. Pass through

update-DR.

r
e

s
c

l
e

i
c

t
o

r
,

I

Freescale Semiconductor, Inc.

For More Information On This Product,

Go to: www.freescale.com

.
.

On-Chip Emulation Module

OnCE Module Examples

MOTOROLA

DSP56309UM/D 10-27

2. Select shift-DR. Shift in the 24-bit opcode: ÒMOVE R0, X:OGDBÓ. Pass through

update-DR to actually write OPDBR and thus begin executing the MOVE
instruction.

3. Wait for DSP to reenter debug mode (wait for DE or poll core status).

4. Select shift-DR and shift in ÒREAD GDB REGISTERÓ. Pass through update-DR.

(This selects OGDBR as the data register for read.)

5. Select shift-DR. Shift out the OGDBR contents. Pass through update-DR. R0 is

now saved.

6. Select shift-DR. Shift in the ÒWrite PDB with no-GO no-EXÓ. Pass through

update-DR.

7. Select shift-DR. Shift in the 24 bit opcode: ÒMOVE #$xxxx,R0Ó. Pass through

update-DR to actually write OPDBR.

8. Select shift-DR. Shift in the ÒWrite PDB with GO no-EXÓ. Pass through

update-DR.

9. Select shift-DR. Shift in the second word of the 24 bit opcode: ÒMOVE #$xxxx,R0Ó

(the $xxxx field). Pass through update-DR to actually write OPDBR and execute
the instruction. R0 is loaded with the base address of the memory block to be
read.

10. Wait for DSP to reenter debug mode. (Wait for DE or poll core status.)

11. Select shift-DR. Shift in the ÒWrite PDB with GO no-EXÓ. Pass through

update-DR.

12. Select shift-DR. Shift in the 24-bit opcode: ÒMOVE X:(R0)+, X:OGDBÓ. Pass

through update-DR to actually write OPDBR and thus begin executing the MOVE
instruction.

13. Wait for DSP to reenter debug mode. (Wait for DE or poll core status.)

14. Select shift-DR and shift in ÒREAD GDB REGISTERÓ. Pass through update-DR.

(This selects OGDBR as the data register for read.)

15. Select shift-DR. Shift out the OGDBR contents. Pass through update-DR. The

memory contents of address $xxxx have been read.

16. Select shift-DR. Shift in the ÒNO SELECT with GO no-EXÓ. Pass through

update-DR. This reexecutes the same ÒMOVE X:(R0)+, X:OGDBÓ instruction.

17. Repeat from step 14 to complete the reading of the entire block. When finished,

restore the original value of R0.

r
e

s
c

l
e

i
c

t
o

r
,

I

Freescale Semiconductor, Inc.

For More Information On This Product,

Go to: www.freescale.com

.
.

10-28

DSP56309UM/D MOTOROLA

On-Chip Emulation Module

OnCE Module Examples

10.12.7

Returning from Debug to Normal Mode (Same Program)

In this case, you have finished examining the current state of the machine, changed some
of the registers, and wish to return and continue execution of the same program from the
point where it stopped. Therefore, you must restore the pipeline of the machine and
enable normal instruction execution. The sequence of actions to do so is listed below:

1. Select shift-DR. Shift in the ÒWrite PDB with no-GO no-EXÓ. Pass through

update-DR.

2. Select shift-DR. Shift in the 24 bits of saved PIL (instruction latch value). Pass

through update-DR to actually write the instruction latch.

3. Select shift-DR. Shift in the ÒWrite PDB with GO and EXÓ. Pass through

update-DR.

4. Select shift-DR. Shift in the 24 bits of saved PDB. Pass through update-DR to

actually write the PDB. At the same time the internally saved value of the PAB is
driven back from the PABFR register onto the PAB, the ODEC releases the chip
from debug mode, and the normal flow of execution is continued.

10.12.8

Returning from Debug to Normal Mode (New Program)

In this case, you have finished examining the current state of the machine, changed some
of the registers, and wish to start the execution of a new program (the GOTO command).
Therefore, you must force a Òchange-of-flowÓ to the starting address of the new program
($xxxx). The sequence of actions to do so is listed below:

1. Select shift-DR. Shift in the ÒWrite PDB with no-GO no-EXÓ. Pass through

update-DR.

1. Select shift-DR. Shift in the 24-bit Ò$0AF080Ó which is the opcode of the JUMP

instruction. Pass through update-DR to actually write the instruction latch.

2. Select shift-DR. Shift in the ÒWrite PDB-GO-TO with GO and EXÓ. Pass through

update-DR.

3. Select shift-DR. Shift in the 16 bit of Ò$xxxxÓ. Pass through update-DR to actually

write the PDB. At this time the ODEC releases the chip from debug mode and the
execution is started from the address $xxxx.

Note:

If the device enters debug mode during a DO LOOP, REP instruction, or other

special cases such as interrupt processing, STOP, WAIT, or conditional
branching, you must first reset the DSP56300 and then proceed with the
execution of the new program.

r
e

s
c

l
e

i
c

t
o

r
,

I

Freescale Semiconductor, Inc.

For More Information On This Product,

Go to: www.freescale.com

.
.

JTAG Port

Introduction

MOTOROLA

DSP56309UM/D 11-3

11.1

INTRODUCTION

The DSP56300 core provides a dedicated user-accessible test access port (TAP) that is
fully compatible with the IEEE 1149.1 Standard Test Access Port and Boundary Scan
Architecture

. Problems associated with testing high density circuit boards have led to

development of this proposed standard under the sponsorship of the Test Technology
Committee of IEEE and the JTAG. The DSP56300 core implementation supports
circuit-board test strategies based on this standard.

The test logic includes a TAP that consists of five dedicated signals, a 16-state controller,
and three test data registers. A Boundary Scan Register (BSR) links all device signals into
a single shift register. The test logic, implemented utilizing static logic design, is
independent of the device system logic. The DSP56300 core implementation provides the
following capabilities:

¥ Performs boundary scan operations to test circuit-board electrical continuity

(EXTEST)

¥ Bypasses the DSP56300 core for a given circuit-board test by effectively reducing

the BSR to a single cell (BYPASS)

¥ Samples the DSP56300 core-based device system signals during operation and

transparently shifts out the result in the BSR

¥ Preloads values to output signals prior to invoking the EXTEST instruction

(SAMPLE/PRELOAD)

¥ Disables the output drive to signals during circuit-board testing (HI-Z)

¥ Provides a means of accessing the OnCE controller and circuits to control a target

system (ENABLE_ONCE)

¥ Provides a means of entering debug Mode (DEBUG_REQUEST)

¥ Queries identification information (manufacturer, part number and version) from

a DSP56300 core-based device (IDCODE)

¥ Forces test data onto the outputs of a DSP56300 core-based device while replacing

its boundary scan register in the serial data path with a single bit register
(CLAMP)

This section, which includes aspects of the JTAG implementation that are specific to the
DSP56300 core, is intended to be used with the supporting IEEE 1149.1 document. The
discussion includes those items required by the standard to be defined and, in certain
cases, provides additional information specific to the DSP56300 core implementation.
For internal details and applications of the standard, refer to the IEEE 1149.1 document.
Figure 11-1

shows a block diagram of the TAP port.

r
e

s
c

l
e

i
c

t
o

r
,

I

Freescale Semiconductor, Inc.

For More Information On This Product,

Go to: www.freescale.com

.
.

JTAG Port

TAP Controller

MOTOROLA

DSP56309UM/D 11-9

¥ Controlling the direction of bidirectional signals

¥ Controlling the output drive of tri-stateable output signals

For more details on the function and use of the EXTEST instruction, please refer to the
IEEE 1149.1 document.

11.3.2.2

SAMPLE/PRELOAD (B[3:0] = 0001)

The SAMPLE/PRELOAD instruction provides two separate functions. First, it provides
a means to obtain a snapshot of system data and control signals. The snapshot occurs on
the rising edge of TCK in the Capture-DR controller state. The data can be observed by
shifting it transparently through the BSR.

Note:

Because there is no internal synchronization between the JTAG clock (TCK)

and the system clock (CLK), the user must provide some form of external
synchronization to achieve meaningful results.

The second function of the SAMPLE/PRELOAD instruction is to initialize the BSR
output cells prior to selection of EXTEST. This initialization insures that known data
appears on the outputs when entering the EXTEST instruction.

11.3.2.3

IDCODE (B[3:0] = 0010)

The IDCODE instruction selects the ID register. This instruction is provided as a public
instruction to allow the manufacturer, part number, and version of a component to be
determined through the TAP. Figure 11-4 shows the ID register configuration.

One application of the ID register is to distinguish the manufacturer(s) of components on
a board when multiple sourcing is used. As more components emerge which conform to
the IEEE 1149.1 standard, it is desirable to allow for a system diagnostic controller unit to
blindly interrogate a board design in order to determine the type of each component in

Figure 11-4

JTAG ID Register

0 0 1 0

0 0 0 0 0 0 0 1 1 1 0

Design

Core

Number

Chip

Derivative

Number

0 0 0 0 0

0 0 0 1 1 0

Center

Number

0 0 0 1 0

Manufacturer

Identity

Version

Information

Customer Part Number

AA0718

r
e

s
c

l
e

i
c

t
o

r
,

I

Freescale Semiconductor, Inc.

For More Information On This Product,

Go to: www.freescale.com

.
.

11-10

DSP56309UM/D MOTOROLA

JTAG Port

TAP Controller

each location. This information is also available for factory process monitoring and for
failure mode analysis of assembled boards.

MotorolaÕs manufacturer identity is 00000001110. The customer part number consists of
two parts: Motorola design center number (bits 27:22) and a sequence number (bits
21:12). The sequence number is divided into two parts: core number (bits 21:17) and chip
derivative number (bits 16:12). Motorola Semiconductor Israel (MSIL) design center
number is 000110 and DSP56300 core number is 00001.

Once the IDCODE instruction is decoded, it selects the ID register, which is a 32-bit data
register. Since the Bypass register loads a logical 0 at the start of a scan cycle, whereas the
ID register loads a logical 1 into its LSB, examination of the first bit of data shifted out of
a component during a test data scan sequence immediately following exit from
Test-Logic-Reset controller state shows whether such a register is included in the design.
When the IDCODE instruction is selected, the operation of the test logic has no effect on
the operation of the on-chip system logic as required by the IEEE 1149.1 standard.

11.3.2.4

CLAMP (B[3:0] = 0011)

The CLAMP instruction is not included in the IEEE 1149.1 standard. It is provided as a
public instruction that selects the 1-bit bypass register as the serial path between TDI and
TDO while allowing signals driven from the component signals to be determined from
the BSR. During testing of ICs on PCB, it may be necessary to place static guarding
values on signals that control operation of logic not involved in the test. The EXTEST
instruction could be used for this purpose, but because it selects the BSR, the required
guarding signals would be loaded as part of the complete serial data stream shifted in,
both at the start of the test and each time a new test pattern is entered. Since the CLAMP
instruction allows guarding values to be applied using the BSR of the appropriate ICs
while selecting their bypass registers, it allows much faster testing than does the EXTEST
instruction. Data in the boundary scan cell remains unchanged until a new instruction is
shifted in or the JTAG state machine is set to its reset state. The CLAMP instruction also
asserts internal reset for the DSP56300 core system logic to force a predictable internal
state while performing external boundary scan operations.

11.3.2.5

HI-Z (B[3:0] = 0100)

The HI-Z instruction is not included in the IEEE 1149.1 standard. It is provided as a
manufacturerÕs optional public instruction to prevent having to backdrive the output
signals during circuit-board testing. When HI-Z is invoked, all output drivers, including
the two-state drivers, are turned off (i.e., high impedance). The instruction selects the
bypass register. The HI-Z instruction also asserts internal reset for the DSP56300 core
system logic to force a predictable internal state while performing external boundary
scan operations.

r
e

s
c

l
e

i
c

t
o

r
,

I

Freescale Semiconductor, Inc.

For More Information On This Product,

Go to: www.freescale.com

.
.

JTAG Port

TAP Controller

MOTOROLA

DSP56309UM/D 11-11

11.3.2.6

ENABLE_ONCE(B[3:0] = 0110)

The ENABLE_ONCE instruction is not included in the IEEE 1149.1 standard. It is
provided as a public instruction to allow you to perform system debug functions. When
the ENABLE_ONCE instruction is decoded the TDI and TDO signals are connected
directly to the OnCE registers. The particular OnCE register connected between TDI and
TDO at a given time is selected by the OnCE controller depending on the OnCE
instruction being currently executed. All communication with the OnCE controller is
done through the Select-DR-Scan path of the JTAG TAP controller. See
Section 10ÑOn-Chip Emulation Module

for more information.

11.3.2.7

DEBUG_REQUEST(B[3:0] = 0111)

The DEBUG_REQUEST instruction is not included in the IEEE 1149.1 standard. It is
provided as a public instruction to allow you to generate a debug request signal to the
DSP56300 core. When the DEBUG_REQUEST instruction is decoded, the TDI and TDO
signals are connected to the instruction registers. Due to the fact that in the Capture-IR
state of the TAP the OnCE status bits are captured in the Instruction shift register, the
external JTAG controller must continue to shift-in the DEBUG_REQUEST instruction
while polling the status bits that are shifted-out until debug mode is entered
(acknowledged by the combination 11 on OS1ÐOS0). After the acknowledgment of
debug mode is received, the external JTAG controller must issue the ENABLE_ONCE
instruction to allow the user to perform system debug functions.

11.3.2.8

BYPASS (B[3:0] = 1111)

The BYPASS instruction selects the single-bit bypass register, as shown in Figure 11-5.
This choice creates a shift-register path from TDI to the bypass register, and finally to
TDO, circumventing the BSR. This instruction is used to enhance test efficiency when a
component other than the DSP56300 core-based device becomes the device under test.
When the bypass register is selected by the current instruction, the shift-register stage is
set to a logical 0 on the rising edge of TCK in the Capture-DR controller state. Therefore,
the first bit shifted out after selecting the bypass register is always a logical 0.

Figure 11-5

Bypass Register

Mux

To TDO

From TDI

Shift DR

CLOCKDR

AA0115

r
e

s
c

l
e

i
c

t
o

r
,

I

Freescale Semiconductor, Inc.

For More Information On This Product,

Go to: www.freescale.com

.
.

11-12

DSP56309UM/D MOTOROLA

JTAG Port

DSP56300 Restrictions

11.4

DSP56300 RESTRICTIONS

The control afforded by the output enable signals using the BSR and the EXTEST
instruction requires a compatible circuit-board test environment to avoid
device-destructive configurations. You must avoid situations in which the DSP56300
core output drivers are enabled into actively driven networks. In addition, the EXTEST
instruction can be performed only after power-up or a regular hardware RESET signal
while EXTAL was provided. Then during the execution of EXTEST, EXTAL can remain
inactive.

There are two constraints related to the JTAG interface. First, the TCK input does not
include an internal pullup resistor and should not be left unconnected. The second
constraint is to insure that the JTAG test logic is kept transparent to the system logic by
forcing the TAP into the Test-Logic-Reset controller state, using either of two methods.
During power-up, TRST must be externally asserted to force the TAP controller into this
state. After power-up is concluded, TMS must be sampled as a logical 1 for five
consecutive TCK rising edges. If TMS either remains unconnected or is connected to
V

, then the TAP controller cannot leave the Test-Logic-Reset state, regardless of the

state of TCK.

The DSP56300 core features a low-power stop mode, which is invoked using the STOP
instruction. The interaction of the JTAG interface with low-power Stop mode is as
follows:

1. The TAP controller must be in the Test-Logic-Reset state to either enter or remain

in the low-power stop mode. Leaving the TAP controller Test-Logic-Reset state
negates the ability to achieve low-power, but does not otherwise affect device
functionality.

2. The TCK input is not blocked in low-power stop mode. To consume minimal

power, the TCK input should be externally connected to V

or GND.

3. The TMS and TDI signals include on-chip pullup resistors. In low-power stop

mode, these two signals should remain either unconnected or connected to V

achieve minimal power consumption.

Since during stop mode all DSP56309 core clocks are disabled, the JTAG interface
provides the means of polling the device status (sampled in the Capture-IR state).

r
e

s
c

l
e

i
c

t
o

r
,

I

Freescale Semiconductor, Inc.

For More Information On This Product,

Go to: www.freescale.com

.
.

A-2

DSP56309UM/D MOTOROLA

Bootstrap Programs

; Revised March, 18 1997.

;

; Bootstrap through the Host Interface, External EPROM or SCI.

;

; This is the Bootstrap program contained in the DSP56309 192-word Boot

; ROM. This program can load any program RAM segment from an external

; EPROM, from the Host Interface or from the SCI serial interface.

;

;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;

; If MD:MC:MB:MA=x000, then the Boot ROM is bypassed and the DSP56309

; will start fetching instructions beginning with address $C00000 (MD=0)

; or $008000 (MD=1) assuming that an external memory of SRAM type is

; used. The accesses will be performed using 31 wait states with no

; address attributes selected (default area).

;

;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;

; Operation modes MD:MC:MB:MA=0001-0111 are reserved.

;

;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;

; If MD:MC:MB:MA=1001, then it loads a program RAM segment from consecutive

; byte-wide P memory locations, starting at P:$D00000 (bits 7-0).

; The memory is selected by the Address Attribute AA1 and is accessed with

; 31 wait states.

; The EPROM bootstrap code expects to read 3 bytes

; specifying the number of program words, 3 bytes specifying the address

; to start loading the program words and then 3 bytes for each program

; word to be loaded. The number of words, the starting address and the

; program words are read least significant byte first followed by the

; mid and then by the most significant byte.

; The program words will be condensed into 24-bit words and stored in

; contiguous PRAM memory locations starting at the specified starting address.

; After reading the program words, program execution starts from the same

; address where loading started.

;

;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;

; If MD:MC:MB:MA=1010, then it loads the program RAM from the SCI interface.

; The number of program words to be loaded and the starting address must

; be specified. The SCI bootstrap code expects to receive 3 bytes

; specifying the number of program words, 3 bytes specifying the address

; to start loading the program words and then 3 bytes for each program

; word to be loaded. The number of words, the starting address and the

; program words are received least significant byte first followed by the

; mid and then by the most significant byte. After receiving the

; program words, program execution starts in the same address where

; loading started. The SCI is programmed to work in asynchronous mode

; with 8 data bits, 1 stop bit and no parity. The clock source is

; external and the clock frequency must be 16x the baud rate.

; After each byte is received, it is echoed back through the SCI

r
e

s
c

l
e

i
c

t
o

r
,

I

Freescale Semiconductor, Inc.

For More Information On This Product,

Go to: www.freescale.com

.
.

Bootstrap Programs

MOTOROLA

DSP56309UM/D A-3

; transmitter.

;

;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;

; Operation mode MD:MC:MB:MA=1011 is reserved.

;

;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;

; If MD:MC:MB:MA=1100, then it loads the program RAM from the Host

; Interface programmed to operate in the ISA mode.

; The HOST ISA bootstrap code expects to read a 24-bit word

; specifying the number of program words, a 24-bit word specifying the address

; to start loading the program words and then a 24-bit word for each program

; word to be loaded. The program words will be stored in

; contiguous PRAM memory locations starting at the specified starting address.

; After reading the program words, program execution starts from the same

; address where loading started.

; The Host Interface bootstrap load program may be stopped by

; setting the Host Flag 0 (HF0). This will start execution of the loaded

; program from the specified starting address.

;

;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;

; If MD:MC:MB:MA=1101, then it loads the program RAM from the Host

; Interface programmed to operate in the HC11 non multiplexed mode.

;

; The HOST HC11 bootstrap code expects to read a 24-bit word

; specifying the number of program words, a 24-bit word specifying the address

; to start loading the program words and then a 24-bit word for each program

; word to be loaded. The program words will be stored in

; contiguous PRAM memory locations starting at the specified starting address.

; After reading the program words, program execution starts from the same

; address where loading started.

; The Host Interface bootstrap load program may be stopped by

; setting the Host Flag 0 (HF0). This will start execution of the loaded

; program from the specified starting address.

;

;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;

; If MD:MC:MB:MA=1110, then it loads the program RAM from the Host

; Interface programmed to operate in the 8051 multiplexed bus mode,

; in double-strob pin configuration.

; The HOST 8051 bootstrap code expects accesses that are byte wide.

; The HOST 8051 bootstrap code expects to read 3 bytes forming a 24-bit word

; specifying the number of program words, 3 bytes forming a 24-bit word

; specifying the address to start loading the program words and then 3 bytes

; forming 24-bit words for each program word to be loaded.

; The program words will be stored in contiguous PRAM memory locations

; starting at the specified starting address.

; After reading the program words, program execution starts from the same

; address where loading started.

; The Host Interface bootstrap load program may be stopped by setting the

; Host Flag 0 (HF0). This will start execution of the loaded program from

r
e

s
c

l
e

i
c

t
o

r
,

I

Freescale Semiconductor, Inc.

For More Information On This Product,

Go to: www.freescale.com

.
.

A-4

DSP56309UM/D MOTOROLA

Bootstrap Programs

; the specified starting address.

;

; The base address of the HI08 in multiplexed mode is 0x80 and is not

; modified by the bootstrap code. All the address lines are enabled

; and should be connected accordingly.

;

;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;

; If MD:MC:MB:MA=1111, then it loads the program RAM from the Host

; Interface programmed to operate in the MC68302 (IMP) bus mode,

; in single-strob pin configuration.

; The HOST MC68302 bootstrap code expects accesses that are byte wide.

; The HOST MC68302 bootstrap code expects to read 3 bytes forming a 24-bit word

; specifying the number of program words, 3 bytes forming a 24-bit word

; specifying the address to start loading the program words and then 3 bytes

; forming 24-bit words for each program word to be loaded.

; The program words will be stored in contiguous PRAM memory locations

; starting at the specified starting address.

; After reading the program words, program execution starts from the same

; address where loading started.

; The Host Interface bootstrap load program may be stopped by setting the

; Host Flag 0 (HF0). This will start execution of the loaded program from

; the specified starting address.

;

;;;;;;;;;;;;;;;;;;;; MEMORY EQUATES ;;;;;;;;;;;;;;;;;;;;;;;;

page 132,55,0,0,0

opt mex

EQUALDATA equ 1 ;; 1 if xram and yram are of equal

;; size and addresses, 0 otherwise.

if (EQUALDATA)

start_dram equ 0 ;; 24k X and Y RAM

length_dram equ $1c00 ;; same addresses

else

start_xram equ 0 ;; 7k XRAM

length_xram equ $1c00

start_yram equ 0 ;; 7k YRAM

length_yram equ $1c00

endif

start_pram equ 0 ;; 20k PRAM

length_pram equ $5000

;;

;;;;;;;;;;;;;;;;;;;; GENERAL EQUATES ;;;;;;;;;;;;;;;;;;;;;;;;

;;

BOOT equ $D00000 ; this is the location in P memory

; on the external memory bus

; where the external byte-wide

; EPROM would be located

r
e

s
c

l
e

i
c

t
o

r
,

I

Freescale Semiconductor, Inc.

For More Information On This Product,

Go to: www.freescale.com

.
.

Bootstrap Programs

MOTOROLA

DSP56309UM/D A-5

AARV equ $D00409 ; AAR1 selects the EPROM as CE~

; mapped as P from $D00000 to

; $DFFFFF, active low

;;

;;;;;;;;;;;;;;;;;;;; DSP I/O REGISTERS ;;;;;;;;;;;;;;;;;;;;;;;;

;;

M_PDRC EQU $FFFFBD ;; Port C GPIO Data Register

M_PRRC EQU $FFFFBE ;; Port C Direction Register

M_SSR EQU $FFFF93 ; SCI Status Register

M_STXL EQU $FFFF95 ; SCI Transmit Data Register (low)

M_SRXL EQU $FFFF98 ; SCI Receive Data Register (low)

M_SCCR EQU $FFFF9B ; SCI Clock Control Register

M_SCR EQU $FFFF9C ; SCI Control Register

M_PCRE EQU $FFFF9F ; Port E Control register

M_AAR1 EQU $FFFFF8 ; Address Attribute Register 1

M_HPCR EQU $FFFFC4 ; Host Polarity Control Register

M_HSR EQU $FFFFC3 ; Host Status Rgister

M_HRX EQU $FFFFC6 ; Host Recceive Register

HRDF EQU $0 ; Host Receive Data Full

HF0 EQU $3 ; Host Flag 0

HEN EQU $6 ; Host Enable

SCK0 EQU $3 ;; SCK0 is bit #3 as GPIO

ORG PL:$ff0000,PL:$ff0000 ; bootstrap code starts at $ff0000

START

clr a ; clear a

jclr #3,omr,OMR0XXX ; If MD:MC:MB:MA=0xxx, go to OMR0XXX

jclr #2,omr,EPRSCILD ; If MD:MC:MB:MA=10xx, load from EPROM/SCI

jclr #1,omr,OMR1IS0 ; IF MD:MC:MB:MA=110x, look for ISA/HC11

jclr #0,omr,I8051HOSTLD ; If MD:MC:MB:MA=1110, load from 8051 Host

; If MD:MC:MB:MA=1111, load from MC68302 Host

;========================================================================

; This is the routine which loads a program through the HI08 host port

; The program is downloaded from the host MCU with the following rules:

; 1) 3 bytes - Define the program length.

; 2) 3 bytes - Define the address to which to start loading the program to.

; 3) 3n bytes (while n is any integer number)

; The program words will be stroed in contiguous PRAM memory locations starting

; at the specified starting address.

; After reading the program words, program execution starts from the same

; address where loading started.

; The host MCU may terminate the loading process by setting the HF1=0 and HF0=1.

; When the downloading is terminated, the program will start execution of the

; loaded program from the specified starting address.

; The HI08 boot ROM program enables the following busses to download programs

; through the HI08 port:

;

r
e

s
c

l
e

i
c

t
o

r
,

I

Freescale Semiconductor, Inc.

For More Information On This Product,

Go to: www.freescale.com

.
.

A-6

DSP56309UM/D MOTOROLA

Bootstrap Programs

; 1 - ISA - Dual strobes non-multiplexed bus with negative strobe

; pulses duale positive request

; 2 - HC11 - Single strobe non-multiplexed bus with positive strobe

; pulse single negative request.

; 4 - i8051 - Dual strobes multiplexed bus with negative strobe pulses

; dual negative request.

; 5 - MC68302 - Single strobe non-multiplexed bus with negative strobe

; pulse single negative request.

;========================================================================

MC68302HOSTLD

movep #%0000000000111000,x:M_HPCR

; Configure the following conditions:

; HAP = 0 Negative host acknowledge

; HRP = 0 Negative host request

; HCSP = 0 Negatice chip select input

; HD/HS = 0 Single strobe bus (R/W~ and DS)

; HMUX = 0 Non multiplexed bus

; HASP = 0 (address strobe polarity has no

; meaning in non-multiplexed bus)

; HDSP = 0 Negative data stobes polarity

; HROD = 0 Host request is active when enabled

; spare = 0 This bit should be set to 0 for

; future compatability

; HEN = 0 When the HPCR register is modified

; HEN should be cleared

; HAEN = 1 Host acknowledge is enabled

; HREN = 1 Host requests are enabled

; HCSEN = 1 Host chip select input enabled

; HA9EN = 0 (address 9 enable bit has no

; meaning in non-multiplexed bus)

; HA8EN = 0 (address 8 enable bit has no

; meaning in non-multiplexed bus)

; HGEN = 0 Host GPIO pins are disabled

bra <HI08CONT

OMR1IS0

jset #0,omr,HC11HOSTLD ; If MD:MC:MB:MA=1101, go load from HC11 Host

; If MD:MC:MB:MA=1100, go load from ISA HOST

ISAHOSTLD

movep #%0101000000011000,x:M_HPCR

; Configure the following conditions:

; HAP = 0 Negative host acknowledge

; HRP = 1 Positive host request

; HCSP = 0 Negatice chip select input

; HD/HS = 1 Dual strobes bus (RD and WR)

; HMUX = 0 Non multiplexed bus

; HASP = 0 (address strobe polarity has no

; meaning in non-multiplexed bus)

; HDSP = 0 Negative data stobes polarity

; HROD = 0 Host request is active when enabled

; spare = 0 This bit should be set to 0 for

; future compatability

r
e

s
c

l
e

i
c

t
o

r
,

I

Freescale Semiconductor, Inc.

For More Information On This Product,

Go to: www.freescale.com

.
.

Bootstrap Programs

MOTOROLA

DSP56309UM/D A-7

; HEN = 0 When the HPCR register is modified

; HEN should be cleared

; HAEN = 0 Host acknowledge is disabled

; HREN = 1 Host requests are enabled

; HCSEN = 1 Host chip select input enabled

; HA9EN = 0 (address 9 enable bit has no

; meaning in non-multiplexed bus)

; HA8EN = 0 (address 8 enable bit has no

; meaning non-multiplexed bus)

; HGEN = 0 Host GPIO pins are disabled

bra <HI08CONT

HC11HOSTLD

movep #%0000001000011000,x:M_HPCR

; Configure the following conditions:

; HAP = 0 Negative host acknowledge

; HRP = 0 Negative host request

; HCSP = 0 Negatice chip select input

; HD/HS = 0 Single strobe bus (R/W~ and DS)

; HMUX = 0 Non multiplexed bus

; HASP = 0 (address strobe polarity has no

; meaning in non-multiplexed bus)

; HDSP = 1 Negative data stobes polarity

; HROD = 0 Host request is active when enabled

; spare = 0 This bit should be set to 0 for

; future compatability

; HEN = 0 When the HPCR register is modified

; HEN should be cleared

; HAEN = 0 Host acknowledge is disabled

; HREN = 1 Host requests are enabled

; HCSEN = 1 Host chip select input enabled

; HA9EN = 0 (address 9 enable bit has no

; meaning in non-multiplexed bus)

; HA8EN = 0 (address 8 enable bit has no

; meaning in non-multiplexed bus)

; HGEN = 0 Host GPIO pins are disabled

bra <HI08CONT

I8051HOSTLD

movep #%0001110000011110,x:M_HPCR

; Configure the following conditions:

; HAP = 0 Negative host acknowledge

; HRP = 0 Negatice host request

; HCSP = 0 Negatice chip select input

; HD/HS = 1 Dual strobes bus (RD and WR)

; HMUX = 1 Multiplexed bus

; HASP = 1 Positive address strobe polarity

; HDSP = 0 Negative data stobes polarity

; HROD = 0 Host request is active when enabled

; spare = 0 This bit should be set to 0 for

; future compatability

; HEN = 0 When the HPCR register is modified

; HEN should be cleared

; HAEN = 0 Host acknowledge is disabled

; HREN = 1 Host requests are enabled

r
e

s
c

l
e

i
c

t
o

r
,

I

Freescale Semiconductor, Inc.

For More Information On This Product,

Go to: www.freescale.com

.
.

A-10

DSP56309UM/D MOTOROLA

Bootstrap Programs

; Can be implemented in future.

;

OMR0XXX

jclr #2,omr,EPRSCILD ; If MD:MC:MB:MA=00xx, default to EPROM/SCI

jclr #1,omr,OMR1IS0 ; IF MD:MC:MB:MA=010x, default to ISA/HC11

jclr #0,omr,I8051HOSTLD ; If MD:MC:MB:MA=0110, default to 8051 Host

; If MD:MC:MB:MA=0111, execute burnin test

;========================================================================

; This mode is reserved for internal testing purposes

; MD:MC:MB:MA=0111

;;---------------------------------------------------------

;;

;; burnin mode

;;

;; Intended to be used for burn-in test. Wake up from reset

;; with PINIT set for execution in maximum frequency.

;; All RAM locations are validated, arithmetic/logic operations

;; are validated (add, eor) and exercised (mac).

;; While all tests pass, the SCK0 pin will continue to toggle.

;; When the test fails the DSP enters DEBUG and stops execution.

;;

;;---------------------------------------------------------

;; get PATTERN pointer

clr b #PATTERNS,r6 ;; b is the error accumulator

move #<(NUM_PATTERNS-1),m6 ;; program runs forever in

;; cyclic form

;; configure SCK0 as gpio output. PRRC register is cleared at reset.

movep b,x:M_PDRC ;; clear GPIO data register

bset #SCK0,x:M_PRRC ;; Define SCK0 as output GPIO pin

;; SCK0 toggles means test pass

do #9,burn1

;;----------------------------

;; test RAM

;; each pass checks 1 pattern

;;----------------------------

move p:(r6)+,x1 ;; pattern for x memory

move p:(r6)+,x0 ;; pattern for y memory

move p:(r6)+,y0 ;; pattern for p memory

;; write pattern to all memory locations

if (EQUALDATA) ;; x/y ram symmetrical

;; write x and y memory

clr a #start_dram,r0 ;; start of x/y ram

move #>length_dram,n0 ;; length of x/y ram

rep n0

mac x0,x1,a x,l:(r0)+ ;; exercise mac, write x/y ram

r
e

s
c

l
e

i
c

t
o

r
,

I

Freescale Semiconductor, Inc.

For More Information On This Product,

Go to: www.freescale.com

.
.

Equates

MOTOROLA

DSP56309UM/D B-5

M_RWU EQU 6 ; Receiver Wakeup Enable

M_WOMS EQU 7 ; Wired-OR Mode Select

M_SCRE EQU 8 ; SCI Receiver Enable

M_SCTE EQU 9 ; SCI Transmitter Enable

M_ILIE EQU 10 ; Idle Line Interrupt Enable

M_SCRIE EQU 11 ; SCI Receive Interrupt Enable

M_SCTIE EQU 12 ; SCI Transmit Interrupt Enable

M_TMIE EQU 13 ; Timer Interrupt Enable

M_TIR EQU 14 ; Timer Interrupt Rate

M_SCKP EQU 15 ; SCI Clock Polarity

M_REIE EQU 16 ; SCI Error Interrupt Enable (REIE)

; SCI Status Register Bit Flags

M_TRNE EQU 0 ; Transmitter Empty

M_TDRE EQU 1 ; Transmit Data Register Empty

M_RDRF EQU 2 ; Receive Data Register Full

M_IDLE EQU 3 ; Idle Line Flag

M_OR EQU 4 ; Overrun Error Flag

M_PE EQU 5 ; Parity Error

M_FE EQU 6 ; Framing Error Flag

M_R8 EQU 7 ; Received Bit 8 (R8) Address

; SCI Clock Control Register

M_CD EQU $FFF ; Clock Divider Mask (CD0-CD11)

M_COD EQU 12 ; Clock Out Divider

M_SCP EQU 13 ; Clock Prescaler

M_RCM EQU 14 ; Receive Clock Mode Source Bit

M_TCM EQU 15 ; Transmit Clock Source Bit

B.4

ESSI EQUATES

;------------------------------------------------------------------------

;Enhanced Synchronous Serial Interface (ESSI) Equates

;------------------------------------------------------------------------

; Register Addresses Of SSI0

M_TX00 EQU $FFFFBC ; SSI0 Transmit Data Register 0

M_TX01 EQU $FFFFBB ; SSIO Transmit Data Register 1

M_TX02 EQU $FFFFBA ; SSIO Transmit Data Register 2

M_TSR0 EQU $FFFFB9 ; SSI0 Time Slot Register

M_RX0 EQU $FFFFB8 ; SSI0 Receive Data Register

M_SSISR0 EQU $FFFFB7 ; SSI0 Status Register

M_CRB0 EQU $FFFFB6 ; SSI0 Control Register B

M_CRA0 EQU $FFFFB5 ; SSI0 Control Register A

M_TSMA0 EQU $FFFFB4 ; SSI0 Transmit Slot Mask Register A

M_TSMB0 EQU $FFFFB3 ; SSI0 Transmit Slot Mask Register B

r
e

s
c

l
e

i
c

t
o

r
,

I

Freescale Semiconductor, Inc.

For More Information On This Product,

Go to: www.freescale.com

.
.

B-6

DSP56309UM/D MOTOROLA

Equates

M_RSMA0 EQU $FFFFB2 ; SSI0 Receive Slot Mask Register A

M_RSMB0 EQU $FFFFB1 ; SSI0 Receive Slot Mask Register B

; Register Addresses Of SSI1

M_TX10 EQU $FFFFAC ; SSI1 Transmit Data Register 0

M_TX11 EQU $FFFFAB ; SSI1 Transmit Data Register 1

M_TX12 EQU $FFFFAA ; SSI1 Transmit Data Register 2

M_TSR1 EQU $FFFFA9 ; SSI1 Time Slot Register

M_RX1 EQU $FFFFA8 ; SSI1 Receive Data Register

M_SSISR1 EQU $FFFFA7 ; SSI1 Status Register

M_CRB1 EQU $FFFFA6 ; SSI1 Control Register B

M_CRA1 EQU $FFFFA5 ; SSI1 Control Register A

M_TSMA1 EQU $FFFFA4 ; SSI1 Transmit Slot Mask Register A

M_TSMB1 EQU $FFFFA3 ; SSI1 Transmit Slot Mask Register B

M_RSMA1 EQU $FFFFA2 ; SSI1 Receive Slot Mask Register A

M_RSMB1 EQU $FFFFA1 ; SSI1 Receive Slot Mask Register B

; SSI Control Register A Bit Flags

M_PM EQU $FF ; Prescale Modulus Select Mask (PM0-PM7)

M_PSR EQU 11 ; Prescaler Range

M_DC EQU $1F000 ; Frame Rate Divider Control Mask (DC0-DC7)

M_ALC EQU 18 ; Alignment Control (ALC)

M_WL EQU $380000 ; Word Length Control Mask (WL0-WL7)

M_SSC1 EQU 22 ; Select SC1 as TR #0 drive enable (SSC1)

; SSI Control Register B Bit Flags

M_OF EQU $3 ; Serial Output Flag Mask

M_OF0 EQU 0 ; Serial Output Flag 0

M_OF1 EQU 1 ; Serial Output Flag 1

M_SCD EQU $1C ; Serial Control Direction Mask

M_SCD0 EQU 2 ; Serial Control 0 Direction

M_SCD1 EQU 3 ; Serial Control 1 Direction

M_SCD2 EQU 4 ; Serial Control 2 Direction

M_SCKD EQU 5 ; Clock Source Direction

M_SHFD EQU 6 ; Shift Direction

M_FSL EQU $180 ; Frame Sync Length Mask (FSL0-FSL1)

M_FSL0 EQU 7 ; Frame Sync Length 0

M_FSL1 EQU 8 ; Frame Sync Length 1

M_FSR EQU 9 ; Frame Sync Relative Timing

M_FSP EQU 10 ; Frame Sync Polarity

M_CKP EQU 11 ; Clock Polarity

M_SYN EQU 12 ; Sync/Async Control

M_MOD EQU 13 ; SSI Mode Select

M_SSTE EQU $1C000 ; SSI Transmit enable Mask

M_SSTE2 EQU 14 ; SSI Transmit #2 Enable

M_SSTE1 EQU 15 ; SSI Transmit #1 Enable

M_SSTE0 EQU 16 ; SSI Transmit #0 Enable

M_SSRE EQU 17 ; SSI Receive Enable

M_SSTIE EQU 18 ; SSI Transmit Interrupt Enable

M_SSRIE EQU 19 ; SSI Receive Interrupt Enable

r
e

s
c

l
e

i
c

t
o

r
,

I

Freescale Semiconductor, Inc.

For More Information On This Product,

Go to: www.freescale.com

.
.

B-8

DSP56309UM/D MOTOROLA

Equates

M_IBL0 EQU 3 ; IRQB Mode Interrupt Priority Level (low)

M_IBL1 EQU 4 ; IRQB Mode Interrupt Priority Level (high)

M_IBL2 EQU 5 ; IRQB Mode Trigger Mode

M_ICL EQU $1C0 ; IRQC Mode Mask

M_ICL0 EQU 6 ; IRQC Mode Interrupt Priority Level (low)

M_ICL1 EQU 7 ; IRQC Mode Interrupt Priority Level (high)

M_ICL2 EQU 8 ; IRQC Mode Trigger Mode

M_IDL EQU $E00 ; IRQD Mode Mask

M_IDL0 EQU 9 ; IRQD Mode Interrupt Priority Level

;(low)

M_IDL1 EQU 10 ; IRQD Mode Interrupt Priority Level

;(high)

M_IDL2 EQU 11 ; IRQD Mode Trigger Mode

M_D0L EQU $3000 ; DMA0 Interrupt priority Level Mask

M_D0L0 EQU 12 ; DMA0 Interrupt Priority Level (low)

M_D0L1 EQU 13 ; DMA0 Interrupt Priority Level (high)

M_D1L EQU $C000 ; DMA1 Interrupt Priority Level Mask

M_D1L0 EQU 14 ; DMA1 Interrupt Priority Level (low)

M_D1L1 EQU 15 ; DMA1 Interrupt Priority Level (high)

M_D2L EQU $30000 ; DMA2 Interrupt priority Level Mask

M_D2L0 EQU 16 ; DMA2 Interrupt Priority Level (low)

M_D2L1 EQU 17 ; DMA2 Interrupt Priority Level (high)

M_D3L EQU $C0000 ; DMA3 Interrupt Priority Level Mask

M_D3L0 EQU 18 ; DMA3 Interrupt Priority Level (low)

M_D3L1 EQU 19 ; DMA3 Interrupt Priority Level (high)

M_D4L EQU $300000 ; DMA4 Interrupt priority Level Mask

M_D4L0 EQU 20 ; DMA4 Interrupt Priority Level (low)

M_D4L1 EQU 21 ; DMA4 Interrupt Priority Level (high)

M_D5L EQU $C00000 ; DMA5 Interrupt priority Level Mask

M_D5L0 EQU 22 ; DMA5 Interrupt Priority Level (low)

M_D5L1 EQU 23 ; DMA5 Interrupt Priority Level (high)

; Interrupt Priority Register Peripheral (IPRP)

M_HPL EQU $3 ; Host Interrupt Priority Level Mask

M_HPL0 EQU 0 ; Host Interrupt Priority Level (low)

M_HPL1 EQU 1 ; Host Interrupt Priority Level (high)

M_S0L EQU $C ; SSI0 Interrupt Priority Level Mask

M_S0L0 EQU 2 ; SSI0 Interrupt Priority Level (low)

M_S0L1 EQU 3 ; SSI0 Interrupt Priority Level (high)

M_S1L EQU $30 ; SSI1 Interrupt Priority Level Mask

M_S1L0 EQU 4 ; SSI1 Interrupt Priority Level (low)

M_S1L1 EQU 5 ; SSI1 Interrupt Priority Level (high)

M_SCL EQU $C0 ; SCI Interrupt Priority Level Mask

M_SCL0 EQU 6 ; SCI Interrupt Priority Level (low)

M_SCL1 EQU 7 ; SCI Interrupt Priority Level (high)

M_T0L EQU $300 ; TIMER Interrupt Priority Level Mask

M_T0L0 EQU 8 ; TIMER Interrupt Priority Level (low)

M_T0L1 EQU 9 ; TIMER Interrupt Priority Level (high)

r
e

s
c

l
e

i
c

t
o

r
,

I

Freescale Semiconductor, Inc.

For More Information On This Product,

Go to: www.freescale.com

.
.

DSP56309 BSDL Listing

MOTOROLA

DSP56309UM/D C-5

ÒSC11: 144 Ò;

attribute TAP_SCAN_IN of TDI : signal is true;

attribute TAP_SCAN_OUT of TDO : signal is true;

attribute TAP_SCAN_MODE of TMS : signal is true;

attribute TAP_SCAN_RESET of TRST_N : signal is true;

attribute TAP_SCAN_CLOCK of TCK : signal is (20.0e6, BOTH);

attribute INSTRUCTION_LENGTH of DSP56309 : entity is 4;

attribute INSTRUCTION_OPCODE of DSP56309 : entity is

ÒEXTEST (0000),Ó &

ÒSAMPLE (0001),Ó &

ÒIDCODE (0010),Ó &

ÒCLAMP (0101),Ó &

ÒHIGHZ (0100),Ó &

ÒENABLE_ONCE (0110),Ó &

ÒDEBUG_REQUEST(0111),Ó &

ÒBYPASS (1111)Ó;

attribute INSTRUCTION_CAPTURE of DSP56309 : entity is Ò0001Ó;

attribute IDCODE_REGISTER of DSP56309 : entity is

Ò0010Ó & -- version

Ò000110Ó & -- manufacturerÕs use

Ò0000000010Ó & -- sequence number

Ò00000001110Ó & -- manufacturer identity

Ò1Ó; -- 1149.1 requirement

attribute REGISTER_ACCESS of DSP56309 : entity is

ÒONCE[8] (ENABLE_ONCE,DEBUG_REQUEST)Ó ;

attribute BOUNDARY_LENGTH of DSP56309 : entity is 144;

attribute BOUNDARY_REGISTER of DSP56309 : entity is

-- num cell port func safe [ccell dis rslt]

Ò0 (BC_1, MODA, input, X),Ó &

Ò1 (BC_1, MODB, input, X),Ó &

Ò2 (BC_1, MODC, input, X),Ó &

Ò3 (BC_1, MODD, input, X),Ó &

Ò4 (BC_6, D(23), bidir, X, 13, 1, Z),Ó &

Ò5 (BC_6, D(22), bidir, X, 13, 1, Z),Ó &

Ò6 (BC_6, D(21), bidir, X, 13, 1, Z),Ó &

Ò7 (BC_6, D(20), bidir, X, 13, 1, Z),Ó &

Ò8 (BC_6, D(19), bidir, X, 13, 1, Z),Ó &

Ò9 (BC_6, D(18), bidir, X, 13, 1, Z),Ó &

Ò10 (BC_6, D(17), bidir, X, 13, 1, Z),Ó &

Ò11 (BC_6, D(16), bidir, X, 13, 1, Z),Ó &

Ò12 (BC_6, D(15), bidir, X, 13, 1, Z),Ó &

Ò13 (BC_1, *, control, 1),Ó &

Ò14 (BC_6, D(14), bidir, X, 13, 1, Z),Ó &

Ò15 (BC_6, D(13), bidir, X, 13, 1, Z),Ó &

Ò16 (BC_6, D(12), bidir, X, 13, 1, Z),Ó &

r
e

s
c

l
e

i
c

t
o

r
,

I

Freescale Semiconductor, Inc.

For More Information On This Product,

Go to: www.freescale.com

.
.

C-6

DSP56309UM/D MOTOROLA

DSP56309 BSDL Listing

Ò17 (BC_6, D(11), bidir, X, 26, 1, Z),Ó &

Ò18 (BC_6, D(10), bidir, X, 26, 1, Z),Ó &

Ò19 (BC_6, D(9), bidir, X, 26, 1, Z),Ó &

-- num cell port func safe [ccell dis rslt]

Ò20 (BC_6, D(8), bidir, X, 26, 1, Z),Ó &

Ò21 (BC_6, D(7), bidir, X, 26, 1, Z),Ó &

Ò22 (BC_6, D(6), bidir, X, 26, 1, Z),Ó &

Ò23 (BC_6, D(5), bidir, X, 26, 1, Z),Ó &

Ò24 (BC_6, D(4), bidir, X, 26, 1, Z),Ó &

Ò25 (BC_6, D(3), bidir, X, 26, 1, Z),Ó &

Ò26 (BC_1, *, control, 1),Ó &

Ò27 (BC_6, D(2), bidir, X, 26, 1, Z),Ó &

Ò28 (BC_6, D(1), bidir, X, 26, 1, Z),Ó &

Ò29 (BC_6, D(0), bidir, X, 26, 1, Z),Ó &

Ò30 (BC_1, A(17), output3, X, 33, 1, Z),Ó &

Ò31 (BC_1, A(16), output3, X, 33, 1, Z),Ó &

Ò32 (BC_1, A(15), output3, X, 33, 1, Z),Ó &

Ò33 (BC_1, *, control, 1),Ó &

Ò34 (BC_1, A(14), output3, X, 33, 1, Z),Ó &

Ò35 (BC_1, A(13), output3, X, 33, 1, Z),Ó &

Ò36 (BC_1, A(12), output3, X, 33, 1, Z),Ó &

Ò37 (BC_1, A(11), output3, X, 33, 1, Z),Ó &

Ò38 (BC_1, A(10), output3, X, 33, 1, Z),Ó &

Ò39 (BC_1, A(9), output3, X, 33, 1, Z),Ó &

-- num cell port func safe [ccell dis rslt]

Ò40 (BC_1, A(8), output3, X, 43, 1, Z),Ó &

Ò41 (BC_1, A(7), output3, X, 43, 1, Z),Ó &

Ò42 (BC_1, A(6), output3, X, 43, 1, Z),Ó &

Ò43 (BC_1, *, control, 1),Ó &

Ò44 (BC_1, A(5), output3, X, 43, 1, Z),Ó &

Ò45 (BC_1, A(4), output3, X, 43, 1, Z),Ó &

Ò46 (BC_1, A(3), output3, X, 43, 1, Z),Ó &

Ò47 (BC_1, A(2), output3, X, 43, 1, Z),Ó &

Ò48 (BC_1, A(1), output3, X, 43, 1, Z),Ó &

Ò49 (BC_1, A(0), output3, X, 43, 1, Z),Ó &

Ò50 (BC_1, BG_N, input, X),Ó &

Ò51 (BC_1, AA(0), output3, X, 55, 1, Z),Ó &

Ò52 (BC_1, AA(1), output3, X, 56, 1, Z),Ó &

Ò53 (BC_1, RD_N, output3, X, 64, 1, Z),Ó &

Ò54 (BC_1, WR_N, output3, X, 64, 1, Z),Ó &

Ò55 (BC_1, *, control, 1),Ó &

Ò56 (BC_1, *, control, 1),Ó &

Ò57 (BC_1, *, control, 1),Ó &

Ò58 (BC_6, BB_N, bidir, X, 57, 1, Z),Ó &

Ò59 (BC_1, BR_N, output2, X),Ó &

-- num cell port func safe [ccell dis rslt]

Ò60 (BC_1, TA_N, input, X),Ó &

Ò61 (BC_1, BCLK_N, output3, X, 64, 1, Z),Ó &

Ò62 (BC_1, BCLK, output3, X, 64, 1, Z),Ó &

Ò63 (BC_1, CLKOUT, output2, X),Ó &

Ò64 (BC_1, *, control, 1),Ó &

Ò65 (BC_1, *, control, 1),Ó &

Ò66 (BC_1, *, control, 1),Ó &

r
e

s
c

l
e

i
c

t
o

r
,

I

Freescale Semiconductor, Inc.

For More Information On This Product,

Go to: www.freescale.com

.
.

DSP56309 BSDL Listing

MOTOROLA

DSP56309UM/D C-7

Ò67 (BC_1, *, control, 1),Ó &

Ò68 (BC_1, EXTAL, input, X),Ó &

Ò69 (BC_1, CAS_N, output3, X, 65, 1, Z),Ó &

Ò70 (BC_1, AA(2), output3, X, 66, 1, Z),Ó &

Ò71 (BC_1, AA(3), output3, X, 67, 1, Z),Ó &

Ò72 (BC_1, RESET_N, input, X),Ó &

Ò73 (BC_1, *, control, 1),Ó &

Ò74 (BC_6, HAD(0), bidir, X, 73, 1, Z),Ó &

Ò75 (BC_1, *, control, 1),Ó &

Ò76 (BC_6, HAD(1), bidir, X, 75, 1, Z),Ó &

Ò77 (BC_1, *, control, 1),Ó &

Ò78 (BC_6, HAD(2), bidir, X, 77, 1, Z),Ó &

Ò79 (BC_1, *, control, 1),Ó &

-- num cell port func safe [ccell dis rslt]

Ò80 (BC_6, HAD(3), bidir, X, 79, 1, Z),Ó &

Ò81 (BC_1, *, control, 1),Ó &

Ò82 (BC_6, HAD(4), bidir, X, 81, 1, Z),Ó &

Ò83 (BC_1, *, control, 1),Ó &

Ò84 (BC_6, HAD(5), bidir, X, 83, 1, Z),Ó &

Ò85 (BC_1, *, control, 1),Ó &

Ò86 (BC_6, HAD(6), bidir, X, 85, 1, Z),Ó &

Ò87 (BC_1, *, control, 1),Ó &

Ò88 (BC_6, HAD(7), bidir, X, 87, 1, Z),Ó &

Ò89 (BC_1, *, control, 1),Ó &

Ò90 (BC_6, HAS, bidir, X, 89, 1, Z),Ó &

Ò91 (BC_1, *, control, 1),Ó &

Ò92 (BC_6, HA8, bidir, X, 91, 1, Z),Ó &

Ò93 (BC_1, *, control, 1),Ó &

Ò94 (BC_6, HA9, bidir, X, 93, 1, Z),Ó &

Ò95 (BC_1, *, control, 1),Ó &

Ò96 (BC_6, HCS, bidir, X, 95, 1, Z),Ó &

Ò97 (BC_1, *, control, 1),Ó &

Ò98 (BC_6, TIO0, bidir, X, 97, 1, Z),Ó &

Ò99 (BC_1, *, control, 1),Ó &

-- num cell port func safe [ccell dis rslt]

Ò100 (BC_6, TIO1, bidir, X, 99, 1, Z),Ó &

Ò101 (BC_1, *, control, 1),Ó &

Ò102 (BC_6, TIO2, bidir, X, 101, 1, Z),Ó &

Ò103 (BC_1, *, control, 1),Ó &

Ò104 (BC_6, HREQ, bidir, X, 103, 1, Z),Ó &

Ò105 (BC_1, *, control, 1),Ó &

Ò106 (BC_6, HACK, bidir, X, 105, 1, Z),Ó &

Ò107 (BC_1, *, control, 1),Ó &

Ò108 (BC_6, HRW, bidir, X, 107, 1, Z),Ó &

Ò109 (BC_1, *, control, 1),Ó &

Ò110 (BC_6, HDS, bidir, X, 109, 1, Z),Ó &

Ò111 (BC_1, *, control, 1),Ó &

Ò112 (BC_6, SCK0, bidir, X, 111, 1, Z),Ó &

Ò113 (BC_1, *, control, 1),Ó &

Ò114 (BC_6, SCK1, bidir, X, 113, 1, Z),Ó &

Ò115 (BC_1, *, control, 1),Ó &

Ò116 (BC_6, SCLK, bidir, X, 115, 1, Z),Ó &

Ò117 (BC_1, *, control, 1),Ó &

r
e

s
c

l
e

i
c

t
o

r
,

I

Freescale Semiconductor, Inc.

For More Information On This Product,

Go to: www.freescale.com

.
.

C-12

DSP56309UM/D MOTOROLA

DSP56309 BSDL Listing

ÒEXTEST (0000),Ó &

ÒSAMPLE (0001),Ó &

ÒIDCODE (0010),Ó &

ÒCLAMP (0101),Ó &

ÒHIGHZ (0100),Ó &

ÒENABLE_ONCE (0110),Ó &

ÒDEBUG_REQUEST (0111),Ó &

ÒBYPASS (1111)Ó;

attribute INSTRUCTION_CAPTURE of DSP56309 : entity is Ò0001Ó;

attribute IDCODE_REGISTER of DSP56309 : entity is

Ò0010Ó & -- version

Ò000110Ó & -- manufacturerÕs use

Ò0000000010Ó & -- sequence number

Ò00000001110Ó & -- manufacturer identity

Ò1Ó; -- 1149.1 requirement

attribute REGISTER_ACCESS of DSP56309 : entity is

ÒONCE[8] (ENABLE_ONCE,DEBUG_REQUEST)Ó ;

attribute BOUNDARY_LENGTH of DSP56309 : entity is 144;

attribute BOUNDARY_REGISTER of DSP56309 : entity is

-- num cell port func safe [ccell dis rslt]

Ò0 (BC_1, MODA, input, X),Ó &

Ò1 (BC_1, MODB, input, X),Ó &

Ò2 (BC_1, MODC, input, X),Ó &

Ò3 (BC_1, MODD, input, X),Ó &

Ò4 (BC_6, D(23), bidir, X, 13, 1, Z),Ó &

Ò5 (BC_6, D(22), bidir, X, 13, 1, Z),Ó &

Ò6 (BC_6, D(21), bidir, X, 13, 1, Z),Ó &

Ò7 (BC_6, D(20), bidir, X, 13, 1, Z),Ó &

Ò8 (BC_6, D(19), bidir, X, 13, 1, Z),Ó &

Ò9 (BC_6, D(18), bidir, X, 13, 1, Z),Ó &

Ò10 (BC_6, D(17), bidir, X, 13, 1, Z),Ó &

Ò11 (BC_6, D(16), bidir, X, 13, 1, Z),Ó &

Ò12 (BC_6, D(15), bidir, X, 13, 1, Z),Ó &

Ò13 (BC_1, *, control, 1),Ó &

Ò14 (BC_6, D(14), bidir, X, 13, 1, Z),Ó &

Ò15 (BC_6, D(13), bidir, X, 13, 1, Z),Ó &

Ò16 (BC_6, D(12), bidir, X, 13, 1, Z),Ó &

Ò17 (BC_6, D(11), bidir, X, 26, 1, Z),Ó &

Ò18 (BC_6, D(10), bidir, X, 26, 1, Z),Ó &

Ò19 (BC_6, D(9), bidir, X, 26, 1, Z),Ó &

-- num cell port func safe [ccell dis rslt]

Ò20 (BC_6, D(8), bidir, X, 26, 1, Z),Ó &

Ò21 (BC_6, D(7), bidir, X, 26, 1, Z),Ó &

Ò22 (BC_6, D(6), bidir, X, 26, 1, Z),Ó &

Ò23 (BC_6, D(5), bidir, X, 26, 1, Z),Ó &

Ò24 (BC_6, D(4), bidir, X, 26, 1, Z),Ó &

Ò25 (BC_6, D(3), bidir, X, 26, 1, Z),Ó &

Ò26 (BC_1, *, control, 1),Ó &

Ò27 (BC_6, D(2), bidir, X, 26, 1, Z),Ó &

r
e

s
c

l
e

i
c

t
o

r
,

I

Freescale Semiconductor, Inc.

For More Information On This Product,

Go to: www.freescale.com

.
.

DSP56309 BSDL Listing

MOTOROLA

DSP56309UM/D C-13

Ò28 (BC_6, D(1), bidir, X, 26, 1, Z),Ó &

Ò29 (BC_6, D(0), bidir, X, 26, 1, Z),Ó &

Ò30 (BC_1, A(17), output3, X, 33, 1, Z),Ó &

Ò31 (BC_1, A(16), output3, X, 33, 1, Z),Ó &

Ò32 (BC_1, A(15), output3, X, 33, 1, Z),Ó &

Ò33 (BC_1, *, control, 1),Ó &

Ò34 (BC_1, A(14), output3, X, 33, 1, Z),Ó &

Ò35 (BC_1, A(13), output3, X, 33, 1, Z),Ó &

Ò36 (BC_1, A(12), output3, X, 33, 1, Z),Ó &

Ò37 (BC_1, A(11), output3, X, 33, 1, Z),Ó &

Ò38 (BC_1, A(10), output3, X, 33, 1, Z),Ó &

Ò39 (BC_1, A(9), output3, X, 33, 1, Z),Ó &

-- num cell port func safe [ccell dis rslt]

Ò40 (BC_1, A(8), output3, X, 43, 1, Z),Ó &

Ò41 (BC_1, A(7), output3, X, 43, 1, Z),Ó &

Ò42 (BC_1, A(6), output3, X, 43, 1, Z),Ó &

Ò43 (BC_1, *, control, 1),Ó &

Ò44 (BC_1, A(5), output3, X, 43, 1, Z),Ó &

Ò45 (BC_1, A(4), output3, X, 43, 1, Z),Ó &

Ò46 (BC_1, A(3), output3, X, 43, 1, Z),Ó &

Ò47 (BC_1, A(2), output3, X, 43, 1, Z),Ó &

Ò48 (BC_1, A(1), output3, X, 43, 1, Z),Ó &

Ò49 (BC_1, A(0), output3, X, 43, 1, Z),Ó &

Ò50 (BC_1, BG_N, input, X),Ó &

Ò51 (BC_1, AA(0), output3, X, 55, 1, Z),Ó &

Ò52 (BC_1, AA(1), output3, X, 56, 1, Z),Ó &

Ò53 (BC_1, RD_N, output3, X, 64, 1, Z),Ó &

Ò54 (BC_1, WR_N, output3, X, 64, 1, Z),Ó &

Ò55 (BC_1, *, control, 1),Ó &

Ò56 (BC_1, *, control, 1),Ó &

Ò57 (BC_1, *, control, 1),Ó &

Ò58 (BC_6, BB_N, bidir, X, 57, 1, Z),Ó &

Ò59 (BC_1, BR_N, output2, X),Ó &

-- num cell port func safe [ccell dis rslt]

Ò60 (BC_1, TA_N, input, X),Ó &

Ò61 (BC_1, BCLK_N, output3, X, 64, 1, Z),Ó &

Ò62 (BC_1, BCLK, output3, X, 64, 1, Z),Ó &

Ò63 (BC_1, CLKOUT, output2, X),Ó &

Ò64 (BC_1, *, control, 1),Ó &

Ò65 (BC_1, *, control, 1),Ó &

Ò66 (BC_1, *, control, 1),Ó &

Ò67 (BC_1, *, control, 1),Ó &

Ò68 (BC_1, EXTAL, input, X),Ó &

Ò69 (BC_1, CAS_N, output3, X, 65, 1, Z),Ó &

Ò70 (BC_1, AA(2), output3, X, 66, 1, Z),Ó &

Ò71 (BC_1, AA(3), output3, X, 67, 1, Z),Ó &

Ò72 (BC_1, RESET_N, input, X),Ó &

Ò73 (BC_1, *, control, 1),Ó &

Ò74 (BC_6, HAD(0), bidir, X, 73, 1, Z),Ó &

Ò75 (BC_1, *, control, 1),Ó &

Ò76 (BC_6, HAD(1), bidir, X, 75, 1, Z),Ó &

Ò77 (BC_1, *, control, 1),Ó &

Ò78 (BC_6, HAD(2), bidir, X, 77, 1, Z),Ó &

r
e

s
c

l
e

i
c

t
o

r
,

I

Freescale Semiconductor, Inc.

For More Information On This Product,

Go to: www.freescale.com

.
.

C-14

DSP56309UM/D MOTOROLA

DSP56309 BSDL Listing

Ò79 (BC_1, *, control, 1),Ó &

-- num cell port func safe [ccell dis rslt]

Ò80 (BC_6, HAD(3), bidir, X, 79, 1, Z),Ó &

Ò81 (BC_1, *, control, 1),Ó &

Ò82 (BC_6, HAD(4), bidir, X, 81, 1, Z),Ó &

Ò83 (BC_1, *, control, 1),Ó &

Ò84 (BC_6, HAD(5), bidir, X, 83, 1, Z),Ó &

Ò85 (BC_1, *, control, 1),Ó &

Ò86 (BC_6, HAD(6), bidir, X, 85, 1, Z),Ó &

Ò87 (BC_1, *, control, 1),Ó &

Ò88 (BC_6, HAD(7), bidir, X, 87, 1, Z),Ó &

Ò89 (BC_1, *, control, 1),Ó &

Ò90 (BC_6, HAS, bidir, X, 89, 1, Z),Ó &

Ò91 (BC_1, *, control, 1),Ó &

Ò92 (BC_6, HA8, bidir, X, 91, 1, Z),Ó &

Ò93 (BC_1, *, control, 1),Ó &

Ò94 (BC_6, HA9, bidir, X, 93, 1, Z),Ó &

Ò95 (BC_1, *, control, 1),Ó &

Ò96 (BC_6, HCS, bidir, X, 95, 1, Z),Ó &

Ò97 (BC_1, *, control, 1),Ó &

Ò98 (BC_6, TIO0, bidir, X, 97, 1, Z),Ó &

Ò99 (BC_1, *, control, 1),Ó &

-- num cell port func safe [ccell dis rslt]

Ò100 (BC_6, TIO1, bidir, X, 99, 1, Z),Ó &

Ò101 (BC_1, *, control, 1),Ó &

Ò102 (BC_6, TIO2, bidir, X, 101, 1, Z),Ó &

Ò103 (BC_1, *, control, 1),Ó &

Ò104 (BC_6, HREQ, bidir, X, 103, 1, Z),Ó &

Ò105 (BC_1, *, control, 1),Ó &

Ò106 (BC_6, HACK, bidir, X, 105, 1, Z),Ó &

Ò107 (BC_1, *, control, 1),Ó &

Ò108 (BC_6, HRW, bidir, X, 107, 1, Z),Ó &

Ò109 (BC_1, *, control, 1),Ó &

Ò110 (BC_6, HDS, bidir, X, 109, 1, Z),Ó &

Ò111 (BC_1, *, control, 1),Ó &

Ò112 (BC_6, SCK0, bidir, X, 111, 1, Z),Ó &

Ò113 (BC_1, *, control, 1),Ó &

Ò114 (BC_6, SCK1, bidir, X, 113, 1, Z),Ó &

Ò115 (BC_1, *, control, 1),Ó &

Ò116 (BC_6, SCLK, bidir, X, 115, 1, Z),Ó &

Ò117 (BC_1, *, control, 1),Ó &

Ò118 (BC_6, TXD, bidir, X, 117, 1, Z),Ó &

Ò119 (BC_1, *, control, 1),Ó &

-- num cell port func safe [ccell dis rslt]

Ò120 (BC_6, RXD, bidir, X, 119, 1, Z),Ó &

Ò121 (BC_1, *, control, 1),Ó &

Ò122 (BC_6, SC00, bidir, X, 121, 1, Z),Ó &

Ò123 (BC_1, *, control, 1),Ó &

Ò124 (BC_6, SC10, bidir, X, 123, 1, Z),Ó &

Ò125 (BC_1, *, control, 1),Ó &

Ò126 (BC_6, STD0, bidir, X, 125, 1, Z),Ó &

Ò127 (BC_1, *, control, 1),Ó &

Ò128 (BC_6, SRD0, bidir, X, 127, 1, Z),Ó &

r
e

s
c

l
e

i
c

t
o

r
,

I

Freescale Semiconductor, Inc.

For More Information On This Product,

Go to: www.freescale.com

.
.

DSP56309 BSDL Listing

MOTOROLA

DSP56309UM/D C-19

attribute BOUNDARY_REGISTER of DSP56309 : entity is

-- num cell port func safe [ccell dis rslt]

Ò0 (BC_1, MODA, input, X),Ó &

Ò1 (BC_1, MODB, input, X),Ó &

Ò2 (BC_1, MODC, input, X),Ó &

Ò3 (BC_1, MODD, input, X),Ó &

Ò4 (BC_6, D(23), bidir, X, 13, 1, Z),Ó &

Ò5 (BC_6, D(22), bidir, X, 13, 1, Z),Ó &

Ò6 (BC_6, D(21), bidir, X, 13, 1, Z),Ó &

Ò7 (BC_6, D(20), bidir, X, 13, 1, Z),Ó &

Ò8 (BC_6, D(19), bidir, X, 13, 1, Z),Ó &

Ò9 (BC_6, D(18), bidir, X, 13, 1, Z),Ó &

Ò10 (BC_6, D(17), bidir, X, 13, 1, Z),Ó &

Ò11 (BC_6, D(16), bidir, X, 13, 1, Z),Ó &

Ò12 (BC_6, D(15), bidir, X, 13, 1, Z),Ó &

Ò13 (BC_1, *, control, 1),Ó &

Ò14 (BC_6, D(14), bidir, X, 13, 1, Z),Ó &

Ò15 (BC_6, D(13), bidir, X, 13, 1, Z),Ó &

Ò16 (BC_6, D(12), bidir, X, 13, 1, Z),Ó &

Ò17 (BC_6, D(11), bidir, X, 26, 1, Z),Ó &

Ò18 (BC_6, D(10), bidir, X, 26, 1, Z),Ó &

Ò19 (BC_6, D(9), bidir, X, 26, 1, Z),Ó &

-- num cell port func safe [ccell dis rslt]

Ò20 (BC_6, D(8), bidir, X, 26, 1, Z),Ó &

Ò21 (BC_6, D(7), bidir, X, 26, 1, Z),Ó &

Ò22 (BC_6, D(6), bidir, X, 26, 1, Z),Ó &

Ò23 (BC_6, D(5), bidir, X, 26, 1, Z),Ó &

Ò24 (BC_6, D(4), bidir, X, 26, 1, Z),Ó &

Ò25 (BC_6, D(3), bidir, X, 26, 1, Z),Ó &

Ò26 (BC_1, *, control, 1),Ó &

Ò27 (BC_6, D(2), bidir, X, 26, 1, Z),Ó &

Ò28 (BC_6, D(1), bidir, X, 26, 1, Z),Ó &

Ò29 (BC_6, D(0), bidir, X, 26, 1, Z),Ó &

Ò30 (BC_1, A(17), output3, X, 33, 1, Z),Ó &

Ò31 (BC_1, A(16), output3, X, 33, 1, Z),Ó &

Ò32 (BC_1, A(15), output3, X, 33, 1, Z),Ó &

Ò33 (BC_1, *, control, 1),Ó &

Ò34 (BC_1, A(14), output3, X, 33, 1, Z),Ó &

Ò35 (BC_1, A(13), output3, X, 33, 1, Z),Ó &

Ò36 (BC_1, A(12), output3, X, 33, 1, Z),Ó &

Ò37 (BC_1, A(11), output3, X, 33, 1, Z),Ó &

Ò38 (BC_1, A(10), output3, X, 33, 1, Z),Ó &

Ò39 (BC_1, A(9), output3, X, 33, 1, Z),Ó &

-- num cell port func safe [ccell dis rslt]

Ò40 (BC_1, A(8), output3, X, 43, 1, Z),Ó &

Ò41 (BC_1, A(7), output3, X, 43, 1, Z),Ó &

Ò42 (BC_1, A(6), output3, X, 43, 1, Z),Ó &

Ò43 (BC_1, *, control, 1),Ó &

Ò44 (BC_1, A(5), output3, X, 43, 1, Z),Ó &

Ò45 (BC_1, A(4), output3, X, 43, 1, Z),Ó &

Ò46 (BC_1, A(3), output3, X, 43, 1, Z),Ó &

Ò47 (BC_1, A(2), output3, X, 43, 1, Z),Ó &

r
e

s
c

l
e

i
c

t
o

r
,

I

Freescale Semiconductor, Inc.

For More Information On This Product,

Go to: www.freescale.com

.
.

C-20

DSP56309UM/D MOTOROLA

DSP56309 BSDL Listing

Ò48 (BC_1, A(1), output3, X, 43, 1, Z),Ó &

Ò49 (BC_1, A(0), output3, X, 43, 1, Z),Ó &

Ò50 (BC_1, BG_N, input, X),Ó &

Ò51 (BC_1, AA(0), output3, X, 55, 1, Z),Ó &

Ò52 (BC_1, AA(1), output3, X, 56, 1, Z),Ó &

Ò53 (BC_1, RD_N, output3, X, 64, 1, Z),Ó &

Ò54 (BC_1, WR_N, output3, X, 64, 1, Z),Ó &

Ò55 (BC_1, *, control, 1),Ó &

Ò56 (BC_1, *, control, 1),Ó &

Ò57 (BC_1, *, control, 1),Ó &

Ò58 (BC_6, BB_N, bidir, X, 57, 1, Z),Ó &

Ò59 (BC_1, BR_N, output2, X),Ó &

-- num cell port func safe [ccell dis rslt]

Ò60 (BC_1, TA_N, input, X),Ó &

Ò61 (BC_1, BCLK_N, output3, X, 64, 1, Z),Ó &

Ò62 (BC_1, BCLK, output3, X, 64, 1, Z),Ó &

Ò63 (BC_1, CLKOUT, output2, X),Ó &

Ò64 (BC_1, *, control, 1),Ó &

Ò65 (BC_1, *, control, 1),Ó &

Ò66 (BC_1, *, control, 1),Ó &

Ò67 (BC_1, *, control, 1),Ó &

Ò68 (BC_1, EXTAL, input, X),Ó &

Ò69 (BC_1, CAS_N, output3, X, 65, 1, Z),Ó &

Ò70 (BC_1, AA(2), output3, X, 66, 1, Z),Ó &

Ò71 (BC_1, AA(3), output3, X, 67, 1, Z),Ó &

Ò72 (BC_1, RESET_N, input, X),Ó &

Ò73 (BC_1, *, control, 1),Ó &

Ò74 (BC_6, HAD(0), bidir, X, 73, 1, Z),Ó &

Ò75 (BC_1, *, control, 1),Ó &

Ò76 (BC_6, HAD(1), bidir, X, 75, 1, Z),Ó &

Ò77 (BC_1, *, control, 1),Ó &

Ò78 (BC_6, HAD(2), bidir, X, 77, 1, Z),Ó &

Ò79 (BC_1, *, control, 1),Ó &

-- num cell port func safe [ccell dis rslt]

Ò80 (BC_6, HAD(3), bidir, X, 79, 1, Z),Ó &

Ò81 (BC_1, *, control, 1),Ó &

Ò82 (BC_6, HAD(4), bidir, X, 81, 1, Z),Ó &

Ò83 (BC_1, *, control, 1),Ó &

Ò84 (BC_6, HAD(5), bidir, X, 83, 1, Z),Ó &

Ò85 (BC_1, *, control, 1),Ó &

Ò86 (BC_6, HAD(6), bidir, X, 85, 1, Z),Ó &

Ò87 (BC_1, *, control, 1),Ó &

Ò88 (BC_6, HAD(7), bidir, X, 87, 1, Z),Ó &

Ò89 (BC_1, *, control, 1),Ó &

Ò90 (BC_6, HAS, bidir, X, 89, 1, Z),Ó &

Ò91 (BC_1, *, control, 1),Ó &

Ò92 (BC_6, HA8, bidir, X, 91, 1, Z),Ó &

Ò93 (BC_1, *, control, 1),Ó &

Ò94 (BC_6, HA9, bidir, X, 93, 1, Z),Ó &

Ò95 (BC_1, *, control, 1),Ó &

Ò96 (BC_6, HCS, bidir, X, 95, 1, Z),Ó &

Ò97 (BC_1, *, control, 1),Ó &

Ò98 (BC_6, TIO0, bidir, X, 97, 1, Z),Ó &

r
e

s
c

l
e

i
c

t
o

r
,

I

Freescale Semiconductor, Inc.

For More Information On This Product,

Go to: www.freescale.com

.
.

DSP56309 BSDL Listing

MOTOROLA

DSP56309UM/D C-21

Ò99 (BC_1, *, control, 1),Ó &

-- num cell port func safe [ccell dis rslt]

Ò100 (BC_6, TIO1, bidir, X, 99, 1, Z),Ó &

Ò101 (BC_1, *, control, 1),Ó &

Ò102 (BC_6, TIO2, bidir, X, 101, 1, Z),Ó &

Ò103 (BC_1, *, control, 1),Ó &

Ò104 (BC_6, HREQ, bidir, X, 103, 1, Z),Ó &

Ò105 (BC_1, *, control, 1),Ó &

Ò106 (BC_6, HACK, bidir, X, 105, 1, Z),Ó &

Ò107 (BC_1, *, control, 1),Ó &

Ò108 (BC_6, HRW, bidir, X, 107, 1, Z),Ó &

Ò109 (BC_1, *, control, 1),Ó &

Ò110 (BC_6, HDS, bidir, X, 109, 1, Z),Ó &

Ò111 (BC_1, *, control, 1),Ó &

Ò112 (BC_6, SCK0, bidir, X, 111, 1, Z),Ó &

Ò113 (BC_1, *, control, 1),Ó &

Ò114 (BC_6, SCK1, bidir, X, 113, 1, Z),Ó &

Ò115 (BC_1, *, control, 1),Ó &

Ò116 (BC_6, SCLK, bidir, X, 115, 1, Z),Ó &

Ò117 (BC_1, *, control, 1),Ó &

Ò118 (BC_6, TXD, bidir, X, 117, 1, Z),Ó &

Ò119 (BC_1, *, control, 1),Ó &

-- num cell port func safe [ccell dis rslt]

Ò120 (BC_6, RXD, bidir, X, 119, 1, Z),Ó &

Ò121 (BC_1, *, control, 1),Ó &

Ò122 (BC_6, SC00, bidir, X, 121, 1, Z),Ó &

Ò123 (BC_1, *, control, 1),Ó &

Ò124 (BC_6, SC10, bidir, X, 123, 1, Z),Ó &

Ò125 (BC_1, *, control, 1),Ó &

Ò126 (BC_6, STD0, bidir, X, 125, 1, Z),Ó &

Ò127 (BC_1, *, control, 1),Ó &

Ò128 (BC_6, SRD0, bidir, X, 127, 1, Z),Ó &

Ò129 (BC_1, PINIT, input, X),Ó &

Ò130 (BC_1, *, control, 1),Ó &

Ò131 (BC_6, DE_N, bidir, X, 130, 1, Pull1),Ó &

Ò132 (BC_1, *, control, 1),Ó &

Ò133 (BC_6, SC01, bidir, X, 132, 1, Z),Ó &

Ò134 (BC_1, *, control, 1),Ó &

Ò135 (BC_6, SC02, bidir, X, 134, 1, Z),Ó &

Ò136 (BC_1, *, control, 1),Ó &

Ò137 (BC_6, STD1, bidir, X, 136, 1, Z),Ó &

Ò138 (BC_1, *, control, 1),Ó &

Ò139 (BC_6, SRD1, bidir, X, 138, 1, Z),Ó &

-- num cell port func safe [ccell dis rslt]

Ò140 (BC_1, *, control, 1),Ó &

Ò141 (BC_6, SC11, bidir, X, 140, 1, Z),Ó &

Ò142 (BC_1, *, control, 1),Ó &

Ò143 (BC_6, SC12, bidir, X, 142, 1, Z)Ó;

end DSP56309;

r
e

s
c

l
e

i
c

t
o

r
,

I

Freescale Semiconductor, Inc.

For More Information On This Product,

Go to: www.freescale.com

.
.

D-22

DSP56309UM/D MOTOROLA

Programming Reference

Figure D-8

Host Base Address and Host Port Control Registers

Application:

Date:

Programmer:

Sheet 3 of 6

HOST

BA5

BA3

BA7

BA4

BA6

Host Base Address Register (HBAR)

X:$FFFFC5

Reset = $80

BA8

BA9

BA10

HAEN

HREN HCSEN HA9EN HA8EN HGEN

= Reserved, Program as 0

HEN

HAP

HRP

HCSP

HDDS

HROD

HMUX

HDSP

HASP

Host Port Control

X:$FFFFC4

Reset = $0

Host Acknowledge Enable
0

® HACK = GPIO

Host Request Enable
0

® HREQ/HACK = GPIO,

® HREQ = HREQ, if HDRQ = 0

Host Chip Select Enable
0

® HCS/HAI0 = GPIO,

® HCS/HA10 = HC8, if HMUX = 0

® HCS/HA10 = HC10, if HMUX = 1

Host Address Line 9 Enable
0

® HA9 = GPIO, 1 ® HA9 = HA9

Host Address Line 8 Enable
0

® HA8 = GPIO, 1 ® HA8 = HA8

Host GPIO Port Enable
0 = GPIO Pins Disable, 1 = GPIO Pin Enable

Host Acknowledge Priority
0 = HACK Active Low, 1 = HACK Active High

Host Chip Select Polarity
0 = HCS Active Low

Host Dual Data Strobe
0 = Singles Stroke, 1 = Dual Stoke

Host Multiplexed Bus
0 = Nonmultiplexed, 1 = Multiplexed

Host Address Strobe Polarity
0 = Strobe Active Low, 1 = Strobe Active High

Host Data Strobe Polarity
0 = Strobe Active Low, 1 = Strobe Active High

Host Enable
0

® HI08 Disable

® HI08 Enable

Pins = GPIO

Register (HPCR)

Read/Write

If HDRQ & HREN = 1,
HACK = HACK

Host Request Open Drain

HDRQ

HROD

HREN/HEW

0
0
1
1

0
1
0
1

1
1
1
1

HTRQ & HRRQ Enable

1 = HCS Active High

Host Request Priority

HDRQ

HRP

0
0
1
1

0
1
0
1

HREQ Active Low
HREQ Active High
HTRQ,HRRQ Active Low
HTRQ,HRRQ Active High

r
e

s
c

l
e

i
c

t
o

r
,

I

Freescale Semiconductor, Inc.

For More Information On This Product,

Go to: www.freescale.com

.
.

Programming Reference

MOTOROLA

DSP56309UM/D D-27

Figure D-13

ESSI Control Register B (CRB)

Application:

Date:

Programmer:

Sheet 2 of 4

ESSI

9876543210

FSL0

SCKD

SCD2

SCD1

SCD0

OF1

OF0

TIE

RIE

RLIE

REIE

SHFD

Serial Control Direction Bits

SCDx = 0 (Output)

SCDx = 1(Output)

SC0 Pin

Rx Clk

Flag 0

SC1 Pin

Rx Frame Sync

Flag 1

SC2 Pin

Tx Frame Sync

Tx,

Frame

Sync

TEIE

TE0

TE1

TE2

MOD

SYN

CKP

Transmit 2 Enable (SYN=1 only)

0 = Disable 1 = Enable

Shift Direction

0 = MSB First 1 = LSB First

Frame Sync Relative Timing (WL Frame Sync only)

0 = with 1st data bit

1 = 1 clock cycle earlier than 1st data bit

Mode Select

0 = Normal

1 = Network

Clock Polarity (clk edge data & Frame Sync clocked out/in)

0 = out on rising / in on falling

1 = in on rising / out on falling

Sync/Async Control (Tx & Rx transfer together or not)

0 =

Asynchronous

1 = Synchronous

ESSI

Control Register B (CRBx)

ESSI0 :$FFFFB6 Read/Write

ESSI1 :$FFFFA6 Read/Write

Reset = $000000

Transmit 1 Enable (SYN=1 only)

0 = Disable 1 = Enable

Transmit Interrupt Enable

0 = Disable 1 = Enable

Receive Interrupt Enable

0 = Disable 1 = Enable

Transmit Last Slot Interrupt Enable

0 = Disable 1 = Enable

Receive Last Slot Interrupt Enable

0 = Disable 1 = Enable

Transmit Exception Interrupt Enable

0 = Disable 1 = Enable

Receive Exception Interrupt Enable

0 = Disable 1 = Enable

Frame Sync Polarity

0 = high level (positive)

1 = low level (negative)

TLIE

FSP

FSR

FSL1

Output Flag x

If SYN = 1 and SCD1 = 1

OFx

SCx Pin

Clock Source Direction

0 = External Clock 1 = Internal Clock

Transmit 0 Enable

0 = Disable 1 = Enable

Receiver Enable

0 = Disable 1 = Enable

FSL1

FSL0

Frame Sync Length

Word

Bit

Word

Bit

Word

Bit

r
e

s
c

l
e

i
c

t
o

r
,

I

Freescale Semiconductor, Inc.

For More Information On This Product,

Go to: www.freescale.com

.
.

D-30

DSP56309UM/D MOTOROLA

Programming Reference

Figure D-16

SCI Control Register (SCR)

Application:

Date:

Programmer:

Sheet 1 of 3

SCI

SCI Control Register (SCR)

15 14 13 12 11 10

WOMS

WAKE SBK SSFTD WDS2 WDS1 WDS0

RWU

SCKP STIR TMIE

TIE

RIE

ILIE

SCI Shift Direction
0 = LSB First
1 = MSB First

Send Break
0 = Send break, then revert
1 = Continually send breaks

Receiver Wakeup Enable
0 = receiver has awakened
1 = Wakeup function enabled

Receiver Enable
0 = Receiver Disabled
1 = Receiver Enabled

Wired-Or Mode Select
1 = Multidrop
0 = Point to Point

Wakeup Mode Select
0 = Idle Line Wakeup
1 = Address Bit Wakeup

Word Select Bits

0 0 0 = 8-bit Synchronous Data (Shift Register Mode)
0 0 1 = Reserved
0 1 0 = 10-bit Asynchronous (1 Start, 8 Data, 1 Stop)
0 1 1 = Reserved
1 0 0 = 11-bit Asynchronous (1 Start, 8 Data, Even Parity, 1 Stop)
1 0 1 = 11-bit Asynchronous (1 Start, 8 Data, Odd Parity, 1 Stop)
1 1 0 = 11-bit Multidrop (1 Start, 8 Data, Data Type, 1 Stop)
1 1 1 = Reserved

Transmitter Enable
0 = Transmitter Disable
1 = Transmitter Enable

Transmit Interrupt Enable
0 = Transmit Interrupts Disabled
1 = Transmit Interrupts Enabled

Idle Line Interrupt Enable
0 = Idle Line Interrupt Disabled
1 = Idle Line Interrupt Enabled

Receive Interrupt Enable

SCI Clock Polarity
0 = Clock Polarity is Positive
1 = Clock Polarity is Negative

SCI Timer Interrupt Rate
0 = Ö 32, 1 = Ö 1

Timer Interrupt Enable
0 = Timer Interrupts Disabled
1 = Timer Interrupts Enabled

0 = Receive Interrupt Disabled
1 = Idle Line Interrupt Enabled

Register (SCR)

Address X:$FFFF9C

Read/Write

SCI Control

REIE

SCI Receive Exception Inerrupt
0 = Receive Interrupt Disable
1 = Receive Interrupt Enable

= Reserved, Program as 0

r
e

s
c

l
e

i
c

t
o

r
,

I

Freescale Semiconductor, Inc.

For More Information On This Product,

Go to: www.freescale.com

.
.

Programming Reference

MOTOROLA

DSP56309UM/D D-31

Figure D-17

SCI Status and Clock Control Registers (SSR, SCCR)

Application:

Date:

Programmer:

Sheet 2 of 3

SCI

SCI Clock Control Register (SCCR)

15 14 13 12 11 10

CD7

CD5

CD4

CD3

CD2

CD1

CD0

= Reserved, Program as 0

CD6

TCM RCM

SCP

COD CD11

TDRE TRNE

= Reserved, Program as 0

CD10 CD9

CD8

RDRF

IDLE

SCI Status Register (SSR)

Address X:$FFFF93

Read Only

Reset = $000003

Received Bit 8
0 = Data
1 = Address

Framing Error Flag
0 = No error
1 = No Stop Bit detected

Parity Error Flag
0 = No error
1 = Incorrect Parity detected

Overrun Error Flag
0 = No error
1 = Overrun detected

Idle Line Flag
0 = Idle not detected
1 = Idle State

Receive Data Register Full
0 = Receive Data Register Empty
1 = Receive Data Register Full

Transmitter Data Register Empty
0 = Transmitter Data Register full
1 = Transmitter Data Register empty

Transmitter Empty
0 = Transmitter full
1 = Transmitter empty

Clock Divider Bits CD11 Ð CD0)

CD11 Ð CD0

cyc

Rate

$000

cyc

$001

cyc

$002

cyc

$FFE

cyc

/4095

$FFF

cyc

/4096

SCI Clock Prescaler
0 = Ö1 1 = Ö 8

SCI Status Register (SSR)

Clock Out Divider
0 = Divide clock by 16 before feed to SCLK
1 = Feed clock to directly to SCLK

Clock Divider Bits CD11 Ð CD0)

TCM RCM TX Clock RX Clock SCLK Pin

Mode

Internal

Output

Synchronous/Asynchronous

Internal

External

Input

Asynchronous only

External

Internal

Input

Asynchronous only

External

Input

Synchronous/Asynchronous

Receiver Clock Mode/Source
0 = Internal clock for Receiver

1 = External clock from SCLK

Transmitter Clock Mode/Source
0 = Internal clock for Transmitter

1 = External clock from SCLK

r
e

s
c

l
e

i
c

t
o

r
,

I

Freescale Semiconductor, Inc.

For More Information On This Product,

Go to: www.freescale.com

.
.

D-34

DSP56309UM/D MOTOROLA

Programming Reference

Figure D-20

Timer Control/Status Register (TCSR)

Application:

Date:

Programmer:

Sheet 2 of 3

15 14 13 12 11 10

TC3

TC1

TC0

TCIE TQIE

19 18 17 16

23 22 21 20

TCF

TC2

PCE

DIR

TOF

TRM

INV

Timers

Timer Enable Bit 0
0 = Timer Disabled
1 = Timer Enabled

Timer Overflow Interrupt Enable Bit 1
0 = Overflow Interrupts Disabled
1 = Overflow Interrupts Enabled

Inverter Bit 8
0 = 0- to-1 transitions on TIO input increment the counter,
or high pulse width measured, or high pulse output on TIO

1 = 1-to-0 transitions on TIO input increment the counter,
or low pulse width measured, or low pulse output on TIO

Timer Compare Interrupt Enable Bit 2
0 = Compare Interrupts Disabled
1 = Compare Interrupts Enabled

Timer Control/Status Register
TCSR0:$FFFF8F Read/Write
TCSR1:$FFFF8B Read/Write
TCSR2:$FFFF87 Read/Write
Reset = $000000

= Reserved, Program as 0

Timer Control Bits 4 Ð 7 (TC0 Ð TC3)

TC (3:0)

TIO

Clock

Mode

0000
0001
0010
0011
0100
0101
0110
0111
1000
1001
1010
1011
1100
1101
1110
1111

GPIO

Output
Output

Input
Input
Input
Input

Output

Output
Output

Ð
Ð
Ð
Ð
Ð

Internal
Internal
Internal

External

Internal
Internal
Internal
Internal

Internal
Internal

Ð
Ð
Ð
Ð
Ð

Timer
Timer Pulse
Timer Toggle
Event Counter
Input Width
Input Period
Capture
Pulse Width Modulation
Reserved
Watchdog Pulse
Watchdog Toggle
Reserved
Reserved
Reserved
Reserved
Reserved

Timer Reload Mode Bit 9

1 = Timer is reloaded when

selected condition occurs

0 = Timer operates as a free

running counter

Timer Overflow Flag Bit 20
0 = Ò1Ó has been written to TCSR(TOF),

or timer Overflow interrupt serviced

1 = Counter wraparound has occurred

Direction Bit 11
0 = TIO pin is input
1 = TIO pin is output

Data Output Bit 13
0 = Zero written to TIO pin
1 = One written to TIO pin

Data Input Bit 12
0 = Zero read on TIO pin
1 = One read on TIO pin

Timer Compare Flag Bit 21
0 = Ò1Ó has been written to TCSR(TCF),

or timer compare interrupt serviced

1 = Timer Compare has occurred

Prescaled Clock Enable Bit 15
0 = Clock source is CLK/2 or TIO
1 = Clock source is prescaler output

r
e

s
c

l
e

i
c

t
o

r
,

I

Freescale Semiconductor, Inc.

For More Information On This Product,

Go to: www.freescale.com

.
.

MOTOROLA

DSP56309UM/D I-1

INDEX

A0ÐA17 signals

2-9

AA0ÐAA3 signals

2-10

adder

modulo

1-9

offset

1-9

reverse-carry

1-9

address attribute signals

2-10

address bus

2-3

signals

2-9

Address Generation Unit

1-9

addressing modes

1-10

AGU

1-9

ALC bit

7-13

Alignment Control bit (ALC)

7-13

applications

1-7

Asynchronous/Synchronous bit (SYN)

7-18

BA3ÐBA10 bits

6-12

barrel shifter

1-8

Base Address bits (BA3ÐBA10)

6-12

BB signal

2-13

BCLK signal

2-13

BCLK signal

2-13

BG signal

2-12

bootstrap

4-4

bootstrap from byte-wide external memory

4-7

bootstrap program options

invoking

4-5

bootstrap ROM

3-7

bootstrap through HI08 (68302/68360)

4-9

bootstrap through HI08 (ISA)

4-8

bootstrap through HI08 (Multiplexed)

4-9

bootstrap through HI08 (non-multiplexed)

4-8

bootstrap through SCI

4-7

Boundary Scan Description Language

PBGA

C-8

TQFP

C-2

Boundary Scan Register (BSR)

11-7

BR signal

2-12

break

8-9

Breakpoint 0 and 1 Event bits (BT0ÐBT1)

10-14

Breakpoint 0 Condition Code Select bits

(CC00ÐCC01)

10-13

Breakpoint 0 Read/Write Select bits

(RW00ÐRW01)

10-12

Breakpoint 1 Condition Code Select bits

(CC10ÐCC11)

10-14

Breakpoint 1 Read/Write Select bits

(RW10ÐRW11)

10-13

BSDL listing

PBGA

C-8

TQFP

C-2

BSR register

11-7

BT0ÐBT1 bits

10-14

bus

address

2-4

data

2-4

external address

2-9

external data

2-9

multiplexed

2-4

non-multiplexed

2-4

bus busy signal (BB)

2-13

bus clock not signal (BCLK)

2-13

bus clock signal (BCLK)

2-13

bus control

2-3

bus grant signal (BG)

2-12

bus parking

2-13

bus request signal (BR)

2-12

buses

internal

1-13

BYPASS instruction

11-11

CAS signal

2-13

CC00ÐCC01 bits

10-13

CC10ÐCC11 bits

10-14

CD0ÐCD11 bits

8-16

Central Processing Unit (CPU)

1-3

CKP bit

7-18

CLAMP instruction

11-10

CLKGEN

1-11

CLKOUT signal

2-8

clock

1-7

2-3

Clock Divider bits (CD0ÐCD11)

8-16

Clock Generator (CLKGEN)

1-11

Clock Out Divider bit (COD)

8-16

clock output signal (CLKOUT)

2-8

Clock Polarity bit (CKP)

7-18

clock signals

2-7

Clock Source Direction bit (SCKD)

7-16

CMOS

1-7

COD bit

8-16

code

compatible

1-7

column address strobe signal (CAS)

2-13

CRA register

7-11

r
e

s
c

l
e

i
c

t
o

r
,

I

Freescale Semiconductor, Inc.

For More Information On This Product,

Go to: www.freescale.com

.
.

I-2

DSP56309UM/D MOTOROLA

bits 0Ð7ÑPrescale Modulus Select bits

(PM0ÐPM7)

7-11

bits 8Ð10Ñreserved bits

7-11

bit 11ÑPrescaler Range bit (PSR)

7-11

bits 12Ð16ÑFrame Rate Divider Control bits

(DC4ÐDC0)

7-12

bit 17Ñreserved bit

7-13

bit 18ÑAlignment Control bit (ALC)

7-13

bits 19Ð21ÑWord Length Control bits

(WL0ÐWL1)

7-14

bit 22ÑSelect SC1 as Transmitter 0 Drive

Enable bit (SSC1)

7-14

bit 23Ñreserved bit

7-14

reserved bitsÑbit 17

7-13

reserved bitsÑbit 23

7-14

reserved bitsÑbits 8Ð10

7-11

CRB register

bits 0Ð1ÑSerial Output Flag bits

(OF0ÐOF1)

7-15

bit 2ÑSerial Control 0 Direction bit

(SCD0)

7-16

bit 3ÑSerial Control 1 Direction bit

(SCD1)

7-16

bit 4ÑSerial Control 2 Direction bit

(SCD2)

7-16

bit 5ÑClock Source Direction bit (SCKD)

7-16

bit 6ÑShift Direction bit (SHFD)

7-17

bits 7Ð8ÑFrame Sync Length bits

(FSL1ÐFSL0)

7-17

bit 9ÑFrame Sync Relative Timing bit

(FSR)

7-17

bit 10ÑFrame Sync Polarity bit (FSP)

7-17

bit 11ÑClock Polarity bit (CKP)

7-18

bit 12ÑAsynchronous/Synchronous bit

(SYN)

7-18

bit 13ÑESSI Mode Select bit (MOD)

7-20

bit 14ÑESSI Transmit 2 Enable bit (TE2)

7-22

bit 15ÑESSI Transmit 1 Enable bit (TE1)

7-23

bit 16ÑESSI Transmit 0 Enable bit (TE0)

7-24

bit 17ÑESSI Receive Enable bit (RE)

7-26

bit 18ÑESSI Transmit Interrupt Enable bit

(TIE)

7-26

bit 19ÑESSI Receive Interrupt Enable bit

(RIE)

7-26

bit 20ÑESSI Transmit Last Slot Interrupt

Enable bit (TLIE)

7-26

bit 21ÑESSI Receive Last Slot Interrupt Enable

bit (RLIE)

7-27

bit 22ÑESSI Transmit Exception Interrupt

Enable bit (TEIE)

7-27

bit 23ÑESSI Receive Exception Interrupt

Enable bit (REIE)

7-27

crystal input

2-8

CVR register

bits 0Ð6ÑHost Vector bits (HV0ÐHV6)

6-25

D0ÐD23

2-10

data ALU

1-8

registers

1-8

data bus

2-3

signals

2-10

Data Output bit (DO)

9-14

DC4ÐDC0 bits

7-12

DE signal

2-37

10-4

Debug Event signal (DE signal)

10-4

Debug mode

in OnCE module

10-16

DEBUG_REQUEST instruction

11-11

executing during Stop state

10-17

executing during Wait state

10-17

executing in OnCE module

10-17

Direct Memory Access (DMA)

1-15

Divide Factor (DF)

1-11

DMA

1-15

triggered by timer

9-27

DO bit

9-14

DO loop

1-10

Double Data Strobe

2-4

Double Host Request bit (HDRQ)

6-23

DRAM

1-13

2-4

DSP56300 core

1-3

1-6

DSP56300 Family Manual

1-3

1-7

DSP56303 Functional Signal Groupings

2-3

signal groupings

2-3

DSP56303 Technical Data

1-3

ENABLE_ONCE instruction

11-11

Enhanced Synchronous Serial Interface

(ESSI)

1-16

2-3

2-25

2-28

Enhanced Synchronous Serial Interface 0

2-24

Enhanced Synchronous Serial Interface 1

2-28

equates

BIU

B-13

r
e

s
c

l
e

i
c

t
o

r
,

I

Freescale Semiconductor, Inc.

For More Information On This Product,

Go to: www.freescale.com

.
.

MOTOROLA

DSP56309UM/D I-3

bus interface unit

B-13

direct memory access

B-10

DMA

B-10

enhanced serial communication interface

B-5

ESSI

B-5

exception processing

B-7

HI08

B-3

host interface

B-3

i/o port programming

B-3

interrupt

B-15

phase locked loop

B-12

PLL

B-12

SCI

B-4

serial communication interface

B-4

timer module

B-9

ESSI

2-4

after reset

7-36

asynchronous operating mode

7-40

frame sync length

7-41

frame sync polarity

7-42

frame sync selection

7-41

frame sync word length

7-41

GPIO functionality

7-43

initialization

7-36

interrupts

7-37

Network mode

7-40

Normal mode

7-40

operating mode

7-36

operating modes

7-40

Port Control Register (PCR)

7-43

Port Data Register (PDR)

7-45

Port Direction Register (PRR)

7-44

programming model

7-8

synchronous operating mode

7-40

ESSI Control Register A (CRA)

7-11

ESSI Mode Select bit (MOD)

7-20

ESSI Receive Data Register (RX)

7-33

ESSI Receive Enable bit (RE)

7-26

ESSI Receive Exception Interrupt Enable bit

(REIE)

7-27

ESSI Receive Interrupt Enable bit (RIE)

7-26

ESSI Receive Last Slot Interrupt Enable bit

(RLIE)

7-27

ESSI Receive Shift Register

7-33

ESSI Receive Slot Mask Registers (RSMA,

RSMB)

7-35

ESSI Status Register (SSISR)

7-27

ESSI Time Slot Register (TSR)

7-34

ESSI Transmit 0 Enable bit (TE0)

7-24

ESSI Transmit 1 Enable bit (TE1)

7-23

ESSI Transmit 2 Enable bit (TE2)

7-22

ESSI Transmit Data registers (TX2, TX1, TX0)

7-34

ESSI Transmit Exception Interrupt Enable bit

(TEIE)

7-27

ESSI Transmit Interrupt Enable bit (TIE)

7-26

ESSI Transmit Last Slot Interrupt Enable bit

(TLIE)

7-26

ESSI Transmit Shift Registers

7-33

ESSI Transmit Slot Mask Registers (TSMA,

TSMB)

7-34

ESSI0

2-24

ESSI0 (GPIO)

5-3

ESSI1

2-28

ESSI1 (GPIO)

5-4

EX bit

10-5

exception processing equates

B-7

Exit Command bit (EX)

10-5

expanded mode

4-6

EXTAL

2-7

EXTAL signal

2-7

external address bus

2-9

external bus control

2-9

2-11

2-12

external clock/crystal input

2-7

external data bus

2-9

external interrupt request A signal

2-14

external interrupt request B signal

2-15

external interrupt request C signal

2-15

external interrupt request D signal

2-16

external memory expansion port

2-9

EXTEST instruction

11-8

FE bit

8-15

Frame Rate Divider Control bits (DC4ÐDC0)

7-12

Frame Sync Length bits (FSL1ÐFSL0)

7-17

Frame Sync Polarity bit (FSP)

7-17

Frame Sync Relative Timing bit (FSR)

7-17

frame sync selection

ESSI

7-41

Framing Error Flag bit (FE)

8-15

frequency

operation

1-7

FSL1ÐFSL0 bits

7-17

FSP bit

7-17

FSR bit

7-17

functional groups

2-4

general purpose input/output (GPIO)

2-34

Global Data Bus

1-13

r
e

s
c

l
e

i
c

t
o

r
,

I

Freescale Semiconductor, Inc.

For More Information On This Product,

Go to: www.freescale.com

.
.

I-4

DSP56309UM/D MOTOROLA

GO Command bit (GO)

10-6

GPIO

1-15

2-4

2-34

on HI08

6-30

Timers

2-4

GPIO (ESSI0, Port C)

5-3

GPIO (ESSI1, Port D)

5-4

GPIO (HI08, Port B)

5-3

GPIO (SCI, Port E)

5-4

GPIO (Timer)

5-4

GPIO functionality

on ESSI

7-43

ground

2-3

2-6

address bus

2-6

bus control

2-7

data bus

2-7

ESSI

2-7

host interface

2-7

PLL

2-6

quiet

2-6

SCI

2-7

timer

2-7

H0ÐH7 signals

2-18

HA0 signal

2-18

HA1 signal

2-19

HA2 signal

2-19

HA8 signal

2-19

HA10 signal

2-21

HA9 signal

2-19

HA8EN bit

6-13

HA9EN bit

6-13

HAD0ÐHAD7 signals

2-18

HAEN bit

6-14

HAP bit

6-16

hardware stack

1-10

HAS/HAS

2-18

HASP bit

6-15

HBAR register

6-12

bits 0Ð7ÑBase Address bits (BA3ÐBA10)

6-12

reserved bitsÑbits 5Ð15

6-12

HCIE bit

6-10

HCP bit

6-11

HCR register

6-9

6-10

bit 0ÑHost Receive Interrupt Enable bit

(HRIE)

6-10

bit 1ÑHost Transmit Interrupt Enable bit

(HTIE)

6-10

bit 2ÑHost Command Interrupt Enable bit

(HCIE)

6-10

bits 3, 4ÑHost Flag 2 and 3 bits (HF2,

HF3)

6-10

reserved bitsÑbits 5Ð15

6-10

HCS signal

2-21

HCSEN bit

6-13

HCSP bit

6-16

HDDR register

6-17

HDDS bit

6-15

HDR register

6-17

HDRQ bit

6-23

HDS signal

2-20

HDSP bit

6-14

HEN bit

6-14

HF0 bit

6-24

HF0, HF1 bits

6-11

HF1 bit

6-24

HF2 bit

6-27

HF2, HF3 bits

6-10

HF3 bit

6-27

HGEN bit

6-13

HI08

1-16

2-3

2-4

2-16

2-18

2-19

2-21

6-3

(GPIO)

5-3

data transfer

6-31

DSP side control registers

6-8

DSP side data registers

6-8

DSP side registers after reset

6-18

DSP to host

data word

6-5

handshaking protocols

6-5

interrupts

6-5

mapping

6-4

transfer modes

6-5

external host programmerÕs model

6-20

GPIO

6-30

HI08 to DSP core interface

6-3

HI08 to host processor interface

6-4

Host Base Address Register (HBAR)

6-12

Host Control Register (HCR)

6-9

6-10

Host Data Direction Register (HDDR)

6-17

Host Data Register (HDR)

6-17

Host Port Control Register (HPCR)

6-12

Host Receive Data Register (HRX)

6-8

host side

Interface Control Register (ICR)

6-22

Interface Status Register (ISR)

6-26

Interface Vector Register (IVR)

6-28

r
e

s
c

l
e

i
c

t
o

r
,

I

Freescale Semiconductor, Inc.

For More Information On This Product,

Go to: www.freescale.com

.
.

MOTOROLA

DSP56309UM/D I-5

Receive Byte Registers (RXH, RXM,

RXL)

6-28

Transmit Byte Registers (TXH, TXM,

TXL)

6-29

host side registers after reset

6-30

Host Status Register (HSR)

6-11

host to DSP

data word

6-3

handshaking protocols

6-4

instructions

6-4

mapping

6-3

transfer modes

6-3

Host Transmit Data Register (HTX)

6-9

polling

6-31

registers

6-7

servicing interrupts

6-32

HI-Z instruction

11-10

HLEND bit

6-24

HMUX bit

6-15

Host Acknowledge Enable bit (HAEN)

6-14

Host Acknowledge Polarity bit (HAP)

6-16

host acknowledge signal (HACK/HACK

2-23

host address 10 signal (HA10)

2-21

host address 8 signal (HA8)

2-19

host address 9 signal (HA9)

2-19

host address input 0 signal (HA0)

2-18

host address input 1 signal (HA1)

2-19

host address input 2 signal (HA2)

2-19

Host Address Line 8 Enable bit (HA8EN)

6-13

Host Address Line 9 Enable bit (HA9EN)

6-13

host address signal HAD0ÐHAD7)

2-18

Host Address Strobe Polarity bit (HASP)

6-15

host address strobe signal (HAS/HAS) signal

2-18

Host Base Address Register (HBAR)

6-12

Host Chip Select Enable bit (HCSEN)

6-13

Host Chip Select Polarity bit (HCSP)

6-16

host chip select signal (HCS)

2-21

Host Command Interrupt Enable bit (HCIE)

6-10

Host Command Pending bit (HCP)

6-11

Host Control Register (HCR)

6-9

6-10

Host Data Direction Register (HDDR)

6-17

Host Data Register (HDR)

6-17

host data signal (H0ÐH7)

2-18

Host Data Strobe Polarity bit (HDSP)

6-14

host data strobe signal (HDS/HDS)

2-20

Host Dual Data Strobe bit (HDDS)

6-15

Host Enable bit (HEN)

6-14

Host Flag 0 and 1 bits (HF0, HF1)

6-11

Host Flag 0 bit (HF0)

6-24

Host Flag 1 bit (HF1)

6-24

Host Flag 2 and 3 bits (HF2, HF3)

6-10

Host Flag 2 bit (HF2)

6-27

Host Flag 3 bit (HF3)

6-27

Host GPIO Port Enable bit (HGEN)

6-13

Host Interface

1-16

2-3

2-4

2-16

2-18

2-19

2-21

6-3

Host Little Endian bit (HLEND)

6-24

Host Multiplexed Bus bit (HMUX)

6-15

host port

configuration

2-17

usage considerations

2-16

Host Port Control Register (HPCR)

6-12

host read data signal (HRD/HRD) signal

2-20

host read/write signal (HRW)

2-20

Host Receive Data Full bit (HRDF)

6-11

Host Receive Data Register (HRX)

6-8

Host Receive Interrupt Enable bit (HRIE)

6-10

Host Request

Double

2-4

Single

2-4

Host Request Enable bit (HREN)

6-14

Host Request Open Drain bit (HROD)

6-14

Host Request Polarity bit (HRP)

6-16

host request signal (HREQ/HREQ

2-22

Host Status Register (HSR)

6-11

Host Transmit Data Empty bit (HTDE)

6-11

Host Transmit Data Register (HTX)

6-9

Host Transmit Interrupt Enable bit (HTIE)

6-10

Host Vector bits (HV0ÐHV6)

6-25

host write data signal (HWR/HWR)

2-20

HPCR register

6-12

bit 0ÑHost GPIO Port Enable bit (HGEN)

6-13

bit 1ÑHost Address Line 8 bit (HA8EN)

6-13

bit 2ÑHost Address Line 9 bit (HA9EN)

6-13

bit 3ÑHost Chip Select Enable bit

(HCSEN)

6-13

bit 4ÑHost Request Enable bit (HREN)

6-14

bit 5ÑHost Acknowledge Enable bit

(HAEN)

6-14

bit 6ÑHost Enable bit (HEN)

6-14

bit 7Ñreserved bit

6-14

bit 8ÑHost Request Open Drain bit

(HROD)

6-14

bit 9ÑHost Data Strobe Polarity bit

(HDSP)

6-14

bit 10ÑHost Address Strobe Polarity bit

(HASP)

6-15

bit 11ÑHost Multiplexed Bus bit (HMUX)

6-15

bit 12ÑHost Dual Data Strobe bit (HDDS)

6-15

bit 13ÑHost Chip Select Polarity bit

(HCSP)

6-16

bit 14ÑHost Request Polarity bit (HRP)

6-16

r
e

s
c

l
e

i
c

t
o

r
,

I

Freescale Semiconductor, Inc.

For More Information On This Product,

Go to: www.freescale.com

.
.

I-6

DSP56309UM/D MOTOROLA

bit 15ÑHost Acknowledge Polarity bit

(HAP)

6-16

reserved bitÑbit 7

6-14

2-4

HRD/HRD

2-20

HRDF bit

6-11

HREN bit

6-14

HRIE bit

6-10

HROD bit

6-14

HRP bit

6-16

HRRQ/HRRQ

2-23

HRW

2-20

HRX register

6-8

HSR register

6-11

bit 0ÑHost Receive Data Full bit (HRDF)

6-11

bit 1ÑHost Transmit Data Empty bit

(HTDE)

6-11

bit 2ÑHost Command Pending bit (HCP)

6-11

bits 3, 4ÑHost Flag 0 and 1 bits (HF0,

HF1)

6-11

reserved bitsÑbits 5Ð15

6-11

HTDE bit

6-11

HTIE bit

6-10

HTRQ/HTRQ

2-22

HTX register

6-9

HV0ÐHV6 bits

6-25

HWR/HWR signal

2-20

ICR register

6-22

bit 0ÑReceive Request Enable bit (RREQ)

6-23

bit 1ÑTransmit Request Enable bit

(TREQ)

6-23

bit 2ÑDouble Host Request bit (HDRQ)

6-23

bit 3ÑHost Flag 0 bit (HF0)

6-24

bit 4ÑHost Flag 1 bit (HF1)

6-24

bit 5ÑHost Little Endian bit (HLEND)

6-24

bit 6Ñreserved bit

6-24

reserved bitÑbit 6

6-24

IDCODE instruction

11-9

IDLE bit

8-14

Idle Line Flag bit (IDLE)

8-14

Idle Line Interrupt Enable bit (ILIE)

8-11

IF0 bit

7-28

IF1 bit

7-28

ILIE bit

8-11

IME bit

10-8

instruction cache

3-3

location

3-8

instruction set

1-7

Interface Control Register (ICR)

6-22

Interface Status Register (ISR)

6-26

Interface Vector Register (IVR)

6-28

internal buses

1-13

interrupt

1-10

ESSI

7-37

priority levels

4-12

servicing on HI08

6-32

sources

4-9

interrupt and mode control

2-3

2-14

2-15

interrupt control

2-14

2-15

interrupt equates

B-15

Interrupt Mode Enable bit (IME)

10-8

Interrupt Priority Register P (IPRÑP)

4-13

interrupts

DMA equates

B-15

ending address

B-16

ESSI equates

B-16

host equates

B-16

non-maskable

B-15

request pins

B-15

SCI equates

B-16

timer equates

B-15

INV bit

9-11

Inverter bit (INV)

9-11

IPRÑP

4-13

ISR register

6-26

bit 0ÑReceive Data Register Full bit

(RXDF)

6-26

bit 1ÑTransmit Data Register Empty bit

(TXDE)

6-27

bit 2ÑTransmitter Ready bit (TRDY)

6-27

bit 3ÑHost Flag 2 bit (HF2)

6-27

bit 4ÑHost Flag 3 bit (HF3)

6-27

bit 5Ñreserved bit

6-27

bit 6Ñreserved bit

6-27

reserved bitsÑbits 5,6

6-27

IVR register

6-28

Joint Test Action Group (JTAG)

11-3

JTAG

1-11

2-35

JTAG instructions

BYPASS instruction

11-11

CLAMP instruction

11-10

DEBUG_REQUEST instruction

11-11

r
e

s
c

l
e

i
c

t
o

r
,

I

Freescale Semiconductor, Inc.

For More Information On This Product,

Go to: www.freescale.com

.
.

MOTOROLA

DSP56309UM/D I-7

ENABLE_ONCE instruction

11-11

EXTEST instruction

11-8

HI-Z instruction

11-10

IDCODE instruction

11-9

SAMPLE/PRELOAD instruction

11-9

JTAG/OnCE Interface signals

Debug Event signal (DE signal)

10-4

keeper, weak

2-24

2-25

2-26

2-27

2-28

2-29

2-30

2-31

2-32

2-33

2-34

2-35

LA register

1-10

LC register

1-10

logic

1-7

Loop Address register (LA)

1-10

Loop Counter register (LC)

1-10

MAC

1-9

Manual Conventions

1-5

MBO bit

10-8

MBS0ÐMBS1 bits

10-12

memory

bootstrap ROM

3-7

enabling breakpoints

10-18

external expansion port

1-13

maps

3-9

on-chip

1-12

program RAM

3-6

X data RAM

3-6

Y data RAM

3-7

Memory Breakpoint Occurrence bit (MBO)

10-8

Memory Breakpoint Select bits

(MBS0ÐMBS1)

10-12

memory configuration

3-7

memory spaces

3-7

RAM

3-8

MF bits

4-18

MIPS

1-7

MOD bit

7-20

MODA/IRQA

2-14

MODB/IRQB

2-15

MODC/IRQC

2-15

MODD/IRQD

2-16

mode control

2-14

2-15

Mode Select bit (MOD)

7-20

mode select A signal

2-14

mode select B signal

2-15

mode select C signal

2-15

mode select D signal

2-16

modulo adder

1-9

multiplexed bus

2-4

Multiplication Factor bits (MF)

4-18

multiplier-accumulator (MAC)

1-8

1-9

non-maskable interrupt

2-8

2-9

non-multiplexed bus

2-4

OBCR register

10-12

bits 0Ð1ÑMemory Breakpoint Select bits

(MBS0ÐMBS1)

10-12

bits 2Ð3ÑBreakpoint 0 Read/Write Select bits

(RW00ÐRW01)

10-12

bits 4Ð5ÑBreakpoint 0 Condition Code Select

bits (CC00ÐCC01)

10-13

bits 6Ð7ÑBreakpoint 1 Read/Write Select bits

(RW10ÐRW11)

10-13

bits 8Ð9ÑBreakpoint 1 Condition Code Select

bits (CC10ÐCC11)

10-14

bits 10Ð11ÑBreakpoint 0 and 1 Event Select

bits (BT0ÐBT1)

10-14

reserved bitsÑbits 12Ð15

10-15

OCR register

bits 0Ð4ÑRegister Select bits (RS0ÐRS4)

10-5

bit 5ÑExit Command bit (EX)

10-5

bit 6ÑGO Command bit (GO)

10-6

bit 7ÑRead/Write Command bit (R/W)

10-6

ODEC

10-8

OF0ÐOF1 bits

7-15

offset adder

1-9

OGDBR register

10-20

OMAC0 comparator

10-11

OMAC1 comparator

10-11

OMAL register

10-11

OMBC counter

10-14

OMLR0 register

10-11

OMLR1 register

10-11

OMR register

1-11

OnCE

1-4

commands

10-23

controller

10-4

trace logic

10-15

OnCE Breakpoint Control Register (OBCR)

10-12

r
e

s
c

l
e

i
c

t
o

r
,

I

Freescale Semiconductor, Inc.

For More Information On This Product,

Go to: www.freescale.com

.
.

I-8

DSP56309UM/D MOTOROLA

OnCE Command Register (OCR)

10-5

OnCE Decoder (ODEC)

10-8

OnCE GDB Register (OGDBR)

10-20

OnCE Memory Address Comparator 0

(OMAC0)

10-11

OnCE Memory Address Comparator 1

(OMAC1)

10-11

OnCE Memory Address Latch register

(OMAL)

10-11

OnCE Memory Breakpoint Counter (OMBC)

10-14

OnCE Memory Limit Register 0 (OMLR0)

10-11

OnCE Memory Limit Register 1 (OMLR1)

10-11

OnCE module

1-12

10-3

checking for Debug mode

10-24

displaying a specified register

10-26

displaying X data memory

10-26

interaction with JTAG port

10-29

polling the JTAG Instruction Shift

10-24

reading the Trace buffer

10-25

returning to Normal mode

10-28

saving pipeline information

10-25

OnCE PAB Register for Decode Register

(OPABDR)

10-20

OnCE PAB Register for Execute (OPABEX)

10-20

OnCE PAB Register for Fetch Register

(OPABFR)

10-20

OnCE PIL Register (OPILR)

10-19

OnCE Program Data Bus Register (OPDBR)

10-19

OnCE Status and Control Register (OSCR)

10-8

OnCE Trace Counter (OTC)

10-16

OnCE/JTAG

2-4

debug event signal (DE)

2-37

test clock signal (TCK)

2-35

test data input signal (TDI)

2-35

test data output signal (TDO)

2-36

test mode select signal (TMS)

2-36

OnCE/JTAG port

2-3

On-Chip Emulation (OnCE) module

1-12

On-Chip Emulation module

10-3

on-chip memory

1-12

program

3-6

X data RAM

3-6

Y data RAM

3-7

OPABDR register

10-20

OPABEX register

10-20

OPABFR register

10-20

OPDBR register

10-19

Operating

4-3

operating mode

4-3

bootstrap from byte-wide external memory

4-7

bootstrap thorugh HI08 (68302/68360)

4-9

bootstrap through HI08 (ISA)

4-8

bootstrap through HI08 (multiplexed)

4-9

bootstrap through HI08 (non-multiplexed)

4-8

bootstrap through SCI

4-7

ESSI

7-36

7-40

expanded

4-6

expanded mode

4-6

Operating Mode Register (OMR)

1-11

operating modes

4-3

OPILR register

10-19

OR bit

8-14

OSCR register

10-8

bit 0ÑTrace Mode Enable bit (TME)

10-8

bit 1ÑInterrupt Mode Enable bit (IME)

10-8

bit 2ÑSoftware Debug Occurrence bit

(SWO)

10-8

bit 3ÑMemory Breakpoint Occurrence bit

(MBO)

10-8

bit 4ÑTrace Occurrence bit (TO)

10-9

bit 5Ñreserved bit

10-9

reserved bitsÑbits 8Ð23

10-9

OTC counter

10-16

Overrun Error Flag bit (OR)

8-14

PAB

1-13

PAG

1-10

Parity Error bit (PE)

8-14

PB0ÐPB7 signals

2-18

PB10 signal

2-19

PB11 signal

2-20

PB12 signal

2-20

PB13 signal

2-21

PB14 signal

2-22

PB15 signal

2-23

PB8 signal

2-18

PB9 signal

2-19

PC register

1-10

PC0 signal

2-24

PC0-PC20 bits

9-9

PC1 signal

2-25

PC2 signal

2-25

PC3 signal

2-26

PC4 signal

2-26

PC5 signal

2-27

r
e

s
c

l
e

i
c

t
o

r
,

I

Freescale Semiconductor, Inc.

For More Information On This Product,

Go to: www.freescale.com

.
.

MOTOROLA

DSP56309UM/D I-9

PCAP signal

2-8

PCRC register

7-43

PCRD register

7-43

PCRE register

8-27

PCTL register

bits 0Ð11ÑMultiplication Factor bits

(MF0ÐMF11)

4-18

bit 16ÑXTAL Disable bit (XTLD)

4-18

bits 20Ð23ÑPreDivider Factor bits

(PD0ÐPD3)

4-18

PCU

1-10

PD bits

4-18

PD0 signal

2-28

PD1 signal

2-28

PD2 signal

2-29

PD3 signal

2-30

PD4 signal

2-30

PD5 signal

2-31

PDB

1-13

PDC

1-10

PDRC register

7-45

PDRD register

7-45

PDRE register

8-28

PE bit

8-14

PE0 signal

2-32

PE1 signal

2-32

PE2 signal

2-33

Peripheral I/O Expansion Bus

1-13

PIC

1-10

PINIT/NMI

2-9

PLL initial

2-8

PL0-PL20 bits

9-7

PL21-PL22 bits

9-7

PLL

1-11

2-3

PLL capacitor signal

2-8

PLL initialize signal

2-9

PLL signals

2-7

PM0ÐPM7 bits

7-11

Port A

2-3

2-9

Port B

2-3

2-4

2-19

5-3

port B 10 signal (PB10)

2-19

port B 11 signal (PB11)

2-20

port B 12 signal (PB12)

2-20

port B 13 signal (PB13)

2-21

port B 14 signal (PB14)

2-22

port B 15 signal (PB15)

2-23

port B 8 signal (PB8)

2-18

port B 9 signal (PB9)

2-19

port B signal (PB0ÐPB7)

2-18

Port C

2-3

2-4

2-24

2-25

2-28

5-3

port C 0 signal (PC0)

2-24

port C 1 signal (PC1)

2-25

port C 2 signal (PC2)

2-25

port C 3 signal (PC3)

2-26

port C 4 signal (PC4)

2-26

port C 5 signal (PC5)

2-27

Port C Control Register (PCRC)

7-43

Port C Data Register (PDRC)

7-45

Port C Direction Register (PRRC)

7-44

Port D

2-3

2-4

2-28

5-4

port D 0 signal (PD0)

2-28

port D 1 signal (PD1)

2-28

port D 2 signal (PD2)

2-29

port D 3 signal (PD3)

2-30

port D 4 signal (PD4)

2-30

port D 5 signal (PD5)

2-31

Port D Control Register (PCRD)

7-43

Port D Data Register (PDRD)

7-45

Port D Direction Register (PRRD)

7-44

Port E

2-3

2-32

5-4

port E 0 signal (PE0)

2-32

port E 1 signal (PE1)

2-32

port E 2 signal (PE2)

2-33

Port E Control Register (PCRE)

8-27

Port E Data Register (PDRE)

8-28

Port E Direction Register (PRRE)

8-27

power

2-3

2-5

ground

2-6

low

1-7

management

1-7

standby modes

1-7

power input

address bus

2-5

bus control

2-5

data bus

2-5

ESSI

2-6

host interface

2-5

PLL

2-5

quiet

2-5

SCI

2-6

timer

2-6

PreDivider Factor bits (PD)

4-18

Prescale Modulus Select bits (PM0ÐPM7)

7-11

Prescaler Counter

9-7

Prescaler Counter Value bits (PC0-PC20)

9-9

Prescaler Load Value bits (PL0-PL20)

9-7

Prescaler Range bit (PSR)

7-11

Prescaler Source bits (PL21-PL22)

9-7

Program Address Bus (PAB)

1-13

Program Address Generator (PAG)

1-10

Program Control Unit (PCU)

1-10

Program Counter register (PC)

1-10

r
e

s
c

l
e

i
c

t
o

r
,

I

Freescale Semiconductor, Inc.

For More Information On This Product,

Go to: www.freescale.com

.
.

I-10

DSP56309UM/D MOTOROLA

Program Data Bus (PDB)

1-13

Program Decode Controller (PDC)

1-10

Program Interrupt Controller (PIC)

1-10

Program Memory Expansion Bus

1-13

program RAM

3-6

Programming Sheets Ñ See Appendix B
PRRC register

7-44

PRRD register

7-44

PRRE register

8-27

PSR bit

7-11

R/W bit

10-6

R8 bit

8-15

RAS0ÐRAS3 signals

2-10

RCM bit

8-17

RD signal

2-10

RDF bit

7-30

RDRF bit

8-14

RE bit

7-26

8-10

read enable signal (RD)

2-10

Read/Write Command bit (R/W)

10-6

Receive Byte Registers (RXH, RXM, RXL)

6-28

Receive Clock Mode Source bit (RCM)

8-17

Receive Data Register (RX)

7-33

Receive Data Register Full bit (RDF)

7-30

Receive Data Register Full bit (RDRF)

8-14

Receive Data Register Full bit (RXDF)

6-26

Receive Data signal (RXD)

8-4

Receive Exception Interrupt Enable bit (REIE)

7-27

Receive Frame Sync Flag bit (RFS)

7-28

receive host request signal (HRRQ/HRRQ)

2-23

Receive Interrupt Enable bit (RIE)

7-26

8-11

Receive Last Slot Interrupt Enable bit (RLIE)

7-27

Receive Request Enable bit (RREQ)

6-23

Receive Shift Register

7-33

Receive Slot Mask Registers (RSMA, RSMB)

7-35

Received Bit 8 Address bit (R8)

8-15

Receiver Enable bit (RE)

8-10

Receiver Overrun Error Flag bit (ROE)

7-29

Receiver Wakeup Enable bit (SBK)

8-9

10-5

REIE bit

7-27

8-13

reserved bits

in CRA register

7-11

7-13

7-14

in HBAR register

bits 5Ð15

6-12

in HCR register

bits 5Ð15

6-10

in HPC register

bit 7

6-14

in HSR register

bits 5Ð15

6-11

in ICR register

bit 6

6-24

in ISR register

bit 5

6-27

bit 6

6-27

in OBCR register

bits 12Ð15

10-15

in OSCR register

bit 5, bits 8Ð23

10-9

in TCSR register

bits 3, 10, 14, 16Ð19, 22, 23

9-15

in TPCR

9-9

in TPLR

9-8

RESET

2-14

reset signal

2-14

reverse-carry adder

1-9

RFS bit

7-28

RIE bit

7-26

8-11

RLIE bit

7-27

ROE bit

7-29

ROM

bootstrap

3-7

row address strobe signals RAS0ÐRAS3

2-10

RREQ bit

6-23

RS0ÐRS4 bits

10-5

RSMA, RSMB registers

7-35

RW00ÐRW01 bits

10-12

RW10ÐRW11 bits

10-13

RWU bit

8-9

RX register

7-33

RXD

2-32

RXD signal

8-4

RXDF bit

6-26

RXH, RXM, RXL registers

6-28

SAMPLE/PRELOAD instruction

11-9

SBK bit

8-9

SC register

1-11

SC0 signal

7-6

7-8

SC00 signal

2-24

SC01 signal

2-25

SC02 signal

2-25

r
e

s
c

l
e

i
c

t
o

r
,

I

Freescale Semiconductor, Inc.

For More Information On This Product,

Go to: www.freescale.com

.
.

MOTOROLA

DSP56309UM/D I-11

SC1 signal

7-7

SC10

2-28

SC11

2-28

SC12

2-29

SCCR register

8-15

bits 0Ð11ÑClock Divider bits

(CD0ÐCD11)

8-16

bit 12ÑClock Out Divider bit (COD)

8-16

bit 13ÑSCI Clock Prescaler bit (SCP)

8-17

bit 14ÑReceive Clock Mode Source bit

(RCM)

8-17

bit 15ÑTransmit Clock Source bit (TCM)

8-18

SCD0 bit

7-16

SCD1 bit

7-16

SCD2 bit

7-16

SCI

1-16

2-4

2-32

exceptions

8-26

Idle Line

8-26

Receive Data

8-26

Receive Data with Exception Status

8-26

Timer

8-26

Transmit Data

8-26

GPIO functionality

8-27

initialization

8-24

example

8-25

operating mode

Asynchronous

8-21

Synchronous

8-21

operating modes

Asynchronous

8-21

programming model

8-4

reset

8-22

state after reset

8-23

transmission priority

preamble, break, and data

8-26

SCI (GPIO)

5-4

SCI Clock Control Register (SCCR)

8-15

SCI Clock Polarity bit (SCKP)

8-12

SCI Clock Prescaler bit (SCP)

8-17

SCI exceptions

Receive Data

8-26

SCI pins

RXD, TXD, SCLK

8-3

SCI Receive Register (SRX)

8-19

SCI Receive with Exception Interrupt bit

(REIE)

8-13

SCI Serial Clock signal (SCLK)

8-4

SCI Shift Direction bit (SSFTD)

8-9

SCI Status Register (SSR)

8-13

SCI Transmit Register (STX)

STX register

8-20

SCK signal

7-5

SCK0

2-26

SCK1 signal

2-30

SCKD bit

7-16

SCKP bit

8-12

SCLK signal

2-33

8-4

SCP bit

8-17

SCR register

bits 0-2ÑWord Select bits (WDS0-WDS2)

8-8

bit 3ÑSCI Shift Direction bit (SSFTD)

8-9

bit 4ÑSend Break bit (SBK)

8-9

bit 5ÑWakeup Mode Select bit (WAKE)

8-9

bit 6ÑReceiver Wakeup Enable bit (RWU)

8-9

bit 7ÑWired-OR Mode Select bit

(WOMS)

8-10

bit 8ÑReceiver Enable bit (RE)

8-10

bit 9ÑTransmitter Enable bit (TE)

8-10

bit 10ÑIdle Line Interrupt Enable bit

(ILIE)

8-11

bit 11ÑReceive Interrupt Enable bit (RIE)

8-11

bit 12ÑTransmit Interrupt Enable bit

(TIE)

8-12

bit 13ÑTimer Interrupt Enable bit (TMIE)

8-12

bit 14ÑTimer Interrupt Rate bit (STIR)

8-12

bit 15ÑSCI Clock Polarity bit (SCKP)

8-12

bit 16ÑSCI Receive with Exception Interrupt

Enable bit (REIE)

8-13

Select SC1 as Transmitter 0 Drive Enable bit

(SSC1)

7-14

Send Break bit (SBK)

8-9

Serial Clock signal (SCK)

7-5

serial clock signal (SCK0)

2-26

serial clock signal (SCK1)

2-30

serial clock signal (SCLK)

2-33

Serial Communication Interface (SCI)

2-32

Serial Communications Interface (SCI)

1-16

2-3

8-3

Serial Control 0 Direction bit (SCD0)

7-16

serial control 0 signal (SC0)

7-6

7-8

serial control 0 signal (SC00)

2-24

serial control 0 signal (SC10)

2-28

Serial Control 1 Direction bit (SCD1)

7-16

serial control 1 signal (SC01)

2-25

serial control 1 signal (SC1)

7-7

serial control 1 signal (SC11)

2-28

Serial Control 2 Direction bit (SCD2)

7-16

serial control 2 signal (SC02)

2-25

serial control 2 signal (SC12)

2-29

Serial Input Flag 0 bit (IF0)

7-28

Serial Input Flag 1 bit (IF1)

7-28

Serial Output Flag bits (OF0ÐOF1)

7-15

r
e

s
c

l
e

i
c

t
o

r
,

I

Freescale Semiconductor, Inc.

For More Information On This Product,

Go to: www.freescale.com

.
.

I-12

DSP56309UM/D MOTOROLA

serial protocol

in OnCE module

10-22

serial receive data signal (RXD)

2-32

Serial Receive Data signal (SRD)

7-4

serial receive data signal (SRD0)

2-26

serial receive data signal (SRD1)

2-30

Serial Transmit Data signal (STD)

7-4

serial transmit data signal (STD0)

2-27

serial transmit data signal (STD1)

2-31

serial transmit data signal (TXD)

2-32

SHFD bit

7-17

Shift Direction bit (SHFD)

7-17

signal groupings

2-3

signals

2-3

functional grouping

2-4

Single Data Strobe

2-4

Sixteen-bit Compatibility

3-3

Size register (SZ)

1-10

Software Debug Occurrence bit (SWO)

10-8

1-11

SR register

1-10

SRAM

interfacing

1-13

SRD signal

7-4

SRD0

2-26

SRD1

2-30

SRX

read as SRXL, SRXM, SRXH

8-19

SRX register

8-19

1-11

SSC1 bit

7-14

SSFTD bit

8-9

SSISR register

7-27

bit 0ÑSerial Input Flag 0 bit (IF0)

7-28

bit 1ÑSerial Input Flag 1 bit (IF1)

7-28

bit 2ÑTransmit Frame Sync Flag bit (TFS)

7-28

bit 3ÑReceive Frame Sync Flag bit (RFS)

7-28

bit 4ÑTransmitter Underrun Error Flag bit

(TUE)

7-29

bit 5ÑReceiver Overrun Error Flag bit

(ROE)

7-29

bit 6ÑTransmit Data Register Empty bit

(TDE)

7-29

bit 7ÑReceive Data Register Full bit

(RDF)

7-30

SSR register

8-13

bit 1ÑTransmitter Empty bit (TRNE)

8-13

bit 2ÑReceive Data Register Full bit

(RDRF)

8-14

bit 2ÑTransmit Data Register Empty bit

(TDRE)

8-13

bit 3ÑIdle Line Flag bit (IDLE)

8-14

bit 4ÑOverrun Error Flag bit (OR)

8-14

bit 5ÑParity Error bit (PE)

8-14

bit 6ÑFraming Error Flag bit (FE)

8-15

bit 7ÑReceived Bit 8 Address bit (R8)

8-15

Stack Counter register (SC)

1-11

Stack Pointer (SP)

1-11

standby

mode

Stop

1-7

Wait

1-7

Status Register (SR)

1-10

STD signal

7-4

STD0

2-27

STD1

2-31

STIR bit

8-12

stop

standby mode

1-7

STX register

read as STXL, STXM. STXH, and STXA

8-20

SWO bit

10-8

SYN bit

7-18

System Stack (SS)

1-11

SZ register

1-10

TA signal

2-11

TAP

1-11

TAP controller

11-6

TC0ÐTC3 bits

9-10

TCIE

9-10

TCK pin

11-5

TCK signal

2-35

TCM bit

8-18

TCR register

9-16

TCSR register

9-9

bit 0ÑTimer Enable bit (TE)

9-9

bits 4Ð7ÑTimer Control bits (TC0ÐTC3)

9-10

bit 8ÑInverter bit (INV)

9-11

bit 13ÑData Output bit (DO)

9-14

reserved bitsÑbits 3, 10, 14, 16Ð19, 22, 23

9-15

TDE bit

7-29

TDI pin

11-5

TDI signal

2-35

TDO signal

2-36

TDRE bit

8-13

r
e

s
c

l
e

i
c

t
o

r
,

I

Freescale Semiconductor, Inc.

For More Information On This Product,

Go to: www.freescale.com

.
.

MOTOROLA

DSP56309UM/D I-13

TE bit

8-10

9-9

TE0 bit

7-24

TE1 bit

7-23

TE2 bit

7-22

TEIE bit

7-27

Test Access Port (TAP)

1-11

11-3

Test Clock Input pin (TCK)

11-5

Test Data Input pin (TDI)

11-5

Test Mode Select Input pin (TMS)

11-5

Test Reset Input pin (TRST)

11-5

TFS bit

7-28

TIE bit

7-26

8-12

Time Slot Register (TSR)

7-34

timer

special cases

9-27

Timer (GPIO)

5-4

timer 0 signal (TIO0)

2-34

timer 1 signal (TIO1)

2-34

timer 2 signal (TIO2)

2-35

Timer Control bits (TC0ÐTC3)

9-10

Timer Control/Status Register (TCSR)

9-9

Timer Count Register (TCR)

9-16

Timer Enable bit (TE)

9-9

Timer Interrupt Enable bit (TMIE)

8-12

Timer Interrupt Rate bit (STIR)

8-12

timer mode

mode 0ÑGPIO

9-17

mode 1Ñtimer pulse

9-18

mode 2Ñtimer toggle

9-19

mode 3Ñtimer event counter

9-20

mode 4Ñmeasurement input width

9-21

mode 5Ñmeasurement input period

9-22

mode 6Ñmeasurement capture

9-23

mode 7Ñpulse width modulation

9-24

mode 8Ñreserved

9-25

mode 9Ñwatchdog pulse

9-25

mode 10Ñmeasurement toggle

9-26

modes 11Ð15Ñreserved

9-27

Timer module

1-17

2-34

architecture

9-3

programming model

9-5

timer block diagram

9-4

Timer Prescaler Count Register (TPCR)

9-8

Timer Prescaler Load Register (TPLR)

9-7

Timers

2-3

2-4

TLIE bit

7-26

TME bit

10-8

TMIE bit

8-12

TMS pin

11-5

TMS signal

2-36

TO bit

10-9

TOIE

9-9

TPCR register

9-8

bits 0-20ÑPrescaler Counter Value bits

(PC0-PC20)

9-9

bit 21-23Ñreserved bits

9-9

reserved bitsÑbits 21-23

9-9

TPLR register

9-7

bits 0-20ÑPrescaler Load Value bits

(PL0-PL20)

9-7

bits 21-22ÑPrescaler Source bits

(PL0-PL20)

9-7

bit 23Ñreserved bit

9-8

reserved bitÑbit 23

9-8

Trace buffer

10-21

Trace mode

enabling

10-18

in OnCE module

10-15

Trace Mode Enable bit (TME)

10-8

Trace Occurrence bit (TO)

10-9

transfer acknowledge signal

2-11

Transmit 0 Enable bit (TE0)

7-24

Transmit 1 Enable bit (TE1)

7-23

Transmit 2 Enable bit (TE2)

7-22

Transmit Byte Registers (TXH, TXM, TXL)

6-29

Transmit Clock Source bit (TCM)

8-18

Transmit Data Register Empty bit (TDE)

7-29

Transmit Data Register Empty bit (TDRE)

8-13

Transmit Data Register Empty bit (TXDE)

6-27

Transmit Data signal (TXD)

8-4

Transmit Exception Interrupt Enable bit

(TEIE)

7-27

Transmit Frame Sync Flag bit (TFS)

7-28

transmit host request signal (HTRQ/HTRQ)

2-22

Transmit Interrupt Enable bit (TIE)

7-26

8-12

Transmit Last Slot Interrupt Enable bit (TLIE)

7-26

Transmit Request Enable bit (TREQ)

6-23

Transmit Shift Registers

7-33

Transmit Slot Mask Registers (TSMA, TSMB)

7-34

Transmitter Empty bit (TRNE)

8-13

Transmitter Enable bit (TE)

8-10

Transmitter Ready bit (TRDY)

6-27

Transmitter Underrun Error Flag bit (TUE)

7-29

TRDY bit

6-27

TREQ bit

6-23

triple timer module

1-17

TRNE bit

8-13

TRST pin

11-5

TSMA, TSMB registers

7-34

TSR register

7-34

TUE bit

7-29

TX2, TX1, TX0 registers

7-34

r
e

s
c

l
e

i
c

t
o

r
,

I

Freescale Semiconductor, Inc.

For More Information On This Product,

Go to: www.freescale.com

.
.

Ð­Ð»ÐµÐºÑ‚Ñ€Ð¾Ð½Ð½Ñ‹Ð¹ ÐºÐ¾Ð¼Ð¿Ð¾Ð½ÐµÐ½Ñ‚: DSP56309

Document Outline

ÐÐ»ÐµÐºÑ‚Ñ€Ð¾Ð½Ð½Ñ‹Ð¹ ÐºÐ¾Ð¼Ð¿Ð¾Ð½ÐµÐ½Ñ‚: DSP56309