DSP56F801/D
Rev. 13.0, 02/2004
Motorola, Inc., 2004. All rights reserved.
56F801
Technical Data
56F801 16-bit Hybrid Controller
Up to 30 MIPS operation at 60MHz core
frequency
Up to 40 MIPS operation at 80MHz core
frequency
DSP and MCU functionality in a unified,
C-efficient architecture
MCU-friendly instruction set supports both
DSP and controller functions: MAC, bit
manipulation unit, 14 addressing modes
Hardware DO and REP loops
6-channel PWM Module
Two 4-channel, 12-bit ADCs
Serial Communications Interface (SCI)
8K
16-bit words Program Flash
1K
16-bit words Program RAM
2K
16-bit words Data Flash
1K
16-bit words Data RAM
2K
16-bit words Boot Flash
Serial Peripheral Interface (SPI)
General Purpose Quad Timer
JTAG/OnCE
TM
port for debugging
On-chip relaxation oscillator
11 shared GPIO
48-pin LQFP Package
Figure 1. 56F801 Block Diagram
JTAG/
OnCE
Port
Digital Reg
Analog Reg
Low Voltage
Supervisor
Program Controller
and
Hardware Looping Unit
Data ALU
16 x 16 + 36
36-Bit MAC
Three 16-bit Input Registers
Two 36-bit Accumulators
Address
Generation
Unit
Bit
Manipulation
Unit
PLL
Clock Gen
or Optional
Internal
Relaxation Osc.
16-Bit
56800
Core
PAB
PDB
XDB2
CGDB
XAB1
XAB2
GPIOB3/XTAL
GPIOB2/EXTAL
INTERRUPT
CONTROLS
IPBB
CONTROLS
IPBus Bridge
(IPBB)
MODULE CONTROLS
ADDRESS BUS [8:0]
DATA BUS [15:0]
COP RESET
RESET
IRQA
Application-
Specific
Memory &
Peripherals
Interrupt
Controller
Program Memory
8188 x 16 Flash
1024 x 16 SRAM
Boot Flash
2048 x 16 Flash
Data Memory
2048 x 16 Flash
1024 x 16 SRAM
COP/
Watchdog
SPI
or
GPIO
SCI0
or
GPIO
Quad Timer D
or GPIO
Quad Timer C
A/D1
A/D2
ADC
4
2
3
4
4
6
PWM Outputs
Fault Input
PWMA
16
16
VCAPC
V
DD
V
SS
V
DDA
V
SSA
6
2
4
5*
VREF
*
includes TCS pin which is reserved for factory use and is tied to
VSS
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2
56F801 Technical Data
Part 1 Overview
1.1 56F801 Features
1.1.1
Digital Signal Processing Core
Efficient 16-bit 56800 family hybrid controller engine with dual Harvard architecture
As many as 40 Million Instructions Per Second (MIPS) at 80MHz core frequency
Single-cycle 16
16-bit parallel Multiplier-Accumulator (MAC)
Two 36-bit accumulators including extension bits
16-bit bidirectional barrel shifter
Parallel instruction set with unique DSP addressing modes
Hardware DO and REP loops
Three internal address buses and one external address bus
Four internal data buses and one external data bus
Instruction set supports both DSP and controller functions
Controller style addressing modes and instructions for compact code
Efficient C compiler and local variable support
Software subroutine and interrupt stack with depth limited only by memory
JTAG/OnCE debug programming interface
1.1.2
Memory
Harvard architecture permits as many as three simultaneous accesses to Program and Data memory
On-chip memory including a low-cost, high-volume Flash solution
-- 8K
16 bit words of Program Flash
-- 1K
16-bit words of Program RAM
-- 2K
16-bit words of Data Flash
-- 1K
16-bit words of Data RAM
-- 2K
16-bit words of Boot Flash
Programmable Boot Flash supports customized boot code and field upgrades of stored code
through a variety of interfaces (JTAG, SPI)
1.1.3
Peripheral Circuits for 56F801
Pulse Width Modulator (PWM) with six PWM outputs, two Fault inputs, fault-tolerant design with
deadtime insertion; supports both center- and edge-aligned modes
Two 12-bit, Analog-to-Digital Converters (ADCs), which support two simultaneous conversions
with two 4-multiplexed inputs; ADC and PWM modules can be synchronized
General Purpose Quad Timer: Timer D with three pins (or three additional GPIO lines)
Serial Communication Interface (SCI) with two pins (or two additional GPIO lines)
Serial Peripheral Interface (SPI) with configurable four-pin port (or four additional GPIO lines)
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56F801 Description
56F801 Technical Data
3
Eleven multiplexed General Purpose I/O (GPIO) pins
Computer-Operating Properly (COP) watchdog timer
One dedicated external interrupt pin
External reset pin for hardware reset
JTAG/On-Chip Emulation (OnCETM) for unobtrusive, processor speed-independent debugging
Software-programmable, Phase Locked Loop-based frequency synthesizer for the hybrid controller
core clock
Oscillator flexibility between either an external crystal oscillator or an on-chip relaxation oscillator
for lower system cost and two additional GPIO lines
1.1.4
Energy Information
Fabricated in high-density CMOS with 5V-tolerant, TTL-compatible digital inputs
Uses a single 3.3V power supply
On-chip regulators for digital and analog circuitry to lower cost and reduce noise
Wait and Stop modes available
1.2 56F801 Description
The 56F801 is a member of the 56800 core-based family of hybrid controllers. It combines, on a single
chip, the processing power of a DSP and the functionality of a microcontroller with a flexible set of
peripherals to create an extremely cost-effective solution. Because of its low cost, configuration flexibility,
and compact program code, the 56F801 is well-suited for many applications. The 56F801 includes many
peripherals that are especially useful for applications such as motion control, smart appliances, steppers,
encoders, tachometers, limit switches, power supply and control, automotive control, engine management,
noise suppression, remote utility metering, and industrial control for power, lighting, and automation.
The 56800 core is based on a Harvard-style architecture consisting of three execution units operating in
parallel, allowing as many as six operations per instruction cycle. The microprocessor-style programming
model and optimized instruction set allow straightforward generation of efficient, compact code for both
DSP and MCU applications. The instruction set is also highly efficient for C compilers to enable rapid
development of optimized control applications.
The 56F801 supports program execution from either internal or external memories. Two data operands can
be accessed from the on-chip Data RAM per instruction cycle. The 56F801 also provides one external
dedicated interrupt lines and up to 11 General Purpose Input/Output (GPIO) lines, depending on peripheral
configuration.
The 56F801 controller includes 8K words (16-bit) of Program Flash and 2K words of Data Flash (each
programmable through the JTAG port) with 1K words of both Program and Data RAM. A total of 2K words
of Boot Flash is incorporated for easy customer-inclusion of field-programmable software routines that can
be used to program the main Program and Data Flash memory areas. Both Program and Data Flash
memories can be independently bulk erased or erased in page sizes of 256 words. The Boot Flash memory
can also be either bulk or page erased.
A key application-specific feature of the 56F801 is the inclusion of a Pulse Width Modulator (PWM)
module. This modules incorporates six complementary, individually programmable PWM signal outputs to
enhance motor control functionality. Complementary operation permits programmable dead-time insertion,
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4
56F801 Technical Data
and separate top and bottom output polarity control. The up-counter value is programmable to support a
continuously variable PWM frequency. Both edge- and center-aligned synchronous pulse width control (0%
to 100% modulation) are supported. The device is capable of controlling most motor types: ACIM (AC
Induction Motors), both BDC and BLDC (Brush and Brushless DC motors), SRM and VRM (Switched and
Variable Reluctance Motors), and stepper motors. The PWMs incorporate fault protection and cycle-by-
cycle current limiting with sufficient output drive capability to directly drive standard opto-isolators. A
"smoke-inhibit", write-once protection feature for key parameters is also included. The PWM is double-
buffered and includes interrupt control to permit integral reload rates to be programmable from 1 to 16. The
PWM modules provide a reference output to synchronize the Analog-to-Digital Converters.
The 56F801 incorporates an 8 input, 12-bit Analog-to-Digital Converter (ADC). A full set of standard
programmable peripherals is provided that include a Serial Communications Interface (SCI), a Serial
Peripheral Interface (SPI), and two Quad Timers. Any of these interfaces can be used as General-Purpose
Input/Outputs (GPIO) if that function is not required. An on-chip relaxation oscillator provides flexibility
in the choice of either on-chip or externally supplied frequency reference for chip timing operations.
Application code is used to select which source is to be used.
1.3 State of the Art Development Environment
Processor Expert
TM
(PE) provides a Rapid Application Design (RAD) tool that combines easy-to-
use component-based software application creation with an expert knowledge system.
The Code Warrior Integrated Development Environment is a sophisticated tool for code navigation,
compiling, and debugging. A complete set of evaluation modules (EVMs) and development system
cards will support concurrent engineering. Together, PE, Code Warrior and EVMs create a
complete, scalable tools solution for easy, fast, and efficient development.
1.4 Product Documentation
The four documents listed in
Table 1
are required for a complete description and proper design with the
56F801. Documentation is available from local Motorola distributors, Motorola semiconductor sales
offices, Motorola Literature Distribution Centers, or online at www.motorola.com/semiconductors.
Table 1. 56F801 Chip Documentation
Topic
Description
Order Number
DSP56800
Family Manual
Detailed description of the 56800 family architecture, and
16-bit core processor and the instruction set
DSP56800FM/D
DSP56F801/803/805/807
User's Manual
Detailed description of memory, peripherals, and interfaces
of the 56F801, 56F803, 56F805, and 56F807
DSP56F801-7UM/D
56F801
Technical Data Sheet
Electrical and timing specifications, pin descriptions, and
package descriptions (this document)
DSP56F801/D
56F801
Product Brief
Summary description and block diagram of the 56F801 core,
memory, peripherals and interfaces
DSP56F801PB/D
DSP56F801
Errata
Details any chip issues that might be present
DSP56F801E/D
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Data Sheet Conventions
56F801 Technical Data
5
1.5 Data Sheet Conventions
This data sheet uses the following conventions:
Part 2 Signal/Connection Descriptions
2.1 Introduction
The input and output signals of the 56F801 are organized into functional groups, as shown in
Table 2
and
as illustrated in
Figure 2
. In
Table 3
through
Table 13
, each table row describes the signal or signals
present on a pin.
OVERBAR
This is used to indicate a signal that is active when pulled low. For example, the RESET pin is
active when low.
"asserted"
A high true (active high) signal is high or a low true (active low) signal is low.
"deasserted"
A high true (active high) signal is low or a low true (active low) signal is high.
Examples:
Signal/Symbol
Logic State
Signal State
Voltage
1
1.
Values for V
IL
, V
OL
, V
IH
, and V
OH
are defined by individual product specifications.
PIN
True
Asserted
V
IL
/V
OL
PIN
False
Deasserted
V
IH
/V
OH
PIN
True
Asserted
V
IH
/V
OH
PIN
False
Deasserted
V
IL
/V
OL
Table 2. Functional Group Pin Allocations
Functional Group
Number of
Pins
Detailed
Description
Power (V
DD
or V
DDA
)
5
Table 3
Ground (V
SS
or V
SSA
)
6
Table 4
Supply Capacitors
2
Table 5
PLL and Clock
2
Table 6
Interrupt and Program Control
2
Table 7
Pulse Width Modulator (PWM) Port
7
Table 8
Serial Peripheral Interface (SPI) Port
1
1.
Alternately, GPIO pins
4
Table 9
Serial Communications Interface (SCI) Port
1
2
Table 10
Analog-to-Digital Converter (ADC) Port
9
Table 11
Quad Timer Module Port
3
Table 12
JTAG/On-Chip Emulation (OnCE)
6
Table 13
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6
56F801 Technical Data
Figure 2. 56F801 Signals Identified by Functional Group
1
1. Alternate pin functionality is shown in parenthesis.
56F801
Power Port
Ground Port
Power Port
Ground Port
PLL and Clock
or GPIO
SCI0 Port
or GPIO
V
DD
V
SS
V
DDA
V
SSA
VCAPC
EXTAL (GPIOB2)
XTAL (GPIOB3)
TCK
TMS
TDI
TDO
TRST
DE
JTAG/OnCE
Port
PWMA0-5
FAULTA0
SCLK (GPIOB4)
MOSI (GPIOB5)
MISO (GPIOB6)
SS (GPIOB7)
TXD0 (GPIOB0)
RXD0 (GPIOB1)
ANA0-7
VREF
TD0-2 (GPIOA0-2)
IRQA
RESET
Quad
Timer D
or GPIO
ADCA Port
Other
Supply
Port
4
5*
1
1
2
1
1
1
1
1
1
1
1
Interrupt/
Program
Control
6
1
1
1
1
1
1
1
8
1
3
1
1
SPI Port
or GPIO
*
includes TCS pin which is reserved for factory use and is tied to
VSS
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Power and Ground Signals
56F801 Technical Data
7
2.2 Power and Ground Signals
2.3 Clock and Phase Locked Loop Signals
Table 3. Power Inputs
No. of Pins
Signal Name
Signal Description
4
V
DD
Power--These pins provide power to the internal structures of the chip, and should
all be attached to V
DD.
1
V
DDA
Analog Power--This pin is a dedicated power pin for the analog portion of the chip
and should be connected to a low noise 3.3V supply.
Table 4. Grounds
No. of Pins
Signal Name
Signal Description
4
V
SS
GND--These pins provide grounding for the internal structures of the chip,
and should all be attached to V
SS.
1
V
SSA
Analog Ground--This pin supplies an analog ground.
1
TCS
TCS--This Schmitt pin is reserved for factory use and must be tied to V
SS
for
normal use. In block diagrams, this pin is considered an additional V
SS.
Table 5. Supply Capacitors and VPP
No. of
Pins
Signal
Name
Signal
Type
State
During Reset
Signal Description
2
VCAPC Supply
Supply
VCAPC--Connect each pin to a 2.2
For greater bypass capacitor
in order to bypass the core logic voltage regulator (required for
proper chip operation). For more information, refer to
Section 5.2
.
Table 6. PLL and Clock
No. of
Pins
Signal
Name
Signal
Type
State
During Reset
Signal Description
1
EXTAL
GPIOB2
Input
Input/
Output
Input
Input
External Crystal Oscillator Input--This input should be connected
to an 8MHz external crystal or ceramic resonator. For more
information, please refer to
Section 3.5
.
Port B GPIO--This multiplexed pin is a General Purpose I/O (GPIO)
pin that can be programmed as an input or output pin. This I/O can be
utilized when using the on-chip relaxation oscillator so the EXTAL pin
is not needed.
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8
56F801 Technical Data
2.4 Interrupt and Program Control Signals
2.5 Pulse Width Modulator (PWM) Signals
1
XTAL
GPIOB3
Output
Input/
Output
Chip-
driven
Input
Crystal Oscillator Output--This output should be connected to an
8MHz external crystal or ceramic resonator. For more information,
please refer to
Section 3.5
.
This pin can also be connected to an external clock source. For more
information, please refer to
Section 3.5.3
.
Port B GPIO--This multiplexed pin is a General Purpose I/O (GPIO)
pin that can be programmed as an input or output pin. This I/O can be
utilized when using the on-chip relaxation oscillator so the XTAL pin is
not needed.
Table 7. Interrupt and Program Control Signals
No. of
Pins
Signal
Name
Signal
Type
State
During
Reset
Signal Description
1
IRQA
Input
(Schmitt)
Input
External Interrupt Request A--The IRQA input is a
synchronized external interrupt request that indicates that an
external device is requesting service. It can be programmed to be
level-sensitive or negative-edge- triggered.
1
RESET
Input
(Schmitt)
Input
Reset--This input is a direct hardware reset on the processor.
When RESET is asserted low, the hybrid controller is initialized
and placed in the Reset state. A Schmitt trigger input is used for
noise immunity. When the RESET pin is deasserted, the initial
chip operating mode is latched from the EXTBOOT pin. The
internal reset signal will be deasserted synchronous with the
internal clocks, after a fixed number of internal clocks.
To ensure complete hardware reset, RESET and TRST should be
asserted together. The only exception occurs in a debugging
environment when a hardware device reset is required and it is
necessary not to reset the OnCE/JTAG module. In this case,
assert RESET, but do not assert TRST.
Table 8. Pulse Width Modulator (PWMA) Signals
No. of
Pins
Signal
Name
Signal
Type
State During
Reset
Signal Description
6
PWMA0-5
Output
Tri-stated
PWMA0-5-- These are six PWMA output pins.
1
FAULTA0
Input
(Schmitt)
Input
FAULTA0-- This fault input pin is used for disabling selected
PWMA outputs in cases where fault conditions originate off-
chip.
Table 6. PLL and Clock (Continued)
No. of
Pins
Signal
Name
Signal
Type
State
During Reset
Signal Description
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Serial Peripheral Interface (SPI) Signals
56F801 Technical Data
9
2.6 Serial Peripheral Interface (SPI) Signals
Table 9. Serial Peripheral Interface (SPI) Signals
No. of
Pins
Signal
Name
Signal
Type
State
During
Reset
Signal Description
1
MISO
GPIOB6
Input/
Output
Input/
Output
Input
Input
SPI Master In/Slave Out (MISO)--This serial data pin is an
input to a master device and an output from a slave device.
The MISO line of a slave device is placed in the high-
impedance state if the slave device is not selected.
Port E GPIO--This pin is a General Purpose I/O (GPIO) pin
that can be individually programmed as input or output pin.
After reset, the default state is MISO.
1
MOSI
GPIOB5
Input/
Output
Input/
Output
Input
Input
SPI Master Out/Slave In (MOSI)--This serial data pin is an
output from a master device and an input to a slave device.
The master device places data on the MOSI line a half-cycle
before the clock edge that the slave device uses to latch the
data.
Port E GPIO--This pin is a General Purpose I/O (GPIO) pin
that can be individually programmed as input or output pin.
After reset, the default state is MOSI.
1
SCLK
GPIOB4
Input/
Output
Input/
Output
Input
Input
SPI Serial Clock--In master mode, this pin serves as an
output, clocking slaved listeners. In slave mode, this pin
serves as the data clock input.
Port E GPIO--This pin is a General Purpose I/O (GPIO) pin
that can be individually programmed as an input or output pin.
After reset, the default state is SCLK.
1
SS
GPIOB7
Input
Input/
Output
Input
Input
SPI Slave Select--In master mode, this pin is used to
arbitrate multiple masters. In slave mode, this pin is used to
select the slave.
Port E GPIO--This pin is a General Purpose I/O (GPIO) pin
that can be individually programmed as an input or output pin.
After reset, the default state is SS.
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10
56F801 Technical Data
2.7 Serial Communications Interface (SCI) Signals
2.8 Analog-to-Digital Converter (ADC) Signals
2.9 Quad Timer Module Signals
Table 10. Serial Communications Interface (SCI0) Signals
No. of
Pins
Signal
Name
Signal
Type
State During
Reset
Signal Description
1
TXD0
GPIOB0
Output
Input/
Output
Input
Input
Transmit Data (TXD0)--SCI0 transmit data output
Port B GPIO--This pin is a General Purpose I/O (GPIO) pin
that can be individually programmed as an input or output
pin.
After reset, the default state is SCI output.
1
RXD0
GPIOB1
Input
Input/
Output
Input
Input
Receive Data (RXD0)--SCI0 receive data input
Port B GPIO--This pin is a General Purpose I/O (GPIO) pin
that can be individually programmed as an input or output
pin.
After reset, the default state is SCI input.
Table 11. Analog to Digital Converter Signals
No. of
Pins
Signal
Name
Signal
Type
State During
Reset
Signal Description
4
ANA0-3
Input
Input
ANA0-3--Analog inputs to ADC, channel 1
4
ANA4-7
Input
Input
ANA4-7--Analog inputs to ADC, channel 2
1
VREF
Input
Input
VREF--Analog reference voltage for ADC. Must be set to
V
DDA
-0.3V for optimal performance.
Table 12. Quad Timer Module Signals
No. of
Pins
Signal
Name
Signal
Type
State During
Reset
Signal Description
3
TD0-2
GPIOA0-2
Input/
Output
Input/
Output
Input
Input
TD0-2--Timer D Channel 0-2
Port A GPIO--This pin is a General Purpose I/O (GPIO) pin
that can be individually programmed as an input or output
pin.
After reset, the default state is the quad timer input.
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JTAG/OnCE
56F801 Technical Data
11
2.10 JTAG/OnCE
Part 3 Specifications
3.1 General Characteristics
The 56F801 is fabricated in high-density CMOS with 5-volt tolerant TTL-compatible digital inputs. The
term "5-volt tolerant" refers to the capability of an I/O pin, built on a 3.3V compatible process technology,
to withstand a voltage up to 5.5V without damaging the device. Many systems have a mixture of devices
designed for 3.3V and 5V power supplies. In such systems, a bus may carry both 3.3V and 5V- compatible
I/O voltage levels (a standard 3.3V I/O is designed to receive a maximum voltage of 3.3V
10% during
normal operation without causing damage). This 5V-tolerant capability therefore offers the power savings
of 3.3V I/O levels while being able to receive 5V levels without being damaged.
Absolute maximum ratings given in
Table 14
are stress ratings only, and functional operation at the
maximum is not guaranteed. Stress beyond these ratings may affect device reliability or cause permanent
damage to the device.
The 56F801 DC and AC electrical specifications are preliminary and are from design simulations. These
specifications may not be fully tested or guaranteed at this early stage of the product life cycle. Finalized
specifications will be published after complete characterization and device qualifications have been
completed.
Table 13. JTAG/On-Chip Emulation (OnCE) Signals
No. of
Pins
Signal
Name
Signal
Type
State During
Reset
Signal Description
1
TCK
Input
(Schmitt)
Input, pulled
low internally
Test Clock Input--This input pin provides a gated clock to
synchronize the test logic and shift serial data to the JTAG/OnCE port.
The pin is connected internally to a pull-down resistor.
1
TMS
Input
(Schmitt)
Input, pulled
high internally
Test Mode Select Input--This input pin is used to sequence the JTAG
TAP controller's state machine. It is sampled on the rising edge of TCK
and has an on-chip pull-up resistor.
1
TDI
Input
(Schmitt)
Input, pulled
high internally
Test Data Input--This input pin provides a serial input data stream to
the JTAG/OnCE port. It is sampled on the rising edge of TCK and has
an on-chip pull-up resistor.
1
TDO
Output
Tri-stated
Test Data Output--This tri-statable output pin provides a serial output
data stream from the JTAG/OnCE port. It is driven in the Shift-IR and
Shift-DR controller states, and changes on the falling edge of TCK.
1
TRST
Input
(Schmitt)
Input, pulled
high internally
Test Reset--As an input, a low signal on this pin provides a reset
signal to the JTAG TAP controller. To ensure complete hardware reset,
TRST should be asserted whenever RESET is asserted. The only
exception occurs in a debugging environment when a hardware device
reset is required and it is necessary not to reset the OnCE/JTAG
module. In this case, assert RESET, but do not assert TRST.
1
DE
Output
Output
Debug Event--DE provides a low pulse on recognized debug events.
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12
56F801 Technical Data
CAUTION
This device contains protective circuitry to guard against
damage due to high static voltage or electrical fields.
However, normal precautions are advised to avoid
application of any voltages higher than maximum rated
voltages to this high-impedance circuit. Reliability of
operation is enhanced if unused inputs are tied to an
appropriate voltage level.
Table 14. Absolute Maximum Ratings
Characteristic
Symbol
Min
Max
Unit
Supply voltage
V
DD
V
SS
0.3
V
SS
+ 4.0
V
All other input voltages, excluding Analog inputs
V
IN
V
SS
0.3
V
SS
+ 5.5V
V
Analog inputs ANA0-7 and VREF
V
IN
V
SSA
0.3
V
DDA
+ 0.3
V
Analog inputs EXTAL, XTAL
V
IN
V
SSA
0.3
V
SSA
+ 3.0
V
Current drain per pin excluding V
DD
, V
SS
, & PWM ouputs
I
--
10
mA
Table 15. Recommended Operating Conditions
Characteristic
Symbol
Min
Typ
Max
Unit
Supply voltage, digital
V
DD
3.0
3.3
3.6
V
Supply Voltage, analog
V
DDA
3.0
3.3
3.6
V
ADC reference voltage
VREF
2.7
V
DDA
V
Ambient operating temperature
T
A
40
85
C
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General Characteristics
56F801 Technical Data
13
Notes:
1.
Theta-JA determined on 2s2p test boards is frequently lower than would be observed in an application.
Determined on 2s2p thermal test board.
2.
Junction to ambient thermal resistance, Theta-JA (
R
JA
) was simulated to be equivalent to the
JEDEC specification JESD51-2 in a horizontal configuration in natural convection. Theta-JA was
also simulated on a thermal test board with two internal planes (2s2p where s is the number of signal
layers and p is the number of planes) per JESD51-6 and JESD51-7. The correct name for Theta-JA
for forced convection or with the non-single layer boards is Theta-JMA.
3.
Junction to case thermal resistance, Theta-JC (R
JC
), was simulated to be equivalent to the measured
values using the cold plate technique with the cold plate temperature used as the "case" temperature.
The basic cold plate measurement technique is described by MIL-STD 883D, Method 1012.1. This
is the correct thermal metric to use to calculate thermal performance when the package is being used
with a heat sink.
4.
Thermal Characterization Parameter, Psi-JT (
JT
), is the "resistance" from junction to reference
point thermocouple on top center of case as defined in JESD51-2.
JT
is a useful value to use to
estimate junction temperature in steady state customer environments.
5.
Junction temperature is a function of on-chip power dissipation, package thermal resistance,
mounting site (board) temperature, ambient temperature, air flow, power dissipation of other
components on the board, and board thermal resistance.
6.
See Section 5.1 from more details on thermal design considerations.
Table 16. Thermal Characteristics
6
Characteristic
Comments
Symbol
Value
Unit
Notes
48-pin LQFP
Junction to ambient
Natural convection
R
JA
50.6
C/W
2
Junction to ambient (@1m/sec)
R
JMA
47.4
C/W
2
Junction to ambient
Natural convection
Four layer board (2s2p)
R
JMA
(2s2p)
39.1
C/W
1,2
Junction to ambient (@1m/sec)
Four layer board (2s2p)
R
JMA
37.9
C/W
1,2
Junction to case
R
JC
17.3
C/W
3
Junction to center of case
JT
1.2
C/W
4, 5
I/O pin power dissipation
P
I/O
User Determined
W
Power dissipation
P
D
P
D
= (I
DD
x V
DD
+ P
I/O
)
W
Junction to center of case
P
DMAX
(TJ - TA) /
JA
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14
56F801 Technical Data
3.2 DC Electrical Characteristics
Table 17. DC Electrical Characteristics
Operating Conditions:
V
SS
= V
SSA
= 0 V, V
DD
= V
DDA
= 3.03.6V, T
A
= 40
to +85
C, C
L
50pF
Characteristic
Symbol
Min
Typ
Max
Unit
Input high voltage (XTAL/EXTAL)
V
IHC
2.25
--
2.75
V
Input low voltage (XTAL/EXTAL)
V
ILC
0
--
0.5
V
Input high voltage [GPIOB(2:3)]
1
V
IH[GPIOB(2:3)]
2.0
--
3.6
V
Input low voltage [GPIOB(2:3)]
1
V
IL[GPIOB(2:3)]
-0.3
--
0.8
V
Input high voltage (Schmitt trigger inputs)
2
V
IHS
2.2
--
5.5
V
Input low voltage (Schmitt trigger inputs)
2
V
ILS
-0.3
--
0.8
V
Input high voltage (all other digital inputs)
V
IH
2.0
--
5.5
V
Input low voltage (all other digital inputs)
V
IL
-0.3
--
0.8
V
Input current high (pullup/pulldown resistors disabled, V
IN
=V
DD
)
I
IH
-1
--
1
A
Input current low (pullup/pulldown resistors disabled, V
IN
=V
SS
)
I
IL
-1
--
1
A
Input current high (with pullup resistor, V
IN
=V
DD
)
I
IHPU
-1
--
1
A
Input current low (with pullup resistor, V
IN
=V
SS
)
I
ILPU
-210
--
-50
A
Input current high (with pulldown resistor, V
IN
=V
DD
)
I
IHPD
20
--
180
A
Input current low (with pulldown resistor, V
IN
=V
SS
)
I
ILPD
-1
--
1
A
Nominal pullup or pulldown resistor value
R
PU
, R
PD
30
K
Output tri-state current low
I
OZL
-10
--
10
A
Output tri-state current high
I
OZH
-10
--
10
A
Input current high (analog inputs, V
IN
=V
DDA
)
3
I
IHA
-15
--
15
A
Input current low (analog inputs, V
IN
=V
SSA
)
3
I
ILA
-15
--
15
A
Output High Voltage (at I
OH
)
V
OH
V
DD
0.7
--
--
V
Output Low Voltage (at I
OL
)
V
OL
--
--
0.4
V
Output source current
I
OH
4
--
--
mA
Output sink current
I
OL
4
--
--
mA
PWM pin output source current
4
I
OHP
10
--
--
mA
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DC Electrical Characteristics
56F801 Technical Data
15
PWM pin output sink current
5
I
OLP
16
--
--
mA
Input capacitance
C
IN
--
8
--
pF
Output capacitance
C
OUT
--
12
--
pF
V
DD
supply current
I
DDT
6
Run
7
(80MHz operation)
--
120
130
mA
Run
7
(60MHz operation)
--
102
111
mA
Wait
8
--
96
102
mA
Stop
--
62
70
mA
Low Voltage Interrupt, external power supply
9
V
EIO
2.4
2.7
3.0
V
Low Voltage Interrupt, internal power supply
10
V
EIC
2.0
2.2
2.4
V
Power on Reset
11
V
POR
--
1.7
2.0
V
1.
Since the GPIOB[2:3] signals are shared with the XTAL/EXTAL function, these inputs are not 5.5 volt tolerant.
2.
Schmitt Trigger inputs are: FAULTA0, IRQA, RESET, TCS, TCK, TMS, TDI, and TRST.
3.
Analog inputs are: ANA[0:7], XTAL and EXTAL. Specification assumes ADC is not sampling.
4.
PWM pin output source current measured with 50% duty cycle.
5.
PWM pin output sink current measured with 50% duty cycle.
6.
I
DDT
= I
DD
+ I
DDA
(Total supply current for V
DD
+ V
DDA
)
7.
Run (operating) I
DD
measured using 8MHz clock source. All inputs 0.2V from rail; outputs unloaded. All ports
configured as inputs; measured with all modules enabled.
8.
Wait I
DD
measured using external square wave clock source (f
osc
= 8MHz) into XTAL; all inputs 0.2V from rail; no DC
loads; less than 50pF on all outputs. C
L
= 20pF on EXTAL; all ports configured as inputs; EXTAL capacitance linearly affects
wait I
DD
; measured with PLL enabled.
9.
This low voltage interrupt monitors the V
DDA
external power supply. V
DDA
is generally connected to the same potential
as V
DD
via separate traces. If V
DDA
drops below V
EIO
, an interrupt is generated. Functionality of the device is guaranteed
under transient conditions when V
DDA
>V
EIO
(between the minimum specified V
DD
and the point when the V
EIO
interrupt is
generated).
10. This low voltage interrupt monitors the internally regulated core power supply. If the output from the internal voltage is
regulator drops below V
EIC
, an interrupt is generated. Since the core logic supply is internally regulated, this interrupt will not
be generated unless the external power supply drops below the minimum specified value (3.0V).
11. Power
on reset occurs whenever the internally regulated 2.5V digital supply drops below 1.5V typical. While power is
ramping up, this signal remains active for as long as the internal 2.5V is below 1.5V typical no matter how long the ramp up
rate is. The internally regulated voltage is typically 100 mV less than V
DD
during ramp up until 2.5V is reached, at which time
it self regulates.
Table 17. DC Electrical Characteristics (Continued)
Operating Conditions:
V
SS
= V
SSA
= 0 V, V
DD
= V
DDA
= 3.03.6V, T
A
= 40
to +85
C, C
L
50pF
Characteristic
Symbol
Min
Typ
Max
Unit
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16
56F801 Technical Data
Figure 3. Maximum Run IDD vs. Frequency (see Note
7.
in
Table 17
)
3.3 AC Electrical Characteristics
Timing waveforms in
Section 3.3
are tested using the V
IL
and V
IH
levels specified in the DC Characteristics
table. In
Figure 4
the levels of V
IH
and V
IL
for an input signal are shown.
Figure 4. Input Signal Measurement References
Figure 5
shows the definitions of the following signal states:
Active state, when a bus or signal is driven, and enters a low impedance state.
Tri-stated, when a bus or signal is placed in a high impedance state.
Data Valid state, when a signal level has reached V
OL
or V
OH.
Data Invalid state, when a signal level is in transition between V
OL
and V
OH.
0
40
80
120
160
10
20
30
40
50
60
70
80
Freq. (MHz)
I
DD (mA)
IDD Digital
IDD Analog
IDD Total
V
IH
V
IL
Fall Time
Input Signal
Note: The midpoint is V
IL
+ (V
IH
V
IL
)/2.
Midpoint1
Low
High
90%
50%
10%
Rise Time
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Flash Memory Characteristics
56F801 Technical Data
17
Figure 5. Signal States
3.4 Flash Memory Characteristics
Table 18. Flash Memory Truth Table
Mode
XE
1
1.
X address enable, all rows are disabled when XE = 0
YE
2
2.
Y address enable, YMUX is disabled when YE = 0
SE
3
3.
Sense amplifier enable
OE
4
4.
Output enable, tri-state Flash data out bus when OE = 0
PROG
5
5.
Defines program cycle
ERASE
6
6.
Defines erase cycle
MAS1
7
7.
Defines mass erase cycle, erase whole block
NVSTR
8
8.
Defines non-volatile store cycle
Standby
L
L
L
L
L
L
L
L
Read
H
H
H
H
L
L
L
L
Word Program
H
H
L
L
H
L
L
H
Page Erase
H
L
L
L
L
H
L
H
Mass Erase
H
L
L
L
L
H
H
H
Table 19. IFREN Truth Table
Mode
IFREN = 1
IFREN = 0
Read
Read information block
Read main memory block
Word program
Program information block
Program main memory block
Page erase
Erase information block
Erase main memory block
Mass erase
Erase both block
Erase main memory block
Data Invalid State
Data1
Data2 Valid
Data
Tri-stated
Data3 Valid
Data2
Data3
Data1 Valid
Data Active
Data Active
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18
56F801 Technical Data
Table 20. Flash Timing Parameters
Operating Conditions:
V
SS
= V
SSA
= 0 V, V
DD
= V
DDA
= 3.03.6V, T
A
= 40
to +85
C, C
L
50pF
Characteristic
Symbol
Min Typ
Max
Unit
Figure
Program time
T
prog*
20
us
Figure 6
Erase time
T
erase*
20
ms
Figure 7
Mass erase time
T
me*
100
ms
Figure 8
Endurance
1
1.
One cycle is equal to an erase program and read.
E
CYC
10,000
20,000
cycles
Data Retention
1
@ 5000 cycles
D
RET
10
30
years
The following parameters should only be used in the Manual Word Programming Mode
PROG/ERASE to NVSTR set
up time
T
nvs*
5
us
Figure 6
,
Figure 7
,
Figure 8
NVSTR hold time
T
nvh*
5
us
Figure 6
,
Figure 7
NVSTR hold time (mass erase)
T
nvh1*
100
us
Figure 8
NVSTR to program set up time
T
pgs*
10
us
Figure 6
Recovery time
T
rcv*
1
us
Figure 6
,
Figure 7
,
Figure 8
Cumulative program
HV period
2
2.
Thv is the cumulative high voltage programming time to the same row before next erase. The same address cannot
be programmed twice before next erase.
T
hv
3
ms
Figure 6
Program hold time
3
3.
Parameters are guaranteed by design in smart programming mode and must be one cycle or greater.
*The Flash interface unit provides registers for the control of these parameters.
T
pgh
Figure 6
Address/data set up time
3
T
ads
Figure 6
Address/data hold time
3
T
adh
Figure 6
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Flash Memory Characteristics
56F801 Technical Data
19
Figure 6. Flash Program Cycle
Figure 7. Flash Erase Cycle
XADR
YADR
YE
DIN
PROG
NVSTR
Tnvs
Tpgs
Tadh
Tprog
Tads
Tpgh
Tnvh
Trcv
Thv
IFREN
XE
XADR
YE=SE=OE=MAS1=0
ERASE
NVSTR
Tnvs
Tnvh
Trcv
Terase
IFREN
XE
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56F801 Technical Data
Figure 8. Flash Mass Erase Cycle
3.5 External Clock Operation
The 56F801 device clock is derived from either 1) an internal crystal oscillator circuit working in
conjunction with an external crystal, 2) an external frequency source, or 3) an on-chip relaxation oscillator.
To generate a reference frequency using the internal crystal oscillator circuit, a reference crystal external to
the chip must be connected between the EXTAL and XTAL pins. Paragrahs
3.5.1
and
3.5.4
describe these
methods of clocking. Whichever type of clock derivation is used provides a reference signal to a phase-
locked loop (PLL) within the 56F801. In turn, the PLL generates a master reference frequency that
determines the speed at which chip operations occur.
Application code can be set to change the frequency source between the relaxation oscillator and crystal
oscillator or external source, and power down the relaxation oscillator if desired. Selection of which clock
is used is determined by setting the PRECS bit in the PLLCR (phase-locked loop control register) word (bit
2). If the bit is set to 1, the external crystal oscillator circuit is selected. If the bit is set to 0, the internal
relaxation oscillator is selected, and this is the default value of the bit when power is first applied.
3.5.1
Crystal Oscillator
The internal oscillator is also designed to interface with a parallel-resonant crystal resonator in the frequency
range specified for the external crystal in
Table 23
.
Figure 9
shows a recommended crystal oscillator
circuit. Follow the crystal supplier's recommendations when selecting a crystal, since crystal parameters
determine the component values required to provide maximum stability and reliable start-up. The crystal
and associated components should be mounted as close as possible to the EXTAL and XTAL pins to
minimize output distortion and start-up stabilization time. The internal 56F80x oscillator circuitry is
designed to have no external load capacitors present. As shown in
Figure 10
no external load capacitors
should be used.
XADR
YE=SE=OE=0
ERASE
NVSTR
Tnvs
Tnvh1
Trcv
Tme
MAS1
IFREN
XE
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External Clock Operation
56F801 Technical Data
21
The 56F80x components internally are modeled as a parallel resonant oscillator circuit to provide a
capacitive load on each of the oscillator pins (XTAL and EXTAL) of 10pF to 13pF over temperature and
process variations. Using a typical value of internal capacitance on these pins of 12pF and a value of 3pF as
a typical circuit board trace capacitance the parallel load capacitance presented to the crystal is 9pF as
determined by the following equation:
This is the value load capacitance that should be used when selecting a crystal and determining the actual
frequency of operation of the crystal oscillator circuit.
Figure 9. External Crystal Oscillator Circuit
3.5.2
Ceramic Resonator
It is also possible to drive the internal oscillator with a ceramic resonator, assuming the overall system
design can tolerate the reduced signal integrity. In
Figure 10
, a typical ceramic resonator circuit is shown.
Refer to supplier's recommendations when selecting a ceramic resonator and associated components. The
resonator and components should be mounted as close as possible to the EXTAL and XTAL pins. The
internal 56F80x oscillator circuitry is designed to have no external load capacitors present. As shown in
Figure 9
no external load capacitors should be used.
Figure 10. Connecting a Ceramic Resonator
Note: Motorola recommends only two terminal ceramic resonators vs. three terminal
resonators (which contain an internal bypass capacitor to ground).
3.5.3
External Clock Source
The recommended method of connecting an external clock is given in
Figure 11
. The external clock
source is connected to XTAL and the EXTAL pin is grounded.
CL =
CL1 * CL2
CL1 + CL2
+ Cs =
+ 3 = 6 + 3 = 9pF
12 * 12
12 + 12
Recommended External Crystal
Parameters:
R
z
= 1 to 3 M
f
c
= 8MHz (optimized for 8MHz)
EXTAL XTAL
R
z
f
c
Recommended Ceramic Resonator
Parameters:
R
z
= 1 to 3 M
f
c
= 8MHz (optimized for 8MHz)
EXTAL XTAL
R
z
f
c
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22
56F801 Technical Data
Figure 11. Connecting an External Clock Signal
Figure 12. External Clock Timing
3.5.4
Use of On-Chip Relaxation Oscillator
An internal relaxation oscillator can supply the reference frequency when an external frequency source or
crystal are not used. During a 56F801 boot or reset sequence, the relaxation oscillator is enabled by default,
and the PRECS bit in the PLLCR word is set to 0 (
Section 3.5
). If an external oscillator is connected, the
relaxation oscillator can be deselected instead by setting the PRECS bit in the PLLCR to 1. When this
occurs, the PRECSS bit in the PLLSR (prescaler clock select status register) data word also sets to 1. If a
changeover between internal and external oscillators is required at startup, internal device circuits
compensate for any asynchronous transitions between the two clock signals so that no glitches occur in the
resulting master clock to the chip. When changing clocks, the user must ensure that the clock source is not
switched until the desired clock is enabled and stable.
To compensate for variances in the device manufacturing process, the accuracy of the relaxation oscillator
can be incrementally adjusted to within
0.
25% of 8MHz by trimming an internal capacitor. Bits 0-7 of the
IOSCTL (internal oscillator control) word allow the user to set in an additional offset (trim) to this preset
value to increase or decrease capacitance. The default value of this trim is 128 units, making the power-up
default capacitor size 432 units. Each unit added or deleted changes the output frequency by about 0.2%,
allowing incremental adjustment until the desired frequency accuracy is achieved.
Table 21. External Clock Operation Timing Requirements
3
Operating Conditions:
V
SS
= V
SSA
= 0 V, V
DD
= V
DDA
= 3.03.6 V, T
A
= 40
to +85
C
Characteristic
Symbol
Min
Typ
Max
Unit
Frequency of operation (external clock driver)
1
1.
See
Figure 11
for details on using the recommended connection of an external clock driver.
f
osc
0
--
80
2
2.
May not exceed 60MHz for the DSP56F801FA60 device.
3.
The high or low pulse width must be no smaller than 6.25ns or the chip will not function.
4.
Parameters listed are guaranteed by design.
MHz
Clock Pulse Width
3, 4
t
PW
6.25
--
--
ns
56F801
XTAL
EXTAL
External Clock
V
SS
External
Clock
V
IH
V
IL
Note: The midpoint is V
IL
+ (V
IH
V
IL
)/2.
90%
50%
10%
90%
50%
10%
t
PW
t
PW
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External Clock Operation
56F801 Technical Data
23
Figure 13. Typical Relaxation Oscillator Frequency vs. Temperature
(Trimmed to 8MHz @ 25
o
C)
Table 22. Relaxation Oscillator Characteristics
Operating Conditions:
V
SS
= V
SSA
= 0 V, V
DD
= V
DDA
= 3.03.6 V, T
A
= 40
to +85
C
Characteristic
Symbol
Min
Typ
Max
Unit
Frequency Accuracy
1
1.
Over full temperature range.
f
--
+2
+5
%
Frequency Drift over Temp
f/
t
--
+0.1
--
%/
o
C
Frequency Drift over Supply
f/
V
--
0.1
--
%/V
Trim Accuracy
f
T
--
+0.25
--
%
8.0
7.8
8.1
8.2
7.7
7.9
7.6
75
55
-40
35
-25
15
-5
85
Temperature (
o
C)
Ou
tpu
t
Fre
que
nc
y
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24
56F801 Technical Data
Figure 14. Typical Relaxation Oscillator Frequency vs. Trim Value @ 25
o
C
3.5.5
Phase Locked Loop Timing
Table 23. PLL Timing
Operating Conditions:
V
SS
= V
SSA
= 0 V, V
DD
= V
DDA
= 3.03.6 V, T
A
= 40
to +85
C
Characteristic
Symbol
Min
Typ
Max
Unit
External reference crystal frequency for the PLL
1
1.
An externally supplied reference clock should be as free as possible from any phase jitter for the PLL to work
correctly. The PLL is optimized for 8MHz input crystal.
2.
ZCLK may not exceed 80MHz. For additional information on ZCLK and
f
out
/2,
please refer to the OCCS chapter
in the User Manual. ZCLK = f
op
3.
Will not exceed 60MHz for the DSP56F801FA60 device.
4.
This is the minimum time required after the PLL setup is changed to ensure reliable operation.
f
osc
4
8
10
MHz
PLL output frequency
2
f
out
/2
40
--
80
3
MHz
PLL stabilization time
4
0
o
to +85
o
C
t
plls
--
10
--
ms
PLL stabilization time
4
-40
o
to 0
o
C
t
plls
--
100
200
ms
0
10
20
30 40 50
60 70 80
90 A0 B0 C0 D0 E0
F0
5
6
7
8
9
10
11
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Reset, Stop, Wait, Mode Select, and Interrupt Timing
56F801 Technical Data
25
3.6 Reset, Stop, Wait, Mode Select, and Interrupt Timing
Table 24. Reset, Stop, Wait, Mode Select, and Interrupt Timing
1, 5
Operating Conditions:
V
SS
= V
SSA
= 0 V, V
DD
= V
DDA
= 3.03.6 V, T
A
= 40
to +85
C, C
L
50pF
1.
In the formulas, T = clock cycle. For an operating frequency of 80MHz, T = 12.5ns.
Characteristic
Symbol
Min
Max
Unit
See
RESET Assertion to Address, Data and Control
Signals High Impedance
t
RAZ
--
21
ns
Figure 15
Minimum RESET Assertion Duration
2
OMR Bit 6 = 0
OMR Bit 6 = 1
2.
Circuit stabilization delay is required during reset when using an external clock or crystal oscillator in two cases:
After power-on reset
When recovering from Stop state
t
RA
275,000T
128T
--
--
ns
ns
Figure 15
RESET De-assertion to First External Address
Output
t
RDA
33T
34T
ns
Figure 15
Edge-sensitive Interrupt Request Width
t
IRW
1.5T
--
ns
Figure 16
IRQA, IRQB Assertion to External Data Memory
Access Out Valid, caused by first instruction
execution in the interrupt service routine
t
IDM
15T
--
ns
Figure 17
IRQA, IRQB Assertion to General Purpose Output
Valid, caused by first instruction execution in the
interrupt service routine
t
IG
16T
--
ns
Figure 17
IRQA Low to First Valid Interrupt Vector Address
Out recovery from Wait State
3
3.
The minimum is specified for the duration of an edge-sensitive IRQA interrupt required to recover from the Stop state.
This is not the minimum required so that the IRQA interrupt is accepted.
t
IRI
13T
--
ns
Figure 18
IRQA Width Assertion to Recover from Stop State
4
4.
The interrupt instruction fetch is visible on the pins only in Mode 3.
5.
Parameters listed are guaranteed by design.
t
IW
2T
--
ns
Figure 19
Delay from IRQA Assertion to Fetch of first
instruction (exiting Stop)
OMR Bit 6 = 0
OMR Bit 6 = 1
t
IF
--
--
275,000T
12T
ns
ns
Figure 19
Duration for Level Sensitive IRQA Assertion to
Cause the Fetch of First IRQA Interrupt Instruction
(exiting Stop)
OMR Bit 6 = 0
OMR Bit 6 = 1
t
IRQ
--
--
275,000T
12T
ns
ns
Figure 20
Delay from Level Sensitive IRQA Assertion to First
Interrupt Vector Address Out Valid (exiting Stop)
OMR Bit 6 = 0
OMR Bit 6 = 1
t
II
--
--
275,000T
12T
ns
ns
Figure 20
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26
56F801 Technical Data
Figure 15. Asynchronous Reset Timing
Figure 16. External Interrupt Timing (Negative-Edge-Sensitive)
Figure 17. External Level-Sensitive Interrupt Timing
First Fetch
A0A15,
D0D15
PS, DS,
RD, WR
RESET
First Fetch
t
RAZ
t
RA
t
RDA
IRQA,
IRQB
t
IRW
A0A15,
PS
,
DS
,
RD
,
WR
IRQA
,
IRQB
First Interrupt Instruction Execution
a) First Interrupt Instruction Execution
General
Purpose
I/O Pin
IRQA
,
IRQB
b) General Purpose I/O
t
IDM
t
IG
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Reset, Stop, Wait, Mode Select, and Interrupt Timing
56F801 Technical Data
27
Figure 18. Interrupt from Wait State Timing
Figure 19. Recovery from Stop State Using Asynchronous Interrupt Timing
Figure 20. Recovery from Stop State Using IRQA Interrupt Service
Instruction Fetch
IRQA,
IRQB
First Interrupt Vector
A0A15,
PS, DS,
RD, WR
t
IRI
Not IRQA Interrupt Vector
IRQA
A0A15,
PS, DS,
RD, WR
First Instruction Fetch
t
IW
t
IF
Instruction Fetch
IRQA
A0A15
PS, DS,
RD, WR
First IRQA Interrupt
t
IRQ
t
II
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28
56F801 Technical Data
3.7 Serial Peripheral Interface (SPI) Timing
Table 25. SPI Timing
1
Operating Conditions:
V
SS
= V
SSA
= 0 V, V
DD
= V
DDA
= 3.03.6 V, T
A
= 40
to +85
C, C
L
50pF
1.
Parameters listed are guaranteed by design.
Characteristic
Symbol
Min
Max
Unit
See Figure
Cycle time
Master
Slave
t
C
50
25
--
--
ns
ns
Figures
21
,
22
,
23
,
24
Enable lead time
Master
Slave
t
ELD
--
25
--
--
ns
ns
Figure
24
Enable lag time
Master
Slave
t
ELG
--
100
--
--
ns
ns
Figure
24
Clock (SCK) high time
Master
Slave
t
CH
17.6
12.5
--
--
ns
ns
Figures
21
,
22
,
23
,
24
Clock (SCK) low time
Master
Slave
t
CL
24.1
25
--
--
ns
ns
Figures
21
,
22
,
23
,
24
Data setup time required for inputs
Master
Slave
t
DS
20
0
--
--
ns
ns
Figures
21
,
22
,
23
,
24
Data hold time required for inputs
Master
Slave
t
DH
0
2
--
--
ns
ns
Figures
21
,
22
,
23
,
24
Access time (time to data active from high-
impedance state)
Slave
t
A
4.8
15
ns
Figure
24
Disable time (hold time to high-impedance state)
Slave
t
D
3.7
15.2
ns
Figure
24
Data Valid for outputs
Master
Slave (after enable edge)
t
DV
--
--
4.5
20.4
ns
ns
Figures
21
,
22
,
23
,
24
Data invalid
Master
Slave
t
DI
0
0
--
--
ns
ns
Figures
21
,
22
,
23
,
24
Rise time
Master
Slave
t
R
--
--
11.5
10.0
ns
ns
Figures
21
,
22
,
23
,
24
Fall time
Master
Slave
t
F
--
--
9.7
9.0
ns
ns
Figures
21
,
22
,
23
,
24
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Serial Peripheral Interface (SPI) Timing
56F801 Technical Data
29
Figure 21. SPI Master Timing (CPHA = 0)
Figure 22. SPI Master Timing (CPHA = 1)
SCLK (CPOL = 0)
(Output)
SCLK (CPOL = 1)
(Output)
MISO
(Input)
MOSI
(Output)
MSB in
Bits 141
LSB in
Master MSB out
Bits 141
Master LSB out
SS
(Input)
SS is held High on master
t
F
t
R
t
DI
(ref)
t
DV
t
DI
t
DS
t
DH
t
CH
t
CL
t
CH
t
F
t
F
t
R
t
R
t
CL
t
C
SCLK (CPOL = 0)
(Output)
SCLK (CPOL = 1)
(Output)
MISO
(Input)
MOSI
(Output)
MSB in
Bits 141
LSB in
Master MSB out
Bits 14 1
Master LSB out
SS
(Input)
SS is held High on master
t
C
t
CL
t
CL
t
CH
t
CH
t
F
t
F
t
R
t
R
t
DS
t
DH
t
DV
t
DI
t
R
t
F
t
DV
(ref)
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56F801 Technical Data
Figure 23. SPI Slave Timing (CPHA = 0)
Figure 24. SPI Slave Timing (CPHA = 1)
SCLK (CPOL = 0)
(Input)
SCLK (CPOL = 1)
(Input)
MISO
(Output)
MOSI
(Input)
Slave MSB out
Bits 141
MSB in
Bits 141
LSB in
SS
(Input)
Slave LSB out
t
C
t
CL
t
F
t
ELG
t
R
t
DS
t
ELD
t
CH
t
CL
t
A
t
CH
t
R
t
F
t
D
t
DI
t
DV
t
DH
t
DI
SCLK (CPOL = 0)
(Input)
SCLK (CPOL = 1)
(Input)
MISO
(Output)
MOSI
(Input)
Slave MSB out
Bits 141
MSB in
Bits 141
LSB in
SS
(Input)
Slave LSB out
t
DI
t
D
t
R
t
DV
t
DH
t
F
t
DS
t
ELG
t
F
t
R
t
CH
t
DV
t
A
t
ELD
t
CL
t
CL
t
CH
t
C
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Quad Timer Timing
56F801 Technical Data
31
3.8 Quad Timer Timing
3.9 Serial Communication Interface (SCI) Timing
Table 26. Timer Timing
1, 2
Operating Conditions:
V
SS
= V
SSA
= 0 V, V
DD
= V
DDA
= 3.03.6 V, T
A
= 40
to +85
C, C
L
50pF
1.
In the formulas listed, T = clock cycle. For 80MHz operation, T = 12.5ns.
2.
Parameters listed are guaranteed by design.
Characteristic
Symbol
Min
Max
Unit
Timer input period
P
IN
4T+6
--
ns
Timer input high/low period
P
INHL
2T+3
--
ns
Timer output period
P
OUT
2T
--
ns
Timer output high/low period
P
OUTHL
1T
--
ns
Figure 25. Timer Timing
Table 27. SCI Timing
4
Operating Conditions:
V
SS
= V
SSA
= 0 V, V
DD
= V
DDA
= 3.03.6 V, T
A
= 40
to +85
C, C
L
50pF
Characteristic
Symbol
Min
Max
Unit
Baud Rate
1
1.
f
MAX
is the frequency of operation of the system clock in MHz.
BR
--
(f
MAX
*2.5)/(80)
Mbps
RXD
2
Pulse Width
2.
The RXD pin in SCI0 is named RXD0 and the RXD pin in SCI1 is named RXD1.
RXD
PW
0.965/BR
1.04/BR
ns
TXD
3
Pulse Width
3.
The TXD pin in SCI0 is named TXD0 and the TXD pin in SCI1 is named TXD1.
4.
Parameters listed are guaranteed by design.
TXD
PW
0.965/BR
1.04/BR
ns
Timer Inputs
Timer Outputs
P
OUTHL
P
OUTHL
P
OUT
P
IN
P
INHL
P
INHL
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32
56F801 Technical Data
Figure 26. RXD Pulse Width
Figure 27. TXD Pulse Width
3.10 Analog-to-Digital Converter (ADC) Characteristics
Table 28. ADC Characteristics
Operating Conditions:
V
SS
= V
SSA
= 0 V, V
DD
= V
DDA
= 3.03.6 V, V
REF
= V
DD
-0.3V, ADCDIV = 4, 9, or 14 (for optimal
performance), ADC clock = 4MHz, 3.03.6 V, T
A
= 40
to +85
C, C
L
50pF
Characteristic
Symbol
Min
Typ
Max
Unit
ADC input voltages
V
ADCIN
0
1
--
V
REF
2
V
Resolution
R
ES
12
--
12
Bits
Integral Non-Linearity
3
INL
--
+/- 4
+/- 5
LSB
4
Differential Non-Linearity
DNL
--
+/- 0.9
+/- 1
LSB
4
Monotonicity
GUARANTEED
ADC internal clock
5
f
ADIC
0.5
--
5
MHz
Conversion range
R
AD
V
SSA
--
V
DDA
V
Conversion time
t
ADC
--
6
--
t
AIC
cycles
6
Sample time
t
ADS
--
1
--
t
AIC
cycles
6
Input capacitance
C
ADI
--
5
--
pF
6
Gain Error (transfer gain)
5
E
GAIN
1.00
1.10
1.15
--
Offset Voltage
5
V
OFFSET
+10
+230
+325
mV
Total Harmonic Distortion
5
THD
55
60
--
dB
Signal-to-Noise plus Distortion
5
SINAD
54
56
--
dB
Effective Number of Bits
5
ENOB
8.5
9.5
--
bit
RXD
SCI receive
data pin
(Input)
RXD
PW
TXD
SCI receive
data pin
(Input)
TXD
PW
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Analog-to-Digital Converter (ADC) Characteristics
56F801 Technical Data
33
Figure 28. Equivalent Analog Input Circuit
1.
Parasitic capacitance due to package, pin to pin, and pin to package base coupling. (1.8pf)
2.
Parasitic capacitance due to the chip bond pad, ESD protection devices and signal routing. (2.04pf)
3.
Equivalent resistance for the ESD isolation resistor and the channel select mux. (500 ohms)
4. Sampling capacitor at the sample and hold circuit. Capacitor 4 is normally disconnected from the input
and is only connected to it at sampling time. (1pf)
Spurious Free Dynamic Range
5
SFDR
60
65
--
dB
Bandwidth
BW
--
100
--
KHz
ADC Quiescent Current (both ADCs)
I
ADC
--
50
--
mA
V
REF
Quiescent Current (both ADCs)
I
VREF
--
12
16.5
mA
1.
For optimum ADC performance, keep the minimum V
ADCIN
value > 250mV. Inputs less than 250mV volts may
convert to a digital output code of 0 or cause erroneous conversions.
2.
V
REF
must be equal to or less than V
DDA
and must be greater than 2.7V. For optimal ADC performance, set V
REF
to V
DDA
-0.3V.
3.
Measured in 10-90% range.
4.
LSB = Least Significant Bit.
5.
Guaranteed by characterization.
6.
t
AIC
= 1/
f
ADIC
Table 28. ADC Characteristics (Continued)
Operating Conditions:
V
SS
= V
SSA
= 0 V, V
DD
= V
DDA
= 3.03.6 V, V
REF
= V
DD
-0.3V, ADCDIV = 4, 9, or 14 (for optimal
performance), ADC clock = 4MHz, 3.03.6 V, T
A
= 40
to +85
C, C
L
50pF
Characteristic
Symbol
Min
Typ
Max
Unit
1
2
3
4
ADC analog input
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56F801 Technical Data
3.11 JTAG Timing
Table 29. JTAG Timing
1, 3
Operating Conditions:
V
SS
= V
SSA
= 0 V, V
DD
= V
DDA
= 3.03.6 V, T
A
= 40
to +85
C, C
L
50pF
1.
Timing is both wait state and frequency dependent. For the values listed, T = clock cycle. For 80MHz
operation, T = 12.5ns.
Characteristic
Symbol
Min
Max
Unit
TCK frequency of operation
2
2.
TCK frequency of operation must be less than 1/8 the processor rate.
3.
Parameters listed are guaranteed by design.
f
OP
DC
10
MHz
TCK cycle time
t
CY
100
--
ns
TCK clock pulse width
t
PW
50
--
ns
TMS, TDI data setup time
t
DS
0.4
--
ns
TMS, TDI data hold time
t
DH
1.2
--
ns
TCK low to TDO data valid
t
DV
--
26.6
ns
TCK low to TDO tri-state
t
TS
--
23.5
ns
TRST assertion time
t
TRST
50
--
ns
DE assertion time
t
DE
8T
--
ns
Figure 29. Test Clock Input Timing Diagram
TCK
(Input)
V
M
V
IL
V
M
= V
IL
+ (V
IH
V
IL
)/2
V
M
V
IH
t
PW
t
PW
t
CY
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JTAG Timing
56F801 Technical Data
35
Figure 30. Test Access Port Timing Diagram
Figure 31. TRST Timing Diagram
Figure 32. OnCE--Debug Event
Input Data Valid
Output Data Valid
Output Data Valid
TCK
(Input)
TDI
(Input)
TDO
(Output)
TDO
(Output
)
TDO
(Output)
TMS
t
DV
t
DV
t
TS
t
DS
t
DH
TRST
(Input)
t
TRST
DE
t
DE
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36
56F801 Technical Data
Part 4 Packaging
4.1 Package and Pin-Out Information 56F801
This section contains package and pin-out information for the 48-pin LQFP configuration of the 56F801.
Figure 33. Top View, 56F801 48-pin LQFP Package
PIN 1
ORIENTATION
MARK
TDO
TD1
TD2
/SS
MISO
MOSI
SCLK
TXDO
V
SS
V
DD
RXD0
DE
TCS
TCK
TM
S
IR
E
Q
A
TDI
VCAPC2
V
SS
V
DD
EXTAL
XTAL
TD
O
TRST
ANA4
ANA3
VREF
ANA2
ANA1
ANA0
FAULTA0
V
SS
V
DD
V
SSA
V
DDA
RESET
PW
M
A5
PW
M
A4
PW
M
A3
PW
M
A2
PW
M
A1
V
SS
V
DD
VCAPC1
PW
M
A0
ANA7
ANA6
ANA5
PIN 1
3
PIN 37
PIN 25
Motorola
56F801
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Package and Pin-Out Information 56F801
56F801 Technical Data
37
Table 30. 56F801 Pin Identification by Pin Number
Pin No.
Signal Name
Pin No.
Signal Name
Pin No.
Signal Name
Pin No.
Signal Name
1
TD0
13
TCS
25
RESET
37
ANA5
2
TD1
14
TCK
26
V
DDA
38
ANA6
3
TD2
15
TMS
27
V
SSA
39
ANA7
4
SS
16
IREQA
28
V
DD
40
PWMA0
5
MISO
17
TDI
29
V
SS
41
VCAPC1
6
MOSI
18
VCAPC2
30
FAULTA0
42
V
DD
7
SCLK
19
V
SS
31
ANA0
43
V
SS
8
TXD0
20
V
DD
32
ANA1
44
PWMA1
9
V
SS
21
EXTAL
33
ANA2
45
PWMA2
10
V
DD
22
XTAL
34
VREF
46
PWMA3
11
RXD0
23
TDO
35
ANA3
47
PWMA4
12
DE
24
TRST
36
ANA4
48
PWMA5
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38
56F801 Technical Data
Figure 34. 48-pin LQFP Mechanical Information
A
A1
Z
0.200 AB T-U
4X
Z
0.200 AC T-U
4X
B
B1
1
12
13
24
25
36
37
48
S1
S
V
V1
P
AE
AE
T, U, Z
DETAIL Y
DETAIL Y
BASE METAL
N
J
F
D
T-U
M
0.080
Z
AC
SECTION AE-AE
AD
G
0.080 AC
M
TOP & BOTTOM
L
W
K
AA
E
C
H
0.
25
0
R
9
DETAIL AD
NOTES:
1.
DIMENSIONING AND TOLERANCING PER
ASME Y14.5M, 1994.
2.
CONTROLLING DIMENSION: MILLIMETER.
3.
DATUM PLANE AB IS LOCATED AT BOTTOM
OF LEAD AND IS COINCIDENT WITH THE
LEAD WHERE THE LEAD EXITS THE PLASTIC
BODY AT THE BOTTOM OF THE PARTING
LINE.
4.
DATUMS T, U, AND Z TO BE DETERMINED AT
DATUM PLANE AB.
5.
DIMENSIONS S AND V TO BE DETERMINED
AT SEATING PLANE AC.
6.
DIMENSIONS A AND B DO NOT INCLUDE
MOLD PROTRUSION. ALLOWABLE
PROTRUSION IS 0.250 PER SIDE. DIMENSIONS
A AND B DO INCLUDE MOLD MISMATCH AND
ARE DETERMINED AT DATUM PLANE AB.
7.
DIMENSION D DOES NOT INCLUDE DAMBAR
PROTRUSION. DAMBAR PROTRUSION
SHALL NOT CAUSE THE D DIMENSION TO
EXCEED 0.350.
8.
MINIMUM SOLDER PLATE THICKNESS
SHALL BE 0.0076.
9.
EXACT SHAPE OF EACH CORNER IS
OPTIONAL.
CASE 932-03
ISSUE F
T
U
Z
AB
AC
GAUGE P
L
ANE
DIM
A
MIN
MAX
7.000 BSC
MILLIMETERS
A1
3.500 BSC
B
7.000 BSC
B1
3.500 BSC
C
1.400
1.600
D
0.170
0.270
E
1.350
1.450
F
0.170
0.230
G
0.500 BSC
H
0.050
0.150
J
0.090
0.200
K
0.500
0.700
M
12 REF
N
0.090
0.160
P
0.250 BSC
L
0
7
R
0.150
0.250
S
9.000 BSC
S1
4.500 BSC
V
9.000 BSC
V1
4.500 BSC
W
0.200 REF
AA
1.000 REF
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Thermal Design Considerations
56F801 Technical Data
39
Part 5 Design Considerations
5.1 Thermal Design Considerations
An estimation of the chip junction temperature, T
J
, in
C can be obtained from the equation:
Equation 1:
Where:
T
A
= ambient temperature C
R
JA
= package junction-to-ambient thermal resistance C/W
P
D
= power dissipation in package
Historically, thermal resistance has been expressed as the sum of a junction-to-case thermal resistance and
a case-to-ambient thermal resistance:
Equation 2:
Where:
R
JA
= package junction-to-ambient thermal resistance C/W
R
JC
= package junction-to-case thermal resistance C/W
R
CA
= package case-to-ambient thermal resistance C/W
R
JC
is device-related and cannot be influenced by the user. The user controls the thermal environment to
change the case-to-ambient thermal resistance, R
CA
. For example, the user can change the air flow around
the device, add a heat sink, change the mounting arrangement on the Printed Circuit Board (PCB), or
otherwise change the thermal dissipation capability of the area surrounding the device on the PCB. This
model is most useful for ceramic packages with heat sinks; some 90% of the heat flow is dissipated through
the case to the heat sink and out to the ambient environment. For ceramic packages, in situations where the
heat flow is split between a path to the case and an alternate path through the PCB, analysis of the device
thermal performance may need the additional modeling capability of a system level thermal simulation tool.
The thermal performance of plastic packages is more dependent on the temperature of the PCB to which the
package is mounted. Again, if the estimations obtained from R
JA
do not satisfactorily answer whether the
thermal performance is adequate, a system level model may be appropriate.
Definitions:
A complicating factor is the existence of three common definitions for determining the junction-to-case
thermal resistance in plastic packages:
Measure the thermal resistance from the junction to the outside surface of the package (case) closest
to the chip mounting area when that surface has a proper heat sink. This is done to minimize
temperature variation across the surface.
Measure the thermal resistance from the junction to where the leads are attached to the case. This
definition is approximately equal to a junction to board thermal resistance.
Use the value obtained by the equation (T
J
T
T
)/P
D
where T
T
is the temperature of the package
case determined by a thermocouple.
T
J
T
A
P
D
R
JA
(
)
+
=
R
JA
R
JC
R
CA
+
=
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40
56F801 Technical Data
The thermal characterization parameter is measured per JESD51-2 specification using a 40-gauge type T
thermocouple epoxied to the top center of the package case. The thermocouple should be positioned so that
the thermocouple junction rests on the package. A small amount of epoxy is placed over the thermocouple
junction and over about 1mm of wire extending from the junction. The thermocouple wire is placed flat
against the package case to avoid measurement errors caused by cooling effects of the thermocouple wire.
When heat sink is used, the junction temperature is determined from a thermocouple inserted at the interface
between the case of the package and the interface material. A clearance slot or hole is normally required in
the heat sink. Minimizing the size of the clearance is important to minimize the change in thermal
performance caused by removing part of the thermal interface to the heat sink. Because of the experimental
difficulties with this technique, many engineers measure the heat sink temperature and then back-calculate
the case temperature using a separate measurement of the thermal resistance of the interface. From this case
temperature, the junction temperature is determined from the junction-to-case thermal resistance.
5.2 Electrical Design Considerations
Use the following list of considerations to assure correct operation:
Provide a low-impedance path from the board power supply to each V
DD
pin on the hybrid
controller, and from the board ground to each V
SS
(GND) pin.
The minimum bypass requirement is to place 0.1
F capacitors positioned as close as possible to
the package supply pins. The recommended bypass configuration is to place one bypass capacitor
on each of the ten V
DD
/V
SS
pairs, including V
DDA
/V
SSA.
Ceramic and tantalum capacitors tend to
provide better performance tolerances.
Ensure that capacitor leads and associated printed circuit traces that connect to the chip V
DD
and
V
SS
(GND) pins are less than 0.5 inch per capacitor lead.
Bypass the V
DD
and V
SS
layers of the PCB with approximately 100
F, preferably with a high-
grade capacitor such as a tantalum capacitor.
Because the controller's output signals have fast rise and fall times, PCB trace lengths should be
minimal.
Consider all device loads as well as parasitic capacitance due to PCB traces when calculating
capacitance. This is especially critical in systems with higher capacitive loads that could create
higher transient currents in the V
DD
and GND circuits.
Take special care to minimize noise levels on the VREF, V
DDA
and V
SSA
pins.
CAUTION
This device contains protective circuitry to guard against
damage due to high static voltage or electrical fields.
However, normal precautions are advised to avoid
application of any voltages higher than maximum rated
voltages to this high-impedance circuit. Reliability of
operation is enhanced if unused inputs are tied to an
appropriate voltage level.
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Electrical Design Considerations
56F801 Technical Data
41
Designs that utilize the TRST pin for JTAG port or OnCE module functionality (such as
development or debugging systems) should allow a means to assert TRST whenever RESET is
asserted, as well as a means to assert TRST independently of RESET. TRST must be asserted at
power up for proper operation. Designs that do not require debugging functionality, such as
consumer products, TRST should be tied low.
Because the Flash memory is programmed through the JTAG/OnCE port, designers should provide
an interface to this port to allow in-circuit Flash programming.
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42
56F801 Technical Data
Part 6 Ordering Information
Table 31
lists the pertinent information needed to place an order. Consult a Motorola Semiconductor sales
office or authorized distributor to determine availability and to order parts.
Table 31. DSP56F801 Ordering Information
Part
Supply
Voltage
Package Type
Pin
Count
Frequency
(MHz)
Order Number
56F801
3.03.6 V
Low Profile Plastic Quad Flat Pack
(LQFP)
48
80
DSP56F801FA80
56F801
3.03.6 V
Low Profile Plastic Quad Flat Pack
(LQFP)
48
60
DSP56F801FA60
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Electrical Design Considerations
56F801 Technical Data
43
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HOW TO REACH US:
USA/EUROPE/LOCATIONS NOT LISTED:
Motorola Literature Distribution
P.O. Box 5405, Denver, Colorado 80217
1-800-521-6274 or 480-768-2130
JAPAN:
Motorola Japan Ltd.
SPS, Technical Information Center
3-20-1, Minami-Azabu
Minato-ku
Tokyo 106-8573, Japan
81-3-3440-3569
ASIA/PACIFIC:
Motorola Semiconductors H.K. Ltd.
Silicon Harbour Centre
2 Dai King Street
Tai Po Industrial Estate
Tai Po, N.T. Hong Kong
852-26668334
HOME PAGE:
http://motorola.com/semiconductors
Information in this document is provided solely to enable system and software
implementers to use Motorola products. There are no express or implied copyright
licenses granted hereunder to design or fabricate any integrated circuits or
integrated circuits based on the information in this document.
Motorola reserves the right to make changes without further notice to any products
herein. Motorola makes no warranty, representation or guarantee regarding the
suitability of its products for any particular purpose, nor does Motorola assume any
liability arising out of the application or use of any product or circuit, and specifically
disclaims any and all liability, including without limitation consequential or incidental
damages. "Typical" parameters which may be provided in Motorola data sheets
and/or specifications can and do vary in different applications and actual
performance may vary over time. All operating parameters, including "Typicals"
must be validated for each customer application by customer's technical experts.
Motorola does not convey any license under its patent rights nor the rights of
others. Motorola products are not designed, intended, or authorized for use as
components in systems intended for surgical implant into the body, or other
applications intended to support or sustain life, or for any other application in which
the failure of the Motorola product could create a situation where personal injury or
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against all claims, costs, damages, and expenses, and reasonable attorney fees
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with such unintended or unauthorized use, even if such claim alleges that Motorola
was negligent regarding the design or manufacture of the part.
Motorola and the Stylized M Logo are registered in the U.S. Patent and Trademark
Office. digital dna is a trademark of Motorola, Inc. All other product or service
names are the property of their respective owners. Motorola, Inc. is an Equal
Opportunity/Affirmative Action Employer.
Motorola, Inc. 2004
DSP56F801/D
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