DSP56F827/D

Rev. 7.0, 04/2003

56F827

Technical Data

56F827 16-bit Hybrid Controller

Up to 40 MIPS at 80MHz core frequency

DSP and MCU functionality in a unified,
C-efficient architecture

Hardware DO and REP loops

64K

× 16-bit words Program Flash

× 16-bit words Program RAM

× 16-bit words Data Flash

× 16-bit words Data RAM

Up to 64K

× 16-bit words external memory

expansion each for Program and Data memory

JTAG/OnCETM for debugging

General Purpose Quad Timer

MCU-friendly instruction set supports both DSP and
controller functions: MAC, bit manipulation unit, 14
addressing modes

8-channel Programmable Chip Select

10-channel, 12-bit ADC

Synchronous Serial Interface (SSI)

Serial Port Interface (SPI)

Serial Communications Interface (SCI)

Time-of-Day (TOD) Timer

128-pin LQFP Package

16-dedicated and 48 shared GPIO

Figure 1. 56F827 Block Diagram

JTAG/
OnCE

Port

Program Controller

and Hardware

Looping Unit

Data ALU

16 x 16 + 36

36-Bit MAC

Three 16-bit Input Registers

Two 36-bit Accumulators

Address

Generation

Unit

Bit

Manipulation

Unit

16-Bit
56800

Core

PAB

PDB

XDB2

CGDB
XAB1
XAB2

INTERRUPT

CONTROLS

IPBB

CONTROLS

IPBus Bridge

(IPBB)

MODULE

CONTROLS

ADDRESS

BUS [8:0]

DATA

BUS [15:0]

COP

RESET

Application-

Specific

Memory &

Peripherals

Interrupt

Controller

COP/

Watchdog

Quad Timer A/

or GPIO

DDA

SSA

External

Bus

Interface

Unit

RESET

IRQA

IRQB

EXTBOOT

DDIO

SSIO

TOD

Timer

DEBUG

ADC

Program and Boot

Memory

64512 x 16 Flash

1024 x 16 SRAM

Data Memory

4096 x 16 Flash

4096 x 16 SRAM

SCI 2 or

GPIO

SSI 0 or

GPI0

SCI 0 &1 or

SPI 0

SPI 1 or

GPIO

Programmable

Chip Select

Dedicated

GPIO

Analog Reg

Low Voltage Supervisor

External

Address Bus

Switch

External

Data Bus

Switch

Bus

Control

PLL

Clock

Gen

inputs

REFLO

REFHI

VPP

CLKO

EXTAL

XTAL

A[00:15]
or
GPIOA16[00:16]

D[00:15]
or
GPIOG16[00:16]

PS or PCS[0]

DS or PCS[1]

REFP

, V

REFMID

REFIN

PCS [2:7}

56F827 Technical Data

MOTOROLA

Part 1 Overview

1.1 56F827 Features

1.1.1

Digital Signal Processing Core

Efficient 16-bit 56800 family DSP engine with dual Harvard architecture

As many as 40 Million Instructions Per Second (MIPS) at 80MHz core frequency

Single-cycle 16

× 16-bit parallel Multiplier-Accumulator (MAC)

Two 36-bit accumulators including extension bits

16-bit bidirectional shifter

Parallel instruction set with unique DSP addressing modes

Hardware DO and REP loops

Three internal address buses and one external address bus

Four internal data buses and one external data bus

Instruction set supports both DSP and controller functions

Controller style addressing modes and instructions for compact code

Efficient C Compiler and local variable support

Software subroutine and interrupt stack with depth limited only by memory

JTAG/OnCE Debug Programming Interface

1.1.2

Memory

Harvard architecture permits as many as three simultaneous accesses to Program and Data memory

On-chip memory including a low-cost, high-volume Flash solution

-- 64K words of Program Flash

-- 1K

words of Program RAM

-- 4K words of Data RAM

-- 4K words of Data Flash

Off-chip memory expansion capabilities programmable for 0, 4, 8, or 12 wait states

-- As much as 64 K

× 16 Data memory

-- As much as 64 K

× 16 Program memory

1.1.3

Peripheral Circuits for 56F827

One 10 channel, 12-bit, Analog-to-Digital Converter (ADC)

One General Purpose Quad Timer totaling 4 pins

One Serial Peripheral Interface with configurable four-pin port multiplexed with two Serial
Communications Interfaces totalling 4 pins or 4 GPIO pins

Three Serial Communication Interfaces with 2 pins each (or 6 additional GPIO pins)

Two Serial Peripheral Interface with configurable four-pin port (or 4 additional GPIO pins)

56F827 Description

MOTOROLA

56F827 Technical Data

One Synchronous Serial Interface with 6 pins (or 6 additional GPIO pins)

One 8-channel Programmable Chip Select

Sixteen dedicated and forty eight multiplexed GPIO pins (64 total)

Computer-Operating Properly (COP) Watchdog timer

Two external interrupt pins

External reset pin for hardware reset

JTAG/On-Chip Emulation (OnCETM) for unobtrusive, processor speed-independent debugging

Software-programmable, Phase Locked Loop-based frequency synthesizer for the DSP core clock

Fabricated in high-density CMOS with 5V-tolerant, TTL-compatible digital inputs

One Time of Day (TOD) Timer

1.1.4

Power Information

Dual power supply, 3.3V and 2.5V

Wait and Multiple Stop modes available

1.2 56F827 Description

The 56F827 is a member of the 56800 core-based family of hybrid controllers. It combines, on a single
chip, the processing power of a DSP and the functionality of a microcontroller with a flexible set of
peripherals to create an extremely cost-effective solution for general purpose applications. Because of its
low cost, configuration flexibility, and compact program code, the 56F827 is well-suited for many
applications. The 56F827 includes many peripherals that are especially useful for applications such as:
noise suppression, ID tag readers, sonic/subsonic detectors, security access devices, remote metering,
sonic alarms, and telephony.

The 56800 core is based on a Harvard-style architecture consisting of three execution units operating in
parallel, allowing as many as six operations per instruction cycle. The microprocessor-style programming
model and optimized instruction set allow straightforward generation of efficient, compact code for both
DSP and MCU applications. The instruction set is also highly efficient for C/C++ Compilers to enable rapid
development of optimized control applications.

The 56F827 supports program execution from either internal or external memories. Two data operands can
be accessed from the on-chip Data RAM per instruction cycle. The 56F827 also provides two external
dedicated interrupt lines, and up to 64 General Purpose Input/Output (GPIO) lines, depending on peripheral
configuration.

The 56F827 controller includes 64K words (16-bit) of Program Flash and 4K words of Data Flash (each
programmable through the JTAG port) with 1K words of Program RAM and 4K words of Data RAM. It
also supports program execution from external memory. The 56800 core is capable of accessing two data
operands from the on-chip Data RAM per instruction cycle.

This controller also provides a full set of standard programmable peripherals that include one 10-input, 12-
bit Analog-to-Digital Converters (ADC), one Synchronous Serial Interface (SSI), two Serial Peripheral
Interfaces (SPI), three Serial Communications Interfaces (SCI). (Note: The second SPI is multiplexed with
the second and third SCIs giving the option to select a second SPI or two additional SCIs.) This hybrid
controller also provides one Programmable Chip Select (PCS), and one Quad Timer. The SCI, SSI, SPI,
Quad Timer A, and select address and data lines can be used as General Purpose Input/Outputs (GPIOs) if
those functions are not required.

56F827 Technical Data

MOTOROLA

1.3 "Best in Class" Development Environment

The SDK (Software Development Kit) provides fully debugged peripheral drivers, libraries and interfaces
that allow programmers to create their unique C application code independent of component architecture.
The CodeWarrior Integrated Development Environment is a sophisticated tool for code navigation,
compiling, and debugging. A complete set of evaluation modules (EVMs) and development system cards
will support concurrent engineering. Together, the SDK, CodeWarrior, and EVMs create a complete,
scalable tools solution for easy, fast, and efficient development.

1.4 Product Documentation

The four documents listed in

Table 2

are required for a complete description and proper design with the

56F827. Documentation is available from local Motorola distributors, Motorola semiconductor sales
offices, Motorola Literature Distribution Centers, or online at www.motorola.com/dsp/.

Table 1. 56F827 Chip Documentation

1.5 Data Sheet Conventions

This data sheet uses the following conventions:

Topic

Description

Order Number

DSP56800
Family Manual

Detailed description of the 56800 family architecture,
and 16-bit DSP core processor and the instruction set

DSP56800FM/D

DSP56F826/F827
User's Manual

Detailed description of memory, peripherals, and
interfaces of the 56F826 and 56F827

DSP56F826-827UM/D

DSP56F827
Technical Data Sheet

Electrical and timing specifications, pin descriptions,
and package descriptions (this document)

DSP56F827/D

DSP56F827
Product Brief

Summary description and block diagram of the 56F827
core, memory, peripherals and interfaces

DSP56F827PB/D

OVERBAR

This is used to indicate a signal that is active when pulled low. For example, the RESET pin is
active when low.

"asserted"

A high true (active high) signal is high or a low true (active low) signal is low.

"deasserted"

A high true (active high) signal is low or a low true (active low) signal is high.

Examples:

Signal/Symbol

Logic State

Signal State

Voltage

Values for VIL, VOL, VIH, and VOH are defined by individual product specifications.

True

Asserted

False

Deasserted

True

Asserted

False

Deasserted

Introduction

MOTOROLA

56F827 Technical Data

Part 2 Signal/Connection Descriptions

2.1 Introduction

The input and output signals of the 56F827 are organized into functional groups, as shown in

Table 2

and

as illustrated in

Figure 2

. In

Table 3

describes the signal or signals present on a pin.

Table 2. Functional Group Pin Allocations

Functional Group

Number of Pins

Power (V

, V

DDIO,

DDA or

DDA_ADC

)

(3,5,1,1)

Ground (V

, V

SSIO,

SSA, or

SSA_ADC

)

(3,5,1,1)

- (This pin should be left unconnected as an open

circuit for normal functionality.)

PLL and Clock

Address Bus

Data Bus

Bus Control

Interrupt and Program Control

Dedicated General Purpose Input/Output

Synchronous Serial Interface (SSI) Port

Serial Peripheral Interface (SPI) Port

Alternately, GPIO pins

Serial Communications Interface1 (SCI0, SCI1) Port

Alternately, SPI pins

Serial Communications Interface2 (SCI2) Port

Quad Timer Module Ports

JTAG/On-Chip Emulation (OnCE)

Analog to Digital Converter (ADC)

Programmable Chip Select (PCS)

In addition, 2 Bus Control pins can be programmed as PCS[0-1].

56F827 Technical Data

MOTOROLA

Figure 2. 56F827 Signals Identified by Functional Group

1. Alternate pin functionality is shown in parenthesis.

56F827

2.5V Power

Ground

3.3V Power

Ground

3.3V Analog Power

Analog Ground

3.3V Analog Power

Analog Ground

PLL

and

Clock

External

Address Bus or

GPIO

External Data

Bus or GPIO

External

Bus Control

Dedicated
GPIO

SPI1 Port
or GPIO

SCI0,SCI1
Port or
SPI0 Port

DDIO

SSIO

DDA

SSA

DDA_ADC

SSA_ADC

EXTAL

XTAL(CLOCKIN)

CLKO

A0-A15(GPIOA015)

D0D15(GPIOG0-15)

PS (PCS0)

DS (PCS1)

TA0 (GPIOF0)

TA1 (GPIOF1)

TA2 (GPIOF2)

TA3 (GPIOF3)

TCK

TMS

TDI

TDO

TRST

Quad Timer A

or GPIO

JTAG/OnCE

Port

GPIOB07

GPIOD07

SRD (GPIOC0)

SRFS (GPIOC1)

SRCK (GPIOC2)

STD (GPIOC3)

STFS (GPIOC4)

STCK (GPIOC5)

SCLK (GPIOF4)

MOSI (GPIOF5)

MISO (GPIOF6)

SS (GPIOF7)

TXD0 (SCLK0)

RXD0 (MOSI0)

TXD1 (MISO0)

RXD1 (SS0)

TXD2 (GPIOC6)

RXD2 (GPIOC7)

PCS2-7

ANA09

VREFN

VREFP

VREFMID

VREFLO

VREFHI

IRQA

IRQB

RESET

EXTBOOT

SSI Port
or GPIO

ADC
Port

SCI2 Port
or GPIO

Other

Supply Port

Interrupt/
Program
Control

Programmable
Chip Select

Signals and Package Information

MOTOROLA

56F827 Technical Data

2.2 Signals and Package Information

All inputs have a weak internal pull-up circuit associated with them. These pull-up circuits are always
enabled. Exceptions:

1. When a pin is owned by GPIO, then the pull-up may be disabled under software control.

2. TCK has a weak pull-down circuit always active.

Table 3. 56F827 Signal and Package Information for the 128 Pin LQFP

Signal Name

Pin No.

Type

Description

116

Power--These pins provide power to the internal structures of the chip,
and are generally connected to a 2.5V supply.

115

GND--These pins provide grounding for the internal structures of the
chip. All should be attached to V

SS.

DDIO

113

DDIO

Power In/Out--These pins provide power to the I/O structures of the
chip, and are generally connected to a 3.3V supply.

DDIO

SSIO

114

SSIO

GND In/Out--These pins provide grounding for the I/O ring on the chip.

All should be attached to V

SS.

SSIO

DDA

Analog Power--This pin is a dedicated power pin for the analog
portion of the chip and should be connected to a low noise 3.3V supply.

SSA

Analog Ground--This pin supplies an analog ground.

DDA_ADC

DDA

Analog Power--This pin is a dedicated power pin for the analog
portion of the ADC module and should be connected to a low noise
3.3V supply.

SSA_ADC

SSA

Analog Ground--This pin is a dedicated ground pin for the analog
portion of the ADC module.

Input

VPP--This pin should be left unconnected as an open circuit for normal
functionality.

56F827 Technical Data

MOTOROLA

EXTAL

Input

Crystal Oscillator Output--This output should be connected to an
8MHz external crystal or ceramic resonator. For more information,
please refer to

Section 3.6

This pin can also be connected to an external clock source. For more
information, please refer to

Section 3.6.3

XTAL

CLOCKIN

Output

Input

Crystal Oscillator Output--This output connects the internal crystal
oscillator output to an external crystal or ceramic resonator. If an
external clock source other than a crystal oscillator is used, XTAL must
be used as the input and EXTAL connected to

DDA/2.

External Clock Input--This input should be used when using an
external clock.

CLKO

Output

Clock Output--This pin outputs a buffered clock signal. By
programming the CLKO Select Register (CLKOSR), the user can select
between outputting a version of the signal applied to XTAL and a
version of the device master clock at the output of the PLL. The clock
frequency on this pin can be disabled by programming the CLKO Select
Register (CLKOSR).

Table 3. 56F827 Signal and Package Information for the 128 Pin LQFP (Continued)

Signal Name

Pin No.

Type

Description

Signals and Package Information

MOTOROLA

56F827 Technical Data

(GPIOA0)

Output

Input/Output

Address Bus--A0A15 specify the address for external Program or
Data memory accesses.

Port A GPIO--These 16 General Purpose I/O (GPIO) pins can be
individually programmed as input or output pins.

After reset, the default state is Address Bus.

(GPIOA1)

(GPIOA2)

(GPIOA3)

(GPIOA4)

(GPIOA5)

(GPIOA6)

(GPIOA7)

(GPIOA8)

(GPIOA9)

A10

(GPIOA10)

A11

(GPIOA11)

A12

(GPIOA12)

A13

(GPIOA13)

A14

(GPIOA14)

A15

(GPIOA15)

Table 3. 56F827 Signal and Package Information for the 128 Pin LQFP (Continued)

Signal Name

Pin No.

Type

Description

56F827 Technical Data

MOTOROLA

(GPIOG0)

125

Input/Output

Data Bus--D0D15 specify the data for external Program or Data
memory accesses. D0-D15 are tri-stated when the external bus is
inactive.

Port G GPIO--These 16 General Purpose I/O (GPIO) pins can be
individually programmed as input or output pins.

After reset, the default state is Address Bus.

(GPIOG1)

126

(GPIOG2)

127

(GPIOG3)

128

(GPIOG4)

(GPIOG5)

(GPIOG6)

(GPIOG7)

(GPIOG8)

(GPIOG9)

D10

(GPIOG10)

D11

(GPIOG11)

D12

(GPIOG12)

D13

(GPIOG13)

D14

(GPIOG14)

D15

(GPIOG15)

(PCS0)

Output

Program Memory Select--PS is asserted low for external program
memory access. This pin can also be programmed as a programmable
chip select.

Table 3. 56F827 Signal and Package Information for the 128 Pin LQFP (Continued)

Signal Name

Pin No.

Type

Description

Signals and Package Information

MOTOROLA

56F827 Technical Data

(PCS1)

Output

Data Memory Select--DS is asserted low for external Data memory
access. This pin can also be programmed as a programmable chip
select.

Output

Read Enable--RD is asserted during external memory read cycles.
When RD is asserted low, pins D0D15 become inputs and an external
device is enabled onto the device data bus. When RD is deasserted
high, the external data is latched inside the device. When RD is
asserted, it qualifies the A0A15, PS, and DS pins. RD can be
connected directly to the OE pin of a Static RAM or ROM.

Output

Write Enable--WR is asserted during external memory write cycles.
When WR is asserted low, pins D0D15 become outputs and the
device puts data on the bus. When WR is deasserted high, the external
data is latched inside the external device. When WR is asserted, it
qualifies the A0A15, PS, and DS pins. WR can be connected directly
to the WE pin of a Static RAM.

TA0

(GPIOF0)

112

Input/Output

TA03--Timer F Channels 0, 1, 2, and 3

Port F GPIO--These four General Purpose I/O (GPIO) pins can be
individually programmed as input or output.

After reset, the default state is Quad Timer.

TA1

(GPIOF1)

111

TA2

(GPIOF2)

110

TA3

(GPIOF3)

109

TCK

Input

(Schmitt)

Test Clock Input--This input pin provides a gated clock to synchronize
the test logic and shift serial data to the JTAG/OnCE port. The pin is
connected internally to a pull-down resistor.

TMS

Input

(Schmitt)

Test Mode Select Input--This input pin is used to sequence the JTAG
TAP controller's state machine. It is sampled on the rising edge of TCK
and has an on-chip pull-up resistor.

TDI

Input

(Schmitt)

Test Data Input--This input pin provides a serial input data stream to
the JTAG/OnCE port. It is sampled on the rising edge of TCK and has
an on-chip pull-up resistor.

TDO

Input/Output

Test Data Output--This tri-statable output pin provides a serial output
data stream from the JTAG/OnCE port. It is driven in the Shift-IR and
Shift-DR controller states, and changes on the falling edge of TCK.

TRST

Input

(Schmitt)

Test Reset--As an input, a low signal on this pin provides a reset
signal to the JTAG TAP controller. To ensure complete hardware reset,
TRST should be asserted whenever RESET is asserted. The only
exception occurs in a debugging environment when a hardware device
reset is required and it is necessary not to reset the JTAG/OnCE
module. In this case, assert RESET, but do not assert TRST. TRST
must always be asserted at powerup.

Output

Debug Event--DE provides a low pulse on recognized debug events.

Table 3. 56F827 Signal and Package Information for the 128 Pin LQFP (Continued)

Signal Name

Pin No.

Type

Description

56F827 Technical Data

MOTOROLA

TCS

Input/Output

(Schmitt)

TCS--This pin is reserved for factory use. It must be tied to V

for

normal use. In block diagrams, this pin is considered an additional V

SS.

GPIOB0

124

Input/Output

Port B GPIO--These eight dedicated General Purpose I/O (GPIO) pins
can be individually programmed as input or output pins.

After reset, the default state is GPIO input.

GPIOB1

123

GPIOB2

122

GPIOB3

121

GPIOB4

120

GPIOB5

119

GPIOB6

118

GPIOB7

117

GPIOD0

Input/ Output

Port D GPIO--These eight dedicated GPIO pins can be individually
programmed as an input or output pins.

After reset, the default state is GPIO input.

GPIOD1

GPIOD2

GPIOD3

GPIOD4

GPIOD5

GPIOD6

GPIOD7

SRD

(GPIOC0)

Input/Output

SSI Receive Data (SRD)--This input pin receives serial data and
transfers the data to the SSI Receive Shift Receiver.

Port C GPIO--This is a General Purpose I/O (GPIO) pin with the
capability of being individually programmed as input or output.

After reset, the default state is GPIO input.

SRFS

(GPIOC1)

Input/Output

SSI Serial Receive Frame Sync (SRFS)--This bidirectional pin is
used by the receive section of the SSI as frame sync I/O or flag I/O. The
STFS can be used only by the receiver. It is used to synchronize data
transfer and can be an input or an output.

Port C GPIO--This is a General Purpose I/O (GPIO) pin with the
capability of being individually programmed as input or output.

After reset, the default state is GPIO input.

Table 3. 56F827 Signal and Package Information for the 128 Pin LQFP (Continued)

Signal Name

Pin No.

Type

Description

Signals and Package Information

MOTOROLA

56F827 Technical Data

SRCK

GPIOC2

Input/Output

SSI Serial Receive Clock (SRCK)--This bidirectional pin provides the
serial bit rate clock for the Receive section of the SSI. The clock signal
can be continuous or gated and can be used by both the transmitter
and receiver in synchronous mode.

Port C GPIO--This is a General Purpose I/O (GPIO) pin with the
capability of being individually programmed as input or output.

After reset, the default state is GPIO input.

STD

(GPIOC3)

Output

Input/Output

SSI Transmit Data (STD)--This output pin transmits serial data from
the SSI Transmitter Shift Register.

Port C GPIO--This is a General Purpose I/O (GPIO) pin with the
capability of being individually programmed as input or output.

After reset, the default state is GPIO input.

STFS

(GPIOC4)

Input

Input/Output

SSI Serial Transmit Frame Sync (STFS)--This bidirectional pin is
used by the Transmit section of the SSI as frame sync I/O or flag I/O.
The STFS can be used by both the transmitter and receiver in
synchronous mode. It is used to synchronize data transfer and can be
an input or output pin.

Port C GPIO--This is a General Purpose I/O (GPIO) pin with the
capability of being individually programmed as input or output.

After reset, the default state is GPIO input.

STCK

(GPIOC5)

Input/ Output

Input/Output

SSI Serial Transmit Clock (STCK)--This bidirectional pin provides the
serial bit rate clock for the transmit section of the SSI. The clock signal
can be continuous or gated. It can be used by both the transmitter and
receiver in synchronous mode.

Port C GPIO--This is a General Purpose I/O (GPIO) pin with the
capability of being individually programmed as input or output.

After reset, the default state is GPIO input.

SCLK

(GPIOF4)

102

Input/Output

SPI Serial Clock--In master mode, this pin serves as an output,
clocking slaved listeners. In slave mode, this pin serves as the data
clock input.

Port F GPIO--This General Purpose I/O (GPIO) pin can be individually
programmed as input or output.

After reset, the default state is SCLK.

MOSI

(GPIOF5)

101

Input/Output

SPI Master Out/Slave In (MOSI)--This serial data pin is an output from
a master device and an input to a slave device. The master device
places data on the MOSI line a half-cycle before the clock edge that the
slave device uses to latch the data.

Port F GPIO--This General Purpose I/O (GPIO) pin can be individually
programmed as input or output.

Table 3. 56F827 Signal and Package Information for the 128 Pin LQFP (Continued)

Signal Name

Pin No.

Type

Description

56F827 Technical Data

MOTOROLA

MISO

(GPIOF6)

100

Input/Output

SPI Master In/Slave Out (MISO)--This serial data pin is an input to a
master device and an output from a slave device. The MISO line of a
slave device is placed in the high-impedance state if the slave device is
not selected.

Port F GPIO--This General Purpose I/O (GPIO) pin can be individually
programmed as input or output.

After reset, the default state is MISO.

(GPIOF7)

Input/Output

SPI Slave Select--In master mode, this pin is used to arbitrate multiple
masters. In slave mode, this pin is used to select the slave.

Port F GPIO--This General Purpose I/O (GPIO) pin can be individually
programmed as input or output.

After reset, the default state is SS.

TXD0

(SCLK0)

108

Output

Input/Output

Transmit Data (TXD0)--transmit data output

SPI Serial Clock--In master mode, this pin serves as an output,
clocking slaved listeners. In slave mode, this pin serves as the data
clock input.

After reset, the default state is SCI output.

RXD0

(MOSI0)

107

Input

Input/Output

Receive Data (RXD0)--receive data input

SPIMaster Out/Slave In--This serial data pin is an input to a master
device and an output from a slave device. The MISO line of a slave
device is placed in the high-impedance state if hte slave device is not
selected.

TXD1

(MISO0)

106

Output

Input/Output

Transmit Data (TXD1)--transmit data output

SPI Master In/Slave Out--This serial data pin is an output to a master
device and an input from a slave device. The master device places data
on the MOSI line one half-cycle before the clock edge the slave device
uses to latch the data.

After reset, the default state is SCI input.

RXD1

(SS0)

105

Input

(Schmitt)

Input

Receive Data (RXD1)-- receive data input

SPI Slave Select--In master mode, this pin is used to arbitrate multiple
masters. In slave mode, this pin is used to select the slave.

After reset, the default state is SCI input.

Table 3. 56F827 Signal and Package Information for the 128 Pin LQFP (Continued)

Signal Name

Pin No.

Type

Description

Signals and Package Information

MOTOROLA

56F827 Technical Data

TXD2

(GPIOC6)

104

Output

Input/Output

Transmit Data (TXD2)--transmit data output

Port C GPIO--This General Purpose I/O (GPIO) pin can be individually
programmed as input or output.

After reset, the default state is GPIO output.

RXD2

(GPIOC7)

103

Input/Output

Receive Data (RXD2)-- receive data input

Port C GPIO--This General Purpose I/O (GPIO) pin can be individually
programmed as input or output.

After reset, the default state is GPIO input.

PCS2

Input/Output

Programmable Chip Select - PCS 2-7

PCS3

Input/Output

PCS4

Input/Output

PCS5

Input/Output

PCS6

Input/Output

PCS7

Input/Output

ANA0

Input

ANA0

9--Analog inputs to ADC

ANA1

Input

ANA2

Input

ANA3

Input

ANA4

Input

ANA5

Input

ANA6

Input

ANA7

Input

ANA8

Input

ANA9

Input

REFN

Input

ADC Reference--This pin is connected to the negative side of the ADC
input range. This pin requires a 0.1

F ceramic capacitor to V

SSA

and a

startup time of 25ms, prior to beginning conversions.

REFP

Input

ADC Reference--This pin is connected to the positive side of the ADC
input range. This pin requires a 0.1

F ceramic capacitor to V

SSA

and a

startup time of 25ms, prior to beginning conversions.

Table 3. 56F827 Signal and Package Information for the 128 Pin LQFP (Continued)

Signal Name

Pin No.

Type

Description

56F827 Technical Data

MOTOROLA

Part 3 Specifications

3.1 General Characteristics

The 56F827 is fabricated in high-density CMOS with 5V-tolerant TTL-compatible digital inputs. The term
"5V-tolerant" refers to the capability of an I/O pin, built on a 3.3V-compatible process technology, to
withstand a voltage up to 5.5V without damaging the device. Many systems have a mixture of devices
designed for 3.3V and 5V power supplies. In such systems, a bus may carry both 3.3V and 5V-compatible
I/O voltage levels. A standard 3.3V I/O is designed to receive a maximum voltage of 3.3V

± 10% during

REFMID

Input

ADC Reference--This pin isconnected to the center of the ADC input
range. This pin requires a 0.1

F ceramic capacitor to V

SSA

and a

startup time of 25ms, prior to beginning conversions.

REFLO

Input

ADC Reference--These pins are Negative Reference for ADC and are
generally connected to a V

SSA

REFHI

Input

ADC Reference--These pins are Positive Reference for ADC and are
generally connected to a 3.3V Analog (V

DDA_ADC)

supply.

IRQA

Input

(Schmitt)

External Interrupt Request A--The IRQA input is a synchronized
external interrupt request that indicates that an external device is
requesting service. It can be programmed to be level-sensitive or
negative-edge- triggered. If level-sensitive triggering is selected, an
external pull up resistor is required for wired-OR operation.

If the processor is in the Stop state and IRQA is asserted, the processor
will exit the Stop state.

IRQB

Input

(Schmitt)

External Interrupt Request B--The IRQB input is an external interrupt
request that indicates that an external device is requesting service. It
can be programmed to be level-sensitive or negative-edge-triggered. If
level-sensitive triggering is selected, an external pull up resistor is
required for wired-OR operation.

RESET

Input

(Schmitt)

Reset--This input is a direct hardware reset on the processor. When
RESET is asserted low, the device is initialized and placed in the Reset
state. A Schmitt trigger input is used for noise immunity. When the
RESET pin is deasserted, the initial chip operating mode is latched from
the external boot pin. The internal reset signal will be deasserted
synchronous with the internal clocks, after a fixed number of internal
clocks.

To ensure complete hardware reset, RESET and TRST should be
asserted together. The only exception occurs in a debugging
environment when a hardware device reset is required and it is
necessary not to reset the OnCE/JTAG module. In this case, assert
RESET, but do not assert TRST.

EXTBOOT

Input

(Schmitt)

External Boot--This input is tied to V

to force device to boot from

off-chip memory. Otherwise, it is tied to V

Table 3. 56F827 Signal and Package Information for the 128 Pin LQFP (Continued)

Signal Name

Pin No.

Type

Description

General Characteristics

MOTOROLA

56F827 Technical Data

normal operation without causing damage. This 5V-tolerant capability, therefore, offers the power savings
of 3.3V I/O levels while being able to receive 5V levels without being damaged.

Absolute maximum ratings given in

Table 4

are stress ratings only, and functional operation at the

maximum is not guaranteed. Stress beyond these ratings may affect device reliability or cause permanent
damage to the device.

The 56F827 DC/AC electrical specifications are preliminary and are from design simulations. These
specifications may not be fully tested or guaranteed at this early stage of the product life cycle. Finalized
specifications will be published after complete characterization and device qualifications have been
completed.

CAUTION

This device contains protective circuitry to guard against
damage due to high static voltage or electrical fields.
However, normal precautions are advised to avoid
application of any voltages higher than maximum rated
voltages to this high-impedance circuit. Reliability of
operation is enhanced if unused inputs are tied to an
appropriate voltage level.

Table 4. Absolute Maximum Ratings

Characteristic

Symbol

Min

Max

Unit

Supply voltage, core

must not exceed V

DDIO

- 0.3

+ 3.0

Supply voltage, IO

Supply voltage, Analog

Supply voltage, ADC

DDIO

DDA

DDA_ADC

DDIO

and V

DDA

must not differ by more that 0.5V

SSIO

- 0.3

SSA

- 0.3

SSA_ADC

-0.3

SSIO

+ 4.0

SSA

+ 4.0

SSA_ADC

+0.3

Digital input voltages
Analog input voltages (XTAL, EXTAL)
Analog input voltages (ANA0-7, VREF)

INA

IN_ADC

SSIO

- 0.3

SSA

- 0.3

SSA_ADC

-0.3

SSIO

+ 5.5

DDA

+ 0.3

SSA_ADC

+0.3

Current drain per pin excluding V

, V

SS,

DDA

SSA,

DDIO

, V

SSIO

Junction temperature

150

°C

Storage temperature range

STG

-55

150

°C

56F827 Technical Data

MOTOROLA

Notes:

Theta-JA determined on 2s2p test boards is frequently lower than would be observed in an application.
Determined on 2s2p thermal test board.

Junction to ambient thermal resistance, Theta-JA (

) was simulated to be equivalent to the

JEDEC specification JESD51-2 in a horizontal configuration in natural convection. Theta-JA was
also simulated on a thermal test board with two internal planes (2s2p where s is the number of signal
layers and p is the number of planes) per JESD51-6 and JESD51-7. The correct name for Theta-JA
for forced convection or with the non-single layer boards is Theta-JMA.

Table 5. Recommended Operating Conditions

Characteristic

Symbol

Min

Typ

Max

Unit

Supply voltage, core

2.4

2.5

2.75

Supply Voltage, IO and analog

DDIO,

DDA

3.0

3.3

3.6

ADC reference voltage, positive

REFHI

2.7

DD_ADC

ADC reference voltage, negative

REFLO

SSA

REFHI

Ambient operating temperature

°C

Table 6. Thermal Characteristics

Characteristic

Comments

Symbol

Value

Unit

Notes

128-pin LQFP

Junction to ambient
Natural convection

50.8

°C/W

Junction to ambient (@1m/sec)

JMA

46.5

°C/W

Junction to ambient
Natural convection

Four layer board

(2s2p)

JMA

(2s2p)

43.9

°C/W

1,2

Junction to ambient (@1m/sec)

Four layer board

(2s2p)

JMA

41.7

°C/W

1,2

Junction to case

13.9

°C/W

Junction to center of case

1.2

°C/W

I/O pin power dissipation

I/O

User Determined

Power dissipation

= (I

x V

+ P

I/O

)

Junction to center of case

DMAX

(TJ - TA) /

°C

DC Electrical Characteristics

MOTOROLA

56F827 Technical Data

Junction to case thermal resistance, Theta-JC (R

), was simulated to be equivalent to the

measured values using the cold plate technique with the cold plate temperature used as the "case"
temperature. The basic cold plate measurement technique is described by MIL-STD 883D, Method
1012.1. This is the correct thermal metric to use to calculate thermal performance when the package
is being used with a heat sink.

Thermal Characterization Parameter, Psi-JT (

), is the "resistance" from junction to reference

point thermocouple on top center of case as defined in JESD51-2.

is a useful value to use to

estimate junction temperature in steady state customer environments.

Junction temperature is a function of on-chip power dissipation, package thermal resistance,
mounting site (board) temperature, ambient temperature, air flow, power dissipation of other
components on the board, and board thermal resistance.

See Section 5.1 from more details on thermal design considerations.

3.2 DC Electrical Characteristics

Table 7. DC Electrical Characteristics

Operating Conditions:

SSIO

= V

SSA

= 0V, V

DDA

DDIO

=3.03.6V, V

= 2.252.75V, T

= 40

° to +85°C, C

50pF, f

= 80MHz

Characteristic

Symbol

Min

Typ

Max

Unit

Input high voltage (XTAL/EXTAL)

IHC

2.25

3.6

Input low voltage (XTAL/EXTAL)

ILC

0.5

Input high voltage (Schmitt trigger inputs)

IHS

2.2

5.5

Input low voltage (Schmitt trigger inputs)

ILS

-0.3

0.8

Input high voltage (all other digital inputs)

2.0

5.5

Input low voltage (all other digital inputs)

-0.3

0.8

Input current high (pull-up/pull-down resistors disabled,
V

)

-1

Input current low (pull-up/pull-down resistors disabled, V

)

-1

Input current high (with pull-up resistor, V

)

IHPU

-0

Input current low (with pull-up resistor, V

)

ILPU

-210

-50

Input current high (with pull-down resistor, V

)

IHPD

180

Input current low (with pull-down resistor, V

)

ILPD

-1

Nominal pull-up or pull-down resistor value

, R

Output tri-state current low

OZL

-10

Output tri-state current high

OZH

-10

Input current high (analog inputs, V

DDA

)

IHA

-15

Input current low (analog inputs, V

SSA

)

ILA

-15

Output High Voltage (at I

)

0.7

Output Low Voltage (at I

)

0.4

56F827 Technical Data

MOTOROLA

Output source current

Output sink current

PWM pin output source current

OHP

PWM pin output sink current

OLP

Input capacitance

Output capacitance

OUT

supply current

DDT

Run

Wait

Stop

Low Voltage Interrupt, V

DDIO

power supply

EIO

2.4

2.7

3.0

Low Voltage Interrupt, V

power supply

EIC

2.0

2.2

2.4

Power-on Reset

POR

1.7

2.0

Schmitt Trigger inputs are: EXTBOOT, IRQA, IRQB, RESET, TCS, TCK, TRST, TMS, TDI, and RXD1.

Analog inputs are: ANA[0:7], XTAL and EXTAL. Specification assumes ADC is not sampling.

PWM pin output source current measured with 50% duty cycle.

PWM pin output sink current measured with 50% duty cycle.

DDT

= I

+ I

DDA

(Total supply current for V

+ V

DDA

)

Run (operating) I

measured using 8MHz clock source. All inputs 0.2V from rail; outputs unloaded. All ports

configured as inputs; measured with all modules enabled.

Wait I

measured using external square wave clock source (f

osc

= 8MHz) into XTAL; all inputs 0.2V from rail; no

DC loads; less than 50pF on all outputs. C

= 20pF on EXTAL; all ports configured as inputs; EXTAL capacitance linearly

affects wait I

; measured with PLL enabled.

This low-voltage interrupt monitors the V

DDIO

power supply. If V

DDIO

drops below V

EIO

, an interrupt is generated.

Functionality of the device is guaranteed under transient conditions when V

DDIO

EIO

(between the minimum specified

DDIO

and the point when the V

EIO

interrupt is generated).

This low-voltage interrupt monitors theV

power supply. If V

DDIO

drops below V

EIC

, an interrupt is generated.

Functionality of the device is guaranteed under transient conditions when V

EIC

(between the minimum specified

and the point when the V

EIC

interrupt is generated).

10. Power

on reset occurs whenever the V

power supply drops below

POR

. While power is ramping up, this signal

remains active as long as V

is below

POR

, no matter how long the ramp-up rate is.

Table 7. DC Electrical Characteristics (Continued)

Operating Conditions:

SSIO

= V

SSA

= 0V, V

DDA

DDIO

=3.03.6V, V

= 2.252.75V, T

= 40

° to +85°C, C

50pF, f

= 80MHz

Characteristic

Symbol

Min

Typ

Max

Unit

Supply Voltage Sequencing and Separation Cautions

MOTOROLA

56F827 Technical Data

Figure 3. Maximum Run I

vs. Frequency (see Note

Table 7

)

3.3 Supply Voltage Sequencing and Separation Cautions

Figure 4

shows two situations to avoid in sequencing the V

and V

DDIO,

DDA

supplies.

Notes: 1. V

rising before V

DDIO

, V

DDA

2. V

DDIO

, V

DDA

rising much faster than V

Figure 4. Supply Voltage Sequencing and Separation Cautions

100

Freq. (MHz)

I
D

D (

IDD Digital

IDD Analog

IDD Total

3.3V

2.5V

Time

Supplies Stable

DDIO,

DDA

DC P

r Supply

l
t
age

56F827 Technical Data

MOTOROLA

should not be allowed to rise early (1). This is usually avoided by running the regulator for the V

supply (2.5V) from the voltage generated by the 3.3V V

DDIO

supply, see

Figure 5

. This keeps V

from

rising faster than V

DDIO

should not rise so late that a large voltage difference is allowed between the two supplies (2). Typically

this situation is avoided by using external discrete diodes in series between supplies, as shown in

Figure 5

The series diodes forward bias when the difference between V

DDIO

and V

reaches approximately 1.4,

causing V

to rise as V

DDIO

ramps up. When the V

regulator begins proper operation, the difference

between supplies will typically be 0.8V and conduction through the diode chain reduces to essentially
leakage current. During supply sequencing, the following general relationship should be adhered to:
V

DDIO

> V

> (V

DDIO

- 1.4V)

In practice, V

DDA

is typically connected directly to V

DDIO

with some filtering.

Figure 5. Example Circuit to Control Supply Sequencing

3.4 AC Electrical Characteristics

Timing waveforms in

Section 3.4

are tested using the V

and V

levels specified in the DC Characteristics

table. In

Figure 6

the levels of V

and V

for an input signal are shown.

Figure 6. Input Signal Measurement References

Figure 7

shows the definitions of the following signal states:

Active state, when a bus or signal is driven, and enters a low impedance state.

Tri-stated, when a bus or signal is placed in a high impedance state.

Data Valid state, when a signal level has reached V

or V

OH.

Data Invalid state, when a signal level is in transition between V

and V

OH.

3.3V

Regulator

2.5V

Regulator

Supply

DDIO,

DDA

Fall Time

Input Signal

Note: The midpoint is V

+ (V

)/2.

Midpoint1

Low

High

Pulse Width

90%

50%

10%

Rise Time

Flash Memory Characteristics

MOTOROLA

56F827 Technical Data

3.5 Flash Memory Characteristics

Figure 7. Signal States

Table 8. Flash Memory Truth Table

Mode

X address enable, all rows are disabled when XE = 0

Y address enable, YMUX is disabled when YE = 0

Sense amplifier enable

Output enable, tri-state Flash data out bus when OE = 0

PROG

Defines program cycle

ERASE

Defines erase cycle

MAS1

Defines mass erase cycle, erase whole block

NVSTR

Defines non-volatile store cycle

Standby

Read

Word Program

Page Erase

Mass Erase

Table 9. IFREN Truth Table

Mode

IFREN = 1

IFREN = 0

Read

Read information block

Read main memory block

Word program

Program information block

Program main memory block

Page erase

Erase information block

Erase main memory block

Mass erase

Erase both block

Erase main memory block

Data Invalid State

Data1

Data2 Valid

Data

Tri-stated

Data3 Valid

Data2

Data3

Data1 Valid

Data Active

56F827 Technical Data

MOTOROLA

Table 10. Flash Timing Parameters

Operating Conditions:

= V

SSA

= 0 V, V

= V

DDA

= 3.03.6V, T

= 40

° to +85°C, C

50pF

Characteristic

Symbol

Min Typ

Max

Unit

Figure

Program time

prog*

Figure 8

Erase time

erase*

Figure 9

Mass erase time

me*

100

Figure 10

Endurance

One cycle is equal to an erase program and read.

CYC

10,000

20,000

cycles

Data Retention

@ 5000 cycles

RET

years

The following parameters should only be used in the Manual Word Programming Mode

PROG/ERASE to NVSTR set
up time

nvs*

Figure 8

Figure 9

Figure 10

NVSTR hold time

nvh*

Figure 8

Figure 9

NVSTR hold time (mass erase)

nvh1*

100

Figure 10

NVSTR to program set up time

pgs*

Figure 8

Recovery time

rcv*

Figure 8

Figure 9

Figure 10

Cumulative program

HV period

Thv is the cumulative high voltage programming time to the same row before next erase. The same address cannot

be programmed twice before next erase.

Figure 8

Program hold time

Parameters are guaranteed by design in smart programming mode and must be one cycle or greater.

*The Flash interface unit provides registers for the control of these parameters.

pgh

Figure 8

Address/data set up time

ads

Figure 8

Address/data hold time

adh

Figure 8

56F827 Technical Data

MOTOROLA

Figure 10. Flash Mass Erase Cycle

3.6 External Clock Operation

The 56F827 system clock can be derived from a crystal or an external system clock signal. To generate a
reference frequency using the internal oscillator, a reference crystal must be connected between the EXTAL
and XTAL pins.

3.6.1

Crystal Oscillator

The internal oscillator is also designed to interface with a parallel-resonant crystal resonator in the
frequency range specified for the external crystal in

Table 11

. In

Figure 11

a recommended crystal

oscillator circuit is shown. Follow the crystal supplier's recommendations when selecting a crystal,
because crystal parameters determine the component values required to provide maximum stability and
reliable start-up. The crystal and associated components should be mounted as close as possible to the
EXTAL and XTAL pins to minimize output distortion and start-up stabilization time.The internal 56F82x
oscillator circuitry is designed to have no external load capacitors present. As shown in

Figure 11

external load capacitors should be used.

The 56F82x components internally are modeled to provide a capacitive load on each of the oscillator pins
(XTAL and EXATL) of 10pF to 13pF over temperature and process variations. Using a typical value of
internal capacitance on these pins of 12pF and a value of 3pF as a typical circuit board trace capacitance
the parallel load capacitance presented to the crystal is 9pF. This is the value load capacitance that should
be used when selecting a crystal and determining the actual frequency of operation of the crystal oscillator
circuit.

XADR

YE=SE=OE=0

ERASE

NVSTR

Tnvs

Tnvh1

Trcv

Tme

MAS1

IFREN

External Clock Operation

MOTOROLA

56F827 Technical Data

Figure 11. Connecting to a Crystal Oscillator Circuit

3.6.2

Ceramic Resonator

It is also possible to drive the internal oscillator with a ceramic resonator, assuming the overall system
design can tolerate the reduced signal integrity. In

Figure 12

, a typical ceramic resonator circuit is shown.

resonator and components should be mounted as close as possible to the EXTAL and XTAL pins. The
internal 56F82x oscillator circuitry is designed to have no external load capacitors present. As shown in

Figure 11

no external load capacitors should be used.

Figure 12. Connecting a Ceramic Resonator

Note: Motorola recommends only two terminal ceramic resonators vs. three terminal
resonators (which contain an internal bypass capacitor to ground).

3.6.3

External Clock Source

The recommended method of connecting an external clock is given in

Figure 13

. The external clock

source is connected to XTAL and the EXTAL pin is held V

DDA

/2.

Figure 13. Connecting an External Clock Signal

Recommended External Crystal
Parameters:
R

= 1 to 3M

= 4Mhz (optimized for 4MHz)

EXTAL XTAL

Recommended Ceramic Resonator
Parameters:
R

= 1 to 3 M

= 4Mhz (optimized for 4MHz)

56F827

XTAL

EXTAL

External

DDA

Clock

56F827 Technical Data

MOTOROLA

Figure 14. External Clock Timing

3.6.4

Phase Locked Loop Timing

Table 11. External Clock Operation Timing Requirements

Operating Conditions:

SSIO

= V

SSA

= 0V, V

DDA

DDIO

=3.03.6V, V

= 2.252.75V, T

= 40

° to +85°C, C

50pF, f

= 80MHz

Characteristic

Symbol

Min

Typ

Max

Unit

Frequency of operation (external clock driver)

See

Figure 13

for details on using the recommended connection of an external clock driver.

osc

When using Time-of-Day (TOD), maximum external frequency is 6MHz.

MHz

Clock Pulse Width

The high or low pulse width must be no smaller than 6.25ns or the chip will not function.

Parameters listed are guaranteed by design.

6.25

Table 12. PLL Timing

Operating Conditions:

SSIO

= V

SSA

= 0V, V

DDA

DDIO

=3.03.6V, V

= 2.252.75V, T

= 40

° to +85°C, C

50pF, f

= 80MHz

Characteristic

Symbol

Min

Typ

Max

Unit

External reference crystal frequency for the PLL

An externally supplied reference clock should be as free as possible from any phase jitter for the PLL to work

correctly. The PLL is optimized for 4MHz input crystal.

osc

MHz

PLL output frequency

ZCLK may not exceed 80MHz. For additional information on ZCLK and

out

/2,

please refer to the OCCS chapter

in the User Manual. ZCLK = f

out

110

MHz

PLL stabilization time

-40

to +85

This is the minimum time required after the PLL set-up is changed to ensure reliable operation.

plls

External

Clock

Note: The midpoint is V

+ (V

)/2.

90%

50%

10%

90%

50%

10%

External Bus Asynchronous Timing

MOTOROLA

56F827 Technical Data

3.7 External Bus Asynchronous Timing

Table 13. External Bus Asynchronous Timing

1, 2

Operating Conditions:

SSIO

= V

SSA

= 0V, V

DDA

DDIO

=3.03.6V, V

= 2.252.75V, T

= 40

° to +85°C, C

50pF, f

= 80MHz

Timing is both wait state and frequency dependent. In the formulas listed, WS = the number of wait states and

T = Clock Period. For 80MHz operation, T = 12.5ns.
2.

Parameters listed are guaranteed by design.

To calculate the required access time for an external memory for any frequency < 80Mhz, use this formula:
Top = Clock period @ desired operating frequency
WS = Number of wait states
Memory Access Time = (Top*WS) + (Top- 11.5)

Characteristic

Symbol

Min

Max

Unit

Address Valid to WR Asserted

AWR

6.5

WR Width Asserted
Wait states = 0
Wait states > 0

7.5

(T*WS) + 7.5

--
--

ns
ns

WR Asserted to D0D15 Out Valid

WRD

T + 4.2

Data Out Hold Time from WR Deasserted

DOH

4.8

Data Out Set Up Time to WR Deasserted
Wait states = 0
Wait states > 0

DOS

2.2

(T*WS) + 6.4

--
--

ns
ns

RD Deasserted to Address Not Valid

RDA

Address Valid to RD Deasserted
Wait states = 0
Wait states > 0

ARDD

18.7

(T*WS) + 18.7

ns
ns

Input Data Hold to RD Deasserted

DRD

RD Assertion Width
Wait states = 0
Wait states > 0

(T*WS) + 19

--
--

ns
ns

Address Valid to Input Data Valid
Wait states = 0
Wait states > 0

--
--

(T*WS) + 1

ns
ns

Address Valid to RD Asserted

ARDA

-4.4

RD Asserted to Input Data Valid
Wait states = 0
Wait states > 0

RDD

--
--

2.4

(T*WS) + 2.4

ns
ns

WR Deasserted to RD Asserted

WRRD

6.8

RD Deasserted to RD Asserted

RDRD

WR Deasserted to WR Asserted

WRWR

14.1

RD Deasserted to WR Asserted

RDWR

12.8

56F827 Technical Data

MOTOROLA

3.8 Reset, Stop, Wait, Mode Select, and Interrupt Timing

Figure 15. External Bus Asynchronous Timing

Table 14. Reset, Stop, Wait, Mode Select, and Interrupt Timing

1, 5

Operating Conditions:

SSIO

= V

SSA

= 0V, V

DDA

DDIO

=3.03.6V, V

= 2.252.75V, T

= 40

° to +85°C, C

50pF, f

= 80MHz

Characteristic

Symbol

Min

Max

Unit

See

Figure

RESET Assertion to Address, Data and Control
Signals High Impedance

RAZ

Figure 16

Minimum RESET Assertion Duration

OMR Bit 6 = 0
OMR Bit 6 = 1

275,000T

128T

--
--

ns
ns

Figure 16

RESET De-assertion to First External Address Output

RDA

33T

34T

Figure 16

Edge-sensitive Interrupt Request Width

IRW

1.5T

Figure 17

IRQA, IRQB Assertion to External Data Memory
Access Out Valid, caused by first instruction execution
in the interrupt service routine

IDM

15T

Figure 18

IRQA, IRQB Assertion to General Purpose Output
Valid, caused by first instruction execution in the
interrupt service routine

16T

Figure 18

A0A15,

PS, DS

(See Note)

D0D15

Note: During read-modify-write instructions and internal instructions, the address lines do not change state.

Data In

Data Out

AWR

ARDA

ARDD

RDA

RDRD

RDWR

WRWR

DOS

WRD

WRRD

DOH

DRD

RDD

Reset, Stop, Wait, Mode Select, and Interrupt Timing

MOTOROLA

56F827 Technical Data

Figure 16. Asynchronous Reset Timing

IRQA Low to First Valid Interrupt Vector Address Out

recovery from Wait State

IRI

13T

Figure 19

IRQA Width Assertion to Recover from Stop State

Figure 20

Delay from IRQA Assertion to Fetch of first instruction
(exiting Stop)
OMR Bit 6 = 0
OMR Bit 6 = 1

--
--

275,000T

12T

ns
ns

Figure 20

Duration for Level Sensitive IRQA Assertion to Cause
the Fetch of First IRQA Interrupt Instruction (exiting
Stop)
OMR Bit 6 = 0
OMR Bit 6 = 1

IRQ

--
--

275,000T

12T

ns
ns

Figure 21

Delay from Level Sensitive IRQA Assertion to First
Interrupt Vector Address Out Valid (exiting Stop)
OMR Bit 6 = 0
OMR Bit 6 = 1

--
--

275,000T

12T

ns
ns

Figure 21

In the formulas, T = clock cycle. For an operating frequency of 80MHz, T = 12.5ns.

Circuit stabilization delay is required during reset when using an external clock or crystal oscillator in two cases:
· After power-on reset
· When recovering from Stop state

The minimum is specified for the duration of an edge-sensitive IRQA interrupt required to recover from the Stop state.

This is not the minimum required so that the IRQA interrupt is accepted.

The interrupt instruction fetch is visible on the pins only in Mode 3.

Parameters listed are guaranteed by design.

Table 14. Reset, Stop, Wait, Mode Select, and Interrupt Timing

1, 5

(Continued)

Operating Conditions:

SSIO

= V

SSA

= 0V, V

DDA

DDIO

=3.03.6V, V

= 2.252.75V, T

= 40

° to +85°C, C

50pF, f

= 80MHz

Characteristic

Symbol

Min

Max

Unit

See

Figure

First Fetch

A0A15,

D0D15

PS, DS,

RD, WR

RESET

First Fetch

RAZ

RDA

56F827 Technical Data

MOTOROLA

Figure 17. External Interrupt Timing (Negative-Edge-Sensitive)

Figure 18. External Level-Sensitive Interrupt Timing

Figure 19. Interrupt from Wait State Timing

Figure 20. Recovery from Stop State Using Asynchronous Interrupt Timing

IRQA,
IRQB

IRW

A0A15,

PS, DS,

RD, WR

IRQA,

IRQB

First Interrupt Instruction Execution

a) First Interrupt Instruction Execution

General

Purpose

I/O Pin

IRQA,

IRQB

b) General Purpose I/O

IDM

Instruction Fetch

IRQA,

IRQB

First Interrupt Vector

A0A15,

PS, DS,

RD, WR

IRI

Not IRQA Interrupt Vector

IRQA

A0A15,

PS, DS,

RD, WR

First Instruction Fetch

Serial Peripheral Interface (SPI) Timing

MOTOROLA

56F827 Technical Data

Figure 21. Recovery from Stop State Using IRQA Interrupt Service

3.9 Serial Peripheral Interface (SPI) Timing

Table 15. SPI Timing

Operating Conditions:

SSIO

= V

SSA

= 0V, V

DDA

DDIO

=3.03.6V, V

= 2.252.75V, T

= 40

° to +85°C, C

50pF, f

= 80MHz

Characteristic

Symbol

Min

Max

Unit

See Figure

Cycle time
Master
Slave

50
25

--
--

ns
ns

Figures

Enable lead time
Master
Slave

ELD

--
--

ns
ns

Figure

Enable lag time
Master
Slave

ELG

100

--
--

ns
ns

Figure

Clock (SCLK) high time
Master
Slave

24
12

--
--

ns
ns

Figures

Clock (SCLK) low time
Master
Slave

24.1

--
--

ns
ns

Figures

Data set-up time required for inputs
Master
Slave

--
--

ns
ns

Figures

Data hold time required for inputs
Master
Slave

0
2

--
--

ns
ns

Figures

Access time (time to data active from high-impedance state)
Slave

4.8

Figure

Disable time (hold time to high-impedance state)
Slave

3.7

15.2

Figure

Instruction Fetch

IRQA

A0A15
PS, DS,

RD, WR

First IRQA Interrupt

IRQ

56F827 Technical Data

MOTOROLA

1.Parameters listed are guaranteed by design.

Figure 22. SPI Master Timing (CPHA = 0)

Data Valid for outputs
Master
Slave (after enable edge)

--
--

4.5

20.4

ns
ns

Figures

Data invalid
Master
Slave

0
0

--
--

ns
ns

Figures

Rise time
Master
Slave

--
--

11.5
10.0

ns
ns

Figures

Fall time
Master
Slave

--
--

9.7
9.0

ns
ns

Figures

Table 15. SPI Timing

(Continued)

Operating Conditions:

SSIO

= V

SSA

= 0V, V

DDA

DDIO

=3.03.6V, V

= 2.252.75V, T

= 40

° to +85°C, C

50pF, f

= 80MHz

SCLK (CPOL = 0)

(Output)

SCLK (CPOL = 1)

(Output)

MISO

(Input)

MOSI

(Output)

MSB in

Bits 141

LSB in

Master MSB out

Bits 141

Master LSB out

(Input)

SS is held High on master

(ref)

Serial Peripheral Interface (SPI) Timing

MOTOROLA

56F827 Technical Data

Figure 23. SPI Master Timing (CPHA = 1)

Figure 24. SPI Slave Timing (CPHA = 0)

SCLK (CPOL = 0)

(Output)

SCLK (CPOL = 1)

(Output)

MISO

(Input)

MOSI

(Output)

MSB in

Bits 141

LSB in

Master MSB out

Bits 14 1

Master LSB out

(Input)

SS is held High on master

(ref)

SCLK (CPOL = 0)

(Input)

SCLK (CPOL = 1)

(Input)

MISO

(Output)

MOSI

(Input)

Slave MSB out

Bits 141

MSB in

Bits 141

LSB in

(Input)

Slave LSB out

ELG

ELD

56F827 Technical Data

MOTOROLA

Figure 25. SPI Slave Timing (CPHA = 1)

3.10 Analog-to-Digital Converter (ADC) Timing

Table 16. ADC Specifications and Timing

Operating Conditions:

SSIO

= V

SSA

= V

SSA_ADC

= 0V, V

DDA_ADC

= V

DDA

DDIO

=3.03.6V, V

= 2.252.75V, V

REFH

= 2.7VV

DDA

= 40

° to +85°C, C

50pF, f

= 80MHz

Characteristic

Symbol

Min

Typ

Max

Unit

ADC Input voltage

ADCIN

REFHI

Resolution

Bits

Integral Non-Linearity

INL

+/- 1

+/- 3

LSB

Differential Non-Linearity

DNL

+/- 0.4

+/- 1

LSB

Monotonicity

GUARANTEED

ADC internal clock

ADIC

0.5

2.5

MHz

Conversion range

REFLO

REFHI

Power-up time

ADPU

Conversion time

ADC

AIC

cycles

Sample time

ADS

AIC

cycles

Input capacitance

ADI

SCLK (CPOL = 0)

(Input)

SCLK (CPOL = 1)

(Input)

MISO

(Output)

MOSI

(Input)

Slave MSB out

Bits 141

MSB in

Bits 141

LSB in

(Input)

Slave LSB out

ELD

ELG

Analog-to-Digital Converter (ADC) Timing

MOTOROLA

56F827 Technical Data

Figure 26. Equivalent Analog Input Circuit

Parasitic capacitance due to package, pin to pin, and pin to package base coupling. (1.8pf)

Parasitic capacitance due to the chip bond pad, ESD protection devices and signal routing. (2.04pf)

Equivalent resistance for the ESD isolation resistor and the channel select mux. (500 ohms)

Sampling capacitor at the sample and hold circuit. Capacitor 4 is normally disconnected from the input and is
only connected to it at sampling time. (1pf)

Gain Error (transfer gain)

GAIN

0.95

1.00

1.10

Offset Voltage

OFFSET

-60

+15

+40

Total Harmonic Distortion

THD

Effective Number of Bits

ENOB

9.3

10.5

bit

Spurious Free Dynamic Range

SFDR

Signal-to-Noise plus Distortion

SINAD

ADC quiescent current

ADC

ADC quiescent current (power
down bit set high)

ADCPD

REF

quiescent current

VREF

REF

quiescent current (power

down bit set high)

VREFPD

REF

must be equal to or less than V

DDA

and must be greater than 2.7V. For optimal ADC performance, set V

REF

DDA

-0.3V.

Measured in 10-90% range.

LSB = Least Significant Bit.

Guaranteed by characterization.

AIC

= 1/

ADIC

Table 16. ADC Specifications and Timing

Operating Conditions:

SSIO

= V

SSA

= V

SSA_ADC

= 0V, V

DDA_ADC

= V

DDA

DDIO

=3.03.6V, V

= 2.252.75V, V

REFH

= 2.7VV

DDA

= 40

° to +85°C, C

50pF, f

= 80MHz

Characteristic

Symbol

Min

Typ

Max

Unit

ADC analog input

56F827 Technical Data

MOTOROLA

3.11 SSI Timing

Table 17. SSI Master Mode

Switching Characteristics

1. Master mode is internally generated clocks and frame syncs

Parameter

Symbol

Min

Typ

Max

Units

STCK frequency

2. Max clock frequency is IP_clk/4 = 40MHz / 4 = 10MHz for an 80MHz part.

MHz

STCK period

3. All the timings for the SSI are given for a non-inverted serial clock polarity (TSCKP=0 in SCR2 and

RSCKP=0 in SCSR) and a non-inverted frame sync (TFSI=0 in SCR2 and RFSI=0 in SCSR). If the
polarity of the clock and/or the frame sync have been inverted, all the timings remain valid by inverting
the clock signal STCK/SRCK and/or the frame sync STFS/SRFS in the tables and in the figures.

SCKW

100

STCK high time

SCKH

4. 50% duty cycle

STCK low time

SCKL

Output clock rise/fall time

Delay from STCK high to STFS (bl) high - Master

5. bl = bit length; wl = word length

TFSBHM

0.1

0.5

Delay from STCK high to STFS (wl) high - Master

TFSWHM

0.1

0.5

Delay from SRCK high to SRFS (bl) high - Master

RFSBHM

0.6

1.3

Delay from SRCK high to SRFS (wl) high - Master

RFSWHM

0.6

1.3

Delay from STCK high to STFS (bl) low - Master

TFSBLM

-1.0

-0.1

Delay from STCK high to STFS (wl) low - Master

TFSWLM

-1.0

-0.1

Delay from SRCK high to SRFS (bl) low - Master

RFSBLM

-0.1

Delay from SRCK high to SRFS (wl) low - Master

RFSWLM

-0.1

STCK high to STXD enable from high impedance - Master

TXEM

STCK high to STXD valid - Master

TXVM

STCK high to STXD not valid - Master

TXNVM

0.1

0.2

STCK high to STXD high impedance - Master

TXHIM

25.5

SRXD Setup time before SRCK low - Master

SRXD Hold time after SRCK low - Master

Synchronous Operation (in addition to standard internal clock parameters)

SRXD Setup time before STCK low - Master

TSM

SRXD Hold time after STCK low - Master

THM

SSI Timing

MOTOROLA

56F827 Technical Data

Figure 27. Master Mode Timing Diagram

Table 18. SSI Slave Mode

Switching Characteristics

Parameter

Symbol

Min

Typ

Max

Units

STCK frequency

MHz

STCK period

SCKW

100

STCK high time

SCKH

STCK low time

SCKL

Output clock rise/fall time

Delay from STCK high to STFS (bl) high - Slave

TFSBHS

0.1

Delay from STCK high to STFS (wl) high - Slave

TFSWHS

0.1

Delay from SRCK high to SRFS (bl) high - Slave

RFSBHS

0.1

Delay from SRCK high to SRFS (wl) high - Slave

RFSWHS

0.1

THM

TSM

RFSWLM

RFSWHM

RFBLM

RFSBHM

TXHIM

TXNVM

TXVM

TXEM

TFSWLM

TFSWHM

TFSBLM

TFSBHM

SCKL

SCKW

SCKH

First Bit

Last Bit

STCK output

STFS (bl) output

STFS (wl) output

STXD

SRCK output

SRFS (bl) output

SRFS (wl) output

SRXD

56F827 Technical Data

MOTOROLA

Delay from STCK high to STFS (bl) low - Slave

TFSBLS

-1

Delay from STCK high to STFS (wl) low - Slave

TFSWLS

-1

Delay from SRCK high to SRFS (bl) low - Slave

RFSBLS

-46

Delay from SRCK high to SRFS (wl) low - Slave

RFSWLS

-46

STCK high to STXD enable from high impedance - Slave

TXES

STCK high to STXD valid - Slave

TXVS

STFS high to STXD enable from high impedance (first bit) - Slave

FTXES

5.5

STFS high to STXD valid (first bit) - Slave

FTXVS

STCK high to STXD not valid - Slave

TXNVS

STCK high to STXD high impedance - Slave

TXHIS

28.5

SRXD Setup time before SRCK low - Slave

SRXD Hold time after SRCK low - Slave

Synchronous Operation (in addition to standard external clock parameters)

SRXD Setup time before STCK low - Slave

TSS

SRXD Hold time after STCK low - Slave

THS

Slave mode is externally generated clocks and frame syncs

Max clock frequency is IP_clk/4 = 40MHz / 4 = 10MHz for an 80MHz part.

All the timings for the SSI are given for a non-inverted serial clock polarity (TSCKP=0 in SCR2 and RSCKP=0 in

SCSR) and a non-inverted frame sync (TFSI=0 in SCR2 and RFSI=0 in SCSR). If the polarity of the clock and/or the
frame sync have been inverted, all the timings remain valid by inverting the clock signal STCK/SRCK and/or the frame
sync STFS/SRFS in the tables and in the figures.

50% duty cycle

bl = bit length; wl = word length

Table 18. SSI Slave Mode

Switching Characteristics (Continued)

Parameter

Symbol

Min

Typ

Max

Units

Quad Timer Timing

MOTOROLA

56F827 Technical Data

Figure 28. Slave Mode Clock Timing

3.12 Quad Timer Timing

Table 19. Timer Timing

1, 2

Operating Conditions:

SSIO

= V

SSA

= 0V, V

DDA

DDIO

=3.03.6V, V

= 2.252.75V, T

= 40

° to +85°C, C

50pF, f

= 80MHz

In the formulas listed, T = clock cycle. For 80MHz operation, T = 12.5ns.

Parameters listed are guaranteed by design.

Characteristic

Symbol

Min

Max

Unit

Timer input period

4T+6

Timer input high/low period

INHL

2T+3

Timer output period

OUT

Timer output high/low period

OUTHL

THS

TSS

RFSWLS

RFSWHS

RFBLS

RFSBHS

TXHIS

TXNVS

FTXVS

TXVS

FTXES

TXES

TFSWLS

TFSWHS

TFSBLS

TFSBHS

SCKL

SCKW

SCKH

First Bit

Last Bit

STCK input

STFS (bl) input

STFS (wl) input

STXD

SRCK input

SRFS (bl) input

SRFS (wl) input

SRXD

56F827 Technical Data

MOTOROLA

3.13 Serial Communication Interface (SCI) Timing

Figure 30. RXD Pulse Width

Figure 31. TXD Pulse Width

Figure 29. Quad Timer Timing

Table 20. SCI Timing

Operating Conditions:

SSIO

= V

SSA

= 0V, V

DDA

DDIO

=3.03.6V, V

= 2.252.75V, T

= 40

° to +85°C, C

50pF, f

= 80MHz

Characteristic

Symbol

Min

Max

Unit

Baud Rate

MAX

is the frequency of operation of the system clock in MHz.

MAX

*2.5)/(80)

Mbps

RXD

Pulse Width

The RXD pin in SCI0 is named RXD0 and the RXD pin in SCI1 is named RXD1.

RXD

0.965/BR

1.04/BR

TXD

Pulse Width

The TXD pin in SCI0 is named TXD0 and the TXD pin in SCI1 is named TXD1.

Parameters listed are guaranteed by design.

TXD

0.965/BR

1.04/BR

Timer Inputs

Timer Outputs

INHL

OUT

OUTHL

RXD

SCI receive

data pin

(Input)

RXD

TXD

SCI receive

data pin

(Input)

TXD

JTAG Timing

MOTOROLA

56F827 Technical Data

3.14 JTAG Timing

Table 21. JTAG Timing

1, 3

Operating Conditions:

SSIO

= V

SSA

= 0V, V

DDA

DDIO

=3.03.6V, V

= 2.252.75V, T

= 40

° to +85°C, C

50pF, f

= 80MHz

Timing is both wait state and frequency dependent. For the values listed, T = clock cycle. For 80MHz

operation, T = 12.5ns.

Characteristic

Symbol

Min

Max

Unit

TCK frequency of operation

TCK frequency of operation must be less than 1/8 the processor rate.

Parameters listed are guaranteed by design.

MHz

TCK cycle time

100

TCK clock pulse width

TMS, TDI data set-up time

0.4

TMS, TDI data hold time

1.2

TCK low to TDO data valid

26.6

TCK low to TDO tri-state

23.5

TRST assertion time

TRST

DE assertion time

Figure 32. Test Clock Input Timing Diagram

TCK

(Input)

= V

+ (V

)/2

Package and Pin-Out Information 56F827

MOTOROLA

56F827 Technical Data

Part 4 Packaging

4.1 Package and Pin-Out Information 56F827

This section contains package and pin-out information for the 128-pin LQFP configuration of the 56F827.

Figure 36. Top View, 56F827 128-pin LQFP Package

PIN 102

PIN 1

PIN 39

PIN 64

TXD2

RXD1

TXD1

RXD0

TXD0

TA3
TA2
TA1
TA0

VDDIO

VSSIO

VSS

VDD

GPIOB7
GPIOB6
GPIOB5
GPIOB4
GPIOB3

GPIOB2
GPIOB1
GPIOB0

D0
D1
D2
D3

Motorola

56F827

ORIENTATION

MARK

DDI

SSI

D10

D12

D13

D14

D15

VSS

VSSA_ADC
VDDA
VSSA
XTAL
EXTAL

VSSIO
CLKO
VDDIO
SRD
SRFS
SRCK
STD
STFS
STCK
IRQB
TDI
TDO
TMS

TRST
TCK
TCS
RESET
DE
IRQA
EXTBOOT

DDI

SSI

A10

A12

A13

A14

A15

VREFLO

EEF

DDA

VSS

DDI

VSSI

VPP

I
O

RXD2

56F827 Technical Data

MOTOROLA

Table 22. 56F827 Pin Identification by Pin Number

Pin No.

Signal Name

Pin No.

Signal Name

Pin No.

Signal Name

Pin No.

Signal Name

A10

REFP

GPIOD1

A11

REFN

GPIOD0

A12

REFHI

DDIO

A13

REFMID

100

MISO

SSIO

A14

DDA_ADC

101

MOSI

A15

ANA0

102

SCLK

EXTBOOT

ANA1

103

RXD2

IRQA

ANA2

104

TXD2

D10

ANA3

105

RXD1

D11

RESET

ANA4

106

TXD1

D12

TCS

ANA5

107

RXD0

D13

TCK

ANA6

108

TXD0

D14

TRST

ANA7

109

TA3

D15

TMS

ANA8

110

TA2

TDO

ANA9

111

TA1

TDI

112

TA0

IRQB

113

DDIO

STCK

DDIO

114

SSIO

STFS

SSIO

115

STD

PCS2

116

SRCK

PCS3

117

GPIOB7

SRFS

PCS4

118

GPIOB6

SRD

PCS5

119

GPIOB5

DDIO

PCS6

120

GPIOB4

CLKO

PCS7

121

GPIOB3

SSIO

VPP

122

GPIOB2

EXTAL

GPIOD7

123

GPIOB1

XTAL

GPIOD6

124

GPIOB0

DDIO

SSA

GPIOD5

125

SSIO

DDA

GPIOD4

126

SSA_ADC

GPIOD3

127

REFLO

GPIOD2

128

Package and Pin-Out Information 56F827

MOTOROLA

56F827 Technical Data

Figure 37. 128-pin LQFP Mechanical Information

NOTES:
1. DIMENSIONING AND TOLERANCING PER ASME

Y14.5M, 1994.

2. CONTROLLING DIMENSION: MILLIMETER.
3. DATUM PLANE H IS LOCATED AT BOTTOM OF LEAD

AND IS COINCIDENT WITH THE LEAD WHERE THE
LEAD EXITS THE PLASTIC BODY AT THE BOTTOM OF
THE PARTING LINE.

4. DATUMS A, B, AND D TO BE DETERMINED AT DATUM

PLANE H.

5. DIMENSIONS D AND E TO BE DETERMINED AT

SEATING PLANE C.

6. DIMENSIONS D1 AND E1 DO NOT INCLUDE MOLD

PROTRUSION. ALLOWABLE PROTRUSION IS 0.25 PER
SIDE. DIMENSIONS D1 AND E1 DO INCLUDE MOLD
MISMATCH AND ARE DETERMINED AT DATUM
PLANE H.

7. DIMENSION b DOES NOT INCLUDE DAMBAR

PROTRUSION. DAMBAR PROTRUSION SHALL NOT
CAUSE THE b DIMENSION TO EXCEED 0.35.

DIM

MILLIMETERS
MIN

MAX

---

1.60

0.05

0.15

1.35

1.45

0.17

0.27

0.17

0.23

0.09

0.20

0.09

0.16

22.00 BSC

20.00BSC

0.50 BSC

16.00 BSC

14.00 BSC

0.45

0.75

1.00 REF

0.50 REF

0.20

---

0.08

---

0.08

0.20

---

Case Outline - 1129-01

128

103

102

56F827 Technical Data

MOTOROLA

Part 5 Design Considerations

5.1 Thermal Design Considerations

An estimation of the chip junction temperature, T

, in

°C can be obtained from the equation:

Equation 1:

Where:

= ambient temperature °C

= package junction-to-ambient thermal resistance °C/W

= power dissipation in package

Historically, thermal resistance has been expressed as the sum of a junction-to-case thermal resistance and
a case-to-ambient thermal resistance:

Equation 2:

Where:

= package junction-to-ambient thermal resistance °C/W

= package junction-to-case thermal resistance °C/W

= package case-to-ambient thermal resistance °C/W

is device-related and cannot be influenced by the user. The user controls the thermal environment to

change the case-to-ambient thermal resistance, R

. For example, the user can change the air flow around

the device, add a heat sink, change the mounting arrangement on the Printed Circuit Board (PCB), or
otherwise change the thermal dissipation capability of the area surrounding the device on the PCB. This
model is most useful for ceramic packages with heat sinks; some 90% of the heat flow is dissipated through
the case to the heat sink and out to the ambient environment. For ceramic packages, in situations where the
heat flow is split between a path to the case and an alternate path through the PCB, analysis of the device
thermal performance may need the additional modeling capability of a system level thermal simulation tool.

The thermal performance of plastic packages is more dependent on the temperature of the PCB to which the
package is mounted. Again, if the estimations obtained from R

do not satisfactorily answer whether the

thermal performance is adequate, a system level model may be appropriate.

Definitions:

A complicating factor is the existence of three common definitions for determining the junction-to-case
thermal resistance in plastic packages:

Measure the thermal resistance from the junction to the outside surface of the package (case) closest
to the chip mounting area when that surface has a proper heat sink. This is done to minimize
temperature variation across the surface.

Measure the thermal resistance from the junction to where the leads are attached to the case. This
definition is approximately equal to a junction to board thermal resistance.

Use the value obtained by the equation (T

)/P

where T

is the temperature of the package

case determined by a thermocouple.

(

)

Electrical Design Considerations

MOTOROLA

56F827 Technical Data

The thermal characterization parameter is measured per JESD51-2 specification using a 40-gauge type T
thermocouple epoxied to the top center of the package case. The thermocouple should be positioned so that
the thermocouple junction rests on the package. A small amount of epoxy is placed over the thermocouple
junction and over about 1mm of wire extending from the junction. The thermocouple wire is placed flat
against the package case to avoid measurement errors caused by cooling effects of the thermocouple wire.

When heat sink is used, the junction temperature is determined from a thermocouple inserted at the interface
between the case of the package and the interface material. A clearance slot or hole is normally required in
the heat sink. Minimizing the size of the clearance is important to minimize the change in thermal
performance caused by removing part of the thermal interface to the heat sink. Because of the experimental
difficulties with this technique, many engineers measure the heat sink temperature and then back-calculate
the case temperature using a separate measurement of the thermal resistance of the interface. From this case
temperature, the junction temperature is determined from the junction-to-case thermal resistance.

5.2 Electrical Design Considerations

Use the following list of considerations to assure correct operation:

Provide a low-impedance path from the board power supply to each V

DD,

DDIO,

and V

DDA

pin on

the hybrid controller, and from the board ground to each V

SS,

SSIO,

and V

SSA

(GND) pin.

The minimum bypass requirement is to place 0.1

µF capacitors positioned as close as possible to the

package supply pins. The recommended bypass configuration is to place one bypass capacitor on
each of the V

pairs, including V

DDA

SSA

and V

DDIO

SSIO.

Ceramic and tantalum

capacitors tend to provide better performance tolerances.

Ensure that capacitor leads and associated printed circuit traces that connect to the chip V

DD,

DDIO,

and V

DDA

and V

SS,

SSIO,

and V

SSA

(GND) pins are less than 0.5 inch per capacitor lead.

Bypass the V

and V

layers of the PCB with approximately 100

µF, preferably with a high-grade

capacitor such as a tantalum capacitor.

Because the controller's output signals have fast rise and fall times, PCB trace lengths should be
minimal.

Consider all device loads as well as parasitic capacitance due to PCB traces when calculating
capacitance. This is especially critical in systems with higher capacitive loads that could create
higher transient currents in the V

and V

circuits.

CAUTION

This device contains protective circuitry to guard
against damage due to high static voltage or
electrical fields. However, normal precautions are
advised to avoid application of any voltages higher
than maximum rated voltages to this high-impedance
circuit. Reliability of operation is enhanced if unused
inputs are tied to an appropriate voltage level.

56F827 Technical Data

MOTOROLA

Take special care to minimize noise levels on the VREF, V

DDA

and V

SSA

pins.

When using Wired-OR mode on the SPI or the IRQx pins, the user must provide an external pull-
up device.

Designs that utilize the TRST pin for JTAG port or OnCE module functionality (such as
development or debugging systems) should allow a means to assert TRST whenever RESET is
asserted, as well as a means to assert TRST independently of RESET. TRST must be asserted at
power up for proper operation. Designs that do not require debugging functionality, such as
consumer products, TRST should be tied low.

Because the Flash memory is programmed through the JTAG/OnCE port, designers should provide
an interface to this port to allow in-circuit Flash programming.

Part 6 Ordering Information

Table 23

lists the pertinent information needed to place an order. Consult a Motorola Semiconductor sales

office or authorized distributor to determine availability and to order parts.

Table 23. 56F827 Ordering Information

Part

Supply

Voltage

Package Type

Pin

Count

Frequency

(MHz)

Order Number

56F827

2.252.75V

Low Profile Quad Flat Pack
(LQFP)

128

DSP56F827FG80

DSP56F827/D

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Document Outline

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Document Outline

ÐÐ»ÐµÐºÑ‚Ñ€Ð¾Ð½Ð½Ñ‹Ð¹ ÐºÐ¾Ð¼Ð¿Ð¾Ð½ÐµÐ½Ñ‚: DSP56F827FG80