HC908JB8AD/D
Rev. 0, 4/2002

Addendum to
MC68HC908JB8
Technical Data

Addendum

This addendum provides additional information to the

MC68HC908JB8 Technical Data, Rev. 2
(Motorola document number MC68HC908JB8/D),

MC68HC08JB8A

The MC68HC08JB8A is the ROM part equivalent to the MC68HC908JB8. The
entire MC68HC908JB8 data book apply to this ROM device, with exceptions
outlined in this addendum.

MCU Block Diagram

Figure 1

shows the block diagram of the MC68HC08JB8A.

Memory Map

The MC68HC08JB8A has 8,192 bytes of user ROM from $DC00 to $FBFF, and
16 bytes of user ROM vectors from $FFF0 to $FFFF. On the MC68HC908JB8,
these memory locations are FLASH memory.

Figure 2

shows the memory map of the MC68HC08JB8A.

Table 1. Summary of MC68HC08JB8A and MC68HC908JB8 Differences

MC68HC08JB8A

MC68HC908JB8

Memory ($DC00$FBFF)

8,192 bytes ROM

8,192 bytes FLASH

User vectors ($FFF0$FFFF)

16 bytes ROM

16 bytes FLASH

Registers at $FE08 and $FF09

Not used;

locations are reserved.

FLASH related registers.
$FE08 -- FLCR
$FF09 -- FLBPR

Monitor ROM
($FC00$FDFF and $FE10$FFDF)

$FC00$FDFF: Not used.
$FE10$FFDF: Used for

testing purposes only.

Used for testing and FLASH

programming/erasing.

OSC1 and OSC2 pins

level (5V logic)

REG

level (3.3V logic)

HC908JB8AD/D

Addendum to MC68HC908JB8 Technical Data

MOTOROLA

gure 1. MC68HC08JB8A

ock D

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19

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M --

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6

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DDRA

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(
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) (4

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)

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T

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PTB

DDRB

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PTD

DDRD

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(

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(2)

ins have i

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(3)

ins have sof

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ware conf

igurable

pull-up device.

(4)

ins

are op

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out

put

(5)

ins have 10

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(6)

ins have 25

sink capabilit

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MC68HC

908JB8

HC908JB8AD/D

MC68HC08JB8A

MOTOROLA

Addendum to MC68HC908JB8 Technical Data

$0000

$003F

I/O Registers

64 Bytes

$0040

$013F

RAM

256 Bytes

$0140

$DBFF

Unimplemented

56,000 Bytes

$DC00

$FBFF

ROM

8,192 Bytes

$FC00

$FDFF

Unimplemented

512 Bytes

$FE00

Break Status Register (BSR)

$FE01

Reset Status Register (RSR)

$FE02

Reserved

$FE03

Break Flag Control Register (BFCR)

$FE04

Interrupt Status Register 1 (INT1)

$FE05

Reserved

$FE06

Reserved

$FE07

Reserved

$FE08

Reserved

$FE09

Reserved

$FE0A

Reserved

$FE0B

Reserved

$FE0C

Break Address High Register (BRKH)

$FE0D

Break Address Low Register (BRKL)

$FE0E

Break Status and Control Register (BRKSCR)

$FE0F

Reserved

$FE10

$FFDF

Monitor ROM

464 Bytes

$FFE0

$FFEF

Reserved

16 Bytes

$FFF0

$FFFF

ROM Vectors

16 Bytes

Figure 2. MC68HC08JB8A Memory Map

HC908JB8AD/D

Addendum to MC68HC908JB8 Technical Data

MOTOROLA

Reserved Registers

The two registers at $FE08 and $FE09 are reserved locations on the
MC68HC08JB8A.

On the MC68HC908JB8, these two locations are the FLASH control register
and the FLASH block protect register respectively.

Monitor ROM

The monitor program (monitor ROM: $FE10$FFDF) on the MC68HC08JB8A
is for device testing only. $FC00$FDFF are unused.

Electrical
Specifications

Electrical specifications for the MC68HC908JB8 apply to the MC68HC08JB8A,
except for the parameters indicated below.

DC Electrical
Characteristics

Table 2. DC Electrical Characteristics

Characteristic

(1)

Symbol

Min

Typ

(2)

Max

Unit

Regulator output voltage

REG

3.0

3.3

3.6

Output high voltage (I

Load

= 2.0 mA)

PTA0PTA7, PTB0PTB7, PTC0PTC7,
PTE0PTE2

REG

0.8

Output low voltage

Load

= 1.6 mA) All I/O pins

Load

= 25 mA) PTD0PTD1 in ILDD mode

Load

= 10 mA) PTE3PTE4 with USB disabled

--
--
--

0.4
0.5
0.4

Input high voltage

All ports, OSC1
IRQ, RST

0.7

REG

0.7

--
--

REG

Input low voltage

All ports, OSC1
IRQ, RST

--
--

0.3

REG

0.3

Output low current (V

= 2.0 V)

PTD2PTD5 in LDD mode

12 (17) 1

7 (22) 22 (27) mA

supply current, V

= 5.25V, f

= 3MHz

Run, with low speed USB

(3)

Run, with USB suspended

(3)

Wait, with low speed USB

(4)

Wait, with USB suspended

(4)

Stop

(5)

°C to 70°C

6.0 (5.0)

5.5 (4.5)

4.0 (3.0)

3.0 (2.5)

7.5

6.5

5.0

4.0

100

µA

HC908JB8AD/D

MC68HC08JB8A

MOTOROLA

Addendum to MC68HC908JB8 Technical Data

Memory
Characteristics

I/O ports Hi-Z leakage current

± 10

µA

Input current

± 1

µA

Capacitance

Ports (as input or output)

Out

--
--

POR re-arm voltage

(6)

POR

100

POR rise-time ramp rate

(7)

POR

0.035

V/ms

Monitor mode entry voltage

1.4

Pullup resistors

Port A, port B, port C, PTE0PTE2, RST, IRQ
PTE3PTE4 (with USB module disabled)
D (with USB module enabled)

1.2

1.5

2.0

LVI reset

LVR

2.8 (2.4)

3.3 (2.7)

3.8 (3.0)

(8)

1. V

= 4.0 to 5.5 Vdc, V

= 0 Vdc, T

= T

to T

, unless otherwise noted.

2. Typical values reflect average measurements at midpoint of voltage range, 25

°C only.

3. Run (operating) I

measured using external square wave clock source (f

XCLK

= 6 MHz). All inputs 0.2 V from rail. No dc

loads. Less than 100 pF on all outputs. C

= 20 pF on OSC2. All ports configured as inputs. OSC2 capacitance linearly

affects run I

. Measured with all modules enabled.

4. Wait I

measured using external square wave clock source (f

XCLK

= 6 MHz); all inputs 0.2 V from rail; no dc loads; less

than 100 pF on all outputs. C

= 20 pF on OSC2; 15 k

± 5% termination resistors on D+ and D pins; all ports configured

as inputs; OSC2 capacitance linearly affects wait I

5. STOP I

measured with USB in suspend mode; OSC1 grounded; transceiver pullup resistor of 1.5 k

± 5% between V

REG

and D pins and 15 k

± 5% termination resistor on D+ pin; no port pins sourcing current.

6. Maximum is highest voltage that POR is guaranteed.
7. If minimum V

REG

is not reached before the internal POR reset is released, RST must be driven low externally until minimum

REG

is reached.

8. The numbers in parenthesis are MC68HC08JB8 (non-A part) values.

Table 2. DC Electrical Characteristics

Characteristic

(1)

Symbol

Min

Typ

(2)

Max

Unit

Table 3. Memory Characteristics

Characteristic

Symbol

Min

Max

Unit

RAM data retention voltage

RDR

1.3

Notes:

Since MC68HC08JB8A is a ROM device, FLASH memory electrical characteristics do not apply.

HC908JB8AD/D

Addendum to MC68HC908JB8 Technical Data

MOTOROLA

MC68HC08JB8A
Order Numbers

These part numbers are generic numbers only. To place an order, ROM code
must be submitted to the ROM Processing Center (RPC).

MC68HC08JB8A and MC68HC08JB8 Differences

The MC68HC08JB8A and MC68HC08JB8 are identical devices, except for the
following:

Table 4. MC68HC08JB8A Order Numbers

MC order number

Package

Operating

temperature range

MC68HC08JB8AJP

20-pin PDIP

°C to +70 °C

MC68HC08JB8AJDW

20-pin SOIC

°C to +70 °C

MC68HC08JB8AADW

28-pin SOIC

°C to +70 °C

MC68HC08JB8AFB

44-pin QFP

°C to +70 °C

Table 5. MC68HC08JB8A and MC68HC08JB8 Differences

MC68HC08JB8A

MC68HC08JB8

OSC1 and OSC2 pins

level (5V logic)

REG

level (3.3V logic)

Output low current on PTD2PTD5
in LDD mode

See

Table 2 . DC Electrical Characteristics

The numbers in parenthesis are MC68HC08JB8 values.

Operating I

currents

LVI trip points

Information in this document is provided solely to enable system and software

implementers to use Motorola products. There are no express or implied copyright

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integrated circuits based on the information in this document.

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herein. Motorola makes no warranty, representation or guarantee regarding the

suitability of its products for any particular purpose, nor does Motorola assume any

liability arising out of the application or use of any product or circuit, and specifically

disclaims any and all liability, including without limitation consequential or incidental

damages. "Typical" parameters which may be provided in Motorola data sheets

and/or specifications can and do vary in different applications and actual

performance may vary over time. All operating parameters, including "Typicals"

must be validated for each customer application by customer's technical experts.

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HC908JB8AD/D
Rev. 0
4/2003

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