Document Outline
- Introduction
- 33887 Simplified Application Diagram
- 33887 Simplified Internal Block Diagram
- HSOP Terminal Definitions
- PQFN Terminal Definitions
- SOICW-EP Terminal Definitiions
- Maximum Ratings
- Static Electrical Characteristics
- Dynamic Electrical Characteristics
- Timing Diagrams
- Electrical Performance Curves
- Typical Switching Waveforms
- Truth Table
- System/Application Information
- Introduction
- Functional Terminal Description
- Performance Features
- Package Information
- Applications
- Package Dimensions
Simplified Application Diagram
5.0 V
V+
MOTOR
MCU
33887
IN
OUT
OUT
OUT
OUT
OUT
OUT2
OUT1
V+
CCP
PGND
AGND
FS
IN1
EN
D1
IN2
D2
FB
A/D
33887
33887 Simplified Application Diagram
MOTOROLA
SEMICONDUCTOR TECHNICAL DATA
Motorola, Inc. 2004
Document order number: MC33887
Rev 9.0, 10/2004
33887
5.0 A H-Bridge with Load Current
Feedback
The 33887 is a monolithic H-Bridge Power IC with a load current feedback
feature making it ideal for closed-loop DC motor control. The IC incorporates
internal control logic, charge pump, gate drive, and low R
DS(ON)
MOSFET
output
circuitry. The 33887 is able to control inductive loads with continuous
DC load currents up to 5.0 A, and with peak current active limiting between
5.2 A and 7.8 A. Output loads can be pulse width modulated (PWM-ed) at
frequencies up to 10 kHz. The load current feedback feature provides a
proportional (1/375th of the load current) constant-current output suitable for
monitoring by a microcontroller's A/D input. This feature facilitates the design
of closed-loop torque/speed control as well as open load detection.
A Fault Status output terminal reports undervoltage, short circuit, and
overtemperature conditions. Two independent inputs provide polarity control
of two half-bridge totem-pole outputs. Two disable inputs force the H-Bridge
outputs to tri-state (exhibit high impedance).
The 33887 is parametrically specified over a temperature range of
-40
C
T
A
125
C and a voltage range of 5.0 V
V+
28 V. The IC can also
be operated up to 40 V with derating of the specifications.
Features
5.0 V to 40 V Continuous Operation
120 m
R
DS(ON)
H-Bridge MOSFETs
TTL/CMOS Compatible Inputs
PWM Frequencies up to 10 kHz
Active Current Limiting (Regulation) via Internal Constant OFF-Time
PWM (with Temperature-Dependent Threshold Reduction)
Output Short Circuit Protection (Short to V+ or Short to GND)
Undervoltage Shutdown
Fault Status Reporting
Sleep Mode with Current Draw
50 A (Inputs Floating or Set to Match
Default Logic States)
Pb-Free Packaging Designated by Suffix Codes VW and PNB
5.0 A H-BRIDGE WITH LOAD
CURRENT FEEDBACK
ORDERING INFORMATION
Device
Temperature
Range (T
A
)
Package
MC33887DH/R2
-40C to 125C
-40C to 125C
-40C to 125C
20 HSOP
PC33887VW/R2
MC33887PNB/R2
36 PQFN
MC33887DWB/R2
54 SOICW-EP
DWB SUFFIX
CASE 1390-01
54-TERMINAL SOICW-EP
DH SUFFIX
VW (Pb-FREE) SUFFIX
CASE 979-04
20-TERMINAL HSOP
PNB (Pb-FREE) SUFFIX
CASE 1503-01
36-TERMINAL PQFN
33887 Simplified Application Diagram
Bottom View
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33887
MOTOROLA ANALOG INTEGRATED CIRCUIT DEVICE DATA
2
Figure 1. 33887 Simplified Internal Block Diagram
Over
Temperature
Gate Drive
Current Limit,
Ov ercurrent
Sens e, &
Feedback
Circuit
Charge Pump
Undervoltage
OUT1
OUT2
FB
Ccp
VPWR
PGND
5.0 V
Regulator
IN1
IN2
D1
D2
FS
AGND
Control
Logic
80 uA
(each)
25 uA
C
CP
80
A
(each)
25
A
Over-
temperature
EN
V+
Charge Pump
Low-Side
Current Limit,
Short Circuit
Sense, and
Current Feedback
Circuit
Undervoltage
Protection
Overtemperature
Detection
Gate Drive
Control
Logic
5.0 V
Regulator
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MOTOROLA ANALOG INTEGRATED CIRCUIT DEVICE DATA
33887
3
EN
AGND
IN2
D1
C
CP
V+
OUT2
OUT2
D2
PGND
PGND
FS
V+
OUT1
OUT1
FB
PGND
PGND
IN1
V+
1
2
3
4
5
6
7
8
9
10
20
19
16
15
14
13
12
11
18
17
Tab
Tab
HSOP TERMINAL DEFINITIONS
A functional description of each terminal can be found in the System/Application Information section,
page 19
.
Terminal
Terminal
Name
Formal Name
Definition
1
AGND
Analog Ground
Low-current analog signal ground.
2
FS
Fault Status for H-Bridge
Open drain active LOW Fault Status output requiring a pullup resistor to 5.0 V.
3
IN1
Logic Input Control 1
Logic input control of OUT1 (i.e., IN1 logic HIGH = OUT1 HIGH).
4, 5, 16
V+
Positive Power Supply
Positive supply connections
6, 7
OUT1
H-Bridge Output 1
Output 1 of H-Bridge.
8
FB
Feedback for H-Bridge
Current sensing feedback output providing ground referenced 1/375th (0.00266)
of H-Bridge high-side current.
912
PGND
Power Ground
High-current power ground.
13
D2
Disable 2
Active LOW input used to simultaneously tri-state disable both H-Bridge outputs.
When D2 is Logic LOW, both outputs are tri-stated.
14, 15
OUT2
H-Bridge Output 2
Output 2 of H-Bridge.
17
C
CP
Charge Pump Capacitor
External reservoir capacitor connection for internal charge pump capacitor.
18
D1
Disable 1
Active HIGH input used to simultaneously tri-state disable both H-Bridge outputs.
When D1 is Logic HIGH, both outputs are tri-stated.
19
IN2
Logic Input Control 2
Logic input control of OUT2 (i.e., IN2 logic HIGH = OUT2 HIGH).
20
EN
Enable
Logic input Enable control of device (i.e., EN logic HIGH = full operation, EN logic
LOW = Sleep Mode).
Tab/Pad
Thermal
Interface
Exposed Pad Thermal
Interface
Exposed pad thermal interface for sinking heat from the device.
Note Must be DC-coupled to analog ground and power ground via very low
impedance path to prevent injection of spurious signals into IC substrate.
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33887
MOTOROLA ANALOG INTEGRATED CIRCUIT DEVICE DATA
4
D2
NC
28
27
26
25
24
23
22
21
2
3
4
5
6
7
8
9
11
12
13
14
15
16
17
18
36
35
34
33
32
31
30
29
PGND
PGND
PGND
PGND
PGND
PGND
IN2
D1
EN
V+
V+
NC
AGND
FS
V+
C
CP
V+
OU
T2
OU
T2
NC
OU
T2
OU
T2
V+
IN1
V+
OUT
1
OUT
1
NC
OUT
1
OUT
1
20
FB
19
NC
10
NC
1
NC
Transparent Top View of Package
PQFN TERMINAL DEFINITIONS
A functional description of each terminal can be found in the System/Application Information section,
page 19
.
Terminal
Terminal
Name
Formal Name
Definition
1, 7, 10, 16,
19, 28, 31
NC
No Connect
No internal connection to this terminal.
2
D1
Disable 1
Active HIGH input used to simultaneously tri-state disable both H-Bridge
outputs. When D1 is Logic HIGH, both outputs are tri-stated.
3
IN2
Logic Input Control 2
Logic input control of OUT2 (i.e., IN2 logic HIGH = OUT2 HIGH).
4
EN
Enable
Logic input Enable control of device (i.e., EN logic HIGH = full operation,
EN logic LOW = Sleep Mode).
5, 6, 12, 13, 34, 35
V+
Positive Power Supply
Positive supply connections.
8
AGND
Analog Ground
Low-current analog signal ground.
9
FS
Fault Status for H-Bridge
Open drain active LOW Fault Status output requiring a pullup resistor to
5.0 V.
11
IN1
Logic Input Control 1
Logic input control of OUT1 (i.e., IN1 logic HIGH = OUT1 HIGH).
14, 15, 17, 18
OUT1
H-Bridge Output 1
Output 1 of H-Bridge.
20
FB
Feedback for H-Bridge
Current feedback output providing ground referenced 1/375th ratio of
H-Bridge high-side current.
2126
PGND
Power Ground
High-current power ground.
27
D2
Disable 2
Active LOW input used to simultaneously tri-state disable both H-Bridge
outputs. When D2 is Logic LOW, both outputs are tri-stated.
29, 30, 32, 33
OUT2
H-Bridge Output 2
Output 2 of H-Bridge.
36
C
CP
Charge Pump Capacitor
External reservoir capacitor connection for internal charge pump capacitor.
Pad
Thermal
Interface
Exposed Pad Thermal
Interface
Exposed pad thermal interface for sinking heat from the device.
Note Must be DC-coupled to analog ground and power ground via very low
impedance path to prevent injection of spurious signals into IC substrate.
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MOTOROLA ANALOG INTEGRATED CIRCUIT DEVICE DATA
33887
5
PGND
NC
V+
V+
V+
V+
NC
NC
NC
NC
C
CP
D1
IN2
EN
NC
NC
NC
OUT2
OUT2
OUT2
OUT2
NC
NC
D2
PGND
PGND
PGND
PGND
NC
V+
V+
V+
V+
NC
NC
NC
NC
IN1
FS
AGND
NC
NC
NC
NC
OUT1
OUT1
OUT1
OUT1
NC
NC
FB
PGND
PGND
PGND
54
40
.35
34
33
32
31
30
29
28
39
38
37
36
47
46
45
44
43
42
41
51
50
49
48
53
52
1
15
20
21
22
23
24
25
26
27
16
17
18
19
8
9
10
11
12
13
14
4
5
6
7
2
3
Transparent Top View of Package
SOICW-EP TERMINAL DEFINITIONS
A functional description of each terminal can be found in the System/Application Information section,
page 19
.
Terminal
Terminal
Name
Formal Name
Definition
14, 5154
PGND
Power Ground
High-current power ground.
57, 9, 14, 1922,
27 29, 3336, 41,
46, 4850
NC
No Connect
No internal connection to this terminal.
8
D2
Disable 2
Active LOW input used to simultaneously tri-state disable both H-Bridge
outputs. When D2 is Logic LOW, both outputs are tri-stated.
1013
OUT2
H-Bridge Output 2
Output 2 of H-Bridge.
15 18, 3740
V+
Positive Power Supply
Positive supply connections.
23
C
CP
Charge Pump Capacitor
External reservoir capacitor connection for internal charge pump capacitor.
24
D1
Disable 1
Active HIGH input used to simultaneously tri-state disable both H-Bridge
outputs. When D1 is Logic HIGH, both outputs are tri-stated.
25
IN2
Logic Input Control 2
Logic input control of OUT2 (i.e., IN2 logic HIGH = OUT2 HIGH).
26
EN
Enable
Logic input Enable control of device (i.e., EN logic HIGH = full operation,
EN logic LOW = Sleep Mode).
30
AGND
Analog Ground
Low-current analog signal ground.
31
FS
Fault Status for H-Bridge
Open drain active LOW Fault Status output requiring a pullup resistor to
5.0 V.
32
IN1
Logic Input Control 1
Logic input control of OUT1 (i.e., IN1 logic HIGH = OUT1 HIGH).
4245
OUT1
H-Bridge Output 1
Output 1 of H-Bridge.
47
FB
Feedback for H-Bridge
Current feedback output providing ground referenced 1/375th ratio of
H-Bridge high-side current.
Pad
Thermal
Interface
Exposed Pad Thermal
Interface
Exposed pad thermal interface for sinking heat from the device.
Note Must be DC-coupled to analog ground and power ground via very low
impedance path to prevent injection of spurious signals into IC substrate.
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33887
MOTOROLA ANALOG INTEGRATED CIRCUIT DEVICE DATA
6
.
MAXIMUM RATINGS
All voltages are with respect to ground unless otherwise noted.
Rating
Symbol
Value
Unit
ELECTRICAL RATINGS
Supply Voltage
V+
40
V
Input Voltage
(Note 1)
V
IN
-0.3 to 7.0
V
FS Status Output
(Note 2)
V
FS
7.0
V
Continuous Current
(Note 3)
I
OUT
5.0
A
DH Suffix HSOP ESD Voltage
Human Body Model
(Note 4)
Each Terminal to AGND
Each Terminal to PGND
Each Terminal to V+
Each I/O to All Other I/Os
Machine Model
(Note 5)
V
ESD1
V
ESD1
V
ESD1
V
ESD1
V
ESD2
1000
1500
2000
2000
200
V
VW Suffix HSOP ESD Voltage
Human Body Model
(Note 4)
Machine Model
(Note 5)
V
ESD1
V
ESD2
2000
200
V
PQFN ESD Voltage
Human Body Model
(Note 4)
Machine Model
(Note 5)
V
ESD1
V
ESD2
2000
200
V
SOICW-EP ESD Voltage
Human Body Model
(Note 4)
Machine Model
(Note 5)
V
ESD1
V
ESD2
1600
200
V
THERMAL RATINGS
Storage Temperature
T
STG
-65 to 150
C
Operating Temperature
(Note 6)
Ambient
Junction
T
A
T
J
-40 to 125
-40 to 150
C
Peak Package Reflow Temperature During Solder Mounting
(Note 7)
HSOP
PQFN
SOICW-EP
T
SOLDER
220
260
240
C
Notes
1.
Exceeding the input voltage on IN1, IN2, EN, D1, or D2 may cause a malfunction or permanent damage to the device.
2.
Exceeding the pullup resistor voltage on the open Drain FS terminal may cause permanent damage to the device.
3.
Continuous current capability so long as junction temperature is
150
C.
4.
ESD1 testing is performed in accordance with the Human Body Model (C
ZAP
= 100 pF, R
ZAP
= 1500
).
5.
ESD2 testing is performed in accordance with the Machine Model (C
ZAP
= 200 pF, R
ZAP
= 0
).
6.
The limiting factor is junction temperature, taking into account the power dissipation, thermal resistance, and heat sinking provided. Brief
nonrepetitive excursions of junction temperature above 150
C can be tolerated as long as duration does not exceed 30 seconds maximum.
(nonrepetitive events are defined as not occurring more than once in 24 hours.)
7.
Terminal soldering temperature limit is for 10 seconds maximum duration. Not designed for immersion soldering. Exceeding these limits may
cause malfunction or permanent damage to the device.
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MOTOROLA ANALOG INTEGRATED CIRCUIT DEVICE DATA
33887
7
THERMAL RESISTANCE (AND PACKAGE DISSIPATION) RATINGS
(Note 8)
,
(Note 9)
,
(Note 10)
,
(Note 11)
Junction-to-Board (Bottom Exposed Pad Soldered to Board)
HSOP (6.0 W)
PQFN (4.0 W)
SOICW-EP (2.0 W)
R
JB
~5.0
~4.3
~8.0
C/W
Junction-to-Ambient, Natural Convection, Single-Layer Board (1s)
(Note 12)
HSOP (6.0 W)
PQFN (4.0 W)
SOICW-EP (2.0 W)
R
JA
~41
~TBD
~62
C/W
Junction-to-Ambient, Natural Convection, Four-Layer Board (2s2p)
(Note 13)
HSOP (6.0 W)
PQFN (4.0 W)
SOICW-EP (2.0 W)
R
JMA
~30
~21.3
~TBD
C/W
Junction-to-Case (Exposed Pad)
(Note 14)
HSOP (6.0 W)
PQFN (4.0 W)
SOICW-EP (2.0 W)
R
JC
~0.5
~0.9
~1.5
C/W
Notes
8.
The limiting factor is junction temperature, taking into account the power dissipation, thermal resistance, and heat sinking.
9.
Exposed heatsink pad plus the power and ground terminals comprise the main heat conduction paths. The actual R
JB
(junction-to-PC board)
values will vary depending on solder thickness and composition and copper trace thickness. Maximum current at maximum die temperature
represents ~16 W of conduction loss heating in the diagonal pair of output MOSFETs. Therefore, the R
JC
-total must be less than 5.0 C/W
for maximum load at 70C ambient. Module thermal design must be planned accordingly.
10.
Thermal resistance between the die and the printed circuit board per JEDEC JESD51-8. Board temperature is measured on the top surface
of the board near the package.
11.
Junction temperature is a function of on-chip power dissipation, package thermal resistance, mounting site (board) temperature, ambient
temperature, air flow, power dissipation of other components on the board, and board thermal resistance.
12.
Per SEMI G38-87 and JEDEC JESD51-2 with the single-layer board (JESD51-3) horizontal.
13.
Per JEDEC JESD51-6 with the board horizontal.
14.
Indicates the average thermal resistance between the die and the exposed pad surface as measured by the cold plate method (MIL SPEC-
883 Method 1012.1) with the cold plate temperature used for the case temperature.
MAXIMUM RATINGS (continued)
All voltages are with respect to ground unless otherwise noted.
Rating
Symbol
Value
Unit
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33887
MOTOROLA ANALOG INTEGRATED CIRCUIT DEVICE DATA
8
STATIC ELECTRICAL CHARACTERISTICS
Characteristics noted under conditions 5.0 V
V+
28 V and -40
C
T
A
125
C unless otherwise noted. Typical values noted
reflect the approximate parameter mean at T
A
= 25
C under nominal conditions unless otherwise noted.
Characteristic
Symbol
Min
Typ
Max
Unit
POWER SUPPLY
Operating Voltage Range
(Note 15)
V+
5.0
40
V
Sleep State Supply Current
(Note 16)
I
OUT
= 0 A, V
EN
= 0 V
I
Q(sleep)
25
50
A
Standby Supply Current
I
OUT
= 0 A, V
EN
= 5.0 V
I
Q(standby)
20
mA
Threshold Supply Voltage
Switch-OFF
Switch-ON
Hysteresis
V+
(thres-OFF)
V+
(thres-ON)
V+
(hys)
4.15
4.5
150
4.4
4.75
4.65
5.0
V
V
mV
CHARGE PUMP
Charge Pump Voltage
V+ = 5.0 V
8.0 V
V+ 40 V
V
CP
- V+
3.35
20
V
CONTROL INPUTS
Input Voltage (IN1, IN2, D1, D2)
Threshold HIGH
Threshold LOW
Hysteresis
V
IH
V
IL
V
HYS
3.5
0.7
1.0
1.4
V
Input Current (IN1, IN2, D1)
V
IN
- 0.0 V
I
INP
-200
-80
A
Input Current (D2, EN)
V
D2
= 5.0 V
I
INP
25
100
A
Notes
15.
Specifications are characterized over the range of 5.0 V
V+ 28 V. Operation >28 V will cause some parameters to exceed listed min/max
values. Refer to typical operating curves to extrapolate values for operation >28 V but
40 V.
16.
I
Q(
sleep)
is with sleep mode function enabled.
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MOTOROLA ANALOG INTEGRATED CIRCUIT DEVICE DATA
33887
9
STATIC ELECTRICAL CHARACTERISTICS (continued)
Characteristics noted under conditions 5.0 V
V+
28 V and -40
C
T
A
125
C unless otherwise noted. Typical values noted reflect
the approximate parameter mean at T
A
= 25
C under nominal conditions unless otherwise noted.
Characteristic
Symbol
Min
Typ
Max
Unit
POWER OUTPUTS (OUT1, OUT2)
Output ON-Resistance
(Note 17)
5.0 V
V+ 28 V, T
J
= 25C
8.0 V
V+ 28 V, T
J
= 150C
5.0 V
V+ 8.0 V, T
J
= 150C
R
DS(ON)
120
225
300
m
Active Current Limiting Threshold (via Internal Constant OFF-Time PWM) on
Low-Side MOSFETs
(Note 18)
I
LIM
5.2
6.5
7.8
A
High-Side Short Circuit Detection Threshold
I
SCH
11
A
Low-Side Short Circuit Detection Threshold
I
SCL
8.0
A
Leakage Current
(Note 19)
V
OUT
= V+
V
OUT
= Ground
I
OUT(
leak)
100
30
200
60
A
Output MOSFET Body Diode Forward Voltage Drop
I
OUT
= 3.0 A
V
F
2.0
V
Overtemperature Shutdown
Thermal Limit
Hysteresis
T
LIM
T
HYS
175
10
225
30
C
HIGH-SIDE CURRENT SENSE FEEDBACK
Feedback Current
I
OUT
= 0 mA
I
OUT
= 500 mA
I
OUT
= 1.5 A
I
OUT
= 3.0 A
I
OUT
= 6.0 A
I
FB
1.07
3.6
7.2
14.4
1.33
4.0
8.0
16
600
1.68
4.62
9.24
18.48
A
mA
mA
mA
mA
FAULT STATUS
(Note 20)
Fault Status Leakage Current
(Note 21)
V
FS
= 5.0 V
I
FS
(
leak)
10
A
Fault Status SET Voltage
(Note 22)
I
FS
= 300
A
V
FS
(LOW)
1.0
V
Notes
17.
Output-ON resistance as measured from output to V+ and ground.
18.
Active current limitation applies only for the low-side MOSFETs.
19.
Outputs switched OFF with D1 or D2.
20.
Fault Status output is an open Drain output requiring a pullup resistor to 5.0 V.
21.
Fault Status Leakage Current is measured with Fault Status HIGH and not SET.
22.
Fault Status Set Voltage is measured with Fault Status LOW and SET with I
FS
= 300
A.
F
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33887
MOTOROLA ANALOG INTEGRATED CIRCUIT DEVICE DATA
10
DYNAMIC ELECTRICAL CHARACTERISTICS
Characteristics noted under conditions 5.0 V
V+
28 V and -40
C
T
A
125
C unless otherwise noted. Typical values noted
reflect the approximate parameter mean at T
A
= 25
C under nominal conditions unless otherwise noted.
Characteristic
Symbol
Min
Typ
Max
Unit
TIMING CHARACTERISTICS
PWM Frequency
(Note 23)
f
PWM
10
kHz
Maximum Switching Frequency During Active Current Limiting
(Note 24)
f
MAX
20
kHz
Output ON Delay
(Note 25)
V+ = 14 V
t
d(ON)
18
s
Output OFF Delay
(Note 25)
V+ = 14 V
t
d(OFF)
18
s
I
LIM
Output Constant-OFF Time for Low-Side MOSFETs
(Note 26), (Note 27)
t
a
15
20.5
26
s
I
LIM
Blanking Time for Low-Side MOSFETs
(Note 28)
,
(Note 27)
t
b
12
16.5
21
s
Output Rise and Fall Time
(Note 29)
V+ = 14 V, I
OUT
= 3.0 A
t
f
, t
r
2.0
5.0
8.0
s
Disable Delay Time
(Note 30)
t
d(disable)
8.0
s
Power-ON Delay Time
(Note 31)
t
pod
1.0
5.0
ms
Wake-Up Delay Time
(Note 31)
t
wud
1.0
5.0
ms
Output MOSFET Body Diode Reverse Recovery Time
(Note 32)
t
rr
100
ns
Notes
23.
The outputs can be PWM-controlled from an external source. This is typically done by holding one input high while applying a PWM pulse
train to the other input. The maximum PWM frequency obtainable is a compromise between switching losses and switching frequency. See
Typical Switching Waveforms,
Figures 11
through
18
, pp. 1516.
24.
The Maximum Switching Frequency during active current limiting is internally implemented. The internal current limit circuitry produces a
constant-OFF-time pulse-width modulation of the output current. The output load's inductance, capacitance, and resistance characteristics
affect the total switching period (OFF-time + ON-time) and thus the PWM frequency during current limit.
25.
Output Delay is the time duration from the midpoint of the IN1 or IN2 input signal to the 10% or 90% point (dependent on the transition
direction) of the OUT1 or OUT2 signal. If the output is transitioning HIGH-to-LOW, the delay is from the midpoint of the input signal to the
90% point of the output response signal. If the output is transitioning LOW-to-HIGH, the delay is from the midpoint of the input signal to the
10% point of the output response signal. See
Figure 2
, page 11.
26.
I
LIM
Output Constant-OFF Time is the time during which the internal constant-OFF time PWM current regulation circuit has tri-stated the
output bridge.
27.
Load currents ramping up to the current regulation threshold become limited at the I
LIM
value. The short circuit currents possess a di/dt that
ramps up to the I
SCH
or I
SCL
threshold during the I
LIM
blanking time, registering as a short circuit event detection and causing the shutdown
circuitry to force the output into an immediate tri-state latch-OFF. See
Figures 6
and
7
, page 12. Operation in
Current Limit mode
may cause
junction temperatures to rise. Junction temperatures above ~160
C will cause the output current limit threshold to progressively "fold back",
or decrease with temperature, until ~175
C is reached, after which the T
LIM
thermal latch-OFF will occur. Permissible operation within this
foldback region is limited to nonrepetitive transient events of duration not to exceed 30 seconds. See
Figure 5
, page 11.
28.
I
LIM
Blanking Time is the time during which the current regulation threshold is ignored so that the short-circuit detection threshold
comparators my have time to act.
29.
Rise Time is from the 10% to the 90% level and Fall Time is from the 90% to the 10% level of the output signal. See
Figure 4
, page 11.
30.
Disable Delay Time is the time duration from the midpoint of the D (disable) input signal to 10% of the output tri-state response. See
Figure 3
,
page 11.
31.
Parameter has been characterized but not production tested.
32.
Parameter is guaranteed by design but not production tested.
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MOTOROLA ANALOG INTEGRATED CIRCUIT DEVICE DATA
33887
11
Timing Diagrams
Figure 2. Output Delay Time
Figure 3. Disable Delay Time
Figure 4. Output Switching Time
Figure 5. Active Current Limiting Versus Temperature (Typical)
TIME
0
5.0
0
V
PWR
t
d(ON)
50%
90%
50%
10%
V
I
N
1
,
I
N
2
(
V
)
t
d(OFF)
V
O
U
T
1
,
2
(
V
)
0 V
5.0 V
0
t
r
0
V
PWR
90%
10%
V
O
U
T
1
,
2
(
V
)
10%
90%
t
f
I
M
A
X
,
O
U
T
P
U
T
C
U
R
R
E
N
T
(
A
)
6.6
2.5
160
175
Thermal Shutdown
TJ, JUNCTION TEMPERATURE (
o
C)
I
LI
M
,
6.5
I
LI
M
,
CUR
RE
NT
(
A
)
4.0
Operation within this region must be
150
limited to nonrepetitive events
not to exceed 30 seconds
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33887
MOTOROLA ANALOG INTEGRATED CIRCUIT DEVICE DATA
12
Figure 6. Operating States
Figure 7. Example Short Circuit Detection Detail on Low-Side
MOSFET
Active
Current
Limiting
>8A
6.5
Short Circuit Detection Threshold
Typical Current Limit Threshold
Hard Short Detect
ion
and Latch-OFF
0
IN1 or IN2
IN2 or IN1
IN1 or IN2
IN2 or IN1
IN1 IN2
[1]
[0]
[1]
[0]
[1]
[0]
[1]
[0]
Outputs
Tri-Stated
Outputs
Tri-Stated
Outputs Operation
(per Input Control Condition)
Time
SF
, LOGIC OUT
D
2
, LOGIC IN
D1, LOGIC IN
IN
n
, LOGIC IN
I
LOAD
, OUTPUT
CURR
ENT (
A
)
High Current Load Being Regulated via Constant-OFF-Time PWM
Moderate Current Load
on Low-Side
MOSFET
Overcurrent Minimum Threshold
t
a
t
b
8.0
TIME
I
L
O
A
D
,
O
U
T
P
U
T
C
U
R
R
E
N
T
(
A
)
Typical PWM Load
Current Limiting
Waveform
Hard Output
Short Latch-OFF
t
a
= Tristate Output OFF Time
t
b
= Current Limit Blank Time
6.5
Hard Short Detect
ion
Short Circuit Detect Threshold
t
a
= Output Constant-OFF Time
t
b
= Output Blanking Time
I
SCL
Short Circuit Detection Threshold
I
OUT
,
C
URRENT
(A)
Typical Current
Limiting Waveform
t
b
5.0
t
a
8.0
Hard short occurs.
Hard short is detected during t
b
I
LIM
Blanking Time
t
on
0.0
and output is latched-off.
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MOTOROLA ANALOG INTEGRATED CIRCUIT DEVICE DATA
33887
13
Electrical Performance Curves
Figure 8. Typical High-Side R
DS(ON)
Versus V+
Figure 9. Typical Low-Side R
DS(ON)
Versus V+
5
9
11
7
13
15
19
37
33
35
39
27
41
29
17
21
23
25
31
0.0
0.05
0.10
0.15
0.20
0.25
0.30
0.35
0.40
Volts
Oh
ms
5
9
11
7
13
15
19
37
33
35
39
27
41
29
17
21
23
25
31
0.13
0.128
0.126
0.124
0.122
0.12
OHMS
V
PWR
Ohms
Volts
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33887
MOTOROLA ANALOG INTEGRATED CIRCUIT DEVICE DATA
14
Figure 10. Typical Quiescent Supply Current Versus V+
5
9
11
7
13
15
19
37
33
35
39
27
41
29
17
21
23
25
31
5.0
4.0
3.0
2.0
1.0
0.0
OHMS
V
PWR
6.0
7.0
8.0
9.0
Milliamperes
Volts
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MOTOROLA ANALOG INTEGRATED CIRCUIT DEVICE DATA
33887
15
Typical Switching Waveforms
Important For all plots, the following applies:
Ch2=2.0 A per division
L
LOAD
=533
H @ 1.0 kHz
L
LOAD
=530
H @ 10.0 kHz
R
LOAD
=4.0
Figure 11. Output Voltage and Current vs. Input Voltage at
V+
= 24 V, PMW Frequency of 1.0 kHz,
and Duty Cycle of 10%
Figure 12. Output Voltage and Current vs. Input Voltage at
V+
= 24 V, PMW Frequency of 1.0 kHz,
and Duty Cycle of 50%
Figure 13. Output Voltage and Current vs. Input Voltage at
V+
= 34 V, PMW Frequency of 1.0 kHz,
and Duty Cycle of 90%, Showing Device in
Current Limiting Mode
Figure 14. Output Voltage and Current vs. Input Voltage at
V+
= 22 V, PMW Frequency of 1.0 kHz,
and Duty Cycle of 90%
V+=24 V
f
PWM
=1.0 kHz
Duty Cycle=10%
Output Voltage
(OUT1)
I
OUT
Input Voltage
(IN1)
V+=24 V
f
PWM
= 1.0 kHz Duty Cycle = 50%
Output Voltage
(OUT1)
I
OUT
Input Voltage
(IN1)
V+=34 V
f
PWM
=1.0 kHz
Duty Cycle=90%
Output Voltage
(OUT1)
I
OUT
Input Voltage
(IN1)
V+=22 V
f
PWM
=1.0 kHz
Duty Cycle=90%
Output Voltage
(OUT1)
I
OUT
Input Voltage
(IN1)
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33887
MOTOROLA ANALOG INTEGRATED CIRCUIT DEVICE DATA
16
Figure 15. Output Voltage and Current vs. Input Voltage at
V+
= 24 V, PMW Frequency of 10 kHz,
and Duty Cycle of 50%
Figure 16. Output Voltage and Current vs. Input Voltage at
V+
= 24 V, PMW Frequency of 10 kHz,
and Duty Cycle of 90%
Figure 17. Output Voltage and Current vs. Input Voltage at
V+
= 12 V, PMW Frequency of 20 kHz,
and Duty Cycle of 50% for a Purely Resistive Load
Figure 18. Output Voltage and Current vs. Input Voltage at
V+
= 12 V, PMW Frequency of 20 kHz,
and Duty Cycle of 90% for a Purely Resistive Load
V+=24 V
f
PWM
=10 kHz
Duty Cycle=50%
Output Voltage
(OUT1)
I
OUT
Input Voltage
(IN1)
V+=24 V
f
PWM
=10 kHz
Duty Cycle=90%
Output Voltage
(OUT1)
I
OUT
Input Voltage
(IN1)
V+=12 V
f
PWM
=20 kHz
Duty Cycle=50%
Output Voltage
(OUT1)
I
OUT
Input Voltage
(IN1)
V+=12 V
f
PWM
=20 kHz
Duty Cycle=90%
Output Voltage
(OUT1)
I
OUT
Input Voltage
(IN1)
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MOTOROLA ANALOG INTEGRATED CIRCUIT DEVICE DATA
33887
17
Table 1. Truth Table
The tri-state conditions and the fault status are reset using D1 or
D2
. The truth table uses the following notations: L = LOW, H = HIGH,
X = HIGH or LOW, and Z = High impedance (all output power transistors are switched off).
Device State
Input Conditions
Fault
Status Flag
Output States
EN
D1
D2
IN1
IN2
FS
OUT1
OUT2
Forward
H
L
H
H
L
H
H
L
Reverse
H
L
H
L
H
H
L
H
Freewheeling Low
H
L
H
L
L
H
L
L
Freewheeling High
H
L
H
H
H
H
H
H
Disable 1 (D1)
H
H
X
X
X
L
Z
Z
Disable 2 (D2)
H
X
L
X
X
L
Z
Z
IN1 Disconnected
H
L
H
Z
X
H
H
X
IN2 Disconnected
H
L
H
X
Z
H
X
H
D1 Disconnected
H
Z
X
X
X
L
Z
Z
D2
Disconnected
H
X
Z
X
X
L
Z
Z
Undervoltage
(Note 33)
H
X
X
X
X
L
Z
Z
Overtemperature
(Note 34)
H
X
X
X
X
L
Z
Z
Short Circuit
(Note 34)
H
X
X
X
X
L
Z
Z
Sleep Mode EN
L
X
X
X
X
H
Z
Z
EN Disconnected
Z
X
X
X
X
H
Z
Z
Notes
33.
In the case of an undervoltage condition, the outputs tri-state and the fault status is SET logic LOW. Upon undervoltage recovery, fault status
is reset automatically or automatically cleared and the outputs are restored to their original operating condition.
34.
When a short circuit or overtemperature condition is detected, the power outputs are tri-state latched-OFF independent of the input signals
and the fault status flag is SET logic LOW.
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33887
MOTOROLA ANALOG INTEGRATED CIRCUIT DEVICE DATA
18
SYSTEM/APPLICATION INFORMATION
INTRODUCTION
Numerous protection and operational features (speed,
torque, direction, dynamic braking, PWM control, and closed-
loop control), in addition to the 5.0 A current capability, make
the 33887 a very attractive, cost-effective solution for
controlling a broad range of small DC motors. In addition, a pair
of 33887 devices can be used to control bipolar stepper motors.
The 33887 can also be used to excite transformer primary
windings with a switched square wave to produce secondary
winding AC currents.
As shown in
Figure 1
, Simplified Internal Block Diagram,
page 2, the 33887 is a fully protected monolithic H-Bridge with
Enable, Fault Status reporting, and High-Side current sense
feedback to accommodate closed-loop PWM control. For a DC
motor to run, the input conditions need be as follows: Enable
input logic HIGH, D1 input logic LOW,
D2
input logic HIGH,
FS
flag cleared (logic HIGH), one IN logic LOW and the other IN
logic HIGH (to define output polarity). The 33887 can execute
dynamic braking by simultaneously turning on either both high-
side
MOSFETs or both low-side MOSFETs in the output
H-Bridge; e.g., IN1 and IN2 logic HIGH or IN1 and IN2 logic
LOW.
The 33887 outputs are capable of providing a continuous DC
load current of 5.0 A from a 40 V V+ source. An internal charge
pump supports PWM frequencies to 10 kHz. An external pullup
resistor is required at the
FS
terminal for fault status reporting.
The 33887 has an analog feedback (current mirror) output
terminal (the FB terminal) that provides a constant-current
source ratioed to the active high-side MOSFET. This can be
used to provide "real time" monitoring of load current to facilitate
closed-loop operation for motor speed/torque control.
Two independent inputs (IN1 and IN2) provide control of the
two totem-pole half-bridge outputs. Two disable inputs (D1 and
D2
) provide the means to force the H-Bridge outputs to a high-
impedance state (all H-Bridge switches OFF). An EN terminal
controls an enable function that allows the 33887 to be placed
in a power-conserving sleep mode.
The 33887 has undervoltage shutdown with automatic
recovery, active current limiting, output short-circuit latch-OFF,
and overtemperature latch-OFF. An undervoltage shutdown,
output short-circuit latch-OFF, or overtemperature latch-OFF
fault condition will cause the outputs to turn OFF (i.e., become
high impedance or tri-stated) and the fault output flag to be set
LOW. Either of the Disable inputs or V+ must be "toggled" to
clear the fault flag.
Active current limiting is accomplished by a constant OFF-
time PWM method employing active current limiting threshold
triggering. The active current limiting scheme is unique in that it
incorporates a junction temperature-dependent current limit
threshold. This means the active current limiting threshold is
"ramped down" as the junction temperature increases above
160
C, until at 175C the current will have been decreased to
about 4.0 A. Above 175
C, the overtemperature shutdown
(latch-OFF) occurs. This combination of features allows the
device to remain in operation for 30 seconds at junction
temperatures above 150
C for nonrepetitive unexpected loads.
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MOTOROLA ANALOG INTEGRATED CIRCUIT DEVICE DATA
33887
19
FUNCTIONAL TERMINAL DESCRIPTION
PGND and AGND
Power and analog ground terminals should be connected
together with a very low impedance connection.
V+
V+ terminals are the power supply inputs to the device. All V+
terminals must be connected together on the printed circuit
board with as short as possible traces offering as low
impedance as possible between terminals.
V+ terminals have an undervoltage threshold. If the supply
voltage drops below a V+ undervoltage threshold, the output
power stage switches to a tri-state condition and the fault status
flag is SET and the Fault Status terminal voltage switched to a
logic LOW. When the supply voltage returns to a level that is
above the threshold, the power stage automatically resumes
normal operation according to the established condition of the
input terminals and the fault status flag is automatically reset
logic HIGH.
Fault Status (FS)
The
FS
terminal is the device fault status output. This output
is an active LOW open drain structure requiring a pullup resistor
to 5.0 V. Refer to
Table 1, Truth Table
, page 17.
IN1, IN2, D1, and D2
These terminals are input control terminals used to control
the outputs. These terminals are 5.0 V CMOS-compatible
inputs with hysteresis. The IN1 and IN2 independently control
OUT1 and OUT2, respectively. D1 and
D2
are complementary
inputs used to tri-state disable the H-Bridge outputs.
When either D1 or
D2
is SET (D1 = logic HIGH or
D2
= logic
LOW) in the disable state, outputs OUT1 and OUT2 are both tri-
state disabled; however, the rest of the device circuitry is fully
operational and the supply I
Q(
standby)
current is reduced to a few
milliamperes. Refer to
Table 1, Truth Table
, and
STATIC
ELECTRICAL CHARACTERISTICS
table, page 8.
OUT1 and OUT2
These terminals are the outputs of the H-Bridge with
integrated output MOSFET body diodes. The bridge output is
controlled using the IN1, IN2, D1, and
D2
inputs. The low-side
MOSFETs have active current limiting above the I
LIM
threshold.
The outputs also have thermal shutdown (tri-state latch-OFF)
with hysteresis as well as short circuit latch-OFF protection.
A disable timer (time t
b
) incorporated to detect currents that
are higher than current limit is activated at each output
activation to facilitate hard short detection (see
Figure 7
,
page 12).
C
CP
A filter capacitor (up to 33 nF) can be connected from the
charge pump output terminal and PGND. The device can
operate without the external capacitor, although the C
CP
capacitor helps to reduce noise and allows the device to
perform at maximum speed, timing, and PWM frequency.
EN
The EN terminal is used to place the device in a sleep mode
so as to consume very low currents. When the EN terminal
voltage is a logic LOW state, the device is in the sleep mode.
The device is enabled and fully operational when the EN
terminal voltage is logic HIGH. An internal pulldown resistor
maintains the device in sleep mode in the event EN is driven
through a high impedance I/O or an unpowered microcontroller,
or the EN input becomes disconnected.
FB
The 33887 has a feedback output (FB) for "real time"
monitoring of H-Bridge high-side current to facilitate closed-
loop operation for motor speed and torque control.
The FB terminal provides current sensing feedback of the
H-Bridge high-side drivers. When running in the forward or
reverse direction, a ground referenced 1/375th (0.00266) of
load current is output to this terminal. Through the use of an
external resistor to ground, the proportional feedback current
can be converted to a proportional voltage equivalent and the
controlling microcontroller can "read" the current proportional
voltage with its analog-to-digital converter (ADC). This is
intended to provide the user with motor current feedback for
motor torque control. The resistance range for the linear
operation of the FB terminal is 100 <R
FB
<200
.
If PWM-ing is implemented using the disable terminal inputs
(either D1 or
D2
), a small filter capacitor (1.0
F or less) may be
required in parallel with the external resistor to ground for fast
spike suppression.
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33887
MOTOROLA ANALOG INTEGRATED CIRCUIT DEVICE DATA
20
PERFORMANCE FEATURES
Short Circuit Protection
If an output short circuit condition is detected, the power
outputs tri-state (latch-OFF) independent of the input (IN1 and
IN2) states, and the fault status output flag is SET logic LOW. If
the D1 input changes from logic HIGH to logic LOW, or if the
D2
input changes from logic LOW to logic HIGH, the output bridge
will become operational again and the fault status flag will be
reset (cleared) to a logic HIGH state.
The output stage will always switch into the mode defined by
the input terminals (IN1, IN2, D1, and
D2
), provided the device
junction temperature is within the specified operating
temperature range.
Active Current Limiting
The maximum current flow under normal operating
conditions is internally limited to I
LIM
(5.2 A to 7.8 A). When the
maximum current value is reached, the output stages are tri-
stated for a fixed time (t
a
) of 20
s typical. Depending on the
time constant associated with the load characteristics, the
current decreases during the tri-state duration until the next
output ON cycle occurs (see
Figures 7
and
13
, page 12 and
page 15, respectively).
The current limiting threshold value is dependent upon the
device junction temperature. When -40
C T
J
160C, I
LIM
is
between 5.2 A to 7.8 A. When T
J
exceeds 160
C, the
I
LIM
current decreases linearly down to 4.0 A typical at 175
C.
Above 175
C the device overtemperature circuit detects T
LIM
and overtemperature shutdown occurs (see
Figure 5
, page 11).
This feature allows the device to remain operational for a longer
time but at a regressing output performance level at junction
temperatures above 160
C.
Overtemperature Shutdown and Hysteresis
If an overtemperature condition occurs, the power outputs
are tri-stated (latched-OFF) and the fault status flag is SET to
logic LOW.
To reset from this condition, D1 must change from logic
HIGH to logic LOW, or
D2
must change from logic LOW to logic
HIGH. When reset, the output stage switches ON again,
provided that the junction temperature is now below the
overtemperature threshold limit minus the hysteresis.
Note Resetting from the fault condition will clear the fault
status flag.
PACKAGE INFORMATION
The 33887 packages are designed for thermal performance.
The significant feature of these packages is the exposed pad on
which the power die is soldered. When soldered to a PCB, this
pad provides a path for heat flow to the ambient environment.
The more copper area and thickness on the PCB, the better the
power dissipation and transient behavior will be.
Example Characterization on a double-sided PCB: bottom
side area of copper is 7.8 cm
2
; top surface is 2.7 cm
2
(see
Figure 19
); grid array of 24 vias 0.3 mm in diameter.
Figure 19. PCB Test Layout
Figure 20
shows the thermal response with the device in the
HSOP package soldered on to the test PCB described in
Figure 19
.
Figure 20. 33887 Thermal Response, HSOP Package
Top Side
Bottom Side
0,1
1
10
100
0,001
0,01
0,1
1
10
100
1000
10000
t, Time (s)
Rth (C/W)
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MOTOROLA ANALOG INTEGRATED CIRCUIT DEVICE DATA
33887
21
APPLICATIONS
Figure 21
shows a typical application schematic. For
precision high-current applications in harsh, noisy
environments, the V+ by-pass capacitor may need to be
substantially larger.
Figure 21. 33887 Typical Application Schematic
MOTOR
AGND
OUT1
FB
PGND
V+
C
CP
OUT2
EN
D2
D1
FS
IN1
IN2
33 nF
47
F
V+
100
1.0
F
33887
+
+
FB
IN2
IN1
FS
D1
D2
EN
DC
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33887
MOTOROLA ANALOG INTEGRATED CIRCUIT DEVICE DATA
22
PACKAGE DIMENSIONS
GAUGE
PLANE
DETAIL Y
(1.600)
L
W
W
q
L1
A1
ccc
C
ccc D
D
SEATING
PLANE
DATUM
PLANE
A
A2
DETAIL Y
C
H
BOTTOM VIEW
D1
E3
E4
EXPOSED
HEATSINK AREA
DIM
MIN
MAX
MILLIMETERS
A
3.100
3.350
A1
0.050 BSC
A2
3.100
3.250
D
15.800
16.000
D1
12.270
12.470
D2
0.900
1.100
E
13.950
14.450
E1
10.900
11.100
E2
2.500
2.700
E3
7.000
7.200
L
0.840
1.100
L1
0.350 BSC
b
0.400
0.520
b1
0.400
0.482
c
0.230
0.310
c1
0.230
0.280
e
1.270 BSC
h
---
1.100
q
0
8
aaa
0.200
bbb
0.200
E4
2.700
2.900
ccc
0.100
NOTES:
1. CONTROLLING DIMENSION: MILLIMETER.
2. DIMENSIONS AND TOLERANCES PER ASME
Y14.5M, 1994.
3. DATUM PLANE -H- IS LOCATED AT BOTTOM OF
LEAD AND IS COINCIDENT WITH THE LEAD
WHERE THE LEAD EXITS THE PLASTIC BODY AT
THE BOTTOM OF THE PARTING LINE.
4. DIMENSIONS D AND E1 DO NOT INCLUDE MOLD
PROTRUSION. ALLOWABLE PROTRUSION IS
0.150 PER SIDE. DIMENSIONS D AND E1 DO
INCLUDE MOLD MISMATCH AND ARE
DETERMINED AT DATUM PLANE -H-.
5. DIMENSION b DOES NOT INCLUDE DAMBAR
PROTRUSION. ALLOWABLE DAMBAR
PROTRUSION SHALL BE 0.178 TOTAL IN EXCESS
OF THE b DIMENSION AT MAXIMUM MATERIAL
CONDITION.
6. DATUMS -A- AND -B- TO BE DETERMINED AT
DATUM PLANE -H-.
7. DIMENSION D DOES NOT INCLUDE TIEBAR
PROTRUSIONS. ALLOWABLE TIEBAR
PROTRUSIONS ARE 0.150 PER SIDE.
X 45
h
E1
E
D
e
18X
e/2
B
M
bbb
C
20
11
10
1
E2
D2
A
B
PIN ONE ID
SECTION W-W
b
c1
b1
c
A
M
aaa
C
DH SUFFIX
VW (Pb-FREE) SUFFIX
20-TERMINAL HSOP
PLASTIC PACKAGE
CASE 979-04
ISSUE C
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MOTOROLA ANALOG INTEGRATED CIRCUIT DEVICE DATA
33887
23
M
M
DETAIL G
PIN 1
INDEX AREA
9
9
0.1 C
2X
C
0.1
2X
0.1
A
C
B
3.2
36
28
19
10
1
2
PIN 1
INDEX
A
B
6.5
5.5
6.5
5.5
3.2
0.1
A
C
B
DETAIL N
0.4
1.08
0.94
32X
0.60
0.45
32X
0.1
M
A
C
B
0.05
M
C
VIEW M M
4.3
40X (0.175)
4.3
2X
40X
0.9
0.7
0.37
0.23
4 PLACES
0.1
M
A
C
B
0.05
M
C
DETAIL N
CORNER CONFIGURATION
2.2
2.0
2.20
1.95
0.05
0.00
(0.8)
(0.55)
DETAIL G
VIEW ROTATED 90 CW
C
0.1
0.05 C
4
C
SEATING PLANE
0.6
0.4
2X
NOTES:
1.
2.
3.
4.
ALL DIMENSIONS ARE IN MILLIMETERS.
DIMENSIONING AND TOLERANCING PER ASME
Y14.5M, 1994.
THE COMPLETE JEDEC DESIGNATOR FOR THIS
PACKAGE IS: F-PQFP-N.
COPLANARITY APPLIES TO LEADS AND CORNER
LEADS.
PNB (Pb-FREE) SUFFIX
36-TERMINAL PQFN
NON-LEADED PACKAGE
CASE 1503-01
ISSUE O
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33887
MOTOROLA ANALOG INTEGRATED CIRCUIT DEVICE DATA
24
17.8
7.4
1
27
28
54
B
9
5
C
7.6
18.0
9
4
10.3
5.15
0.3
A
B
C
2X 27 TIPS
B
B
PIN 1 INDEX
0.10 A
2.35
SEATING
PLANE
0.65
A
54X
52X
2.65
0.9
SECTION B-B
R0.08
MIN
0.1
0.0
0.5
0
8
0
0.25
GAUGE PLANE
MIN
(1.43)
NOTES:
1. ALL DIMENSIONS ARE IN MILLIMETERS.
2. DIMENSIONING AND TOLERANCING PER ASME
Y14.5M, 1994.
3. DATUMS B AND C TO BE DETERMINED AT THE
PLANE WHERE THE BOTTOM OF THE LEADS
EXIT THE PLASTIC BODY.
4. THIS DIMENSION DOES NOT INCLUDE MOLD
FLASH, PROTRUSION OR GATE BURRS. MOLD
FLASH, PROTRUSION OR GATE BURRS SHALL
NOT EXCEED 0.15 MM PER SIDE. THIS
DIMENSION IS DETERMINED AT THE PLANE
WHERE THE BOTTOM OF THE LEADS EXIT THE
PLASTIC BODY.
5. THIS DIMENSION DOES NOT INCLUDE
INTERLEAD FLASH OR PROTRUSIONS.
INTERLEAD FLASH AND PROTRUSIONS SHALL
NOT EXCEED 0.25 MM PER SIDE. THIS
DIMENSION IS DETERMINED AT THE PLANE
WHERE THE BOTTOM OF THE LEADS EXIT THE
PLASTIC BODY.
6. THIS DIMENSION DOES NOT INCLUDE DAMBAR
PROTRUSION. ALLOWABLE DAMBAR
PROTRUSION SHALL NOT CAUSE THE LEAD
WIDTH TO EXCEED 0.46 MM. DAMBAR CANNOT
BE LOCATED ON THE LOWER RADIUS OR THE
FOOT. MINIMUM SPACE BETWEEN
PROTRUSION AND ADJACENT LEAD SHALL NOT
LESS THAN 0.07 MM.
7. EXACT SHAPE OF EACH CORNER IS OPTIONAL.
8. THESE DIMENSIONS APPLY TO THE FLAT
SECTION OF THE LEAD BETWEEN 0.1 MM AND
0.3 MM FROM THE LEAD TIP.
9. THE PACKAGE TOP MAY BE SMALLER THAN
THE PACKAGE BOTTOM. THIS DIMENSION IS
DETERMINED AT THE OUTERMOST EXTREMES
OF THE PLASTIC BODY EXCLUSIVE OF MOLD
FLASH, TIE BAR BURRS, GATE BURRS AND
INTER-LEAD FLASH, BUT INCLUDING ANY
MISMATCH BETWEEN THE TOP AND BOTTOM
OF THE PLASTIC BODY.
A
A
C
C
(0.29)
0.38
0.30
(0.25)
PLATING
BASE METAL
SECTION A-A
ROTATED 90 CLOCKWISE
8
0.25
0.22
M
0.13
C
A B
6
4.8
4.3
0.30
C
A B
4.8
4.3
0.30
C
A B
VIEW C-C
DWB SUFFIX
54-TERMINAL SOICW EXPOSED PAD
PLASTIC PACKAGE
CASE 1390-01
ISSUE B
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MOTOROLA ANALOG INTEGRATED CIRCUIT DEVICE DATA
33887
25
NOTES
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33887
MOTOROLA ANALOG INTEGRATED CIRCUIT DEVICE DATA
26
NOTES
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MOTOROLA ANALOG INTEGRATED CIRCUIT DEVICE DATA
33887
27
NOTES
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Information in this document is provided solely to enable system and software implementers to use Motorola products. There are no express or implied
copyright licenses granted hereunder to design or fabricate any integrated circuits or integrated circuits based on the information in this document.
Motorola reserves the right to make changes without further notice to any products herein. Motorola makes no warranty, representation or guarantee
regarding the suitability of its products for any particular purpose, nor does Motorola assume any liability arising out of the application or use of any product
or circuit, and specifically disclaims any and all liability, including without limitation consequential or incidental damages. "Typical" parameters which may be
provided in Motorola data sheets and/or specifications can and do vary in different applications and actual performance may vary over time. All operating
parameters, including "Typicals" must be validated for each customer application by customer's technical experts. Motorola does not convey any license
under its patent rights nor the rights of others. Motorola products are not designed, intended, or authorized for use as components in systems intended for
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MOTOROLA and the Stylized M Logo are registered in the US Patent and Trademark Office. All other product or service names are the property of their
respective owners.
Motorola, Inc. 2004
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MC33887
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