Document Outline
- Application Benefits
- Distinctive Characteristics
- General Description
- Operational Overview
- Pin Descriptions
- DQ310 (Data Bus, Three-state, Common Input/Output)
- AC110 (Address/Control Bus, Input)
- AA110 (Active Address, Output)
- PA30 (Page Address, Output)
- /E (Chip Enable, Input)
- /CS1, /CS2 (Chip Select 1, Chip Select 2, Inputs)
- /W (Write Enable, Input)
- /OE (Output Enable, Input)
- /AV (Address Valid, Input)
- /VB (Validity Bit, Three-state, Common Input/Output)
- /MF (Match Flag, Output)
- /MI (Match Input, Input)
- /FF (Full Flag, Output)
- /FI (Full Input, Input)
- /MM (Multiple Match, Open Drain Output)
- /MV (Match Valid, Output)
- /RESET
- TCLK (JTAG Test Clock, Input)
- TMS (JTAG Test Mode Select, Input)
- TDI (JTAG Test Data Input, Input)
- TDO (JTAG Test Data Output, Output)
- /TRST (JTAG Reset, Input)
- VDD, GND (Positive Power Supply, Ground)
- Functional Description
- Operational Characteristics
- Register Descriptions
- Control State Overview
- Control State Descriptions
- Electrical
- Timing Diagrams
- Ordering Information
- Package
Data Sheet
MUSIC Semiconductors, the MUSIC logo, and the phrase "MUSIC Semiconductors" are
November 13, 2000 Rev. 3
Registered trademarks of MUSIC Semiconductors. MUSIC is a trademark of
MUSIC Semiconductors.
APPLICATION BENEFITS
High performance VPI/VCI translation for ATM
switches and routers, up to OC-48
Fully deterministic translation, independent from the
size of the list and the length of VPI/VCI
Pipelined architecture for increased throughput
No limitation of the range of legal values for
VPI/VCI, guaranteeing full interoperability
Cell tagging can be performed without any time
penalty
Easy buffer management in "Find and Replace" mode
because of the ability to check CLP field during
VPI/VCI translation
No limitation in the amount of associated information
stored with each connection
No time penalty when checking both VPI/VCI and
VPI only connections
DISTINCTIVE CHARACTERISTICS
4096 x 32-bit Content Addressable Memory (CAM)
70 ns compare and output time per VPI/VCI
32-bit Data I/O port
16-bit Match Address Output port directly addresses
external RAM containing associated data of any
width
Address/Control bus directly controls CAM
operations for faster throughput
Instruction and Status registers for optional software
control
Simultaneously compares Virtual Paths and Virtual
Channels
Cascadable for increased depth
Extensive set of control states for flexibility
JTAG interface
100-pin TQFP package; 3.3 volt operation
Figure 1: Block Diagram
AC110
/FI
4K x 1 VP VALIDITY
INSTRUCTION REGISTER
DEVICE SELECT REGISTER
STATUS REGISTER
CONFIGURATION REGISTER
ADDRESS REGISTER
MASK REGISTERS 17
DQ310
/VB
AA110
PA30
/FF
/MI
/MF
/MV
/ MM
/E
/CS1
/CS2
/W
/OE
/AV
/RESET
TCLK
TMS
TDI
TDO
/TRST
COMPARAND REGISTER
4K x 32CAM
CONTROL
AND
ADDRESS
DECODER
PRIORITY
ENCODER
AND
FLAG
LOGIC
MU9C4320L ATMCAM
MU9C4320L ATMCAM
MU9C4320L ATMCAM
MU9C4320L ATMCAM
MU9C4320L ATMCAM
General Description
2
Rev. 3
GENERAL DESCRIPTION
The MU9C4320L ATMCAM is a 4K x 32 Content
Addressable Memory (CAM) with a 32-bit wide data
interface. The device is designed for use in ATM switches
and routers to provide very high throughput VPI/VCI
translation through lookup tables held in external RAM.
VPI/VCI fields from the ATM cell header are compared
against a list of current connections stored in the CAM
array. As a result of the comparison, the ATMCAM
generates an address that is used to access an external
RAM where VPI/VCI mapping data and other information
associated with the connection are stored.
The ATMCAM simultaneously compares the VPI/VCI in
the CAM array as well as the VPI in a separate VP table.
This capability provides support for both VPCs and VCCs,
and halves the number of cycles needed to compare VPI
and VCI information. A set of control states provides a
powerful and flexible control interface to the ATMCAM.
This control structure allows memory read and write,
register read and write, data move, comparison, validity
control, addressing control, and initialization operations.
The ATMCAM architecture uses a non-multiplexed data
bus, direct hardware control of the device, and an
independent bus for returning match results. Software
control is also supported for systems where optimum
performance is not needed.
OPERATIONAL OVERVIEW
The ATMCAM is designed to act as an address translator
for lookup tables in ATM switch and router systems. It
takes incoming VP/VC identifiers in ATM cell headers
and generates addresses that access data in an external
RAM. The RAM holds translated VPI/VCI information
and other data relating to the particular connection. Refer
to Figure 2 for a simplified block diagram of an ATM
switch.
When a new connection is set up, the VPI/VCI of the
connection is written to the ATMCAM. The write cycle
can be to either a specific address within the device, or to
the next free address. The address at which the write takes
place is driven onto the Output Address bus, so VPI/VCI
mapping data can be written simultaneously into the
external RAM at the correct address.
With the connection established, the controller strips the
VPI/VCI information off an arriving cell to form the
Comparand, which is then compared against the contents
of the ATMCAM. The ATMCAM generates an address
that is used to access the VPI/VCI mapping data in the
external RAM. The controller reads the data from the
RAM and prefixes the translated header to the cell
payload.
If the switch operates on VPI only, as well as on full VPI/
VCI, the ATMCAM can compare both the VPI and VPI/
VCI fields simultaneously. The option to test VPI fields is
selected in the Configuration register of the ATMCAM.
When selected, the VPI field is used to form an address
that accesses a single-bit RAM array in the ATMCAM.
This area of memory is referred to as the VP Table, and
holds a single bit of information indicating the validity of
a VP value.
Figure 2: Switch Block Diagram
ATMCAM
Switch
Fabric
ATM Data Stream
ATM Controller
CAM
Control
Switch
Control
and
Data
VPI/VCI
Address
RAM
Data
Operational Overview
MU9C4320L ATMCAM
Rev. 3
3
The VP Table contains 4K entries, corresponding to the 12
bits in the VPI field of the ATM header. In a multiple
device system, only the lowest-priority device holds the
VP Table. A hit in the VP Table takes lower priority than a
match in the CAM array where the VPI/VCI fields are
compared associatively. If there is a mismatch in the CAM
array, but a hit in the VP Table, the VPI value is driven
onto the Address Output bus. Flags indicate whether a
CAM match or VP Table hit has occurred.
The VP Table eliminates the need to do two sequential
compares, one on the full VPI/VCI fields, and the other on
the VPI fields. The test of both sets of fields is
accomplished by the ATMCAM in a single compare cycle.
The validity of a location in the CAM array is determined
by an extra bit called the Validity bit. This bit is set and
reset either with an address or an associative match.
Therefore, when a new VPI/VCI entry is written to the
CAM, its Validity bit is set valid.
When a connection is removed, the Validity bit for that
entry is reset, and the address of the location is driven onto
the Active Address bus. This simple mechanism allows
easy maintenance of the connection list in both the CAM
array and the external RAM.
The ATMCAM supports simple daisy chained vertical
cascading that serves to prioritize multiple devices and
provides system-level match and full indication. If the
slight timing overhead associated with the daisy chain is
unacceptable in the fastest systems, the ATMCAM is
designed to facilitate external prioritization across
multiple devices.
MU9C4320L ATMCAM
Pin Descriptions
4
Rev. 3
PIN DESCRIPTIONS
Note: Signal names that start with a slash ("/") are active LOW. All signals are 3.3V CMOS level. Never leave inputs floating. The
CAM architecture draws large currents during compare operations, mandating the use of good layout and bypassing techniques. Refer
to the Electrical Characteristics section for more information.
DQ310 (Data Bus, Three-state, Common
Input/Output)
The DQ310 lines convey data to and from the
ATMCAM. When the /E input is HIGH the DQ310 lines
are held in their high-impedance state. The /W input
determines whether data flows to or from the device on the
DQ310 lines. The source or destination of the data is
determined by the AC110 lines and the /AV line. During
a Write cycle, data on the DQ310 lines is registered by
the falling edge of /E.
AC110 (Address/Control Bus, Input)
When Hardware control is selected, the AC110 lines
convey address or control information to the ATMCAM,
depending on the state of the /AV input. When /AV is
LOW then AC110 carry an address; when /AV is HIGH
AC110 carry control information. Data on the AC110
lines are registered by the falling edge of /E. When
software control is selected, the state of the AC110 lines
does not affect the operation of the device.
AA110 (Active Address, Output)
The AA110 lines convey the CAM Match address, the
VP Table address, the Next Free address, or Random
Access address, depending on the most recent memory
cycle. The /OE input enables the AA110 outputs; when
the /OE input is HIGH, the AA110 outputs are in their
high-impedance state; when /OE is LOW the AA110
lines are active. In a vertically cascaded system after a
Comparison cycle, Write at Next Free Address cycle or
Read/Write at Highest-Priority match, only the
highest-priority device will enable its AA110 lines,
regardless of the state of the /OE input. In the event of a
mismatch in both CAM array and VP Table after a
Compare cycle, or after a Write at Next Free Address
cycle into an already full system, the lowest-priority
device will drive the AA110 lines with all 1s. The
AA110 lines are latched when /E is LOW, and are free to
change only when /E is HIGH.
Figure 3: ATMCAM Pinout
ATMCAM
100-Pin TQFP
(Top View)
82
83
84
85
86
87
88
89
90
91
92
93
94
95
96
97
98
81
31
100
99
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
32
TCLK
TMS
TDI
DQ0
DQ1
DQ2
DQ3
VDD
DQ4
DQ5
DQ6
DQ7
GND
DQ8
DQ9
DQ10
DQ11
VDD
DQ12
DQ13
DQ14
DQ15
GND
GND
GND
AC11
AC10
AC9
AC8
AC7
AC6
VDD
AC5
AC4
AC3
AC2
AC1
AC0
TDO
NC
80
79
78
77
76
75
74
73
72
71
70
69
68
67
66
65
64
63
62
61
60
59
58
57
56
55
54
53
52
51
DQ16
DQ17
DQ18
DQ19
VDD
DQ20
DQ21
DQ22
DQ23
GND
DQ24
DQ25
DQ26
DQ27
VDD
DQ28
DQ29
DQ30
DQ31
GND
/E
/W
/CS1
/CS2
/OE
GND
/AV
/VB
/RESET
/TRST
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
GND
GND
NC
AA8
GND
AA7
AA6
AA5
AA4
VDD
AA3
AA2
AA1
AA0
GND
/MF
/FF
VDD
/MI
/FI
GND
/MV
/MM
PA3
PA2
PA1
PA0
AA10
AA9
AA11
Pin Descriptions
MU9C4320L ATMCAM
Rev. 3
5
PA30 (Page Address, Output)
The PA30 lines convey Page Address information. When
the /OE input is HIGH, the PA30 outputs are in their
high-impedance state; when /OE is LOW the PA30 lines
carry the Page Address value held in the Configuration
register. The PA30 lines are latched when /E is LOW, and
are free to change only when /E is HIGH. The Page
Address value of the currently active or highest-priority
responding device is output at the same time, and under
the same conditions, as the AA110 lines are active.
/E (Chip Enable, Input)
The /E input is the main chip enable and synchronizing
control for the ATMCAM. When /E is HIGH, the chip is
disabled and the DQ310 lines are held in their
high-impedance state. The falling edge of /E registers the
/W, /CS1, /CS2, /AV, /AC110 lines, and the /VB and
DQ310 lines for a Write cycle. /E being LOW causes the
results of the previous comparison or memory access to be
latched on the PA30:AA110 lines; when /E goes HIGH
the latches open allowing the new comparison results or
random access memory address to flow to the
PA30:AA110 lines.
/CS1, /CS2 (Chip Select 1, Chip Select 2,
Inputs)
The /CS1 and /CS2 inputs enable the ATMCAM. If either
/CS1 or /CS2 are LOW, the device is selected for a Read,
Write, or Compare cycle through the DQ310 lines, or for
an internal data transfer. The /CS1 and /CS2 lines do not
have any effect on the PA30:AA110 outputs. The state
of the /CS1 and /CS2 lines is registered by the falling edge
of /E.
/W (Write Enable, Input)
The /W input determines the direction of data transfer on
the DQ310 lines during Read, Write, and Data Move
cycles. When /W is LOW, data flows into the DQ310
lines; when /W is HIGH, data flows out. The /W line also
conditions the control state present on the AC110 lines.
The state of the /W line is registered by the falling edge of
/E.
/OE (Output Enable, Input)
The /OE input enables the PA30:AA110 outputs. When
/OE is HIGH, PA30:AA110 are in their high-impedance
state. When /OE is LOW, PA30:AA110 outputs are
active, and convey the results of the last Comparison
Cycle Match address or Memory Access address. In a
vertically cascaded system, only the PA30:AA110
outputs of the highest-priority device will be activated by
/OE being LOW; in lower-priority devices, the
PA30:AA110 outputs remain in high impedance
regardless of the state of /OE.
/AV (Address Valid, Input)
When Hardware control is selected, the /AV input
determines whether the AC110 lines carry address or
control information. When /AV is LOW, the AC110 lines
convey a memory address; when /AV is HIGH, the
AC110 lines convey control information. The state of the
/AV line is registered by the falling edge of /E. When
software control is selected, the /AV line distinguishes
between instructions and data on the DQ310 lines; when
/AV is LOW, data is present on the DQ310 lines; when
/AV is HIGH, an instruction is present on the DQ110
lines.
/VB (Validity Bit, Three-state, Common
Input/Output)
During accesses over the DQ310 lines, the /VB line
conveys validity information to and from the ATMCAM.
During a Write cycle (/W=LOW), when /VB is LOW the
addressed location is set valid; when /VB is HIGH it is set
empty. During a Read cycle (/W=HIGH), the validity of
the addressed location is read on the /VB line. During a
Write cycle, the state of the /VB line is registered by the
falling edge of /E.
/MF (Match Flag, Output)
The /MF output indicates whether a valid match has
occurred during the previous Comparison cycle. If the
/MF output is HIGH at the end of a Comparison cycle,
then no match occurred; if it is LOW then either a match
occurred within the device, or the /MI input is LOW,
conditioned by the /MF output from a higher-priority
device in the system. The /MF line is used in conjunction
with the /MV line to indicate when a match occurred in the
CAM array or the VP Table. If /MF is LOW, then the
match occurred in the CAM array; if /MF is HIGH and
/MV is LOW, then the match occurred in the VP Table.
Both /MF and /MV lines are HIGH after a Compare cycle
that results in a mismatch. The state of the /MF line will
not change until after the rising edge of /E during the
Comparison cycle. Note that /MF indicates the results of
the most recent Comparison cycle; it will not change when
the PA30:AA110 lines carry an address other than the
Match address.
/MI (Match Input, Input)
The /MI input receives match information from the next
higher-priority ATMCAM in a vertically cascaded system
to provide system-level prioritization. When the /MI input
is HIGH, the /MF output will only go LOW if there is a
match during a Comparison cycle; when the /MI input is
LOW, the /MF output will go LOW. The /MF output from
one device is connected to the /MI input of the next
lower-priority device. The /MI pin of the highest-priority
device must be tied HIGH.
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