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10/100Mb Ethernet switching, bridging, and remote
access at wire speed

Glueless connection to MUSIC LANCAM and most
10/100Mb Ethernet chip sets

Offloads all DA/SA processing and management
functions from host processor

Scalable up to eight ports of 100Mb Ethernet sharing
a common LANCAM database

Support station lists from 0.25K up to 32K

Full support of Unicast, Multicast, and
Broadcast frames

Built-in generic Processor port

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Four industry-standard 10/100Mb MII ports

Supports station list up to 32K addresses

Built-in arbitration supports eight 100Mb Ethernet
ports

Port ID identification and MAC Frame Reject signal
based on DA search results

Read search results from the Result port or CPU port

Hardware support for Tag switching

Optional automatic learning of new SAs

Optional automatic Aging and Purging

208-pin LQFP package

3.3 Volt operation

Figure 1: Block Diagram

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MU9C8358L Quad 10/100Mb

Ethernet Filter Interface

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The MU9C8358L, when configured with MUSIC
Semiconductors MU9Cx480B family of LANCAMs,
provides a high performance, large capacity Ethernet
address processing subsystem for use in Ethernet bridge,
switch, or remote access products. The device is designed

to work in multi-port systems that require a common
address database for all ports. Built-in arbitration allows
two MU9C8358L devices to share a common CAM
database, supporting up to eight 100Mb/s Ethernet ports at
wire speed.

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Because of the flexibility of the MU9C8358L, the best
way to approach the feature set of the device is to first
look at a typical Multiport 10/100Mb Ethernet application.
The MU9C8358L captures the Destination address (DA)
and the Source address (SA) of an incoming Ethernet
frame on the MII port. After checking for a frame error or
collision, the DA is processed and the result (associated
data, usually a port ID) is made available. The SA then is
checked, and either learned if new, or aged if already in the
list.

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The MU9C8358L plays an integral role in the example of
an Ethernet switching system, shown in Figure 2.

This system can handle up to 32,768 addresses distributed
over eight independent, bidirectional 100Mb Ethernet
ports by utilizing two MU9C8358L devices and four
LANCAMs connected as shown in Figure 1. The system is
based on several industry-standard and proprietary busses,
which are described in more detail later. The MII bus is
"tapped" to collect packet data as it passes from the PHY
to the MAC. That data is processed automatically by the
MU9C8358L/LANCAM combination. The LANCAM
bus is utilized to transfer the DA and SA to the CAMs for
comparisons, and to transfer the match results from the
CAMs to the MU9C8358L. The results of
MU9C8358L/LANCAM data processing are available
through the Result bus or through the Processor bus. In
addition to the Result bus, there is a serial Tag port per MII
port to relay the Tag ID to the system for systems that
support Tag switching. The Arbitration bus provides
communication between two MU9C8358L devices to
service eight MII ports with a shared CAM-based station
list.

When the DA is processed, the MU9C8358L first checks
if the frame is Unicast, Multicast, or Broadcast. Unicast
frames destined for the same collision domain (visible on
the same switch port as it came in on) are rejected. Unicast
frames that are destined for a different collision domain
(visible on a different switch port) are processed by the
system. If the DA is found in the CAM database, the port
ID associated with it is stored in the Result register.
Multicast and Broadcast frames are not processed by the
system. Instead they are identified and their classification
is stored in the Result register. Once processing completes,
the Result register is accessed through the Result port or
Processor port.

Provided the frame length is correct, and no errors are
detected, the SA is processed. If the SA exists in the CAM
database, the time stamp and Port ID are updated. If the
SA is not found in the CAM database, the address is
learned automatically, along with its Port ID and the
current time stamp information.

The built-in arbitration allows all ports equal access to the
CAM database. The arbitration scheme gives DA
processing the highest-priority, then SA processing.
Address processing always has priority over management
routines, such as purging aged entries, inserting permanent
entries, deleting entries, or reading from the CAM
database. Using the 70 ns speed grade CAMs and a 50
MHz system clock, there is sufficient time to support eight
DA searches, eight SA searches, and one management
routine, within the minimum frame time (about 6.2

S). In

addition, the arbitration bus allows the MU9C8358L to be
used with future MUSIC devices, sharing a common CAM
database.

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Figure 3: Pinout Diagram

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All signals are implemented in CMOS technology with TTL levels. Signal names that start with a slash ("/") are active
LOW. Inputs should never be left floating. Pins designated as "Reserved" must not be connected to any external circuitry.
Refer to the Electrical Characteristics section for more information.

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RXD[3:0] is the 4-bit MII Receive Data nibble (see
Timing Diagrams: Timing Data for RXD, RX_DV, and
RX_ER).

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Data Valid is on RX_DV; RX_DV is asserted by the PHY
at the beginning of the first nibble of the data frame and
deasserted at the end of the last nibble of the frame. It
indicates that the data is synchronous to RX_CLK and is
itself synchronous to the clock (see Timing Diagrams:
Timing Data for RXD, RX_DV, and RX_ER).

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RX_ER indicates a data symbol error in 100Mb/s mode or
any other error that the PHY can detect, even if the MAC
is not capable of detecting that error (see Timing
Diagrams: Timing Data for RXD, RX_DV, and RX_ER).

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RX_CLK is the receive clock recovered from the data by
the PHY. It is equal to 25 MHz in 100Base-X mode or 2.5
MHz in 10Base-X mode.

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Carrier sense CRS indicates that the medium is active
(non-idle) and remains asserted during a collision. For Rx
or Tx: CRS is HIGH in 10/100Base-X half-duplex mode;
for Rx it is HIGH in repeater, full-duplex, and loopback
modes. CRS is not synchronized to RX_CLK.

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Collision detect COL is asserted by the PHY upon
detection of a collision on the medium and remains
asserted as long as the collision persists. It is HIGH in
half-duplex modes and remains HIGH for 1 microsecond
following the end of transmission; it is LOW in
full-duplex mode. It is asserted in response to
signal_quality_error message from the PMA in 10Base-X
Heartbeat mode.

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REJ is the reject packet command issued by the
MU9C8358L; the minimum length is 110 nanoseconds.

REJ is driven HIGH to reject a data frame, and can be
detected by and responded to by the MAC devices from 2
bit times after SFD to 512 bit times (64 byte times) after
SFD. The REJ signal can be made active LOW by setting
Bit 0 in the SSCFG register. (See Timing Diagrams:
Timing Data for REJ (Base 100.))

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The Forced Receive Error pins provide the logical OR of
the RX_ER and REJ lines for the appropriate MII port (see
Timing Diagrams: Timing Data for FRX_ER in Relation
to REJ and RX_ER).

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The Tag Port Serial Data pin carries the destination Port
ID to external circuitry as soon as it is collected from the
CAM (see Timing Diagrams: Timing Data for Tag Ports
TP_DV and TP_SD).

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The Tag Port Data Valid pins are driven HIGH for as long
as unread data exists for each Destination Port ID. Pins
TP_SD_A through TP_SD_D carry the Destination Port
ID (4 bits) to external circuitry as soon as it is collected
from the CAM (see Timing Diagrams: Timing Data for
Tag Ports TP_DV and TP_SD).

Document Outline

Ð­Ð»ÐµÐºÑ‚Ñ€Ð¾Ð½Ð½Ñ‹Ð¹ ÐºÐ¾Ð¼Ð¿Ð¾Ð½ÐµÐ½Ñ‚: MU9C8358L-THC

Document Outline

ÐÐ»ÐµÐºÑ‚Ñ€Ð¾Ð½Ð½Ñ‹Ð¹ ÐºÐ¾Ð¼Ð¿Ð¾Ð½ÐµÐ½Ñ‚: MU9C8358L-THC