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Электронный компонент: MU9C8K64-70TDC

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Data Sheet
MUSIC Semiconductors, the MUSIC logo, and the phrase "MUSIC Semiconductors" are
June 1
2002 Rev. 6
Registered trademarks of MUSIC Semiconductors. MUSIC is a trademark of
MUSIC Semiconductors.
DQ310
/VB
AA Bus
PA30
/MM
/RESET
TCLK
TMS
TDI
TDO
/TRST
CONTROL
AND
ADDRESS
DECODER
PRIORITY
ENCODER
AND
FLAG
LOGIC
/E
/CS1
/CS2
/W
/OE
/AV
AC Bus
/DSC
INSTRUCTION REGISTER
DEVICE SELECT REGISTER
STATUS REGISTER
CONFIGURATION REGISTER
ADDRESS REGISTER
MASK REGISTERS 17
COMPARAND REGISTER
4 K x 64 Word
(MU9C4K64)
8 K x 64 Word
(MU9C8K64)
Address Database
/M F
/M I
/FF
/FI
Figure 1: Block Diagram
APPLICATION BENEFITS
28 million IPv4 packets per second supports up to 18
Gb Ethernet or 7 OC-48 ATM ports at wire speed
Exact match on MAC addresses
Processes DA and SA within 190 ns, supporting three ports
of 1 Gb or 34 ports of 100 Mb Ethernet at wire
speed
Mixed mode L3 and L2 single search engine for two ports
at 1 Gb or 29 ports of 100 Mb Ethernet at wire
speed
Directly addresses external RAM containing
associated data of any width
Hardware control states directly address memory and
registers; Instruction and Status registers for optional
software control
DISTINCTIVE CHARACTERISTICS
4K and 8K x 64-bit words
64-bit binary compares
35 ns deterministic compare and output time
32-bit Data I/O port
16-bit Match Address Output port
Address/Control bus directly controls device operations for
faster operation or higher throughput
Seven selectable mask registers
Synchronous operation
Cascadable for increased depth
Extensive set of control states for flexibility
JTAG interface
100-pin LQFP package; 3.3 Volt operation
MU9C Routing Coprocessor (RCP) Family
MU9C Binary Routing Coprocessor (RCP) Family General Description
2
Rev. 6
GENERAL DESCRIPTION
The MU9C RCP family consists of 4K and 8K x 64-bit
Routing Coprocessors (RCPs) with a 32-bit wide data
interface. The device is designed for use in layer 2
switches to provide very high throughput address
translation using tables held in external RAM. The MU9C
RCP has a fully deterministic search time, independent of
the size of the list and the position of the data in the list.
This unique feature guarantees that the wire speed address
recognition does not impact the latency or induce some
jitter on the latency of the global system. Address fields
from the packet header are compared against a list of
entries stored in the array. As a result of the comparison,
the MU9C RCP generates an index that is used to access
an external RAM where port mapping data and other
associated information is stored.
A set of control states provides a powerful and flexible
control interface to the MU9C RCP. This control structure
allows memory read and write, register read and write,
data move, comparison, validity control, addressing
control, and initialization operations.
The MU9C RCP architecture uses direct hardware control
of the device and an independent bus for returning match
results. Software control is also supported for systems
where maximum performance is not needed.
OPERATIONAL OVERVIEW
The MU9C RCP is designed to act as an address translator
for lookup tables in layer 2 switches. Refer to Figure 2 for
a simplified block diagram of a switch. During normal
operation, the controller extracts the address information
from an arriving packet to form the comparand, which is
then compared against the contents of the MU9C RCP.
The MU9C RCP generates an index that is used to access
the data in an external RAM, which holds the destination
port for accessing the network. The controller reads the
data from the RAM and forwards the packet.
The validity of a location in the Address Database is
determined by an extra bit called the Validity bit. This bit is
set and reset either with an index or an associative match.
Therefore, when a new entry is written to the database, its
Validity bit is set valid. The index at which a write takes
place is driven onto the PA:AA bus, so that output port
data can be written simultaneously into the external RAM
at the correct index.
When a database location is deleted, the Validity bit for that
entry is reset, and the index of the location is driven onto
the Active Address bus. This simple mechanism allows
easy maintenance of the tables in both the database and the
external RAM.
The MU9C RCP supports simple daisy chained vertical
cascading that serves to prioritize multiple devices and
provides system-level match and full indication. If the
slight timing overhead associated with the daisy chain is
unacceptable, the MU9C RCP is designed to facilitate
external prioritization across multiple devices.
Figure 2: Switch Block Diagram
Controller
RAM
Switch
Fabric
MU
9C
Switch Control
and Packet Data
Network
Address
Data
RCP
Control
Packet Stream
RAM
Address
Pin Descriptions MU9C Binary Routing Coprocessor (RCP) Family
Rev. 6
3
PIN DESCRIPTIONS
Note: Signal names that start with a slash ("/") are active LOW.
All signals are 3.3V CMOS level. Never leave inputs floating.
The CAM architecture draws large currents during compare
operations, mandating the use of good layout and bypassing
techniques. Refer to the Electrical Characteristics section for
more information.
DQ310 (Data Bus, Three-state, Common Input/
Output)
The DQ310 lines convey data to and from the MU9C
RCP. When the /E input is HIGH the DQ310 lines are
held in their high-impedance state. The /W input
determines whether data flows to or from the device on the
DQ310 lines. The source or destination of the data is
determined by the AC bus, DSC, and the /AV line. During
a Write cycle, data on the DQ310 lines is registered by
the falling edge of /E.
AC120/AC110 (Address/Control Bus, Input)
When Hardware control is selected, the AC bus conveys
address or control information to the MU9C RCP,
depending on the state of the /AV input. When /AV is
LOW then the AC bus carries an address; when /AV is
HIGH the AC bus carries control information. Data on the
AC bus is registered by the falling edge of /E. When
software control is selected, the state of the AC bus does
not affect the operation of the device.
DSC (Data Segment Control, Input)
When DQ bus access to a 64 bit register or memory word
is performed, the DSC input determines whether bits 310
(DSC LOW) or bits 6332 (DSC HIGH) are accessed.
Access to 32 bit registers require that DSC be held LOW.
AA120/AA110 (Active Address, Output)
The AA bus conveys the Match address, the Next Free
address, or Random Access address, depending on the
most recent memory cycle. The /OE input enables the AA
bus; when the /OE input is HIGH, the AA bus is in its
high-impedance state; when /OE is LOW the AA bus is
active. In a vertically cascaded system after a Comparison
cycle, Write at Next Free Address cycle or Read/Write at
Highest-Priority match, only the highest-priority device
will enable its AA bus, regardless of the state of the /OE
input. In the event of a mismatch in the Address Database
after a Compare cycle, or after a Write at Next Free
Address cycle into an already full system, the
lowest-priority device will drive the AA bus with all 1s.
The AA bus is latched when /E is LOW, and are free to
change only when /E is HIGH.
Figure 3: MU9C RCP Pinout
82
83
84
85
86
87
88
89
90
91
92
93
94
95
96
97
98
81
31
10 0
99
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
32
TCLK
TMS
TDI
DQ0
DQ1
DQ2
DQ3
VDD
DQ4
DQ5
DQ6
DQ7
VSS
DQ8
DQ9
DQ10
DQ11
VDD
DQ12
DQ13
DQ14
DQ15
VSS
VSS
VSS
AC11
AC10
AC9
AC8
AC7
AC6
VDD
AC5
AC4
AC3
AC2
AC1
AC0
TDO
AA12/NC*
8
0
7
9
7
8
7
7
7
6
7
5
7
4
7
3
7
2
7
1
7
0
6
9
6
8
6
7
6
6
6
5
6
4
6
3
6
2
6
1
6
0
5
9
5
8
5
7
5
6
5
5
5
4
5
3
5
2
5
1
D
Q
1
6
D
Q
1
7
D
Q
1
8
D
Q
1
9
V
D
D
D
Q
2
0
D
Q
2
1
D
Q
2
2
D
Q
2
3
V
S
S
D
Q
2
4
D
Q
2
5
D
Q
2
6
D
Q
2
7
V
D
D
D
Q
2
8
D
Q
2
9
D
Q
3
0
D
Q
3
1
V
S
S
/
E
/
W
/
C
S
1
/
C
S
2
/
O
E
V
S
S
/
A
V
/
V
B
/
R
E
S
E
T
/
T
R
S
T
1
2
3
4
5
6
7
8
9
1
0
1
1
1
2
1
3
1
4
1
5
1
6
1
7
1
8
1
9
2
0
2
1
2
2
2
3
2
4
2
5
2
6
2
7
2
8
2
9
3
0
V
S
S
V
S
S
A
A
1
2
/
N
C
*
A
A
8
V
S
S
A
A
7
A
A
6
A
A
5
A
A
4
V
D
D
A
A
3
A
A
2
A
A
1
A
A
0
V
S
S
/
M
F
/
F
F
V
D
D
/
M
I
/
F
I
V
S
S
/
M
M
D
S
C
P
A
3
P
A
2
P
A
1
P
A
0
A
A
1
0
A
A
9
A
A
1
1
MU9CxK64
100-Pin
LQFP
(Top View)
* NC on MU9C4K64
MU9C Binary Routing Coprocessor (RCP) Family Pin Descriptions
4
Rev. 6
PA30 (Page Address, Output)
The PA30 lines convey Page Address information. When
the /OE input is HIGH, the PA30 outputs are in their
high-impedance state; when /OE is LOW the PA30 lines
carry the Page Address value held in the Configuration
register. The PA30 lines are latched when /E is LOW, and
are free to change only when /E is HIGH. The Page
Address value of the currently active or highest-priority
responding device is output at the same time, and under
the same conditions, as the AA bus is active.
/E (Chip Enable, Input)
The /E input is the main chip enable and synchronizing
control for the MU9C RCP. When /E is HIGH, the chip is
disabled and the DQ310 lines are held in their
high-impedance state. The falling edge of /E registers the
/W, /CS1, /CS2, /AV, /AC bus, DSC, and the /VB and
DQ310 lines for a Write cycle. /E being LOW causes the
results of the previous comparison or memory access to be
latched on the PA:AA bus; when /E goes HIGH the latches
opens allowing the new comparison results or random
access memory address to flow to the PA:AA bus.
/CS1, /CS2 (Chip Select 1, Chip Select 2, Inputs)
The /CS1 and /CS2 inputs enable the MU9C RCP. If
either /CS1 or /CS2 are LOW, the device is selected for a
Read, Write, or Compare cycle through the DQ310 lines,
or for an internal data transfer. The /CS1 and /CS2 lines do
not have any effect on the PA:AA bus. The state of the
/CS1 and /CS2 lines is registered by the falling edge of /E.
/W (Write Enable, Input)
The /W input determines the direction of data transfer on
the DQ310 lines during Read, Write, and Data Move
cycles. When /W is LOW, data flows into the DQ310
lines; when /W is HIGH, data flows out. The /W line also
conditions the control state present on the AC bus and
DSC lines. The state of the /W line is registered by the
falling edge of /E.
/OE (Output Enable, Input)
The /OE input enables the PA:AA bus. When /OE is
HIGH, PA:AA bus are in their high-impedance state.
When /OE is LOW, PA:AA bus are active, and convey the
results of the last Comparison Cycle Match address or
Memory Access address. In a vertically cascaded system,
only the PA:AA bus of the highest-priority device will be
activated by /OE being LOW; in lower-priority devices,
the PA:AA bus remains in high-impedance regardless of
the state of /OE.
/AV (Address Valid, Input)
When Hardware control is selected, the /AV input
determines whether the AC bus carries address or control
information. When /AV is LOW, the AC bus conveys a
memory address; when /AV is HIGH, the AC bus conveys
control information. The state of the /AV line is registered
by the falling edge of /E. When software control is
selected, the /AV line distinguishes between instructions
and data on the DQ310 lines; when /AV is LOW, data is
present on the DQ310 lines; when /AV is HIGH, an
instruction is present on the DQ110 lines.
/VB (Validity Bit, Three-state, Common
Input/Output)
During accesses over the DQ310 lines, the /VB line
conveys validity information to and from the MU9C RCP.
During a Write cycle (/W=LOW), when /VB is LOW the
addressed location is set valid; when /VB is HIGH it is set
empty. During a Read cycle (/W=HIGH), the validity of
the addressed location is read on the /VB line. During a
Write cycle, the state of the /VB line is registered by the
falling edge of /E.
/MF (Match Flag, Output)
The /MF output indicates whether a valid match has
occurred during the previous Comparison cycle. If the /MF
output is HIGH at the end of a Comparison cycle, then no
match occurred; if it is LOW then either a match occurred
within the device, or the /MI input is LOW, conditioned by
the /MF output from a higher-priority device in the system.
The state of the /MF line will not change until after the
rising edge of /E during the Comparison cycle. Note that
/MF indicates the results of the most recent Comparison
cycle; it will not change when the PA:AA bus carry an
address other than the Match address.
/MI (Match Input, Input)
The /MI input receives match information from the next
higher-priority MU9C RCP in a vertically cascaded
system to provide system-level prioritization. When the
/MI input is HIGH, the /MF output will only go LOW if
there is a match during a Comparison cycle; when the /MI
input is LOW, the /MF output will go LOW. The /MF
output from one device is connected to the /MI input of the
next lower-priority device. The /MI pin of the
highest-priority device must be tied HIGH.
/FF (Full Flag, Output)
The /FF output indicates when all the memory locations
have their Validity bits set valid (LOW). When there is at
least one location with its Validity bit set HIGH, the /FF
output will be HIGH; when all locations have their Validity
bits set LOW, and the /FI input is LOW, the /FF output will
MU9C Binary Routing Coprocessor (RCP) Family
Rev. 6
5
be LOW. If the /FI input is HIGH, the /FF output will be
HIGH. The state of the /FF line will not change until after
the rising edge of /E during a Write cycle.
/FI (Full Input, Input)
The /FI input receives full information from the next
higher-priority MU9C RCP in a vertically cascaded
system to provide system-level full information. When the
/FI input is LOW the /FF output will be HIGH if there is at
least one location whose Validity bit is set invalid; when
all locations have their Validity bits set valid, the /FF
output goes LOW. When the /FI input is HIGH, the /FF
output will remain HIGH. The /FF output from one device
is connected to the /FI input of the next lower-priority
device to give system-full indication. The /FI pin of the
highest-priority device must be tied LOW.
/MM (Multiple Match, Open Drain Output)
The /MM line indicates that there is a multiple match
within the system. When the /MI input is HIGH, the /MM
line is pulled LOW if there are at least two matches within
the MU9C RCP as a result of the previous Comparison
cycle; when there are less than two matches, the /MM line
floats HIGH. When the /MI input is LOW, the /MM line is
pulled LOW if there are one or more matches within the
MU9C RCP as a result of the previous Comparison cycle;
when there are no matches, the /MM line floats HIGH.
The /MM lines have open-drain outputs, so all /MM lines
within the system are connected together to give
system-level multiple match indication. The state of the
/MM line will not change until after the rising edge of /E
during a Comparison cycle.
/RESET
The /RESET input is used to reset the MU9C RCP to a
known state. When the /RESET line is pulled LOW it
causes the MU9C RCP to enter its reset state. After power
is applied to the MU9C RCP, the /RESET line must be
held LOW for a time equal to or greater than the minimum
RESET pulse width before the device can operate
correctly. This pin is internally pulled up.
TCLK (JTAG Test Clock, Input)
The TCLK input is the Test Clock input. This pin is
internally pulled up.
TMS (JTAG Test Mode Select, Input)
The TMS input is the Test Mode Select input. This pin is
internally pulled up.
TDI (JTAG Test Data Input, Input)
The TDI input is the Test Data input. This pin is internally
pulled up.
TDO (JTAG Test Data Output, Output)
The TCLK output is the Test Data Output. This pin is
internally pulled up.
/TRST (JTAG Reset, Input)
The /TRST input is the Reset input, and serves to reset the
Test Access Port circuitry to its reset condition. This pin is
internally pulled up.
VDD, VSS (Positive Power Supply, Ground)
These pins are the main power supply connections to the
MU9C RCP. VDD must be held at +3.3 Volts and 0.3
Volts relative to the VSS pin, which is at 0 Volts, system
reference potential, for correct operation of the device.
Note: The TCLK, TMS, TDI, TDO, and /TRST lines are defined
in the IEEE Standard Test Access Port and Boundary-scan
Architecture IEEE Standard. 1149.1-1990 and IEEE Standard.
1149.1a-1993.
FUNCTIONAL DESCRIPTION
Data is read from and written to the MU9C RCP through
the DQ310 lines. The Control bus, which is comprised of
Chip Enable (/E), two Chip Selects (/CS1, /CS2), Write
Enable (/W), Output Enable (/OE), Validity Bit Control
(/VB), Address Valid (/AV), Data Segment Control (DSC),
and the Address/Control inputs (AC bus) controls the
MU9C RCP. When the /AV line is LOW, the AC bus
carries an address for random access into the Memory
array; when it is HIGH, the AC bus conveys control
information. The MU9C RCP control states perform
Register Read/Write, Memory Read/Write, Data Move,
Comparison, Validity Bit Control, Initialization, and
Address Register Control. These functions are
summarized in Control State Overview on page 15.
Random access to memory locations occurs when the /AV
line is LOW; during a Write cycle, the validity of the
location is set by the /VB input. When the /AV line is
HIGH the control states allow read and write access to the
register set comprising Comparand register, seven mask
registers, a Configuration register, a Status register, an
Address register, a Device Select register, and an
Instruction register. The Configuration register sets the
persistent operating conditions of the device: the Page
address of the device, selection of mask register for
directly addressed memory writes, and selection between
hardware and software control.