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High-performance MAC Address processor for
multiport switches and routers (up to 48 10/100Mb or
4 Gigabit Ethernet at wire speed)
Layer 4 flow recognition for Quality of Service up to
16.7 million packets per second
ARP cache manager/IP address caching at 12.5
million packets per second
Synchronous interfaces and programmable priority
between ports for simplicity of design
Learn, age, and auto-age functions with "virtual
queues" keeping track of aged and learned entries
Transparent cascade of up to four devices without
external logic, software setup, or performance hit
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2K and 8K x 80-bit partitionable CAM/RAM data
field in address database
32-bit synchronous port with separate inputs and
outputs; optional 16-bit configuration
32-bit bi-directional processor port; optional 16-bit
configuration
Pipelined operation
Operations performed from the synchronous port or
processor port; all flags independently available to
both ports
9-bit internal time stamp
50 MHz clock
160-pin PQFP package
3.3 Volt core with 3.3 Volt/5 Volt tolerant IO buffers
IEEE 1149.1 (JTAG) compliant
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MUAA Routing Co-Processor (RCP) Family
MUAA Routing Co-Processor (RCP) Family
MUAA Routing Co-Processor (RCP) Family
MUAA Routing Co-Processor (RCP) Family
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The MUSIC MUAA Routing Co-Processor (RCP) family
consists of 80-bit wide content-addressable memories
(CAMs), available in depths of 2K and 8K words. The
CAM/RAM associated data partition is programmable
from 32 bits of CAM and 48 bits of associated data, to 80
bits of CAM and 0 bits of RAM. The MUAA RCP can
perform normal routing functions such as search, insert,
and delete on single entries and can age multiple entries
simultaneously. In addition, there is a learn instruction,
particularly useful in networking applications. For
maximum flexibility all the operations may be performed
either through the processor port or through the synchro-
nous port. Operations may occur on both ports simulta-
neously; the port with the highest priority will gain access
first if both ports require a read or write into the CAM
array simultaneously.
The synchronous interface consists of 32-bit wide input
and output ports, both of which may be configured as 16
bits. The data is multiplexed into and out of the CAM and
RAM associated data field. Where input or output data is
wider than the port, it is loaded or unloaded in multiple
cycles starting with the least significant word. Internally
the device is pipelined; once an operation is started on the
synchronous port the next operation may be loaded and the
results of the previous operation unloaded, thus
maximizing device throughput.
Multiple MUAA RCPs may be chained transparently to
provide deeper memory. No software configuration is
necessary. Each MUAA RCP detects where it is in the
chain from the chaining pins on the previous device. A
register is provided to inform the host of the total available
CAM memory and the number of CAMs chained. All
operations to the chained CAM are totally transparent. No
individual device selection or addressing is required.
The MUSIC MUAA RCP has aging, auto-aging, and
learning functions. All entries have a 9-bit time stamp and
may be marked as static to prevent the aging function from
deleting them. When auto aging is enabled it may be
configured to have higher or lower priority access than the
ports.
Two internal virtual queues of learned and aged entries are
available. As entries are learned or aged out they are
tagged as such and may be read from the device through
either of the ports. This feature enables simple host
management of aged out and learned entries.
IEEE Standard. 1149.1 (JTAG) testability is implemented
providing BYPASS, SAMPLE/PRELOAD, EXTEST,
CLAMP, and HIGH-Z functions.
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Note: Signal names that start with a slash ("/") are active LOW. All signals are 3.3 Volt CMOS level. All input
and bi-directional pins are 5-Volt tolerant, except for CLK. Never leave inputs floating except where
indicated. The CAM architecture draws large currents during search operations, mandating the use of good
layout and bypassing techniques. Refer to the Electrical Characteristics section for more information.
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DIN[31:0] are synchronous port data input pins. Data is
loaded into the MUAA RCP right aligned, least significant
word first.
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DIN is sampled by the rising edge of CLK when /DINE is
asserted.
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OP[3:0] is a synchronous port operation to be performed on
the data applied to the DIN pins. OP is sampled by the rising
edge of CLK when /DINE is asserted. When loading the
CAM/RAM words to DIN, OP is set to LOAD except for the
last word. OP for the last word is set to the desired operation.
160-Pin
PQFP
160
121
122
123
124
125
126
127
128
129
130
131
132
133
134
135
136
137
138
139
140
141
142
143
144
145
146
147
148
149
150
151
152
153
154
155
156
157
158
159
41
80
79
78
77
76
75
74
73
72
71
70
69
68
67
66
65
64
63
62
61
60
59
58
57
56
55
54
53
52
51
50
49
48
47
46
45
44
43
42
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119
118
117
116
115
114
113
112
111 110 109 108 107
106
105
104
103
102
101
100
99
98
97
96 95
94
93 92
91
90 89
88
87 86 85
84 83 82
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3 4
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6
7
8
9 10
11
12 13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36 37 38
39
GN
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VCC
DOUT0
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DIN
30
DIN
29
DIN
28
DIN
27
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DIN
26
DIN
25
DIN
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DIN
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VCC DIN
20
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19
DIN
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GND
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VCC
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GND
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VCC
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VCC
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GND
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When DINREADY is HIGH, the synchronous port
accepted the current operation. This is affected by the
priority set for the DIN port and the processor port. Note,
DINREADY may be LOW for up to 800 CLK periods
after /RESET is taken HIGH. The JTAG interface is able
to set DINREADY to HIGH-Z. Active HIGH.
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DOUT[31:0] is the synchronous port data output. Data is
read out right aligned, least significant word first. The
address index (bits 250), SWEX flag (bit 26), PWEX flag
(bit 27), LQUEUE flag (bit 28), AQUEUE flag (bit 29),
Sync Port Match flag (bit 30), and Full flag (bit 31) may
also be read from this port before or after operation data
depending on configuration.
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/DOUTVALID indicates when new data is available at the
synchronous output port. /DOUTVALID is active LOW
for one CLK cycle. /DOUTVALID may be configured to
become active on the same clock as new DOUT becomes
valid or the CLK before. The JTAG interface is able to set
/DOUTVALID to HIGH-Z.
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/OE is the DOUT High Impedance control.
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/DOUTE is the DOUT enable control. When the DOUT
data word is configured to be wider than the output port
then this strobe enables the next word(s) of the DOUT data
onto the DOUT pins.
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The bi-directional Processor data port provides the
processor interface to the device. On write cycles, all
devices respond in parallel. On read cycles, the appro-
priate device responds without additional intervention
from the processor.
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Processor port address bus. Selects which device register
is accessed. Bit 0 is only used when the port is set to 16-bit
mode, otherwise it should be held at a valid logic level.
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R/W is the processor port read/write control pin. This pin
is HIGH for reads, LOW for writes.
3&6 ,QSXW
/PCS is the processor port chip select pin. When LOW this
pin indicates a cycle to the processor port. On write cycles
data must be set up to the rising edge of /PCS. On read
cycles /PCS controls the output enable of the PROCD bus.
Note that /PCS may be asynchronous to CLK.
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When PROCREADY is HIGH, indicates the processor
read data is available or the processor write data is
accepted. Priority may be set between the DIN port and
the processor port. Note PROCREADY may be LOW for
up to 800 CLK periods after /RESET is taken HIGH. The
JTAG interface is able to set PROCREADY to HIGH-Z.
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INT interrupt. Indicates the aged or learned queue has at
least one entry or a write exception occurred. The service
routine should either check the AQUEUE, LQUEUE, and
WEX registers, or bits 2629 of the Address Index
register, to determine the cause. The interrupt is cleared
after the appropriate flag register has been read and will
not be reasserted until either the queue(s) are emptied and
then get at least one entry again, or another write exception
occurs. The JTAG interface is able to set INT to HIGH-Z.
5(6(7 ,QSXW
The /RESET input is used to reset the MUAA RCP.
/RESET must be asserted for at least 3 CLK periods.
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The rising edge of CLK input is the device clock.
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/FF is active when the device (or chain of devices) is full.
/FF becomes inactive when any one device has two open
entries. The JTAG interface is able to set /FF to HIGH-Z.
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When two or more devices are chained they communicate
among themselves using the CHAIN[3:0] signals. See
Chaining section. Internally Pulled-up.
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When two or more devices are chained they communicate
among themselves using the CHAINUP signals. See
Chaining section. The JTAG interface is able to set
CHAINUP to HIGH-Z.
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When two or more devices are chained they communicate
among themselves using the CHAINDN signals. See
Chaining section. The JTAG interface is able to set
CHAINDOWN to HIGH-Z.
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When two or more devices are chained they communicate
among themselves using the CHAINCS signals. See
Chaining section. Internally pulled up.
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The /MF output indicates whether a match was found. The
JTAG interface is able to set /MF to HIGH-Z.
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The /TRST is the Test Reset pin. Internally pulled up with
25K minimum. Must be tied to /RESET or tied LOW
when not in use.
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The /TCLK input is the Test Clock input. Must be tied at a
valid logic level when not in use.
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The TMS input is the Test Mode Select input. Internally
pulled up with 25K minimum.
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The TDI input is the Test Data input. Internally pulled up
with 25K minimum.
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The TDO output is the Test Data output.
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These pins are the power supply connection to the MUAA
RCP. VCC must meet the voltage supply requirements in
the Operating Conditions section relative to the GND pins,
which are at 0 Volts (system reference potential), for
correct operation of the device. All the ground and power
pins must be connected to their respective planes with
adequate bulk and high frequency bypassing capacitors in
close proximity to the device.
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In order to keep data alignment simple, the number of
words to be loaded and unloaded for each operation is kept
consistent for each CAM/RAM partition configuration and
the width of the port.
Tables 1 and 2 show the cycle sequence and CAM/RAM
bit mappings for 32- and 16-bit bus modes. The bus may
be selected for each port independently. Table 3 shows
whether CAM, RAM or both types of segments are used
on input or output cycles for each operation.
Loads always start right aligned from the least significant
word, CAM partition first, followed by RAM if necessary.
Most instructions do not require the entire 80 bits to be
loaded.
CAM data is required as an input for all operations except
READ LQUEUE and READ AQUEUE. The use of RAM
data is optional (i.e., it is not necessary to perform all
RAM cycles when inputting data). However, the user must
be aware that INSERT and LEARN operations will
over-write RAM data. Therefore, the application should
remain consistent in the number of RAM bits used for
these operations.
All CAM and RAM segment writes except the last use the
LOAD instruction. The last segment of data uses the
instruction for the desired operation.
Depending on the operation, unloads either start from the
right aligned, least significant word of CAM followed by
the right aligned, least significant word of RAM or just
from the right aligned, least significant word of RAM. For
instance, a QUEUE read returns CAM then RAM,
whereas a search just returns RAM. Where the
CAM/RAM partition does not lie on a port width
boundary the last word of the read may contain undefined
data in the most significant bits. The number of unload
cycles actually completed is optional.
The DOUT register stores the results of operations from
the asynchronous processor port. Search results are
obtained by repeated reads of DOUT until all RAM data is
read. When performed from the processor port, READ
LQUEUE and READ AQUEUE return the first segment
of CAM data on the cycle that requests the operation;
additional CAM and RAM segments are obtained by
repeated reads of the DOUT register.
Loading is flow controlled on the synchronous DIN port
with the DINREADY signal, which is HIGH when data is
accepted by the DIN port. On the Processor port the
PROCREADY signal is HIGH when the current write
cycle may complete.
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On the synchronous port, operations are started on the
CLK cycle in which the requested Op-Code is written. On
the processor port operations are started when the chosen
operation register is written. The user should use the flow
control mechanisms to determine when results are avail-
able. On the synchronous port the /DOUTVALID signal is
asserted for one CLK cycle when new data is written to
the DOUT port. The processor port will assert its
PROCREADY signal on the CLK edge that data is avail-
able. Note that there is no internal flow control from the
sync DOUT port back to the sync DIN port. The DOUT
data is overwritten if it is not unloaded.
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