2-Port 10M/100M Switch With Built-in Memory
USA:
4020 Moorpark Avenue Suite 115
San Jose, CA, 95117
Tel: 408-243-8388 Fax: 408-243-3188
Sales@myson.com.tw
www.myson.com.tw
Rev. 1.4 December 2002
page 1 of 12
Myson Century, Inc.
Taiwan:
No. 2, Industry East Rd. III,
Science-Based Industrial Park, Hsin-Chu, Taiwan
Tel: 886-3-5784866 Fax: 886-3-5784349
MTD502E
BLOCK DIAGRAM
GENERAL DESCRIPTION
FEATURES
The MTD502E is a highly integrated, 10M/
100M two port switch controller with built-in
embedded memory. It supports 2 MII ports for 10M/
100M operation, and both meet IEEE802.3 and
IEEE802.3u specification.
The MTD502E is an ideal solution for two-port
bridge applications, and no needs any external
memory buffers in application design.
The MTD502E provides packet forwarding,
address filtering, learning, and aging between two
10/100Mbps ethernet ports. The two ethernet ports
support half/full duplex operation , and have an
optional backpressure control implemented in half
duplex mode.
The MTD502E supports an effective address
filtering database, which can recognize up to 2048
MAC addresses. It also supports an automatic aging
function for address table updating (the default value
of aging time is 300 seconds).
IEEE802.3 and IEEE802.3u compliant.
Single chip, two port switch controller.
Built-in embedded memory on chip for packet buff-
ering, no need any external memory buffers in
application.
Provide 2 MII ports.
Support half/full duplex operation per port.
Optional backpressure control for half duplex
mode.
Provide "store and forward" switching, and for-
warding rate at full-wire speed.
Support up to 2048 MAC addresses filtering data-
base.
Support automatical address aging-out function
(300 secs).
Low power CMOS design, with single 3.3V supply
voltage.
50 MHZ operation, 128-pin PQFP package.
Port1 DMA
Two
Embedded
MII1
Port0 DMA
MAC0
MAC1
Port
Switch
Engine
Memory
Jumper
Setting
SPEED0/1,
FULL0/1,
LINK0/1
LED
RSTB
SYSCLK
MII0
RXD0,RXC0,
TXD0,TXEN0
CRS0,COL0
RXD1,RXC1,
TXD1,TXEN1
CRS1,COL1
RXDV0,TXC0,
RXDV1,TXC1
CLK25OUT
page 2 of 12
MTD502E
SYSTEM DIAGRAM
Two-Port Swtich Application
MTD502E
MII0
MII1
10M/100M
PHYsceiver
Transformer
10M/100M
PHYsceiver
Transformer
RJ45
RJ45
Dual-Speed Hub Application
MTD502E
10M/100M
Repeater
(Without 2P_sw)
10M/100M
Repeater
(Without 2P_sw)
page 3 of 12
MTD502E
PIN CONNECTION
64
63
62
61
60
59
58
57
56
55
54
53
52
51
50
49
48
47
46
45
44
43
42
41
40
39
103
104
105
106
107
108
109
110
111
112
113
114
115
116
117
118
119
120
121
122
123
124
125
126
127
128
10
2
10
1
10
0
99
98
97
96
95
94
93
92
91
90
89
88
87
86
85
84
83
82
81
80
79
78
77
76
75
74
73
72
71
70
69
68
67
66
65
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
LI
N
K
0
TXD
0
_3
VCC
TXD
0
_2
NC
NC
NC
NC
TXD
0
_1
TXD
0
_0
TXEN0
TXC
0
NC
GND
RXC0
NC
NC
NC
RXD0
_
0
RXD0
_
1
FU
L
L
0
NC
NC
NC
RXD0
_
2
RXD0
_
3
RXDV0
CRS0
COL
0
SPEED0
VCC
GND
LI
N
K
1
TXD
1
_3
TXD
1
_2
NC
NC
NC
NC
NC
NC
NC
L
N
K
R
X
0
_LE
D
L
N
K
R
X
1
_LE
D
L
N
K
A
C
T
0_
LE
D
L
N
K
A
C
T
1_
LE
D
F
DCOL
0
_
L
E
D
F
DCOL
1
_
L
E
D
GND
C
O
L0
_L
E
D
C
O
L1
_L
E
D
NC
NC
NC
NC
NC
NC
NC
GND
NC
NC
NC
NC
NC
NC
NC
GND
NC
VCC
NC
NC
NC
NC
VCC
NC
NC
VCC
NC
GND
NC
NC
NC
NC
NC
NC
NC
NC
CLK25OUT
NC
NC
GND
NC
NC
NC
VCC
SYSCLK
GND
NC
NC
NC
NC
RSTB
SPEED1
COL1
CRS1
RXDV1
GND
VCC
RXD1_3
RXD1_2
NC
NC
NC
FULL1
RXD1_1
RXD1_0
NC
NC
NC
RXC1
GND
VCC
NC
TXC1
TXEN1
TXD1_0
TXD1_1
NC
MTD502E
page 4 of 12
MTD502E
PIN DESCRIPTION
Name
I/O
Pin
Descriptions
LINK0
I
1
Port0 : LINK input indicator from PHY devices, low-active. *
TXD0_3
O
2
Port0: TXD bit [3], output to PHY device.
VCC
3
TXD0_2
O
4
Port0: TXD bit [2], output to PHY device.
(NC)
O
5
(NC)
I
6~8
TXD0_1
O
9
Port0: TXD bit [1], output to PHY device.
TXD0_0
O
10
Port0: TXD bit [0], output to PHY device.
TXEN0
O
11
Port0: TXEN, output to PHY device, high-active.
TXC0
I
12
Port0: TXC, input from PHY device.
(NC)
I 13
GND
14
RXC0
I
15
Port0: RXC, input from PHY device.
(NC)
O
16
(NC)
O
17
(NC)
O
18
RXD0_0
I
19
Port0: RXD bit [0], input from PHY device.
RXD0_1
I
20
Port0: RXD bit [1], input from PHY device.
FULL0
I
21
Port0: FULL_duplex indicator from PHY device, low-active. *
(NC)
O
22~24
RXD0_2
I
25
Port0: RXD bit [2], input from PHY device.
RXD0_3
I
26
Port0: RXD bit [3], input from PHY device.
RXDV0
I
27
Port0: RXDV, input from PHY device, high-active.
CRS0
I
28
Port0: CRS, input from PHY device, high-active.
COL0
I
29
Port0: COL indicator from PHY device, low-active. *
SPEED0
I
30
Port0: SPEED indicator from PHY device, low-active. *
VCC
31
GND
32
LINK1
I
33
Port1 : LINK input indicator from PHY devices, low _active. *
TXD1_3
O
34
Port1: TXD bit [3], output to PHY device.
TXD1_2
O
35
Port1: TXD bit [2], output to PHY device.
(NC)
O
36
(NC)
I
37,38
(NC)
I
39
TXD1_1
O
40
Port1: TXD bit [1], output to PHY device.
page 5 of 12
MTD502E
TXD1_0
O
41
Port1: TXD bit [0], output to PHY device.
TXEN1
O
42
Port1: TXEN, output to PHY device, high-active.
TXC1
I
43
Port1: TXC, input from PHY device.
(NC)
I
44
VCC
45
GND
46
RXC1
I
47
Port1: RXC, input from PHY device.
(NC)
O
48~50
RXD1_0
I
51
Port1: RXD bit [0], input from PHY device.
RXD1_1
I
52
Port1: RXD bit [1], input from PHY device.
FULL1
I
53
Port1: FULL duplex indicator from PHY device, low-active. *
(NC)
O
54~56
RXD1_2
I
57
Port1: RXD bit [2], input from PHY device.
RXD1_3
I
58
Port1: RXD bit [3], input from PHY device.
VCC
59
GND
60
RXDV1
I
61
Port1: RXDV, input from PHY device, high-active.
CRS1
I
62
Port1: CRS, input from PHY device, high-active.
COL1
I
63
Port1: COL indicator from PHY device, low-active. *
SPEED1
I
64
Port1: SPEED indicator from PHY device, low-active. *
(NC)
I
65~66
VCC
67
(NC)
IO
68~71
VCC
72
(NC)
IO
73
GND
74
(NC)
IO
75,76
(NC)
I
77~79
(NC)
O
80
(NC)
IO
81
GND
82
(NC)
IO
83~85
(NC)
I
86~88
(NC)
O
89
COL1_LED
IO
90
Port1: COL LED display, low-active. This pin represents Port1's collision.
COL0_LED
IO
91
Port0: COL LED display, low-active. This pin represents Port0's collision.
GND
92
Name
I/O
Pin
Descriptions
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