BLOCK DIAGRAM

GENERAL DESCRIPTION

FEATURES

MTD981

USA:
4020 Moorpark Avenue Suite 115
San Jose, CA, 95117
Tel: 408-243-8388 Fax: 408-243-3188

Sales@myson.com.tw

www.myson.com.tw

Rev. 1.4 February 2003

page 1 of 17

Myson Century, Inc.
Taiwan:
No. 2, Industry East Rd. III,
Science-Based Industrial Park, Hsin-Chu, Taiwan
Tel: 886-3-5784866 Fax: 886-3-5784349

10/100M Ethernet Transceiver

· 10BASE-T, 100BASE-TX, and 100BASE-FX

IEEE802.3 compliant transmit and receive
functions

· IEEE802.3u Clause 28 compliant Auto-

Negotiation function

· Full duplex operation capable
· Baseline wander compensation
· Supports 1:1 or 1.25:1 transmit transformer
· Output waveform shaping - no external filter

required

· LED indicators: LINK, TX, RX, COL, 100, 10, FDX
· Single 3.3V power supply with 5V tolerant I/O
· 100-pin PQFP package

The MTD981 is a highly integrated analog

interface IC for twisted-pair Ethernet applications. It
provides the active circuitry to interface IEEE 802.3
media independent interface (MII) compliant
controllers to 10BASE-T or 100BASE-TX media. It
also provides an ECL-type interface for use with
100BASE-FX fiber networks.

The MTD981 supports full duplex operation at 10

and 100Mbps. Its operating condition can be set by
using Auto-Negotiation, parallel detection, or manual
control. The MTD981 is ideal as a media interface for
10BASE-T/100BASE-TX network interface cards,
motherboards, 10/100Mbps repeaters, switching
hubs, and external PHYs.

Transmit

10M

100M

MII Serial

Management

Control

Receive

MII

Registers

Interface

Logic

4B/5B Encoder,

Scrambler,

Parallel/Serial

Parallel/Serial,

Mnachester

Encoder

Manchester

Decoder,

Serial/Parallel

Descrambler,

5B/4B Decoder

NRZ/NRZI,

MLT3 Encoder

TX Clock

Generator

Carrier Sense,

Collision Detect

Clock

Recovery

Clock

Reference

Pulse

Shaper &

Filter

Auto

Negotiation

Adaptive EQ.

Baseline Wander

Corrector,

Decoder,

Vcc Ground

10M

100M

UTP

Driver

LEDs

UTP

Receiver

MLT3

NRZ/NRZI

TXOP

TXON

LINK

COLLISION

100X

RXIP
RXIN

MTD981

page 2 of 17

PIN CONNECTION DIAGRAM

50
49
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
32
31

81
82
83
84
85
86
87
88
89
90
91
92
93
94
95
96
97
98
99
100

TXD3
TXD2
TXD1
TXD0
CVDD
CGND
TXEN
TXCLK
TXER
RXER
RXCLK
RXDV
OGND
OVDD
RXD0
RXD1
RXD2
RXD3
MDC
MDIO

RPTR

SDP

RXIN

RXIP

GNDEQ

FIN

FIP

TEST2

FOP

FON

GNDREF

RBIAS

VAAREF

NC0
NC1

GNDT

TXOP

TXON

VAAT
VAAT

NC2

NC1

AAEQ

AAFQ

L
E

LED

ANEN

SEL

AACR

GNDCR

OGND

OVDD

L
E

NK_

LED

L
_

LED

MDINT

CRS

COL

NC1

CN1

NC1

MODE

ISODE

ISO

CKIN

NC2

TES

RST

APL

GNDPL

OGND

PHY

MODE

1
2

NC1

MTD981F

100-pin PQFP

MTD981

page 3 of 17

PIN DESCRIPTION

Name

I/O

Pin No.

Description

TXD3

Transmit data bit 3.

TXD2

Transmit data bit 2.

TXD1

Transmit data bit 1.

TXD0

Transmit data bit 0.

TXEN

Transmit enable.

TXCLK

Transmit clock.

TXER

Transmit error.

RXD3

Receive data bit 3.

RXD2

Receive data bit 2.

RXD1

Receive data bit 1

RXD0

Receive data bit 0.

RXDV

Receive data valid.

RXER

Receive data error.

RXCLK

Receive clock.

COL

Collision detect.

CRS

Carrier sense.

MDC

MII management clock.

MDIO

IO, U

MII management data input/output. Weakly pull up.

MDINT

MII management interrupt.

TXOP

Twisted-pair output positive node.

TXON

Twisted-pair output negative node.

RXIP

Twisted-pair input positive node.

RXIN

Twisted-pair output negative node.

FOP

Fiber output positive node.

FON

Fiber output negative node.

FIP

Fiber input positive node.

FIN

Fiber input negative node.

SDP

Signal detect positive node. Used only in fiber mode.

LEDSPD_

IO, U

100BT LED.

0 = 100baseTX; 1 = other connection.

When RST_ is low, this pin works as FIBER_DESEL to select the fiber mode.

Weakly pull up.

LED10_

10BT LED.

0 = 10baseTX; 1 = other connection.

LEDTX_

Transmit LED. Toggles when there are transmit activities.

LEDRX_

Receive LED. Toggles when there are receive activities.

LEDFD_

Full duplex LED.

0 = full duplex; 1 = half duplex.

MTD981

page 4 of 17

LEDLNK_

Link LED. 0 = link on; 1 = link off.

LEDCOL_

IO, U

Collision LED.

0 = collision; 1 = no collision. Weakly pull up.

When RST_ is low, this pin will load the SCRAM_SEL to enable/disable the

scrambler and descrambler set.

TEST

I, D

Test mode select. Weakly pull down.

CKIN

Oscillator input. 25MHz oscillator clock input.

RBIAS

Bias control resistor, to provide the internal voltage control.

I, D

Power down control. 1 = power down mode; 0 or floating = normal. Weakly pull

down.

RPTR

I, D

Repeater mode select.

1 = repeater mode; 0 = normal. Weakly pull down.

ISODEF

I, D

Isolate Default.

1 = isolation; 0 or floating = normal. Weakly pull down.

ISO

I, D

Isolate.

1 = isolation; 0 or floating = normal. Weakly pull down.

RST_

I, U

Pin reset select.

0 = reset; 1or floating = normal. Weakly pull up.

ANEN

I, U

auto-negotiation enable.

1 = enable auto-negotiation; 0 = disable auto-negotiation. Weakly pull up.

SEL2

I, U

Operation mode select, bit 2. Used only when auto-negotiation is disabled. Weakly

pull up.

SEL2 SEL1 SEL0 operation mode

X 0 0 mode select by MII registers;

0 0 1 10BaseT, half duplex;

0 1 X 100BaseT, half duplex;

1 0 1 10BaseT, full duplex;

1 1 X 100BaseT, full duplex.

SEL1

I, U

Operation mode select, bit 1. Weakly pull up.

SEL0

I, U

Operation mode select, bit 0. Weakly pull up.

PHYAD0

I, U

PHY ID bit 0. Weakly pull up.

PHYAD1

I, U

PHY ID bit 1. Weakly pull up.

PPHYAD2

I, U

PHY ID bit 2. Weakly pull up.

PHYAD3

I, U

PHY ID bit 3. Weakly pull up.

PHYAD4

I, U

PHY ID bit 4. Weakly pull up.

TP125

IO, U

Value latched in while reset to select transformer turns ratio.

1 = select the transmit transformer with ratio 1.25:1;

0 = select the transmit transformer with ratio 1:1 (default).

Works as link_established after reset. Weakly pull down.

MODE1

I, D

Test mode select bit 1. Weakly pull down.

MODE0

I, D

Test mode select bit 0. Weakly pull down.

TEST2

Used as the test mode output monitor pin.

Name

I/O

Pin No.

Description

MTD981

page 6 of 17

FUNCTIONAL DESCRIPTION

Media Independent Interface (MII)

The MTD981 implements an IEEE802.3u Clause 22 compliant MII interface described as the following:

The interface signals can be grouped into transmit, receive, and status. The transmit data signals comprise
TXD[3:0], TXEN, TXER, and TXCLK. TXD[3:0] are the nibble size data path, TXEN signals the presence of data
on TXD[3:0], TXER indicates substitution of data with the HALT symbol, and TXCLK carries the transmit clock
that synchronizes all the transmit signals. The receive data signals also include seven signals, RXD[3:0], RXDV,
RXER, and RXCLK. RXD[3:0] are the nibble size data path, RXDV signals the presence of data on RXD[3:0],
RXER indicates the validity of data, and RXCLK carries the receive clock. Depending on the operation mode,
RXCLK signal is generated by the clock recovery module of either the 100Base-X or 10Base-T receiver. Two
status signals, COL and CRS, are generated in the MTD981 to indicate Collision status and Carrier Sense status
to the MAC.

Serial Management Interface (SMI)

The MTD981 implements a Serial Management Interface (SMI) used both to obtain status from and to configure
the PHY. This mechanism corresponds to the MII Spec for 100BASE-X (Clause 22). The SMI interface consists
of two signals, MDC and MDIO. MDC is a clock input to the PHY and is used to latch data and instructions for the
PHY. The clock rate can run up to 2.5MHz. MDIO is bi-directional and is used to write instruction to, write data to,
or read data from the PHY. Each data bit is latched either in or out on the rising edge of MDC. MDC/MDIO is a
common signal pair up to 32 PHYs. Therefore, each PHY needs its unique address. The MTD981 uses 5 bits as
PHY address. The address is latched into internal register during reset from the pin setting. The SMI interface
supports registers 0 through 6. Additional "vendor-specific" registers are implemented. All the registers are
described in the register section. The access method of these registers is described as follows:

Figure-1 MII Read/Write Operation

0 1 1 0 0

0 0 0 0 0 0

0 0

1 1

1 0 0 0 0 0 0 0 0 0 z

MDC

MIDIO

(STA)

DMIO

(PHY)

MDC

MIDIO

(STA)

0 1 0 1 0 1 1 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 z

idle

start

opcode

phyaddr

regaddr

idle

start

opcode

phyaddr

regaddr

idle

Typical MII Read Operation

Typical MII Write Operation

MTD981

page 7 of 17

Before any transaction, the station must send 32 continuous logic "1" on MDIO to establish synchronization.
Figure 1 shows the read and write operations. The start code is "01" followed by an op code, either "01" for read
or "10" for write. For read operations, the device address must match the address of the target PHY device. For
write operations, the address may be all zero or match a specific PHY address. Turnaround cycle is an idle cycle
consisted of two bit times between the register address field and data field in order to avoid conflict. For reading,
no device drives MDIO in the first bit time, PHY drives "0" in the second bit time. For writing, station drives "10"
during the idle cycle.

10BASE-T

When configured to run in 10BASE-T mode, either through hardware configuration, software, or Auto-
Negotiation, the MTD981 will support all the functions specified in the IEEE802.3 Standard for 10BASE-T
(Clause 14).

I. Transmit Function
In 10BASE-T mode, the transmit function uses parallel-to-serial logic to convert the 4-bit transmit data into a
serial data stream. This serial data stream is Manchester-encoded and then outputs through the waveshaping
driver. Filtering is performed in silicon to reduce EMI emission. TXOP/TXON can be connected directly to a
standard transformer. External filtering modules are not needed.

II. Receive Function
In 10BASE-T mode, the signals at RXIP/RXIN first pass a smart squelch circuit. A Manchester decoder and a
serial-to-parallel converter then follow to generate the 4-bit nibble in MII interface. The squelch level of the
amplitude signals to mitigate carrier fade in the event of worst case signal attenuation.

III. Link Monitor
In 10BASE-T mode, link pulse detection circuit will constantly monitor the RXIP/RXIN pins for the presence of
valid link pulses. In the absence of valid link pulses, the LINK LED will de-assert.

100BASE-TX

When configured to run in 100BASE-T mode, either through hardware configuration, software, or Auto-
Negotiation, the MTD981 will support all the functions specified in the IEEE802.3 Standard for 100BASE-TX.

I. Transmit Function
In 100BASE-TX mode, the transmit function converts synchronous 4-bit data nibbles from the MII to a 125Mbps
differential serial data stream in MLT-3 format. The entire operation is synchronous to a 25-MHz clock and a
125MHz clock. Both clocks are generated by an on-chip PLL clock synthesizer that is locked to an external
25MHz clock source. There are three functional blocks in the transmit function: 4B/5B encoder, scrambler, and
MLT-3 output driver. The 4B/5B encoder, defined in IEEE802.3 Clause 24, converts 4-bit raw data to 5-bit code-
group. It also inserts the stream boundary delimiters (/J/K/ and /T/R/) at the beginning and end of the data stream
as appropriate. The 4B/5B encoded data have repetitive patterns which result in peaks in the RF spectrum. The
peaks in the radiated signal are reduced significantly by scrambling the transmitted signal. The scrambler,
defined by the TP-PMD Stream Cipher function, encodes a plain text NRZ bit stream using a key stream periodic
sequence of 2047 bits generated by the recursive linear function:

X[n] - X[n-11] + X[n-9] (module 2)

The scrambler reduces peak emission by randomly spreading the signal energy over the transmit frequency
range, thus eliminating peaks at a single frequency. The scrambled NRZ data stream is then converted to MLT-3
encoded data and outputted to the UTP-5 cable. The MLT-3 is a tri-level signal. The presence of a transition has

MTD981

page 8 of 17

a logical value of 1 and the lack of a transition has a logical value of 0. The benefit of MLT-3 is that it reduces the
maximum frequency from 62.5MHz to 31.25MHz.

II. Receive Function
in 100BASE-TX mode, the receive function includes a receiver with adaptive equalization and baseline wander
compensation, data and clock recovery at 125MHz, descrambling, and 5B to 4B decoding. An energy detect
circuit is also added to determine whether there is any signal energy on the media.

III. Link Monitor
In 100BASE-TX mode, when no signal or invalid signal is detected on the receiver pair, the link monitor will enter
the "link fail" state where only the scrambled idle code is transmitted. When a valid signal is detected for a
minimum period of time, the link monitor will then enter the "link pass" state when transmit and receive functions
are entered.

100BASE-FX

When configured to run in 100BASE-FX mode, either through hardware configuration or software configuration,
the MTD981 will support all the features and parameters of the industry standards.

I. Transmit Function
In 100BASE-FX mode, the 4B/5B encoded data stream bypasses the scrambler. The output is NRZI PECL
signals. The PECL level signals are used to drive the transmitter of the fiber module.

II. Receive Function
in 100BASE-FX mode, the signal is received through the PECL receiver and directly passed to the clock recovery
circuit for clock/data extraction. The descrambler is bypassed. The data still need 5B/4B decoding.

III. Link Monitor
In 100BASE-FX mode, the external fiber module performs the signal energy detection and communicates the
information directly to the SDP pin of the MTD981.

AUTO-NEGOTIATION

The MTD981 implements Auto-Negotiation logic conforming to the 802.3u specification. The basic operation is
based on using Fast Link Pulse (FLP) to communicate information between link partners. The Auto-Negotiation
takes three phases to complete: advertising, detection and selection. The Auto-Negotiation mode can be
optionally selected using external pin selection SEL[0:2]. The MTD981 also implements parallel detect function to
allow compatibility with legacy network devices.

MTD981

page 9 of 17

REGISTER DESCRIPTIONS

Register 0. Control Register

Register 1. Status Register

Register 2. OUI Register

Bit

Name

R/W

Def.

Description

RST

RW, SC

Reset.

1: reset; 0: normal operation.

LPBK

Loopback select.

1: loopback; 0: normal operation.

SPEED

Speed select.

1: 100Mbps selected; 0: 10Mbps selected.

ANEN

Auto-negotiation enable.

1: enabled; 0: disabled.

PWDN

Power down enable.

1: power down; 0: normal operation.

ISO

MII isolation.

1: isolation; 0: normal operation.

RESTART_AN

RW, SC

Restart auto-negotiation.

1: restart; 0: normal operation.

DUPLEX

Duplex mode select.

1: full duplex; 0: half duplex.

COLTST

Collision test enable.

1: enable; 0: disable.

6:0

Reserved.

Bit

Name

R/W

Def.

Description

Not capable of T4 operation.

TXFD

Capable of 100-TX full duplex operation.

TXHD

Capable of 100-TX half duplex operation.

TPFD

Capable of 10-TP full duplex operation.

TPHD

Capable of 10-TP half duplex operation.

10:7

Reserved.

SPREM

Accepting MII frames with preamble suppressed.

ANC

1: auto-negotiation complete;

0: auto-negotiation not complete.

R, LH

1: remote fault detected;

0: no remote falut.

1: capable of auto-negotiation operatoin.

LINK

R/LL

1: link established;

0: link not established.

JAB

R/LH

1: jabber detected;

0: jabber not detected.

EXT

1: extended registers exist.

Bit

Name

R/W

Def.

Description

15:0

OUI_L

0302h

OUI[3:18] = 0302h

MTD981

page 10 of 17

Register 3. OUI_H Register

Register 4. Advertisment Register

Register 5. Link Partner Ability Register

Bit

Name

R/W

Def.

Description

15:10

OUI_H

110100

OUI[19:24] = 1101_00

9:4

PARTNO

Part number.

3:0

REV

Revision number.

Bit

Name

R/W

Def.

Description

Next page.

0: No next page.

ACK

Acknowledgement.

1: received link code word acknowledged;

0: received link code word not acknowledged.

RFDET

Remote fault detected.

1 remote fault detected;

0: no remote fault.

12:10

000

Reserved (for pause function).

1: capable of T4 operation;

0: not capable of T4 operation.

TXFD

1: capable of 100-TX full duplex operation;

0: not capable of 100-TX full duplex operation.

TXHD

1: capable of 100-TX half duplex operation;

0: not capable of 100-TX half duplex operation.

TPFD

1: capable of 10-TP full duplex operation;

0: not capable of 10-TP full duplex operation.

TPHD

1: capable of 10-TP half duplex operation;

0: not capable of 10-TP half duplex operation.

4:0

SELECT

Selector field: 5'b00001 means IEEE802.3 selected.

Bit

Name

R/W

Def.

Description

Next page.

0: No next page.

ACK

Acknowledgement.

1: received link code word acknowledged;

0: received link code word not acknowledged.

RFDET

Remote fault detected.

1 remote fault detected;

0: no remote fault.

12:10

Reserved.

1: capable of T4 operation;

0: not capable of T4 operation.

TXFD

1: capable of 100-TX full duplex operation;

0: not capable of 100-TX full duplex operation.

TXHD

1: capable of 100-TX half duplex operation;

0: not capable of 100-TX half duplex operation.

TPFD

1: capable of 10-TP full duplex operation;

0: not capable of 10-TP full duplex operation.

TPHD

1: capable of 10-TP half duplex operation;

0: not capable of 10-TP half duplex operation.

MTD981

page 11 of 17

Register 16. Proprietary Control Register

Register 17. Interrupt Register

4:0

SELECT

Selector field: 5'b00001 means IEEE802.3 selected.

Bit

Name

R/W

Def.

Description

REP

1: repeater mode.

- full duplex disabled;

- SQE function disable;

- CRS response to receive activity only.

INT_SEL

1: set the interrupt pin to be active high;

0: set the interrupt pin to be active low.

13:12

stable_time_sel[1:0]

Stabilize timer select.

00: 700us; 01: 1ms; 10: 5ms; 11: 45ms.

SQE_DIS

1: disable SQE function;

0: enable SQE function.

FLP_RX_IDLE_EN

FLP_idle enable (arbitration state machine).

1: single_link_ready = (flp_idle) &
(((link_status_nlp == 1'b0) & (link_status_x == READY))

((link_status_nlp == 1'b1) & (link_status_x != READY)));

0: single_link_ready =
(((link_status_nlp == 1'b0) & (link_status_x == READY))

((link_status_nlp == 1'b1) & (link_status_x != READY))).

FDDI_LOAD_EN

FDDI load enable (descrambler lock time).
1: load = (~locked) & (quiet

halt

master

idle);

0: load = (~locked) & (idle).

EDPSM

1: energy detect power saving mode;

0: no power down.

FEF_EN

1: far-end-fault enabled;

0: far-end-fault disabled.

XFSEL

1: select transmit transformer ratio to be 1.25:1;

0: select transmit transformer ratio to be 1:1.

POL_DIS

1: disable auto polarity detection/correction function;

0: enable auto polarity detection/correction function.

NLP_DIS

1: force link up without checking NLP;

0: normal operation.

Reserved.

BP_JAB

1: bypass jabber function;

0: enable jabber function.

SCRAM_EN

1: enable scrambler/discrambler;

0: disable scrambler/discrambler.

FX_SEL

1: FX mode selected, SCRAM_EN will be set to 0;

0: disable FX mode. SCRAM_EN can be programmed

after FX mode is disabled.

Bit

Name

R/W

Def.

Description

15:13

Reserved.

PDFM

1: enable parallel detection fault interrupt;

0: disable parallel detectoin fault interrupt.

Reserved.

Bit

Name

R/W

Def.

Description

MTD981

page 12 of 17

Register 18. Porprietary Status Register

Register 19. Test Register

LFM

1: enable link fail interrupt;

0: disable link fail interrupt.

Reserved.

ANCM

1: enable auto-negotiation complete interrupt;

0: disable auto-negotiation complete interrupt.

7:5

Reserved.

PDFINT

W1C

1: parallel detection fault interrupt.

This bit is write 1 cleared.

Reserved.

LFINT

W1C

1: link fail interrupt.

This bit is write 1 cleared.

Reserved.

ANCINT

W1C

1: auto-negotiation complete interrupt

This bit is write 1 cleared.

Bit

Name

R/W

Def.

Description

15:12

Reserved.

DUPLEX

1: link status is full duplex;

0: link status is half duplex or link fail.

SPEED

1: link speed is 100Base-TX;

0: link speed is 10Base-TX.

9:5

Reserved.

4:0

PHYAD

00000

PHY address.

Bit

Name

R/W

Def.

Description

15:14

TSTMD[3:2]

125MHz clock source;

00: use internal (cgm) 125MHz clk;

11: use external 125MHz clk.

13:12

TSTMD[1:0]

mlt3shmx control signal.
00: clk0 clk0 nrz0

(normal mode);

01: clk0 clkd0 (high)

(test mode with nrz high and clk

from cgm);
10: f25m f25m (high)

(test mode with nrz high and clk

from ckin);
11: f25m f25m (high)

(test mode with nrz high and clk

from ckin).

11:8

RESERVED

Reserved.

NO_PWRDN

1: force no power down;

0: accept power down setting.

MANUAL_CTRL_

PWRDN

1: enable manual control power down;

0: bypass manual control power down.

5:4

RESERVED

Reserved.

TSTMD_DESCRM

1: accelerate descrambler lock time;

0: normal descrambler lock time.

LB_DIG

1: enable digital loopback;

0: disable digital loopback.

Bit

Name

R/W

Def.

Description

MTD981

page 14 of 17

ELECTRICAL CHARACTERISTICS

DC CHARACTERISTICS

Absolute Maximum Ratings

Recommended Operating Conditions

Total Power Consumption

Symbol

Name

Range

Unit

Maximum Supply Voltage

-0.3 to +5.0

Maximum Input Voltage

-0.3 to V

+ 0.3

OUT

Maximum Output Voltage

-0.3 to V

+ 0.3

STG

Maximum Storage Temperature

-25 to + 125

Symbol

Parameter

Min

Typ

Max

Unit

Power Supply

3.0

3.6

OPG

Operating Temperature

+70

Symbol

Parameter

Conditions

Min

Typ

Max

Unit

10 Base-T, Idle

131

Supply Current

10 Base-T

196

100 Base-TX

218

MTD981

page 16 of 17

PACKAGE OUTLINE

100-pin PQFQ

Symbol

Dimensions in Millimeters

Dimensions in Inches

MIN

NOM

MAX

MIN

NOM

MAX

3.30

0.130

0.10

0.004

2.73

2.85

2.97

0.107

0.112

0.117

0.25

0.30

0.40

0.010

0.012

0.016

0.10

0.15

0.25

0.004

0.006

0.010

18.49

18.80

19.10

0.728

0.740

0.752

13.87

14.00

14.13

0.546

0.551

0.556

24.49

24.80

25.10

0.964

0.976

0.988

19.87

20.00

20.13

0.782

0.787

0.792

0.50

0.65

0.80

0.020

0.026

0.032

1.00

1.20

1.40

0.039

0.047

0.055

2.21

2.40

2.62

0.087

0.094

0.103

100

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