MTL007
SXGA Flat Panel Controller
sales@myson.com.tw
www.myson.com.tw
Rev. 1.1 November 2002
page 1 of 65
Myson Century, Inc.
Taiwan:
No. 2, Industry East Rd. III,
Science-Based Industrial Park, Hsin-Chu, Taiwan
Tel: 886-3-5784866 Fax: 886-3-5784349
USA:
4020 Moorpark Avenue Suite 115
San Jose, CA, 95117
Tel: 408-243-8388 Fax: 408-243-3188
GENERAL DESCRIPTION
The MTL007 Flat Panel Display (FPD) Controller is a
low-cost input format converter for TFT-LCD Monitor
or LCD TV application which accepts 15-pin D-sub
RGB graphic signals (through ADC), YUV signals
from digital video decoder or digital RGB graphic
signals from PanelLink TMDS receiver. It includes a
RGB/YUV input processor, video scaling up
processor, OSD input interface and output display
processor in 128-pin PQFP.
FEATURES
General
Auto configuration of sampling clock frequency,
phase, H/V center, as well as white balance.
Auto detection of present or non-present or over
range sync signals and their polarities.
Composite sync separation and odd/even field
detection of interlaced video.
No external memory required.
On-chip output PLL provide clock frequency fine-
tune (inverse, duty cycle and delay).
Serial 2-wire I
2
C host interface.
Embedded power regulator.
Embedded power on reset circuit.
3.3V supplier in 128-pin PQFP package.
Input Processor
Single RGB (24-bit) input rates up to 135MHz.
Support both non-interlaced and interlaced RGB
graphic input signals.
YUV 4:2:2 or YUV 4:1:1 (CCIR601/CCIR656)
interlaced video input.
Glue-less connection to Philips SAA711x digital
video decoder.
Built-in YUV to RGB color space converter.
Compliant with digital LVDS/PanelLink TMDS
input interface.
PC input resolution up to SXGA 1280x1024 @
75Hz.
Video Processor
Independent programmable Horizontal and Vertical
scaling up ratios from 1 to 32
Flexible de-interlacing unit for digital YUV video
input data.
Zoom to full screen resolution of de-interlaced YUV
video data stream.
Built-in programmable gain control for white
balance alignments.
Built-in programmable 10-bit gamma correction
table.
Built-in programmable temporal color dithering.
Built-in programmable interpolation look-up table.
Built-in programmable sharpening & smoothing
filters for edge enhancement.
Support smooth panning under viewing window
change.
Output Processor
Dual pixel (36/48-bit) per clock digital RGB output.
Built-in output timing generator with programmable
clock and H/V sync.
Support VGA/SVGA/XGA/SXGA display resolution.
Overlay input interface with external OSD
controller.
Double scan capability for interlaced input.
MTL007
page 4 of 65
PIN DESCRIPTION
ADC Input Interface (RGB or YUV or TMDS Input Data)
Name Type Pin
No.
Description
IPCLK
I
92
Input pixel clock
VSYNC
I
94
Input Vertical sync
HSYNC/CS I 93
Input
Horizontal or Composite sync
RIN[7:0]/YIN[7:0]
(RIN[5:0])
I
91-84
(89-84)
Red or Y channel or TMDS input data
(Red channel for 6-bit input)
GIN[7:0]/UVIN[7:0]
(GIN[5:0])
I
82-75
(78-75, 91, 90)
Green or UV channel or TMDS input data
(Green channel for 6-bit input)
BIN[7:0]
(BIN[5:0])
I
74-67
(68, 67, 82-79)
Blue or TMDS input data, or Control bit for YUV video input
Bit 4: VPHREF, Video input Horizontal reference signal
Bit 3: VPVS, Video input VSYNC signal
Bit 2: VPODD, Video input ODD/EVEN field signal
Bit 1: VPHS, Video input HSYNC signal
Bit 0: VPCLK, Video input clock signal
(Blue channel for 6-bit input)
RAWHS
I
62
Input source HSYNC for measurement
TDIE
I
66
TMDS digital input enable
CLAMP
O
60
Clamp pulse output for ADC
Display Output Interface
Name Type Pin
No.
Description
DDCLK1
1
Display
output
clock
DVSYNC
O
37
Display Vertical sync output
OE O
39
Display
output
enable
DHSYNC
O
35
Display Horizontal sync output
DDCLK2 O
38
Display
output
clock
R1OUT[0:7]
O
33-30, 28, 26-25, 23 Red output even data , bit[7:2] for 6-rlogin rbit panel
G1OUT[0:7]
O
22, 20-15, 13
Green output even data , bit[7:2] for 6-bit panel
B1OUT[0:7]
O
11-9, 7, 5-3, 2
Blue output even data , bit[7:2] for 6-bit panel
R2OUT[0:7] O
128-127, 125-124,
122-119
Red output odd data , bit[7:2] for 6-bit panel
G2OUT[0:7] O
118,117, 115, 113-
111, 109,107
Green output odd data , bit[7:2] for 6-bit panel
B2OUT[0:7]
O
106-101, 99-98
Blue output odd data , bit[7:2] for 6-bit panel
Host Interface
Name Type Pin
No.
Description
RST#
I
44
System reset input, active low.
SCL
I
48
Serial bus clock
MTL007
page 5 of 65
SDA
I/O
47
Serial bus data
TESTMODE
I
95
Test Mode, Normally grounded.
IRQ
O
58
Interrupt request output
OSD Interface
Name Type Pin
No.
Description
OVSYNC
O
49
Vertical sync for external OSD
OHSYNC
O
50
Horizontal sync for external OSD
OCLK
O
51
Clock for external OSD
OSDRED
I
52
OSD red input
OSDGRN
I
53
OSD green input
OSDBLU
I
54
OSD blue input
OSDEN
I
55
OSD overlay enable
OSDINT I
56 OSD
intensity
Other Interface
Name Type Pin
No.
Description
XI I
42
Oscillator
frequency
input
XO O
41
Oscillator
frequency
output
EXTDCLK1
I
46
External display clock input 1
EXTDCLK2
I
45
External display clock input 2
ADVS
O
61
Vertical sync for A/D converter
3.3V Power and Ground
Name PIN
No.
Description
DVDD
14,29,63,83,116
Digital power 3.3V
DCAP
64
External CAP for digital Power
DVSS 12,27,65,96,114
Digital ground
PVDD
6,24,36,57,97,108,
126
Pad power 3.3V
PVSS
8,21,34,59,100,110,
123
Pad ground
AVDD 40
Analog
power
3.3V
AVSS 43
Analog
ground
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