BLOCK DIAGRAM

GENERAL DESCRIPTION

FEATURES

MTV130

On-Screen Display for LCD Monitor

USA:
4020 Moorpark Avenue, Suite 115
San Jose, CA, 95117
Tel: 408-243-8388 Fax: 408243--3188

Sales@myson.com.tw

www.myson.com.tw

Rev.1.2 May 2003

page 1 of 26

Myson Century, Inc.
Taiwan:
No. 2, Industry East Rd. III,
Science-Based Industrial Park, Hsin-Chu, Taiwan
Tel: 886-3-5784866 Fax: 886-3-5784349

· Horizontal SYNC input up to 150 KHz.

· Acceptable wide-range pixel clock up to 150 MHz.

· Full screen self-test pattern generator.

· Full-screen display consists of 15 (rows) by 30

(columns) characters.

· Two font size 12x16 or 12x18 dot matrix per character.

· True totally 512 mask ROM fonts including 496

standard fonts and 16 multi-color fonts.

· 8 color selection maximum per display character.

· Double character height and/or width control.

· Programmable positioning for display screen center.

· Character bordering, shadowing and blinking effect.

· Programmable character height (18 to 71 lines)

control.

· Row to row spacing control to avoid expansion

distortion.

· 4 programmable windows with multi-level operation.

· Shadowing on windows with programmable shadow

width/height/color.

· Software clears bit for full-screen erasing.

· Intensity and fast blanking output.

· Fade-in/fade-out or blending-in/blending-out effects.

· 5-channel/8-bit PWM D/A converter output.
· Compatible with SPI bus or I

C interface with slave

address 7AH (slave address is mask option).

· 16-pin or 20-pin or 24-pin PDIP/SOP package.

The MTV130 is designed for LCD monitor

applications to display built-in characters or fonts
onto an LCD monitor screens. The display operation
occurs by transferring data and control information
from the micro-controller to RAM through a serial
data interface. It can execute full-screen display
automatically, as well as specific functions such as
character background, bordering, shadowing,
blinking, double height and width, font by font color
control, frame positioning, frame size control by
character height and row-to-row spacing, horizontal
display resolution, full-screen erasing, fade-in/fade-
out effect, windowing effect, shadowing on window
and full-screen self-test pattern generator.

The MTV130 provides true 512 fonts including 496

standard fonts and 16 multi-color fonts and 2 font
sizes, 12x16 or 12x18 for more efficacious
applications. So each one of the 512 fonts can be
displayed at the same time. The full OSD menu is
formed by 15 rows x 30 columns, which can be
positioned anywhere on the monitor screen by
changing vertical or horizontal delay.

SERIAL DATA

INTERFACE

ADDRESS BUS

ADMINISTRATOR

VERTICAL

DISPLAY

CONTROL

DISPLAY & ROW

CONTROL

REGISTERS

COLOR

ENCODER

WINDOWS &

FRAME

CONTROL

BKG

BLANK

LUMAR

LUMAG

LUMAB

BLINK

VCLKX

DATA

VERTD

HORD

8
8
7

BSEN
SHADOW
OSDENB
HSP
VSP

HORIZONTAL

DISPLAY CONTROL

CLOCK

GENERATOR

DATA

LPN

CWS

VCLKS

DATA

CWS

CHS

LUMAR
LUMAG
LUMAB
BLINK
CRADDR

LUMA

BORDER

ARWDB

HDREN

VCLKX

HORD 8

CHS

VERTD

LPN

NROW

VDREN

RCADDR
DADDR
FONTADDR
WINADDR
PWMADDR

5
9
9
5
5

ARWDB

HDREN

VDREN

NROW

DATA

ROW, COL

ACK

CHARACTER ROM

USER FONT RAM

LUMINANCE &

BORDGER

GENERATOR

VDD

VSS

VDDA

VSSA

ROUT

GOUT

BOUT

FBKG

HTONE

HFLB

XIN

VFLB

SSB

SCK

SDA

VSP

HSP

PWM D/A

CONVERTER

PWM0
PWM1
PWM2
PWM3
PWM4

DATA

POWER ON

RESET

PRB

page 2 of 26

MTV130

PIN CONNECTION DIAGRAM

Note: New Myson Century logo is used in this data sheet. However, it shall be noted that the MTV130 is a prior Myson

product, and the prior Myson logo is still used for the IC marking (see below for the prior Myson logo).

VSS

XIN

VDD

HFLB

SSB

SDA

SCK

VSS

ROUT

GOUT

BOUT

FBKG

INT

VFLB

VDD

30N

-
x
x /

VSS

XIN

VDD

HFLB

SSB

SDA

SCK

PWM0

PWM1

VSS

ROUT

GOUT

BOUT

FBKG

INT

VFLB

VDD

PWM3

PWM2

MTV130N

20-xx /

VSS

XIN

VDD

HFLB

SSB

SDA

SCK

PWM0

PWM1

PWM2

PWM3

VSS

ROUT

GOUT

BOUT

FBKG

INT

VFLB

VDD

PWM4

MTV130P24-

MTV130P20-

130

P-x

MTV130N24-

xx /

page 3 of 26

MTV130

PIN DESCRIPTION

Name

I/O

Pin

Description

P16

P20

P24

VSS

Ground. This ground pin is used to internal circuitry.

XIN

Pixel clock input. This is a clock input pin. MTV130 is driven by an external

pixel clock source for all the logics inside. The frequency of XIN must be the

integral time of pin HFLB.

No connection.

VDD

Power supply. Positive 5 V DC supply for internal circuitry. And a 0.1uF

decoupling capacitor should be connected across to VDD and VSS.

HFLB

Horizontal input. This pin is used to input the horizontal synchronizing signal.

It is a leading edge triggered and has an internal pull-up resistor.

SSB

Serial interface enable. It is used to enable the serial data and is also used

to select the operation of I

C or SPI bus. If this pin is left floating, I

C bus is

enabled, otherwise the SPI bus is enabled.

SDA

Serial data input. The external data transfer through this pin to internal dis-

play registers and control registers. It has an internal pull-up resistor.

SCK

Serial clock input. The clock-input pin is used to synchronize the data trans-

fer. It has an internal pull-up resistor.

No connection.

PWM0

Open-Drain PWM D/A converter 0. The output pulse width is programmable

by the register of Row 15, Column 23.

PWM1

Open-Drain PWM D/A converter 1. The output pulse width is programmable

by the register of Row 15, Column 24.

PWM2

Open-Drain PWM D/A converter 2. The output pulse width is programmable

by the register of Row 15, Column 25.

PWM3

Open-Drain PWM D/A converter 3. The output pulse width is programmable

by the register of Row 15, Column 26.

PWM4

Open-Drain PWM D/A converter 4. The output pulse width is programmable

by the register of Row 15, Column 27.

VDD

Power supply. Positive 5 V DC supply for internal circuitry and a 0.1uF

decoupling capacitor should be connected across to VDD and VSS.

VFLB

Vertical input. This pin is used to input the vertical synchronizing signal. It is

leading triggered and has an internal pull-up resistor.

INT

Intensity color output. 16-color selection is achievable by combining this

intensity pin with R/G/B output pins.

FBKG

Fast Blanking output. It is used to cut off external R, G, B signals of VGA

while this chip is displaying characters or windows.

BOUT

Blue color output. It is a blue color video signal output.

GOUT

Green color output. It is a green color video signal output.

ROUT

Red color output. It is a red color video signal output.

VSS

Ground. This ground pin is used to internal circuitry.

page 4 of 26

MTV130

FUNCTIONAL DESCRIPTION

SERIAL DATA INTERFACE

The serial data interface receives data transmitted from an external controller. And there are 2 types of bus can
be accessed through the serial data interface, one is SPI bus and other is I

C bus.

(i) SPI Bus
While SSB pin is pulled to "high" or "low" level, the SPI bus operation is selected. And a valid transmission
should be starting from pulling SSB to "low" level, enabling MTV130 to receiving mode, and retain "low" level until
the last cycle for a complete data packet transfer. The protocol is shown in Figure 1.

Figure-1 Data Transmission Protocol (SPI)

There are three transmission formats shown as below:

Format (a) R - C - D

R - C - D

R - C - D .....

Format (b) R - C - D

C - D

C - D .....

Format (c) R - C - D

D .....

Where R=Row address, C=Column address, D=Display data

(ii) I

C Bus

C bus operation is only selected when SSB pin is left floating. And a valid transmission should be starting from

writing the slave address 7AH to MTV130. The protocol is shown in Figure 2.

Figure-2 Data Transmission Protocol (I

There are three transmission formats shown as below:

Format (a) S - R - C - D

R - C - D

R - C - D .....

MS
B

LSB

SSB

SCK

SDA

first byte

last byte

SCK

SDA

first byte

START

ACK

second byte

last byte

ACK

STOP

page 5 of 26

MTV130

Format (b) S - R - C - D

C - D

C - D .....

Format (c) S - R - C - D

D .....

Where S=Slave address, R=Row address, C=Column address, D=Display data

Each arbitrary length of data packet consists of 3 portions viz, Row address (R), Column address (C), and
Display data (D). Format (a) is suitable for updating small amount of data which will be allocated with different
row address and column address. Format (b) is recommended for updating data that has same row address but
different column address. Massive data updating or full screen data change should use format (c) to increase
transmission efficiency. The row and column address will be incremented automatically when the format (c) is
applied. Furthermore, the undefined locations in display or fonts RAM should be filled with dummy data.

Table 1. The Configuration of Transmission Formats

There are 2 types of data should be accessed through the serial data interface, one is ADDRESS bytes of
display registers, and other is ATTRIBUTE bytes of display registers, the protocol are same for all except the bit5
of row address and the bit5 of column address. The MSB(b7) is used to distinguish row and column addresses
when transferring data from external controller. The bit6 of column address is used to differentiate the column
address for format (a), (b) and format (c) respectively. Bit5 of row address for display register is used to
distinguish ADDRESS byte when it is set to "0" and ATTRIBUTE byte when it is set to "1". And at address bytes,
bit5 of column address is the MSB (bit8) and data bytes are the 8 LSB (bit7~bit0) of display fonts address
to save half MCU memory for true 512 fonts. So each one of the 512 fonts can be displayed at the same time.
See Table 1. And for format (c), since D8 is filled while program column address of address bytes, the continued
data will be the same bank of upper 256 fonts or lower 256 fonts until program column address of address bytes
again.

The data transmission is permitted to change from format (a) to format (b) and (c), or from format (b) to format (a)
and (c), but not from format (c) back to format (a) and (b). The alternation between transmission formats is
configured as the state diagram shown in Figure-3.

Address

Format

Address Bytes of Display

Reg.

Row

a,b,c

Column

a,b

Column

Data

a,b,c

Attribute Bytes of Display

Reg.

Row

a,b,c

Column

a,b

Column

Data

a,b,c

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