Stock No. 23001-06 7/99
1
EM02R2XX
NanoAmp Solutions, Inc.
1982 Zanker Road, San Jose, CA 95112
ph: 408-573-8878, FAX: 408-573-8877
www.nanoamp.com
EM02R2XX Family - Combination SRAM with ROM
Low Power 32Kx8 SRAM with on board 256Kx8 Mask ROM
Overview
The EM02R2XX is an integrated memory device
containing both a low power 256 Kbit Static Ran-
dom Access Memory (organized as 32,768 words
by 8 bits), and a 2 Mbit Mask ROM (organized as
262,144 words by 8 bits). It is fabricated using an
advanced CMOS process and NanoAmp's high-
speed/low-Power circuit technology. This device is
designed for low voltage operation and is very suit-
able for battery powered devices. Low power
applications are also well served by this device due
to its very low operating and standby current. Also,
this device allows the user to make independent
requests to the ROM or RAM without incurring
unwanted I
CC
overhead.
FIGURE 1: Pin Configuration
Features
Extended Operating Voltage Range
1.5 to 3.6 V
Very Low Standby Voltage
1.2 V
Extended Temperature Range
-20
o
to +80
o
C
Fast Cycle Time
100 ns (@ 2.7V)
Very Low Operating Current
I
CC
< 1 mA typical at 3V, 1 Mhz
Very Low Standby Current
I
SB
= 100 nA typical
Available in 32-pin STSOP or TSOP
package
TABLE 1: Pin Descriptions
FIGURE 2: Operating Envelope
EM02R2XX
STSOP, TSOP
2
3
4
5
1
6
7
8
9
10
11
12
13
14
15
16
23
18
17
22
21
20
19
27
26
25
24
31
30
29
28
32
A11
A9
A8
A13
WE
A15
VCC
A17
A16
A14
A12
A7
A6
A5
A4
A2
A10
RAMCS
VSS
A3
A1
A0
D0
D1
D2
D3
D4
D5
D6
D7
OE
ROMCS
Pin Name
Pin Function
A0-A14
Address Inputs
D0-D7
Data Inputs/Outputs
CE
Chip Enable (Active Low)
OE
Output Enable (Active Low)
WE
Write Enable (Active Low)
V
CC
Power
V
SS
Ground
NC
Not Connected (Floating)
8
4
0
T
y
p
i
c
a
l
I
C
C
(
m
A
)
8 Mhz
2.5 Mhz
1 Mhz
V
CC
(V)
5 Mhz
6
2
0
1
2
3
4
(50% RAM/ROM Cycles)
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NanoAmp Solutions
EM02R2XX
FIGURE 3: Functional Block Diagram
TABLE 2: Functional Description
*The device will consume active power in this mode whenever addresses are changed
** No output is available
TABLE 3: Absolute Maximum Ratings*
*Stresses greater than those listed above may cause permanent damage to the device. This is a stress rating only and
functional operation of the device at these or any other conditions above those indicated in the operating section of this
specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect reliability.
Control
Logic
32K x 8
RAM Array
256K x 8
ROM Array
Address
Decode
Logic
Address
Inputs
A
0
- A
17
ROMCS
RAMCS
WE
OE
Input/
Output
Mux
and
Buffers
Data I/O
D
0
- D
7
ROMCS
RAMCS
WE
OE
D0-D7
MODE
POWER
H
H
X
X
High Z
Standby
Standby
L
H
X
H
High Z
Standby
Standby*
L
H
L
L
High Z
ROM READ**
Active -> Standby
L
H
H
L
Data Out
ROM READ
Active -> Standby
H
L
H
H
High Z
Standby
Standby*
H
L
H
L
Data Out
RAM READ
Active -> Standby
H
L
L
X
Data In
RAM WRITE
Active -> Standby
Item
Symbol
Rating
Unit
Voltage on any pin relative to V
SS
V
IN,OUT
0.3 to V
CC
+0.3
V
Voltage on V
CC
Supply Relative to V
SS
V
CC
0.3 to 4.6
V
Power Dissipation
P
D
500
mW
Storage Temperature
T
STG
40 to +125
o
C
Operating Temperature - Extended Commercial
T
A
-20 to +80
o
C
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EM02R2XX
TABLE 4: Operating Characteristics (Over specified temperature range)
Notes:
Note 1. Operating current is a linear function of frequency and voltage. You may calculate operating current using the
formula shown with operating frequency (f) expressed in Mhz and operating voltage (V) in volts. Example: Operating
at 2 Mhz in the RAM selected mode at 2.0 volts will draw a typical current of 0.25*2*2 = 1.0 mA.
Note 2. This device assumes a standby mode if both ROMCS and RAMCS are disabled (high). It will also automati-
cally go into a standby mode whenever all input signals are quiescent (not toggling) for more than one cycle time
regardless of the states of ROMCS and RAMCS . In order to achieve low standby current all input levels must be within
0.2 volts of either V
CC
or GND.
TABLE 5: Capacitance*
Note: These parameters are verified in device characterization and are not 100% tested
TABLE 6: Timing Test Conditions
Item
Symbol
Test Conditions
Min.
Typical
Max.
Unit
Supply Voltage
V
CC
1.5
3.6
V
Data Retention Supply
Voltage
V
DR
RAMCS = V
CC
ROMCS = V
CC
1.2
3.6
V
Input High Voltage
V
IH
0.7V
CC
V
CC
+0.3
V
Input Low Voltage
V
IL
0.3
0.3V
CC
V
Output High Voltage
V
OH
I
OH
= -100
A
V
CC
0.2
V
Output Low Voltage
V
OL
I
OL
= 100
A
0.2
V
Input Leakage Current
I
LI
V
IN
= 0 to V
CC
1
A
Output Leakage Current
I
LO
OE = V
IH
or
RAMCS = 1, ROMCS = 1
1
A
ROM Operating Supply
Current (Note 1)
I
CC1
V
IN
= V
CC
or 0V
RAMCS = 1, ROMCS = 0
0.4 * f * V
0.5 * f * V
mA
RAM Operating Supply
Current (Note 1)
I
CC2
V
IN
= V
CC
or 0V
RAMCS = 0, ROMCS = 1
0.25 * f * V
0.3 * f * V
mA
Standby Current (Note 2)
I
SB
V
IN
= V
CC
or 0V
0.1
10
A
Item
Symbol
Test Condition
Min
Max
Unit
Input Capacitance
C
IN
V
IN
= 0V, f = 1 Mhz, T
A
= 25
o
C
5
pF
I/O Capacitance
C
I/O
V
IN
= 0V, f = 1 Mhz, T
A
= 25
o
C
5
pF
Item
Input Pulse Level
0.1V
CC
to 0.9 V
CC
Input Rise and Fall Time
5ns
Input and Output Timing Reference Levels
0.5V
CC
Output Load
CL = 30pF
Operating Temperature (Unless otherwise stated)
-20 to +80
o
C
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EM02R2XX
TABLE 7: RAM Read Cycle Timing
TABLE 8: RAM Write Cycle Timing
TABLE 9: ROM Read Timing
Item
Symbol
Min/Max
1.5V
1.8V
2.4V
2.7-3.6V
Units
Read Cycle Time
t
RC
Min
750
250
150
100
ns
Address-RAMCS Setup Time
t
ASC
Min
-80
-40
-25
-15
ns
Address-RAMCS Hold Time
t
AHC
Min
600
200
120
75
ns
Address Access Time
t
AA
Max
750
250
150
100
ns
RAM Select Access Time
t
CS
Max
750
250
150
100
ns
Output Enable to Valid Output
t
OE
Max
250
70
50
30
ns
RAM Select to Low-Z output
t
LZ
Min
0
0
0
0
ns
Output Enable to Low-Z Output
t
OLZ
Min
0
0
0
0
ns
RAM Select to High-Z Output
t
HZ
Min
0
0
0
0
ns
Max
100
50
40
25
Output Disable to High-Z Output
t
OHZ
Min
0
0
0
0
ns
Max
100
50
40
25
Output Hold from Address Change
t
OH
Min
40
20
15
10
ns
Item
Symbol
Min/Max
1.5V
1.8V
2.4V
2.7-3.6V
Unit
Write Cycle Time
t
WC
Min
750
250
150
100
ns
Address-RAMCS Setup Time
t
ASC
Min
-80
-40
-30
-20
ns
Address-RAMCS Hold Time
t
AHC
Min
600
200
120
75
ns
RAM Select to End of Write
t
CW
Min
750
250
150
100
ns
Address Valid to End of Write
t
AW
Min
750
250
150
100
ns
Address Set-Up Time
t
AS
Min
0
0
0
0
ns
Write Pulse Width
t
WP
Min
400
150
75
65
ns
Write Recovery Time
t
WR
Min
0
0
0
0
ns
Write to High-Z Output
t
WHZ
Min
0
0
0
0
ns
Max
150
70
50
30
Data to Write Time Overlap
t
DW
Min
400
150
75
50
ns
Data Hold from Write Time
t
DH
Min
0
0
0
0
ns
End Write to Low-Z Output
t
OW
Min
40
20
15
10
ns
Item
Symbol
Min/Max
1.5V
1.8V
2.4
2.7-3.6V
Unit
Read Cycle Time
t
RC
Min
1000
400
200
150
ns
Address-ROMCS Setup Time
t
ASC
Min
-80
-40
-25
-15
ns
Address-ROMCS Hold Time
t
AHC
Min
750
300
170
120
ns
Address Access Time
t
ACC
Max
1000
400
200
150
ns
ROM Select Access Time
t
CS
Max
1000
400
200
150
ns
Output Enable Access Time
t
OE
Max
250
100
50
30
ns
Output Hold Time
t
OH
Min
0
0
0
0
ns
Output Floating Time
t
DF
Max
100
50
40
25
ns
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EM02R2XX
FIGURE 4: ROM Read Timing (ROMCS = 0)
FIGURE 5: RAM Read Cycle Timing (WE = V
IH
)
FIGURE 6: RAM Write Cycle Timing (OE fixed)
A0-A17
ROMCS
OE
D0-D7
t
RC
t
OH
t
CS
t
OE
t
DF
t
ACC
t
ASC
t
AHC
A0-A14
RAMCS
OE
D0-D7
t
RC
t
CS
t
OE
t
OHZ
t
HZ
t
AA
Data Valid
t
LZ
t
OH
t
OLZ
t
ASC
t
AHC
A0-A14
RAMCS
WE
Data In
Data Out
t
WP
t
DW
t
DH
Data Valid
High-Z
t
WHZ
t
OW
t
WC
t
AW
t
CW
t
WR
t
AS
t
OH
t
ASC
t
AHC
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EM02R2XX
FIGURE 7: RAM Write Cycle Timing (OE clock)
TABLE 10: RAM/ROM Assertion Timing
FIGURE 8: RAM/ROM Assertion Timing
Item
Symbol
Min
Typ
Max
Unit
Disable ROMCS to Enable RAMCS
t
ROMRAM
0
ns
Disable RAMCS to Enable ROMCS
t
RAMROM
0
ns
A0-A14
OE
RAMCS
WE
Data In
Data Out
t
WC
t
A W
t
CW
t
W P
t
WHZ
t
DW
t
DH
Data
High-Z
t
W R
t
OHZ
t
O W
t
AS
t
ASC
t
AHC
ROMCS
RAMCS
t
ROMRAM
t
RAMROM
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EM02R2XX
TABLE 11: Data Retention Characteristics (Over full specified temperature range)
FIGURE 9: Data Retention Waveform (CS Controlled)
TABLE 12: Ordering Information
* This part number must appear on your order. The code number is to be inserted in place of the XX.
TABLE 13: Revision History
1997-2001 Nanoamp Solutions, Inc. All rights reserved.
NanoAmp Solutions, Inc. ("NanoAmp") reserves the right to change or modify the in-
formation contained in this datasheet and the products described therein, without prior
notice. NanoAmp does not convey any license under its patent rights nor the rights of
others. Charts, drawings and schedules contained in this datasheet are provided for
illustration purposes only and they vary depending upon specific applications.
NanoAmp makes no warranty or guarantee regarding suitability of these products for
any particular purpose, nor does NanoAmp assume any liability arising out of the ap-
plication or use of any product or circuit described herein. NanoAmp does not autho-
rize use of its products as critical components in any application in which the failure of
the NanoAmp product may be expected to result in significant injury or death, including
life support systems and critical medical instruments.
Parameter
Symbol
Minimum
Maximum
Unit
Data Retention Set-up Time
t
SDR
0
s
Recovery Time
t
RDR
1
s
V
CC
V
IH
V
DR
ROMCS /RAMCS
Data Retention Mode
t
SDR
t
RDR
>V
CC
0.2V
GND
Part Number*
Package
Temperature
Range
Voltage
Range
Speed (@ 2.7V+)
EM02R2XXN
32 pin STSOP
-20 to +80
o
C
1.5 to 3.6 V
100RAM/150ROM ns
EM02R2XXT
32 pin TSOP
-20 to +80
o
C
1.5 to 3.6 V
100RAM/150ROM ns
Revision #
Date
Change Description
01
Nov. 1, 1997
Initial Formal Release
02
Feb 1, 1998
Miscellaneous Errata Correction
Changed "V" version from 150 to 200
03
Mar 25, 1998
Changed "L" version to 2.4 volts
Adjusted maximum current per chrz.
04
May 11, 1998 Added Address Setup and Hold Requirements with respect to
RAM Chip Select
05
Aug. 1, 1998
Eliminated L,V,U Specification in favor of a single Specification
that includes 1.5 to 3.6 volts operation. Extended Temp to 80C
Increased twp to 65ns at 2.7 volts.
06
July 8, 1999
Modified Table 2 (WE must be high to output ROM data)
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