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EM28C1602C3FL

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NanoAmp Solutions, Inc.
1982 Zanker Road, San Jose, CA 95112
ph: 408-573-8878, FAX: 408-573-8877
www.nanoamp.com

FLASH AND SRAM COMBO MEMORY

EM28C1602C3FL

Low Voltage, Extended Temperature

FEATURES

· Organization: 1,048K x 16 (Flash)

128K x 16 (SRAM)

· Basic configuration:

Flash

Thirty-nine erase blocks
Eight 4K-word parameter blocks
Thirty-one 32K-word main memory blocks

SRAM

2Mb SRAM for data storage
128K-words

· F_V

, F_V

, S_V

voltages

2.7V (MIN)/3.3V (MAX) F_V

read voltage

2.7V (MIN)/3.3V (MAX) S_V

read voltage

1.8V (TYP) F_V

(in-system PROGRAM/ERASE)

12V ±5% (HV) F_V

(production programming

compatibility)

1.0V (MIN) S_V

(SRAM data retention)

· Asynchronous access time

Flash access time: 90ns @ 2.7V F_V

SRAM access time: 85ns @ 2.7V S_V

· Low power consumption
· Enhanced WRITE/ERASE suspend option
· Read/Write SRAM during program/erase of Flash
· 128-bit chip OTP protection register for security

purposes

· Cross-compatible command set support
· PROGRAM/ERASE cycles

100,000 WRITE/ERASE cycles per block

BALL ASSIGNMENT

66-Ball FBGA (Top View)

OPTIONS

MARKING

· Timing

90ns

-90

· Boot Block

Top

Bottom

· Operating Temperature Range

Extended Temperature (-40

C to +85

· Package

66-ball FBGA (8 x 8 grid)

Part Number Example:

EM28C1602C3FL-90 TET

F_WE #

A16

S_Vss

F_WP #

S_LB#

A18

A11

A15

A14

A13

A12

F_Vss

1 2 3 4 5

6 7 8

9 10 11

A10

F_RP#

F_Vpp

S_UB#

A17

S_OE #

A19

DQ15

DQ13

DQ12

S_W E#

DQ11

DQ9

F_CE#

DQ6

S_CE2

DQ10

DQ8

F_Vss

DQ14

DQ4

S_Vcc

DQ2

DQ0

F_OE#

DQ7

DQ5

F_Vcc

DQ3

DQ1

S_CE1#

F_WE #

A16

S_Vss

F_WP #

S_LB#

A18

A11

A15

A14

A13

A12

F_Vss

1 2 3 4 5

6 7 8

9 10 11

A10

F_RP#

F_Vpp

S_UB#

A17

S_OE #

A19

DQ15

DQ13

DQ12

S_W E#

DQ11

DQ9

F_CE#

DQ6

S_CE2

DQ10

DQ8

F_Vss

DQ14

DQ4

S_Vcc

DQ2

DQ0

F_OE#

DQ7

DQ5

F_Vcc

DQ3

DQ1

S_CE1#

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Table 1

Cross Reference for Abbreviated Device Marks

PRODUCT

SAMPLE

MECHANICAL

PART NUMBER

MARKING

SAMPLE MARKING

EM28C1602C3FL-90 BET

FW220

ES220

FY220

EM28C1602C3FL-90 TET

FW221

ES221

FY221

DEVICE MARKING

Due to the size of the package, NanoAmp's standard

part number is not printed on the top of each device.
Instead, an abbreviated device mark comprised of a
five-digit alphanumeric code is used. The abbreviated
device marks are cross referenced to NanoAmp part
numbers in Table 1.

GENERAL DESCRIPTION

The EM28C1602C3FL, a combination of Flash and

SRAM memory, provides a compact, low-power
solution for systems where PCB real estate is at a
premium. The device contains a nonvolatile, electrically
block-erasable (flash), programmable, read-only memory
containing 16,777,216 bits organized as 1,048,576 words
(16 bits).

The device also provides soft protection for blocks by

configuring soft protection registers with dedicated com-
mand sequences. A 128-bit (OTP )one time programmable
register is provided.

The embedded WORD WRITE and BLOCK ERASE

functions are fully automated by an on-chip write state
machine (WSM). The WSM simplifies these operations and
relieves the system processor of secondary tasks. An
on-chip status register, can be used to monitor the WSM
status to determine the progress of a PROGRAM/ERASE
command.

The erase/program suspend functionality allows com-

patibility with existing EEPROM emulation software pack-
ages.

The device takes advantage of a dedicated power

source for the Flash device (F_V

) and a dedicated

power source for the SRAM device (S_V

), both at

2.7V3.3V for optimized power consumption and im-
proved noise immunity. The separate S_V

pin for the

SRAM provides the data retention capability whenever
required. The data retention S_V

is specified as low as

1.0V. The device supports two V

voltages; in-circuit

of 1.65V3.3V and production compatibility of 12V

±5%. The 12V ±5% V

is supported for a maximum of 100

cycles and 10 cumulative hours.

The EM28C1602C3FL contains an asynchronous 2Mb

SRAM organized as 128K-words by 16 bits. This device
is fabricated using an advanced CMOS process and high-
speed/ultra-low-power circuit technology.

The EM28C1602C3FL is packaged in a 66-ball FBGA

package with 0.80mm pitch.

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BALL DESCRIPTIONS

66-BALL FBGA

NUMBERS

SYMBOL

TYPE

DESCRIPTION

A4, A5, A6,

A0A19

Input

Address Inputs: Inputs for the addresses during READ and WRITE

A7, A8, B3, B4,

operations. Addresses are internally latched during READ and WRITE

B5, B6, E5, G3,

cycles. Flash: A0A19; SRAM: A0A16.

G4, G5, G6, G7,

G8, G9, H4, H5,

H6
H7

F_CE#

Input

Flash Chip Enable: Activates the device when LOW. When CE# is HIGH, the
device is disabled and goes into standby power mode.

F_OE#

Input

Flash Output Enable: Enables flash output buffers when LOW. When F_OE#
is HIGH, the output buffers are disabled.

F_WE#

Input

Flash Write Enable: Determines if a given cycle is a flash WRITE cycle.
F_WE# is active LOW.

F_RP#

Input

Reset. When F_RP# is a logic LOW, the device is in reset, which drives the
outputs to High-Z and resets the WSM. When F_RP# is a logic HIGH, the
device is in standard operation. When F_RP# transitions from logic LOW to
logic HIGH, the device resets all blocks to locked and defaults to the read
array mode.

F_WP#

Input

Flash Write Protect. Controls the lock down function of the flexible
locking feature.

G10

S_CE1#

Input

SRAM Chip Enable1: Activates the SRAM when it is LOW. HIGH level
deselects the SRAM and reduces the power consumption to standby
levels.

S_CE2

Input

SRAM Chip Enable2: Activates the SRAM when it is HIGH. LOW level
deselects the SRAM and reduces the power consumption to standby
levels.

S_OE#

Input

SRAM Output Enable: Enables SRAM output buffers when LOW. When
S_OE# is HIGH, the output buffers are disabled.

S_WE#

Input

SRAM Write Enable: Determines if a given cycle is an SRAM WRITE cycle.
S_WE# is active LOW.

S_LB#

Input

SRAM Lower Byte: When LOW, it selects the SRAM address lower byte
(DQ0DQ7).

S_UB#

Input

SRAM Upper Byte: When LOW, it selects the SRAM address upper byte
(DQ8DQ15).

B7, B9, B10,

DQ0DQ15

Input/

Data Inputs/Outputs: Input array data on the second CE# and WE#

C7, C8, C9,

Output

cycle during PROGRAM command. Input commands to the command

C10, D7, E6,

user interface when CE# and WE# are active. Output data when CE#

E8, E9, E10,

and OE# are active.

F7, F8, F9, F10

(continued on next page)

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BALL DESCRIPTIONS (continued)

66-BALL FBGA

NUMBERS

SYMBOL

TYPE

DESCRIPTION

F_V

Input/

Flash Program/Erase Power Supply: [1.65V3.3V or 11.4V12.6V]. Operates

Supply

as input at logic levels to control complete device protection. Provides
backward compatibility for factory programming when driven to 11.4V
12.6V. Lower F_V

voltages are available; consult factory for availability.

D10

F_V

Supply

Flash Power Supply: [2.7V3.3V]. Supplies power for device operation.

A9, H8

F_V

Supply

Flash Specific Ground: Do not float any ground pin.

S_V

Supply

SRAM Power Supply: [2.7V3.3V]. Supplies power for device operation.

S_V

Supply

SRAM Specific Ground: Do not float any ground pin.

A1, A2, A3,

No Connect: Lead is not internally connected; it may be driven or

A10, A11, A12,

floated.

C4, H1, H2, H3,

H10, H11, H12

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NOTES: 1. Two devices may not drive the memory bus at the same time.

2. Allowable flash read modes include read array, read configuration, and read status.
3. Outputs are dependent on a separate device controlling bus outputs.
4. Modes of the Flash and SRAM can be interleaved so that while one is disabled, the other controls outputs.
5. The SRAM may be placed into data retention mode by lowering S_V

to the V

range, as specified.

6. SRAM is enabled and/or disabled with the logical function: S_CE1# or S_CE2.
7. Simultaneous operations can exist, as long as the operations are interleaved such that only one device attempts to

control the bus outputs at a time.

8. Data output on lower byte only; upper byte High-Z.
9. Data output on upper byte only; lower byte High-Z.

10. Data input on lower byte only.
11. Data input on upper byte only.

TRUTH TABLE FLASH

FLASH SIGNALS

SRAM SIGNALS

MEMORY OUPUT

MODES

F_RP# F_CE# F_OE# F_WE#S_CE1#S_CE2 S_OE# S_WE# S_UB# S_LB#

MEMORY

DQ0DQ15

NOTES

BUS CONTROL

Read

SRAM must be High-Z

Flash

OUT

1, 2, 3

Write

Flash

Standby

Other

High-Z

4, 5

Output Disable

SRAM any mode allowable

Other

High-Z

4, 6

Reset

Other

High-Z

4, 7

TRUTH TABLE SRAM

FLASH SIGNALS

SRAM SIGNALS

MEMORY OUPUT

MODES

F_RP# F_CE# F_OE# F_WE# S_CE1# S_CE2 S_OE# S_WE# S_UB# S_LB#

MEMORY

DQ0DQ15

NOTES

BUS CONTROL

Read

DQ0DQ15

SRAM

OUT

1, 3

DQ0DQ7

SRAM

OUT

DQ8DQ15

Flash must be High-Z

SRAM

OUT

Write

DQ0DQ15

SRAM

1, 3

DQ0DQ7

SRAM

DQ8DQ15

SRAM

Standby

Other

High-Z

4, 5

Flash any mode allowable

Other

High-Z

4, 5

Output Disable

Other

High-Z

4, 5

Data Retention

Same as standby

Other

High-Z

4, 6

FLASH

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Figure 1

Top Boot Block Device

8 x 4K-Word Blocks

32K-Word Block

4K-Word Block

Parameter

Blocks

FFFFFH

F8000H

F7FFFH

F0000H

EFFFFH

E8000H

E7FFFH

E0000H

DFFFFH

D8000H

D7FFFH

D0000H

CFFFFH

C8000H

C7FFFH

C0000H

BFFFFH

B8000H

B7FFFH

B0000H

AFFFFH

A8000H

A7FFFH

A0000H

9FFFFH

98000H

97FFFH

90000H

8FFFFH

88000H

87FFFH

80000H

7FFFFH

78000H

77FFFH

70000H

6FFFFH

68000H

67FFFH

60000H

5FFFFH

58000H

57FFFH

50000H

4FFFFH

48000H

47FFFH

40000H

3FFFFH

38000H

37FFFH

30000H

2FFFFH

28000H

27FFFH

20000H

1FFFFH

18000H

17FFFH

10000H

0FFFFH

08000H

07FFFH

00000H

FFFFFH
FF000H
FEFFFH

FE000H
FDFFFH

FD000H
FCFFFH

FC000H
FBFFFH

FB000H
FAFFFH

FA000H
F9FFFH

F9000H
F8FFFH

F8000H

ADDRESS RANGE

FLASH

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Figure 2

Bottom Boot Block Device

32K-Word Block

8 x 4K-Word Blocks

4K-Word Block

Parameter

Blocks

FFFFFH

F8000H

F7FFFH

F0000H

EFFFFH

E8000H

E7FFFH

E0000H

DFFFFH

D8000H

D7FFFH

D0000H

CFFFFH

C8000H

C7FFFH

C0000H

BFFFFH

B8000H

B7FFFH

B0000H

AFFFFH

A8000H

A7FFFH

A0000H

9FFFFH

98000H

97FFFH

90000H

8FFFFH

88000H

87FFFH

80000H

7FFFFH

78000H

77FFFH

70000H

6FFFFH

68000H

67FFFH

60000H

5FFFFH

58000H

57FFFH

50000H

4FFFFH

48000H

47FFFH

40000H

3FFFFH

38000H

37FFFH

30000H

2FFFFH

28000H

27FFFH

20000H

1FFFFH

18000H

17FFFH

10000H

0FFFFH

08000H

07FFFH

00000H

07FFFH
07000H
06FFFH

06000H
05FFFH

05000H
04FFFH

04000H
03FFFH

03000H
02FFFH

02000H
01FFFH

01000H
00FFFH

00000H

ADDRESS RANGE

FLASH

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FLASH MEMORY OPERATING MODES

COMMAND STATE MACHINE

Commands are issued to the command state ma-

chine (CSM) using standard microprocessor write tim-
ings. The CSM acts as an interface between external
microprocessors and the internal write state machine
(WSM). The available commands are listed in Table 2,
their definitions are given in Table 3 and their descrip-
tions in Table 4. Program and erase algorithms are au-
tomated by the on-chip WSM. Table 5 shows the CSM
transition states. Once a valid PROGRAM/ERASE com-
mand is entered, the WSM executes the appropriate
algorithm, which generates the necessary timing sig-
nals to control the device internally. A command is
valid only if the exact sequence of WRITEs is completed.
After the WSM completes its task, the write state ma-
chine status (WSMS) bit (SR7) (see Table 7) is set to a logic
HIGH level (V

), allowing the CSM to respond to the full

command set again.

OPERATIONS

Device operations are selected by entering a stan-

dard JEDEC 8-bit command code with conventional
microprocessor timings into an on-chip CSM through
I/O pins DQ0DQ7. The number of bus cycles required
to activate a command is typically one or two. The first
operation is always a WRITE. Control pins F_CE# and
F_WE# must be at a logic LOW level (V

), and F_OE#

and F_RP# must be at logic HIGH (V

). The second

operation, when needed, can be a WRITE or a READ
depending upon the command. During a READ opera-
tion, control pins F_CE# and F_OE# must be at a logic LOW
level (V

), and F_WE# and F_RP# must be at logic HIGH

Table 6 illustrates the bus operations for all the modes:

write, read, reset, standby, and output disable.

When the device is powered up, internal reset circuitry

initializes the chip to a read array mode of operation.
Changing the mode of operation requires that a command
code be entered into the CSM. The on-chip status register
allows the monitoring of the progress of various opera-
tions that can take place. The status register is interro-
gated by entering a READ STATUS REGISTER command
onto the CSM (cycle 1) and reading the register data on
I/O pins DQ0DQ7 (cycle 2). Status register bits SR0-SR7
correspond to DQ0DQ7 (see Table 7).

COMMAND DEFINITION

Once a specific command code has been entered,

the WSM executes an internal algorithm, generating the
necessary timing signals to program, erase, and verify
data. See Table 3 for the CSM command definitions and
data for each of the bus cycles.

STATUS REGISTER

The status register allows the user to determine

whether the state of a PROGRAM/ERASE operation is
pending or complete. The status register is monitored
toggling F_OE#, F_CE#, and address lines by reading
the resulting status code on I/O pins DQ0DQ7. The high-
order I/Os (DQ8DQ15) are set to 00h internally, so only
the low-order I/O pins (DQ0DQ7) need to be interpreted.
Address lines select the status register pertinent to the
selected memory partition.

or F_CE#, whichever occurs first. The latest falling edge
of either of these two signals updates the latch within a

Table 2

Command State Machine Codes For Device Mode Selection

COMMAND DQ0DQ7

CODE ON DEVICE MODE

10h/40h

Program setup/alternate program setup

20h

Block erase setup

50h

Clear status register

60h

Reserved

70h

Read status register

90h

Read device identity

0Fh

Soft protection

B0h

Program/erase suspend

D0h

Program/erase resume - erase confirm

FFh

Read array/OTP exit

AFh

OTP entry

FLASH

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Table 3

Command Definitions

FIRST CYCLE

SECOND CYCLE

COMMAND

OPERATION

ADDRESS

CSM/INPUT

OPERATION

ADDRESS

DATA

READ ARRAY

WRITE

FFh

READ

IDENTIFY DEVICE

WRITE

90h

READ

READ STATUS REGISTER

WRITE

70h

READ

SRD

WORD PROGRAM

WRITE

10h/40h

WRITE

BLOCK ERASE

WRITE

20h

WRITE

D0h

PROGRAM/ERASE SUSPEND

WRITE

B0h

PROGRAM/ERASE RESUME

WRITE

D0h

CLEAR STATUS REGISTER

WRITE

50h

SOFT PROTECTION

WRITE

0Fh

WRITE

SPC

OTP ENTRY

WRITE

AFh

WRITE

AFh

OTP EXIT

WRITE

FFh

WRITE

FFh

NOTE: 1. The command data is written through DQ0-DQ7

2. ID = Manufacturer ID: 002Ch; Device ID (Top Boot): 4492h; Device ID (Bottom Boot): 4493h
3. IA = Identify address: 00000h for manufacturer code and 00001h for device code
4. BA = Any address within the block to be selected
5. WA = Word address
6. AD = Array data
7. SRD = Data read from status register
8. PD = Data to be written at location WA
9. SPC = Soft protect command:

00h = Clear all soft protection
FFh = Set all soft protection
F0h = Clear addressed block soft protection
0Fh = Set addressed block soft protection

10. X = Don't Care

given READ cycle. Latching the data prevents errors from
occurring if the register input changes during a status
register read. To ensure that the status register output
contains updated status data, CE# or OE# must be toggled
for each subsequent STATUS READ.

The status register provides the internal state of the

WSM to the external microprocessor. During periods
when the WSM is active, the status register can be polled
to determine the WSM status. Table 7 defines the status
register bits.

After monitoring the status register during a

PROGRAM/ERASE operation, the data appearing on
DQ0DQ7 remains as status register data until a new
command is issued to the CSM. To return the device to
other modes of operation, a new command must be issued
to the CSM.

COMMAND STATE MACHINE OPERATIONS

The CSM decodes instructions for the commands

listed in Table 2. The 8-bit command code is input to the
device on DQ0DQ7 (see Table 3 for command defini-
tions). During a PROGRAM or ERASE cycle, the CSM
informs the WSM that a PROGRAM or ERASE cycle has
been requested.

program sequences and the CSM responds to a PRO-
GRAM SUSPEND command only.

During an ERASE cycle, the CSM responds to an

ERASE SUSPEND command only. When the WSM has
completed its task, the WSMS bit (SR7) is set to a logic HIGH
level and the CSM responds to the full command set. The
CSM stays in the current command state until the micro-
processor issues another command.

The WSM successfully initiates an ERASE or PRO-

GRAM operation only when V

is within its correct

voltage range.

During a PROGRAM cycle, the WSM controls the

FLASH

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Table 4

Command Descriptions

CODE DEVICE MODE

BUS CYCLE

DESCRIPTION

10h

Alt. Program Setup

First

Operates the same as a PROGRAM SETUP command.

20h

Erase Setup

First

Prepares the CSM for an ERASE CONFIRM command. If the next command

is not ERASE CONFIRM, the CSM will set both SR4 and SR5 of the status
register to a "1," place the device into read status register mode, and wait
for another command.

40h

Program Setup

First

A two-cycle command: The first cycle prepares for a PROGRAM

operation, the second cycle latches addresses and data and initiates the
WSM to execute the program algorithm. The flash outputs status register
data on the falling edge of F_OE# or F_CE#, whichever occurs first.

50h

Clear Status

First

The WSM can set the program status (SR4), and erase status (SR5) bits

in the status register to "1," but it cannot clear them to "0." Issuing
this command clears those bits to "0."

70h

Read Status

First

Places the device into read status register mode. Reading the device

will output the contents of the status register, regardless of the
address presented to the device. The device will automatically enter
this mode after a PROGRAM or ERASE operation has been initiated.

90h

Read Device Identity

First

Puts the device into the read configuration mode so that
reading the device will output the manufacturer/device codes.

0Fh

Soft Protection

First

Puts the device into the soft protection mode so that the protection bit for
each block can be set and cleared.

B0h

Program Suspend

First

Suspends the currently executing PROGRAM/ERASE operation. The
status register will indicate when the operation has been successfully

Erase Suspend

First

suspended by setting either the program suspend (SR2) or erase
suspend (SR6) and the WSMS bit (SR7) to a "1" (ready). The WSM
will continue to idle in the suspend state, regardless of the state of all
input control pins except F_RP#, which will immediately shut down the
WSM and the remainder of the chip if F_RP# is driven to V

D0h

Erase Confirm

First

If the previous command was an ERASE SETUP command, then the CSM
will close the address and data latches, and it will begin erasing the block
indicated on the address pins. During programming/erase, the device will
respond only to the ERASE SUSPEND command and will output status
register data on the falling edge of F_OE# or F_CE#, whichever occurs
last.

Program/Erase

First

If a PROGRAM or ERASE operation was previously suspended, this

Resume

command will resume the operation.

FFh

Read Array

First

During the array mode, array data will be output on the data bus.

OTP Exit

Second

Exits the OTP area on second FFh command.

AFh

OTP Entry

Second

Allows programming or reading of the OTP area on second AFh
command.

FLASH

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CLEAR STATUS REGISTER

The internal circuitry can set, but not clear, the block

lock status bit (SR1), the V

status bit (SR3), the program

status bit (SR4), and the erase status bit (SR5) of the
status register. The CLEAR STATUS REGISTER command
(50h) allows the external microprocessor to clear these
status bits and synchronize to the internal operations.
When the status bits are cleared, the device returns to the
read array mode.

READ OPERATIONS

The following READ operations are available: READ

ARRAY, READ DEVICE IDENTIFICATION and READ STA-
TUS REGISTER.

READ ARRAY

The array is read by entering the command code

FFh on DQ0DQ7. Control pins F_CE# and F_OE# must
be at a logic LOW level (V

), and F_WE# and F_RP#

must be at a logic HIGH level (V

) to read data from the

array. Data is available on DQ0DQ15. Any valid address
within any of the blocks selects that address and allows
data to be read from that address. Upon initial power-up,
the device defaults to the read array mode.

READ DEVICE IDENTIFICATION DATA

Device identification codes are read by entering com-

mand code 90h on DQ0-DQ7. Two bus cycles are required
for this operation, the first to enter the command code and
the second to read the selected code. Control pins CE# and
OE# must be at a logic LOW level (V

) and WE# and RP#

must be at a logic HIGH level (V

). The manufacturer code

is obtained on DQ0-DQ15 in the second cycle, after the
identify address 00000h is latched. The device code is
obtained on DQ0-DQ15 in the second cycle, after the
identify address 00001h is latched (see Table 3).

READ STATUS REGISTER

The status register is read by entering the command

code 70h on DQ0-DQ7. Control pins F_CE# and F_OE#
must be at a logic LOW level (V

), andF_ WE# and F_RP#

must be at a logic HIGH level (V

). Two bus cycles are

required for this operation: one to enter the command
code, and one to read the status register. The status
register contents are updated on the falling edge of F_CE#
or F_OE#, whichever occurs last within the cycle.

PROGRAMMING OPERATIONS

There are two CSM commands for programming:

PROGRAM SETUP and ALTERNATE PROGRAM SETUP
(see Table 2).

After the desired command code is entered (10h or 40h

command code on DQ0DQ7), the WSM takes over and
correctly sequences the device to complete the PRO-
GRAM operation. The WRITE operation may be monitored
through the status register (see the Status Register
section). During this time, the CSM will only respond to a
PROGRAM SUSPEND command until the PROGRAM op-
eration has been completed, after which time all com-
mands to the CSM become valid again. During program-
ming, V

P P

must remain in the

appropriate V

voltage range as shown in the recom-

mended operating conditions table. Different combina-
tions of RP#, WP#, and V

pin voltage levels ensure that

data in certain blocks are secure and therefore cannot be
programmed (see Table 5 for a list of combinations). Only
"0s" are written and compared during a PROGRAM opera-
tion. If "1s" are programmed, the memory cell contents do
not change and no error occurs. The PROGRAM operation
can be suspended by issuing a PROGRAM SUSPEND
command (B0h). Once the WSM reaches the suspend
state, it allows the CSM to respond only to READ ARRAY,
READ STATUS REGISTER or PROGRAM RESUME com-
mands. During the PROGRAM SUSPEND operation, array
data should be read from an address other than the one
being programmed. To resume the PROGRAM operation,
a PROGRAM RESUME command (D0h) must be issued to
cause the CSM to clear the suspend state previously set
(see Figure 3 for programming operation and Figure 4 for
program suspend and program resume).

ERASE OPERATIONS

An ERASE operation must be used to initialize all bits

in an array block to "1s." After BLOCK ERASE confirm is
issued, the CSM responds only to an ERASE SUSPEND
command until the WSM completes its task.

Block erasure inside the memory array sets all bits

within the address block to logic 1s. Erase is accomplished
only by blocks; data at single address locations within the
array cannot be erased individually. The block to be
erased is selected by using any valid address within that
block. Block erasure is initiated by a command sequence
to the CSM: BLOCK ERASE setup (20h) followed by
BLOCK ERASE CONFIRM (D0h) (see Table 3). A two-
command erase sequence protects against accidental
erasure of memory contents.

When the BLOCK ERASE CONFIRM command is com-

plete, the WSM automatically executes a sequence of
events to complete the block erasure. During this se-
quence, the block is programmed with logic 0s, data is
verified, all bits in the block are erased, and finally
verification is performed to ensure that all bits are cor-
rectly erased. Monitoring of the ERASE operation is
possible through the status register (see the Status

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Table 5

Command State Machine Transition Table

COMMAND INPUTS (and next state)

Current

SR7

Data

Read

Write

Block

Erase

Prog./

Read

Clear

Identify

Soft

Otp

State

when

Array

setup

erase

confirm

erase

device

prot.

entry

Read

(FFh)

(10h/

setup

(D0h)

susp.

resume

(70h)

(50h)

(90h)

setup

(SPC)

(AFh)

40h)

(20h)

(B0h)

(D0h)

(0Fh)

Read Array

Array

Read

Write

Erase

Read array

Read

Identify Soft prot. Soft prot.

Otp

array

setup

status

array

device

setup

setup/

entry

read

array

Read

Status

Read

Write

Erase

Read array

Read

Identify

Soft

Soft prot.

Otp

Status

array

setup

status

array

device

prot.

setup/

entry

setup

read

array

Identify

Read

Write

Erase

Read array

Read

Identify

Soft

Soft prot.

Otp

Device

array

setup

status

array

device

prot.

setup/

entry

setup

read

array

Soft Prot.

Status

Soft

Read array

Soft prot.

Soft

Read

Setup

prot. all

block

prot.

array

Soft

Status

Read

Write

Erase

Read array

Read

Identify Soft prot. Soft prot.

Otp

Protection

array

setup

status

array

device

setup

setup/

entry

Complete

read

array

Write

Status

Program

Setup

Program Not

Status

Program

Prog.

Program

Complete

(not complete)

susp.

(not complete)

status

Program

Status

Program Program suspend Program Program Program Program

Program suspend read array

Suspend

susp.

read array

susp.

Status

read

status

array

Program

Array

Program Program suspend Program Program Program Program

Program suspend read array

Suspend

susp.

read array

susp.

Read Array

read

status

array

Program

Status

Read

Write

Erase

Read array

Read

Identify Soft prot. Soft prot.

Otp

Complete

Array

setup

status

array

device

setup

setup/

entry

read

array

Erase

Status

Erase command error

Erase

Erase command error

Setup

Erase

Status

Read

Write

Erase

Read array

Read

Identify

Soft

Soft prot.

Otp

Comd. Error

array

setup

status

array

device

prot.

setup/

entry

setup

Read

array

Erase Not

Status

Erase (not complete)

Erase

Erase (not complete)

Complete

susp. to

status

Erase

Status

Erase

Write

Erase

Erase suspend read array

Suspend

susp.

setup

susp.

Status

read

status

array

Erase

Array

Erase

Write

Erase

Erase suspend read array

Suspend

susp.

setup

susp.

Array

read

status

array

Erase

Status

Read

Write

Erase

Read array

Read

Identify

Soft

Soft prot.

Otp

Complete

array

setup

status

array

device

prot.

setup/

entry

setup

read

array

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During the execution of an ERASE operation, the

ERASE SUSPEND command (B0h) can be entered to direct
the WSM to suspend the ERASE operation. Once the WSM
has reached the suspend state, it allows the CSM to
respond only to the READ ARRAY, READ STATUS REG-
ISTER, PROGRAM SETUP, PROGRAM RESUME and ERASE
RESUME. During the ERASE SUSPEND operation, array
data must be read from a block other than the one being
erased. To resume the ERASE operation, an ERASE
RESUME command (D0h) must be issued to cause the CSM
to clear the suspend state previously set (see Figure 6).
It is also possible that an ERASE in any block can be
suspended and a WRITE to another block can be initiated.
After the completion of a WRITE, the ERASE can be
resumed by writing an ERASE RESUME command.

Table 6

Bus Operations

MODE

F_RP#

F_CE#

F_OE#

F_WE#

ADDRESS

DQ0DQ15

Read (array, status register,

OUT

device identification register)

Standby

High-Z

Output Disable

High-Z

Reset

High-Z

Write

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STATUS

BIT #

STATUS REGISTER BIT

DESCRIPTION

SR7

WRITE STATE MACHINE STATUS (WSMS) Check write state machine bit first to determine word
1 = Ready

program or block erase completion, before checking

0 = Busy

program or erase status bits.

SR6

ERASE SUSPEND STATUS (ESS)

When ERASE SUSPEND is issued, WSM halts execution and

1 = BLOCK ERASE Suspended

sets both WSMS and ESS bits to "1." ESS bit remains set to

0 = BLOCK ERASE in

"1" until an ERASE RESUME command is issued.

Progress/Completed

SR5

ERASE STATUS (ES)

When this bit is set to "1," WSM has applied the maximum

1 = Error in Block Erasure

number of erase pulses to the block and is still unable to

0 = Successful BLOCK ERASE

verify successful block erasure.

SR4

PROGRAM STATUS (PS)

When this bit is set to "1," WSM has attempted but failed to

1 = Error in PROGRAM

program a word.

0 = Successful PROGRAM

SR3

STATUS (V

The V

status bit does not provide continuous indication

1 = V

Low Detect, Operation Abort

of the V

level. The WSM interrogates the V

level only

0 = V

= OK

after the program or erase command sequences have been
entered and informs the system if V

has not been switched

on. The V

level is also checked before the PROGRAM/ERASE

operation is verified by the WSM.

SR2

PROGRAM SUSPEND STATUS (PSS)

When PROGRAM SUSPEND is issued, WSM halts execution

1 = PROGRAM Suspended

and sets both WSM and PSS bits to "1." PSS bit remains set to

0 = PROGRAM in Progress/Completed

"1" until a PROGRAM RESUME command is issued.

SR1

BLOCK LOCK STATUS (BLS)

If a PROGRAM or ERASE operation is attempted to one of

1 = PROGRAM/ERASE Attempted on a

the locked blocks, this is set by the WSM. The operation

Locked Block; Operation Aborted

specified is aborted and the device is returned to read status

0 = No Operation to Locked Blocks

mode.

SR0

RESERVED FOR FUTURE

This bit is reserved for future.

ENHANCEMENT

Table 7

Status Register Bit Definition

WSMS

ESS

PSS

BLS

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Figure 3

Automated Word Programming

Flowchart

NOTE: 1. Full status register check can be done after each word or after a sequence of words.

2. SR3 must be cleared before attempting additional PROGRAM/ERASE operations.
3. SR4 is cleared only by the CLEAR STATUS REGISTER command, but it does not prevent additional program operation

attempts.

BUS
OPERATION C O M M A N D COMMENTS
WRITE

WRITE

Data =

40h or 10h

PROGRAM

Addr =

Don't care

SETUP

WRITE

Data =

Word to be

DATA

programmed

Addr =

Address of word to be
programmed

READ

Status register data;
toggle OE# or CE# to update
status register.

Standby

Check SR7
1 = Ready, 0 = Busy

Repeat for subsequent words.
Write FFh after the last word programming operation
to reset the device to read array mode.

BUS
OPERATION C O M M A N D COMMENTS

Standby

Check SR1
1 = Detect locked block

Standby

Check SR3

1 = Detect V

low

Standby

Check SR4

1 = Word program error

YES

Full Status Register

Check (optional)

YES

PROGRAM

SUSPEND?

SR7 = 1?

Issue PROGRAM SETUP

Command and

Word Address

Start

Word Program Passed

Range Error

Word Program Failed

FULL STATUS REGISTER CHECK FLOW

Read Status Register

Bits

Issue Word Address

and Word Data

PROGRAM

SUSPEND Loop

YES

SR1 = 0?

YES

SR3 = 0?

YES

SR4 = 0?

Word Program

Completed

Read Status Register

Bits

PROGRAM Attempted

on a Locked Block

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Figure 5

BLOCK ERASE Flowchart

NOTE: 1. Full status register check can be done after each block or after a sequence of blocks.

2. SR3 must be cleared before attempting additional PROGRAM/ERASE operations.
3. SR5 is cleared only by the CLEAR STATUS REGISTER command in cases where multiple blocks are erased before full

status is checked.

BUS
OPERATION C O M M A N D COMMENTS

WRITE

Data = 20h

ERASE

Addr = Don't care

SETUP

WRITE

ERASE

Data = D0h
Block Addr = Address
within block to be erased

READ

Status register data;
toggle OE# or CE# to
update status register.

Standby

Check SR7
1 = Ready, 0 = Busy

Repeat for subsequent blocks.
Write FFh after the last BLOCK ERASE operation to
reset the device to read array mode.

BUS
OPERATION C O M M A N D COMMENTS

Standby

Check SR1
1 = Detect locked block

Standby

Check SR3

1 = Detect V

block

Standby

Check SR4 and SR5
1 = BLOCK ERASE

command error

Standby

Check SR5

1 = BLOCK ERASE error

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READ

PROGRAM

Issue READ ARRAY

Command

PROGRAM

Loop

ERASE

Complete

READ or

PROGRAM?

YES

Issue ERASE

RESUME Command

READ or

PROGRAM
Complete?

YES

SR6 = 1?

Start

ERASE Continued

Read Status Register

Bits

Issue ERASE

SUSPEND Command

(Note 2)

YES

SR7 = 1?

Figure 6

ERASE SUSPEND/ERASE RESUME

Flowchart

NOTE: 1. See BLOCK ERASE Flowchart for complete erasure procedure.

2. See Word Programming Flowchart for complete programming procedure.

BUS
OPERATION

COMMAND

COMMENTS

WRITE

ERASE

Data = B0h

SUSPEND

READ

Status register data
Toggle OE# or CE# to update
status register

Standby

Check SR7
1 = Ready

Standby

Check SR6
1 = Suspended

WRITE

READ

Data = FFh

MEMORY

or
WRITE

WRITE

Data = 40h or 10h

SETUP

Addr = Don't Care

READ

Read data from block other
than that being erased

or
WRITE

WRITE

Data = Word to be

DATA

programmed
Addr = Address of word to be
programmed

WRITE

ERASE

Data = D0h

RESUME

Addr = Don't Care

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NOTE: 1. Always locked.

2. Locked by programming DQ15 at address 00040H.

4 Words

Factory-Programmed

4 Words

User-Programmed

DQ15

00000H
00002H
00004H
00006H

00020H
00022H
00024H
00026H

00040H

Figure 7

OTP Area Map

OTP MODE

The device has 128 bits of OTP (one time program-

mable) area. There are 64 bits that are programmed at the
factory with a unique 64-bit code that is not modifiable. The
other 64-bit OTP area is left blank to program for customer
design requirements if needed. Protection of the user-
programmable, 64-bit contents is provided, after the area
is programmed, by programming the lock-bit.

To program the OTP area, two "AFh" commands must

be written, followed by two WRITE cycles of the normal
program sequences. When in the OTP mode, the WSM
programs the OTP area and not the array. During program-
ming, a read can acquire only the WSM status (status
register output). When the programming is complete, the
device remains in the OTP mode and only the status can
be read in the OTP area. Writing two "FFh" commands exits
the OTP mode and causes the device to go into the read
array mode. To read the OTP area after programming, the
OTP mode must be re-entered.

To read the OTP area contents, two "AFh" commands

must be written, followed by a READ. Writing two "FFh"
commands exits the OTP mode and causes the device to
go into the read array mode.

After programming the 64-bit OTP area, the lock-bit can

be programmed. The lock-bit is at address 00040H and is
on DQ15. Once the lock-bit is programmed to a "0," the 64-
bit, user-programmable area is permanently protected
(see Figure 7). The lock- bit can be read in OTP mode, as
described above.

STANDBY MODE

Icc supply current is reduced by applying a logic HIGH

level on F_CE# and F_RP# to enter the standby mode. In
the standby mode, the outputs are placed in High-Z.
Applying a CMOS logic HIGH level on F_CE# and F_RP#
reduces the current to I

(MAX). If the device is dese-

lected during an ERASE operation or during programming,
the device continues to draw current until the operation
is complete.

SOFT BLOCK DATA PROTECTION

Soft protection is available with CSM command 0Fh

(see Table 3). The protection bit for each block can be set
and cleared individually, or all at once. After the soft
protection bit of a block is set, the block is protected when
V

> V

PPLK

, RP# is HIGH, and WP# is LOW. When V

PPLK

the block is protected (locked) as well. A block is

unlocked when WP# is HIGH, even if its soft protection bit
is set (see Table 8)..

When the device is powered down or RP# reset, the

soft protection blocks will be set to the protected state. So,
if WP# goes LOW after first power-up, RP# reset, or
power-down, all blocks will be protected. The CSM
command 0Fh is needed to clear the soft protected blocks.
When WP# goes LOW the cleared blocks will be unpro-
tected.

The block lock status bit SR1 is used to monitor the

individual block lock status after the second WRITE cycle
of the soft protection CSM command. Additionally, to
monitor the block lock status of any block, the read status
register command 70h can be used. On the command's
second cycle, any address within a block is issued and
SR1 will indicate the block lock status for that block. When
monitoring the block lock status bit SR1, the correct status
can only be obtained with WP# LOW.

AUTOMATIC POWER SAVE MODE (APS)

Substantial power savings are realized during periods

when the Flash array is not being read and the device is
in the active mode. During this time the device switches
to the automatic power save (APS) mode. When the
device switches to this mode, I

is reduced to I

. The

low level of power is maintained until another operation is
initiated. In this mode, the I/O pins retain the data from the
last memory address read until a new address is read.
This mode is entered automatically if no address or control
pins toggle. At least one transition of F_CE# must occur
after power-up to activate this mode's availability.

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Table 9

RANGE (V)

M I N

M A X

In-System

1.65

2.2

In-Factory

11.4

12.6

/ V

PROGRAM AND ERASE

VOLTAGES

The flash memory of the EM28C1602C3FL provides

in-system programming and erase with V

in the

1.65V3.3V range. V

at 12V ±5% is supported for a

maximum of 100 cycles and 10 cumulative hours. The
device can withstand 100,000 WRITE/ERASE opera-
tions with V

= V

. During WRITE and ERASE

operations, the WSM monitors the V

voltage level.

WRITE/ERASE operations areallowed only when V

within the ranges specified in Table 9.

POWER-UP

During a power-up, it is not necessary to sequence

Q, V

and V

. However, it is recommended that RP#

be held LOW during power-up for additional protection
while V

is ramping above V

LKO

to a stable operative level.

After a power-up or RESET, the status register is reset,
and the device will enter the array read mode.

POWER-UP PROTECTION

The likelihood of unwanted WRITE or ERASE opera-

tions is minimized since two consecutive cycles are
required to execute either operation. When V

< V

LKO

, the

device does not accept any WRITE cycles, and noise
pulses < 5ns on CE# or WE# do not initiate a WRITE cycle.

Table 8

Data Protection Combinations

DATA PROTECTION PROVIDED

RP#

WP#

All blocks locked

PPLK

All blocks locked

All blocks unlocked

PPLK

Soft-protected blocks unlocked

PPLK

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ABSOLUTE MAXIMUM RATINGS*

Voltage to Any Pin Except V

and V

with Respect to V

..................... -0.5V to +4.0V

Voltage (for BLOCK ERASE and PROGRAM)

with Respect to V

................ -0.5V to +13.0V**

Supply Voltage

with Respect to V

..................... -0.3V to +4.0V

Output Short Circuit Current ................................. 100mA
Operating Temperature Range ................. -40

C to +85

Storage Temperature Range .................. -55

C to +125

Soldering Cycle .......................................... 260

C for 10s

*Stresses greater than those listed under "Absolute
Maximum Ratings" may cause permanent damage to the
device. This is a stress rating only and functional opera-
tion of the device at these or any other conditions above
those indicated in the operational sections of this speci-
fication is not implied. Exposure to absolute maximum
rating conditions for extended periods may affect reliabil-
ity.
**Maximum DC voltage on Vpp may overshoot to +13.5V
for periods less than 20ns.

RECOMMENDED OPERATING CONDITIONS

PARAMETER

SYMBOL

M I N

M A X

UNITS

NOTES

Operating temperature

-40

+85

supply voltage

F_V

, S_V

2.7

3.3

Supply voltage, when used as logic control

1.65

3.3

in-factory programming voltage

11.4

12.6

Data retention supply voltage

S_V

1.0

Block erase cycling

100,000

Cycles

Figure 8

Output Load Circuit

I/O

14.5K

30pF

14.5K

FLASH ELECTRICAL SPECIFICATIONS

NOTE: 1. 12V V

is supported for a maximum of 100 cycles and may be connected for up to 10 cumulative hours.

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COMBINED DC CHARACTERISTICS

= 2.7V3.3V

DESCRIPTION

CONDITIONS

SYMBOL

MIN

TYP

MAX

UNITS NOTES

Input Low Voltage

-0.2

0.2

Input High Voltage

0.2V

Output Low Voltage

Vcc = Vcc (MIN),

0.10

= 100 A

Output High Voltage

Vcc=Vcc(MIN),

= 100 A

0.1V

Lock Out Voltage

PPLK

1.0

During Program/Erase

1.65

3.3

Operations

11.4

12.6

Program/Erase Lock Voltage

LKO

1.5

Input Leakage Current

(MAX)

Output Leakage Current

(MAX)

F_V

Vcc=Vcc(MAX)

Read Current at 5MHz

CE#=Vil,OE#=VihRP#=Vih

F_V

plus S_V

Standby Current

Vcc=Vcc(MAX)

F_V

Program Current

m A

F_V

Erase Current

F_V

/S_V

Erase Suspend Current

F_V

/S_V

Program Suspend

Current
Read-While-Write Current

S_V

Read/Write Operating

= V

or V

Supply Current Word Access

Chip Enabled, I

= 0

Mode

NOTE: 1. All currents are in RMS unless otherwise noted.

2. 12V V

is supported for a maximum of 100 cycles and may be connected for up to 10 cumulative hours.

3. Icc is dependent on cycle rates.
4. Operating current is a linear function of operating frequency and voltage. Operating current can be calculated using the

formula shown with operating frequency (f) expressed in MHz and operating voltage (V) in volts.
Example: When operating at 2 MHz at 2V, the device will draw a typical active current of 0.8*2* = 3.2mA in the page
access mode. This parameter is specified with the outputs disabled to avoid external loading effects. The user must
add current required to drive output capacitance expected in the actual system.

(continued on the next page)

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FLASH WRITE CYCLE TIMING REQUIREMENTS

-90

= 2.7V

3.3V

PARAMETER

SYMBOL

MIN

MAX

UNITS

Reset HIGH recovery to WE# going LOW

150

CE# setup to WE# going LOW

Write pulse width

Data setup to WE# going HIGH

Address setup to WE# going HIGH

CE# hold from WE# HIGH

Data hold from WE# HIGH

Address hold from WE# HIGH

Write pulse width HIGH

WPH

WP# setup to WE# going HIGH

WHS

setup to WE# going HIGH

VPS

200

OE# hold from WE# going HIGH

OHH

WP# hold from valid SRD

WHH

hold from valid SRD

VPH

WE# HIGH to busy status

200

WRITE duration

tWED1

Boot BLOCK ERASE duration

WED2

0.5

Parameter BLOCK ERASE duration

WED3

0.5

Main BLOCK ERASE duration

WED4

FLASH READ CYCLE TIMING REQUIREMENTS

-90

= 2.7V

3.3V

PARAMETER

SYMBOL

MIN

MAX

UNITS

Address to output delay

CE# LOW to output delay

ACE

OE# LOW to output delay

AOE

F_RP# HIGH to output delay

RWH

600

CE# or OE# HIGH to output High-Z

Output hold from address, CE# or OE# change

CE# HIGH between subsequent synchronous READs

CBPH

READ Cycle Time

FLASH ERASE AND PROGRAM CYCLE TIMING REQUIREMENTS

2.7V3.3V Vcc

1.65V3.3V V

12V V

PARAMETER

TYP

MAX

TYP

MAX

UNITS NOTES

Boot/parameter BLOCK ERASE time

0.5

Main BLOCK ERASE time

Boot/parameter BLOCK WRITE time

0.1

Main BLOCK WRITE time

0.3

Program/erase suspend latency

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WRITE/ERASE OPERATION

CE#

A0-A19

OE#

DQ0-DQ15

DON'T CARE

tWED1, 2, 3, 4

WE#

RP#

tRS

tCH

tCS

tOHH

PPH

tAS

tAH

tWP

tWPH

tDS

tDH

CMD

CMD/

Data-in

CMD

WRITE SETUP or

ERASE SETUP

input

WRITE or ERASE

executed, status register

checked for completion

Command for next

operation issued

tDH

tWB

tDS

WRITE or block

address asserted, and

WRITE data or ERASE

CONFIRM

Note 1

tAS

tAH

Status

(SR7=1)

Status

(SR7=0)

tVPS

tWHS

[Unlock soft-protected blocks]

WP#

tVPH

tWHH

TIMING PARAMETERS

-90

SYMBOL

MIN

UNITS

WPH

VPS

200

150

WED1

WED2

0.5

WED3

0.5

WED4

VPH

200

WHS

WHH

OHH

-90

SYMBOL

MIN

UNITS

SRAM

Stock No. 23134-A 1/01

Advance - Subject to Change without Notice

NanoAmp Solutions, Inc.

EM28C1602C3FL

Advance

SRAM OPERATING MODES

SRAM READ ARRAY

The operational state of the SRAM is determined by

S_CE1#, S_CE2, S_WE#, S_OE#, S_UB#, and S_LB#, as
indicated in the Truth Table. In order to perform an
SRAM READ operation, S_CE1#, and S_OE#, must be at
V

, and S_CE2 and S_WE# must be at V

. When in this

state, S_UB# and S_LB# control whether the lower byte
is read (S_UB# V

, S_LB# V

), the upper byte is read

(S_UB# V

, S_LB# V

), both upper and lower bytes are

read (S_UB# V

, S_LB# V

), or neither are read (S_UB#

, S_LB# V

) and the device is in a standby state.

While performing an SRAM READ operation, cur-

rent consumption may be reduced by reading within a
16-word page. This is done by holding S_CE1# and

SRAM FUNCTIONAL BLOCK DIAGRAM

S_OE# at V

, S_WE# and S_CE2 at V

, and toggling

addresses A0-A3. S_UB# and S_LB# control the data
width as described above.

SRAM WRITE ARRAY

In order to perform an SRAM WRITE operation,

S_CE1# and S_WE# must be at V

, and S_CE2 and

S_OE# must be at V

. When in this state, S_UB# and

S_LB# control whether the lower byte is written (S_UB#
V

, S_LB# V

), the upper byte is written (S_UB# V

S_LB# V

), both upper and lower bytes are written

(S_UB# V

, S_LB# V

), or neither are written (S_UB#

, S_LB# V

) and the device is in a standby state.

SRAM

Stock No. 23134-A 1/01

Advance - Subject to Change without Notice

NanoAmp Solutions, Inc.

EM28C1602C3FL

Advance

TIMING TEST CONDITIONS

Input pulse levels .................... 0.1V V

to 0.9V V

Input rise and fall times ....................................... 5ns
Input timing reference levels ............................. 0.5V
Output timing reference levels .......................... 0.5V
Operating Temperature ..................... -40

C to +85

SRAM READ CYCLE TIMING

DESCRIPTION

SYMBOL

M I N

M A X

UNITS

Read Cycle Time

Address Access Time

A A

Chip Enable to Valid Output

Output Enable to Valid Output

Byte Select to Valid Output

LB,

Chip Enable to Low-Z Output

Output Enable to Low-Z Output

OLZ

Byte Select to Low-Z Output

LBZ,

UBZ

Chip Enable to High-Z Output

Output Disable to High-Z Output

OHZ

Byte Select Disable to High-Z Output

LBHZ,

UBHZ

Output Hold from Address Change

SRAM WRITE CYCLE TIMING

DESCRIPTION

SYMBOL

M I N

M A X

UNITS

Write Cycle Time

Chip Enable to End of Write

Address Valid to End of Write

Byte Select to End of Write

LBW,

UBW

Address Setup Time

Write Pulse Width

Write Recovery Time

Write to High-Z Output

WHZ

Data to Write Time Overlap

Data Hold from Write Time

End Write to Low-Z Output

Stock No. 23134-A 1/01

EM28C1602C3FL

Advance

NanoAmp Solutions, Inc.

Advance - Subject to Change without Notice

66-BALL FBGA

TO P V IEW: Ba ll Down

A1 BALL
CORNER

SEATING PLAN E - Z
(Coplanarity)

A1 BALL
CORNER

BO TTOM V IEW : Ball Up

S IDE VIEW

FBGA PACKAGE DIMENSIONS

MIN

NOM

MAX

Package height A

1.20

1.30

1.40

Solder ball height (Standoff) A1

0.30

0.35

0.40

Package body thickness A2

0.92

0.97

1.02

Ball lead diameter b

0.325

0.40

0.475

Body length D

11.90

12.00

12.10

Body width E

7.90

8.00

8.10

Ball pitch e

0.80

Seating plane coplanarity Z

0.10

Corner to first bump distance S1

1.10

1.20

1.30

Corner to first bump distance S2

1.50

1.60

1.70

All dimensions in millimeters.
Solder ball material: 63% Sn, 37% Pb
Substrate: plastic laminate
Mold compound: epoxy novolac

Revision History

Revision #

Date

Description

January 2001

Preliminary Release

May 8, 2001

Updated ballout, removed -11

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