NT256D64S88AAG
256MB : 32M x 64
PC2100 / PC1600 Unbuffered DIMM
184pin One Bank
Unbuffered DDR SDRAM MODULE
Based on DDR266/200 32Mx8 SDRAM
Features
184-Pin Unbuffered 8-Byte Dual In-Line Memory Module
32Mx64 Double Data Rate (DDR) SDRAM DIMM
Performance:
PC1600
PC2100
Speed Sort
- 8B
- 75B
- 7K
DIMM CAS Latency
2
2.5
2
Unit
f
CK
Clock Frequency
100
133
133 MHz
t
CK
Clock Cycle
10
7.5
7.5
ns
f
DQ
DQ Burst Frequency
200
266
266
MHz
Intended for 100 MHz and 133 MHz applications
Inputs and outputs are SSTL-2 compatible
V
DD
= 2.5Volt
0.2, V
DDQ
= 2.5Volt 0.2
SDRAMs have 4 internal banks for concurrent operation
Module has one physical bank
Differential clock inputs
Data is read or written on both clock edges
DRAM D
LL
aligns DQ and DQS transitions with clock
transitions.
Address and control signals are fully synchronous to positive
clock edge
Programmable Operation:
- DIMM CAS Latency: 2, 2.5
- Burst Type: Sequential or Interleave
- Burst Length: 2, 4, 8
- Operation: Burst Read and Write
Auto-Refresh (CBR) and Self-Refresh Modes
Automatic and controlled precharge commands
13/10/1 Addressing (row/column/bank)
7.8
s Max. Average Periodic Refresh Interval
Serial Presence Detect
Gold contacts
SDRAMs in 66-pin TSOP Type II Package
Description
NT256D64S88AAG is an unbuffered 184-Pin Double Data Rate (DDR) Synchronous DRAM Dual In-Line Memory Module (DIMM),
organized as a one-bank high-speed memory array. The 32Mx64 module is a single-bank DIMM that uses eight 32Mx8 DDR
SDRAMs in 400 mil TSOP packages. The DIMM achieves high-speed data transfer rates of up to 266MHz. The DIMM is intended for use
in applications operating from 100 MHz to 133 MHz clock speeds with data rates of 200 to 266 MHz. Clock enable CKE0 controls all
devices on the DIMM.
Prior to any access operation, the device CAS latency and burst type/ length/operation type must be programmed into the DIMM by
address inputs A0-A12 and I/O inputs BA0 and BA1 using the mode register set cycle.
These DIMMs are manufactured using raw cards developed for broad industry use as reference designs. The use of these common
design files minimizes electrical variation between suppliers.
The DIMM uses serial presence detects implemented via a serial EEPROM using the two-pin IIC protocol. The first 128 bytes of serial PD
data are programmed and locked during module assembly. The last 128 bytes are available to the customer.
All NANYA 184 DDR SDRAM DIMMs provide a high-performance, flexible 8-byte interface in a 5.25" long space-saving footprint.
Ordering Information
Part Number
Speed Organization
Leads
Power
143MHz (7ns @ CL = 2.5)
NT256D64S88AAG-7K
133MHz (7.5ns @ CL= 2)
PC2100
133MHz (7.5ns @ CL= 2.5)
NT256D64S88AAG-75B
100MHz (10ns @ CL = 2)
PC2100
125MHz (8ns @ CL = 2.5)
NT256D64S88AAG-8B
100MHz (10ns @ CL = 2)
PC1600
32Mx64 Gold 2.5V
REV 1.1
1
08/2002
NANYA TECHNOLOGY CORP.
NANYA TECHNOLOGY CORP. reserves the right to change Products and Specifications without notice.
NT256D64S88AAG
256MB : 32M x 64
PC2100 / PC1600 Unbuffered DIMM
Pin Description
CK0, CK1, CK2,
CK0, CK1, CK2
Differential Clock Inputs
DQ0-DQ63
Data input/output
CKE0 Clock
Enable
RAS Row
Address
Strobe
DQS0-DQS7,
DQS9-DQS16
Bi-directional data strobes
CAS Column
Address
Strobe V
DD
Power
(2.5V)
WE Write
Enable V
DDQ
Supply voltage for DQs (2.5V)
S0 Chip
Selects V
SS
Ground
A0-A9, A11, A12
Address Inputs
NC
No Connect
A10/AP Address
Input/Auto-precharge
SCL Serial Presence Detect Clock Input
BA0, BA1
SDRAM Bank Address Inputs
SDA
Serial Presence Detect Data input/output
V
REF
Ref. Voltage for SSTL_2 inputs
SA0-2
Serial Presence Detect Address Inputs
V
DDID
V
DD
Identification flag.
V
DDSPD
Serial EEPROM positive power supply (2.5V)
Pinout
Pin Front Pin Back Pin Front Pin
Back Pin
Front Pin Back
1 V
REF
93 V
SS
32 A5 124
V
SS
62 V
DDQ
154 RAS
2 DQ0 94 DQ4 33 DQ24
125
A6 63 WE 155 DQ45
3 V
SS
95 DQ5 34 V
SS
126
DQ28 64 DQ41 156 V
DDQ
4 DQ1 96 V
DDQ
35 DQ25 127
DQ29 65 CAS 157 S0
5 DQS0 97 DQS9 36 DQS3 128
V
DDQ
66 V
SS
158 NC
6 DQ2 98 DQ6 37 A4 129
DQS12
67
DQS5
159
DQS14
7 V
DD
99 DQ7 38 V
DD
130
A3 68 DQ42 160 V
SS
8 DQ3
100 V
SS
39 DQ26 131
DQ30 69 DQ43 161 DQ46
9 NC
101 NC 40
DQ27
132
V
SS
70 V
DD
162 DQ47
10 NC 102 NC 41 A2 133
DQ31
71 NC 163 NC
11 V
SS
103 NC 42 V
SS
134
NC 72 DQ48 164 V
DDQ
12 DQ8 104 V
DDQ
43 A1 135
NC 73 DQ49 165 DQ52
13 DQ9 105 DQ12 44 NC 136
V
DDQ
74 V
SS
166 DQ53
14 DQS1 106 DQ13 45 NC 137
CK0 75 CK2 167 NC
15 V
DDQ
107 DQS10 46 V
DD
138
CK0 76 CK2 168 V
DD
16 CK1 108 V
DD
47 NC 139
V
SS
77 V
DDQ
169 DQS15
17
CK1 109 DQ14 48 A0 140
NC 78 DQS6 170 DQ54
18 V
SS
110 DQ15 49 NC 141
A10 79 DQ50 171 DQ55
19 DQ10 111 NC 50 V
SS
142
NC 80 DQ51 172 V
DDQ
20 DQ11 112 V
DDQ
51 NC 143
V
DDQ
81 V
SS
173 NC
21 CKE0 113 NC 52 BA1 144
NC 82 V
DDID
174 DQ60
22 V
DDQ
114 DQ20
KEY
KEY
83 DQ56 175 DQ61
23 DQ16 115 A12 53 DQ32 145
V
SS
84 DQ57
176 V
SS
24 DQ17 116 V
SS
54 V
DDQ
146
DQ36 85 V
DD
177
DQS16
25 DQS2 117 DQ21 55 DQ33 147
DQ37 86 DQS7 178 DQ62
26 V
SS
118 A11 56 DQS4 148
V
DD
87 DQ58
179
DQ63
27 A9 119 DQS11 57 DQ34 149
DQS13 88 DQ59 180 V
DDQ
28 DQ18 120 V
DD
58 V
SS
150
DQ38 89 V
SS
181 SA0
29 A7 121 DQ22 59 BA0 151
DQ39 90 NC 182 SA1
30 V
DDQ
122 A8 60 DQ35 152
V
SS
91 SDA 183 SA2
31 DQ19 123 DQ23 61 DQ40 153
DQ44 92 SCL 184
V
DDSPD
Note: All pin assignments are consistent for all 8-byte unbuffered versions.
REV 1.1
2
08/2002
NANYA TECHNOLOGY CORP.
NANYA TECHNOLOGY CORP. reserves the right to change Products and Specifications without notice.
NT256D64S88AAG
256MB : 32M x 64
PC2100 / PC1600 Unbuffered DIMM
Input/Output Functional Description
Symbol
Type
Polarity
Function
CK0, CK1, CK2
(SSTL)
Positive
Edge
The positive line of the differential pair of system clock inputs. All the DDR SDRAM
address and control inputs are sampled on the rising edge of their associated clocks.
CK0, CK1, CK2 (SSTL)
Negative
Edge
The negative line of the differential pair of system clock inputs.
CKE0
(SSTL)
Active
High
Activates the SDRAM CK signal when high and deactivates the CK signal when low. By
deactivating the clocks, CKE low initiates the Power Down mode, or the Self-Refresh
mode.
S0
(SSTL)
Active
Low
Enables the associated SDRAM command decoder when low and disables the command
decoder when high. When the command decoder is disabled, new commands are ignored
but previous operations continue.
RAS, CAS, WE
(SSTL)
Active
Low
When sampled at the positive rising edge of the clock, RAS, CAS, WE define the operation
to be executed by the SDRAM.
V
REF
Supply
Reference voltage for SSTL-2 inputs
V
DDQ
Supply
Isolated power supply for the DDR SDRAM output buffers to provide improved noise
immunity
BA0, BA1
(SSTL)
-
Selects which SDRAM bank is to be active.
A0 - A9
A10/AP
A11, A12
(SSTL)
-
During a Bank Activate command cycle, A0-A12 defines the row address (RA0-RA12)
when sampled at the rising clock edge.
During a Read or Write command cycle, A0-A9 defines the column address (CA0-CA9)
when sampled at the rising clock edge. In addition to the column address, AP is used to
invoke Auto-precharge operation at the end of the Burst Read or Write cycle. If AP is high,
auto-precharge is selected and BA0/BA1 define the bank to be precharged. If AP is low,
auto-precharge is disabled.
During a Precharge command cycle, AP is used in conjunction with BA0/BA1 to control
which bank(s) to precharge. If AP is high all 4 banks will be precharged regardless of the
state of BA0/BA1. If AP is low, then BA0/BA1 are used to define which bank to pre-charge.
DQ0 - DQ63
(SSTL)
-
Data and Check Bit input/output pins operate in the same manner as on conventional
DRAMs.
DQS0 - DQS7
DQS9 - DQS16
(SSTL)
Active
High
Data strobes: Output with read data, input with write data. Edge aligned with read data,
centered on write data. Used to capture write data.
V
DD,
V
SS
Supply
Power and ground for the DDR SDRAM input buffers and core logic
SA0 SA2
-
Address inputs. Connected to either V
DD
or V
SS
on the system board to configure the
Serial Presence Detect EEPROM address.
SDA
-
This bi-directional pin is used to transfer data into or out of the SPD EEPROM. A resistor
must be connected from the SDA bus line to V
DD
to act as a pullup.
SCL
-
This signal is used to clock data into and out of the SPD EEPROM. A resistor may be
connected from the SCL bus time to V
DD
to act as a pullup.
V
DDSPD
Supply
Serial EEPROM positive power supply.
REV 1.1
3
08/2002
NANYA TECHNOLOGY CORP.
NANYA TECHNOLOGY CORP. reserves the right to change Products and Specifications without notice.
NT256D64S88AAG
256MB : 32M x 64
PC2100 / PC1600 Unbuffered DIMM
Functional Block Diagram
(1 Bank, 32Mx8 DDR SDRAMs)
Serial PD
A0
A2
A1
SCL
WP
SDA
SA0
SA2
SA1
A0-A13
RAS
BA0-BA1
BA0-BA1 : SDRAMs D0-D7
A0-A13 : SDRAMs D0-D7
RAS : SDRAMs D0-D7
CKE0
CAS
CAS : SDRAMs D0-D7
CKE : SDRAMs D0-D7
WE
WE : SDRAMs D0-D7
V
DDSPD
V
SS
V
REF
V
DDID
V
DD
/V
DDQ
Strap: see Note 4
SPD
D0-D7
D0-D7
D0-D7
S0
DQS9
DQ0
DQ1
DQ2
DQ7
DQ4
DQ6
DQ5
DQ3
DQ8
DQ9
DQ10
DQ15
DQ12
DQ14
DQ13
DQ11
DQ16
DQ17
DQ18
DQ23
DQ20
DQ22
DQ21
DQ19
DQ24
DQ25
DQ26
DQ31
DQ28
DQ30
DQ29
DQ27
I/O 7
I/O 6
I/O 3
I/O 4
I/O 5
I/O 0
I/O 1
I/O 2
DM
CS
D3
I/O 7
I/O 6
I/O 3
I/O 4
I/O 5
I/O 0
I/O 1
I/O 2
DM
CS
D2
I/O 7
I/O 6
I/O 3
I/O 4
I/O 5
I/O 0
I/O 1
I/O 2
DM
CS
D4
DQS0
DQS13
DQS4
DQS
I/O 7
I/O 6
I/O 3
I/O 4
I/O 5
I/O 0
I/O 1
I/O 2
DM
CS
D0
DQS
DQS10
DQS1
DQS
DQS11
DQS2
DQS12
DQS3
DQS
DQ32
DQ33
DQ34
DQ39
DQ36
DQ38
DQ37
DQ35
DQ40
DQ41
DQ42
DQ47
DQ44
DQ46
DQ45
DQ43
I/O 7
I/O 6
I/O 3
I/O 4
I/O 5
I/O 0
I/O 1
I/O 2
DM
CS
D1
DQS
I/O 7
I/O 6
I/O 3
I/O 4
I/O 5
I/O 0
I/O 1
I/O 2
DM
CS
D5
DQS
DQS5
DQS14
DQ48
DQ49
DQ50
DQ55
DQ52
DQ54
DQ53
DQ51
I/O 7
I/O 6
I/O 3
I/O 4
I/O 5
I/O 0
I/O 1
I/O 2
DM
CS
D6
DQS
DQ56
DQ57
DQ58
DQ63
DQ60
DQ62
DQ61
DQ59
I/O 7
I/O 6
I/O 3
I/O 4
I/O 5
I/O 0
I/O 1
I/O 2
DM
CS
D7
DQS
DQS6
DQS15
DQS7
DQS16
* Wire per Clock Loading Table/
Wiring Diagrams
* Clock Wiring
Clock Input
SDRAMs
*CK0/CK0
*CK1/CK1
*CK2/CK2
2 SDRAMs
3 SDRAMs
3 SDRAMs
Notes :
1. DQ-to-I/O wiring is shown as recommended but may be changed.
2. DQ/DQS/DM/CKE/S relationships must be maintained as shown.
3. DQ, DQS, DM/DQS resistors: 22 Ohms.
4. V
DDID
strap connections (for memory device V
DD
, V
DDQ
):
STRAP OUT (OPEN): V
DD
= V
DDQ
STRAP IN (V
SS
): V
DD
is not equal to V
DDQ
.
REV 1.1
4
08/2002
NANYA TECHNOLOGY CORP.
NANYA TECHNOLOGY CORP. reserves the right to change Products and Specifications without notice.
NT256D64S88AAG
256MB : 32M x 64
PC2100 / PC1600 Unbuffered DIMM
Serial Presence Detect --
Part 1 of 2
32Mx64 SDRAM DIMM based on 32Mx8, 4Banks, 8K Refresh, 2.5V DDR SDRAMs with SPD
SPD Entry Value
Serial PD Data Entry (Hexadecimal) Note
Byte
Description
DDR266A
-7K
DDR266B
-75B
DDR200
-8B
DDR266A
-7K
DDR266B
-75B
DDR200
-8B
0
Number of Serial PD Bytes Written during
Production
128 80
1
Total Number of Bytes in Serial PD device
256
08
2
Fundamental Memory Type
SDRAM DDR
07
3
Number of Row Addresses on Assembly
13
0D
4
Number of Column Addresses on Assembly
10
0A
5
Number of DIMM Bank
1
01
6
Data Width of Assembly
X64
40
7
Data Width of Assembly (cont')
X64
00
8
Voltage Interface Level of this Assembly
SSTL 2.5V
04
9
DDR SDRAM Device Cycle Time at CL=2.5
7ns
7.5ns
8ns
70
75
80
10
DDR SDRAM Device Access Time from
Clock at CL=2.5
0.75ns
0.75ns
0.8ns
75 75 80
11 DIMM
Configuration
Type
Non-Parity
00
12 Refresh
Rate/Type
SR/1x(7.8
s) 82
13
Primary DDR SDRAM Width
X8
08
14
Error Checking DDR SDRAM Device Width
N/A
00
15
DDR SDRAM Device Attr: Min CLk Delay,
Random Col Access
1 Clock
01
16
DDR SDRAM Device Attributes:
Burst Length Supported
2,4,8 0E
17
DDR SDRAM Device Attributes: Number of
Device Banks
4 04
18
DDR SDRAM Device Attributes: CAS
Latencies Supported
2/2.5 2/2.5 2/2.5 0C 0C 0C
19
DDR SDRAM Device Attributes: CS Latency
0
01
20
DDR SDRAM Device Attributes: WE Latency
1
02
21 DDR
SDRAM
Device
Attributes: Differential
Clock
20
22
DDR SDRAM Device Attributes: General
+/-0.2V Voltage Tolerance
00
23
Minimum Clock Cycle at CL=2
7.5ns
10ns
10ns
75
A0
A0
24
Maximum Data Access Time from Clock at
CL=2
0.75ns
0.75ns
0.8ns
75 75 80
25
Minimum Clock Cycle Time at CL=1
N/A
00
26
Maximum Data Access Time from Clock at
CL=1
N/A 00
27
Minimum Row Precharge Time (t
RP
)
20ns 20ns 20ns 50 50 50
28
Minimum Row Active to Row Active delay
(t
RRD
)
15ns 15ns 15ns 3C 3C 3C
29
Minimum RAS to CAS delay (t
RCD
)
20ns 20ns 20ns 50 50 50
30
Minimum RAS Pulse Width (t
RAS
)
45ns 45ns 50ns 2D 2D 32
31
Module Bank Density
256MB
40
32
Address and Command Setup Time Before
Clock
0.9ns 0.9ns 1.1ns 90
90
B0
33
Address and Command Hold Time After
Clock
0.9ns 0.9ns 1.1ns 90
90
B0
34
Data Input Setup Time Before Clock
0.5ns
0.5ns
0.6ns
50
50
60
35
Data Input Hold Time After Clock
0.5ns
0.5ns
0.6ns
50
50
60
36-61 Reserved
Undefined
00
62
SPD
Revision
Initial Initial Initial 00
00
00
63
Checksum
Data
8F
BF
45
REV 1.1
5
08/2002
NANYA TECHNOLOGY CORP.
NANYA TECHNOLOGY CORP. reserves the right to change Products and Specifications without notice.
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