NT256D64S88AMGM
256MB : 32M x 64
PC2100 / PC1600 Unbuffered DDR SO-DIMM
200pin One Bank
Unbuffered DDR SO-DIMM
Based on DDR266/200 32Mx8 SDRAM
Features
JEDEC Standard 200-Pin Small Outline Dual In-Line Memory
Module (SO-DIMM)
32Mx64 Double Unbuffered DDR SO-DIMM based on 32Mx8
DDR SDRAM.
Performance:
PC1600
PC2100
Speed Sort
- 8B
- 75B
- 7K
DIMM CAS Latency
2
2.5
2
Unit
f
CK
Clock Frequency
100
133
133 MHz
t
CK
Clock Cycle
10
7.5
7.5
ns
f
DQ
DQ Burst Frequency
200
266
266
MHz
Intended for 100 MHz and 133 MHz applications
Inputs and outputs are SSTL-2 compatible
V
DD
= 2.5Volt
0.2, V
DDQ
= 2.5Volt 0.2
SDRAMs have 4 internal banks for concurrent operation
Module has one physical bank
Differential clock inputs
Data is read or written on both clock edges
DRAM D
LL
aligns DQ and DQS transitions with clock
transitions.
Address and control signals are fully synchronous to positive
clock edge
Programmable Operation:
- DIMM CAS Latency: 2, 2.5
- Burst Type: Sequential or Interleave
- Burst Length: 2, 4, 8
- Operation: Burst Read and Write
Auto-Refresh (CBR) and Self-Refresh Modes
Automatic and controlled precharge commands
13/10/1 Addressing (row/column/bank)
7.8
s Max. Average Periodic Refresh Interval
Serial Presence Detect
Gold contacts
SDRAMs in 66-pin TSOP Type II Package
Description
NT256D64S88AMGM is an unbuffered 200-Pin Double Data Rate (DDR) Synchronous DRAM Dual In-Line Memory Module (DIMM),
organized as a one-bank high-speed memory array. The 32Mx64 module is a single-bank DIMM that uses eight 32Mx8 DDR
SDRAMs in 400 mil TSOP packages. The DIMM achieves high-speed data transfer rates of up to 266MHz. The DIMM is intended for use
in applications operating from 100 MHz to 133 MHz clock speeds with data rates of 200 to 266 MHz. Clock enable CKE0 controls all
devices on the DIMM.
Prior to any access operation, the device CAS latency and burst type/ length/operation type must be programmed into the DIMM by
address inputs A0-A12 and I/O inputs BA0 and BA1 using the mode register set cycle.
These DIMMs are manufactured using raw cards developed for broad industry use as reference designs. The use of these common
design files minimizes electrical variation between suppliers.
The DIMM uses serial presence detects implemented via a serial EEPROM using the two-pin IIC protocol. The first 128 bytes of serial PD
data are programmed and locked during module assembly. The last 128 bytes are available to the customer.
All NANYA 200pin DDR SO-DIMMs provide a high-performance, flexible 8-byte interface in a 2.66" long space-saving footprint.
Ordering Information
Part Number
Speed Organization
Leads
Power
143MHz (7ns @ CL = 2.5)
NT256D64S88AMGM-7K
133MHz (7.5ns @ CL= 2)
PC2100
133MHz (7.5ns @ CL= 2.5)
NT256D64S88AMGM-75B
100MHz (10ns @ CL = 2)
PC2100
125MHz (8ns @ CL = 2.5)
NT256D64S88AMGM-8B
100MHz (10ns @ CL = 2)
PC1600
32Mx64 Gold 2.5V
REV 1.1
1
08/2002
NANYA TECHNOLOGY CORP.
NANYA TECHNOLOGY CORP. reserves the right to change Products and Specifications without notice.
NT256D64S88AMGM
256MB : 32M x 64
PC2100 / PC1600 Unbuffered DDR SO-DIMM
Pin Description
CK0, CK1,
CK0, CK1
Differential Clock Inputs
DQ0-DQ63
Data input/output
CKE0 Clock
Enable
DQS0-DQS7
Bi-directional data strobes
RAS
Row Address Strobe
DM0-DM7 Data
Masks
CAS
Column Address Strobe
V
DD
Power
(2.5V)
WE
Write Enable
V
DDQ
Supply voltage for DQs (2.5V)
S0
Chip Selects
V
SS
Ground
A0-A9, A11, A12
Address Inputs
NC
No Connect
A10/AP Address
Input/Auto-precharge
SCL Serial Presence Detect Clock Input
BA0, BA1
SDRAM Bank Address Inputs
SDA
Serial Presence Detect Data input/output
V
REF
Ref. Voltage for SSTL_2 inputs
SA0-2
Serial Presence Detect Address Inputs
V
DDID
V
DD
Identification flag.
V
DDSPD
Serial EEPROM positive power supply (2.5V)
Pinout
Pin Front Pin Back Pin Front Pin
Back Pin
Front
Pin
Back
Pin Front Pin
Back
1 V
REF
2 V
REF
51 V
SS
52
V
SS
101
A9 102
A8 151 DQ42 152
DQ46
3 V
SS
4 V
SS
53 DQ19 54
DQ23
103
V
SS
104
V
SS
153 DQ43 154
DQ47
5 DQ0 6 DQ4 55 DQ24 56
DQ28
105
A7 106
A6
155 V
DD
156
V
DD
7 DQ1 8 DQ5 57 V
DD
58
V
DD
107
A5 108
A4 157 V
DD
158
CK1
9 V
DD
10 V
DD
59 DQ25 60
DQ29
109
A3 110
A2 159 V
SS
160
CK1
11 DQS0 12 DM0 61 DQS3 62
DM3 111
A1 112
A0 161 V
SS
162
V
SS
13 DQ2 14 DQ6 63 V
SS
64
V
SS
113
V
DD
114
V
DD
163 DQ48 164
DQ52
15 V
SS
16 V
SS
65 DQ26 66
DQ30
115
A10/AP
116
BA1
165
DQ49
166
DQ53
17 DQ3 18 DQ7 67 DQ27 68
DQ31
117
V
DD
118
RAS
167 V
DD
168
V
DD
19 DQ8 20 DQ12 69 V
DD
70
V
DD
119
WE 120
CAS
169 DQS6 170
DM6
21 V
DD
22 V
DD
71 NC 72
NC 121
S0 122
DU
171
DQ50
172
DQ54
23 DQ9
24 DQ13 73 NC 74
NC 123
DU 124
DU
173 V
SS
174
V
SS
25 DQS1 26 DM1 75 V
SS
76
V
SS
125
V
SS
126
V
SS
175 DQ51 176
DQ55
27 V
SS
28 V
SS
77 NC 78
NC 127
DQ32
128
DQ36
177
DQ56
178
DQ60
29 DQ10 30 DQ14 79 NC 80
NC 129
DQ33
130
DQ37
179 V
DD
180
V
DD
31 DQ11 32 DQ15 81 V
DD
82
V
DD
131
V
DD
132
V
DD
181 DQ57 182
DQ61
33 V
DD
34 V
DD
83 NC 84
NC 133
DQS4
134
DM4
183
DQS7
184
DM7
35 CK0 36 V
DD
85 DU 86
DU 135
DQ34
136
DQ38
185 V
SS
186
V
SS
37
CK0 38 V
SS
87 V
SS
88
V
SS
137
V
SS
138
V
SS
187 DQ58 188
DQ62
39 V
SS
40 V
SS
89 NC 90
V
SS
139
DQ35
140
DQ39
189 DQ59 190
DQ63
41 DQ16 42 DQ20 91 NC 92
V
DD
141
DQ40
142
DQ44
191 V
DD
192
V
DD
43 DQ17 44 DQ21 93 V
DD
94
V
DD
143
V
DD
144
V
DD
193 SDA 194
SA0
45 V
DD
46 V
DD
95 CKE1 96
CKE0
145
DQ41
146
DQ45
195 SCL 196
SA1
47 DQS2 48 DM2 97 NC 98
DU 147
DQS5
148
DM5
197
V
DDSPD
198
SA2
49 DQ18 50 DQ22 99 NC 100
A11 149
V
SS
150
V
SS
199 V
DDID
200
DU
Note: All pin assignments are consistent for all 8-byte unbuffered versions.
REV 1.1
2
08/2002
NANYA TECHNOLOGY CORP.
NANYA TECHNOLOGY CORP. reserves the right to change Products and Specifications without notice.
NT256D64S88AMGM
256MB : 32M x 64
PC2100 / PC1600 Unbuffered DDR SO-DIMM
Input/Output Functional Description
Symbol
Type
Polarity
Function
CK0, CK1
(SSTL)
Positive
Edge
The positive line of the differential pair of system clock inputs. All the DDR SDRAM
address and control inputs are sampled on the rising edge of their associated clocks.
CK0, CK1 (SSTL)
Negative
Edge
The negative line of the differential pair of system clock inputs.
CKE0
(SSTL)
Active
High
Activates the SDRAM CK signal when high and deactivates the CK signal when low. By
deactivating the clocks, CKE low initiates the Power Down mode, or the Self-Refresh
mode.
S0
(SSTL)
Active
Low
Enables the associated SDRAM command decoder when low and disables the command
decoder when high. When the command decoder is disabled, new commands are ignored
but previous operations continue.
RAS
,
CAS
,
WE
(SSTL)
Active
Low
When sampled at the positive rising edge of the clock, RAS
,
CAS
,
WE define the operation
to be executed by the SDRAM.
V
REF
Supply
Reference voltage for SSTL-2 inputs
V
DDQ
Supply
Isolated power supply for the DDR SDRAM output buffers to provide improved noise
immunity
BA0, BA1
(SSTL)
-
Selects which SDRAM bank is to be active.
A0 - A9
A10/AP
A11, A12
(SSTL)
-
During a Bank Activate command cycle, A0-A12 defines the row address (RA0-RA12)
when sampled at the rising clock edge.
During a Read or Write command cycle, A0-A9 defines the column address (CA0-CA9)
when sampled at the rising clock edge. In addition to the column address, AP is used to
invoke Auto-precharge operation at the end of the Burst Read or Write cycle. If AP is high,
auto-precharge is selected and BA0/BA1 define the bank to be precharged. If AP is low,
auto-precharge is disabled.
During a Precharge command cycle, AP is used in conjunction with BA0/BA1 to control
which bank(s) to precharge. If AP is high all 4 banks will be precharged regardless of the
state of BA0/BA1. If AP is low, then BA0/BA1 are used to define which bank to pre-charge.
DQ0 - DQ63,
(SSTL)
-
Data and Check Bit input/output pins operate in the same manner as on conventional
DRAMs.
DQS0 - DQS7
(SSTL)
Active
High
Data strobes: Output with read data, input with write data. Edge aligned with read data,
centered on write data. Used to capture write data.
DM0 DM7
Input
Active
High
The data write masks, associated with one data byte. In Write mode, DM operates as a
byte mask by allowing input data to be written if it is low but blocks the write operation if it
is high. In Read mode, DM lines have no effect. DM8 is associated with check bits
CB0-CB7, and is not used on x64 modules.
V
DD,
V
SS
Supply
Power and ground for the DDR SDRAM input buffers and core logic
SA0 SA2
-
Address inputs. Connected to either V
DD
or V
SS
on the system board to configure the
Serial Presence Detect EEPROM address.
SDA
-
This bi-directional pin is used to transfer data into or out of the SPD EEPROM. A resistor
must be connected from the SDA bus line to V
DD
to act as a pullup.
SCL
-
This signal is used to clock data into and out of the SPD EEPROM. A resistor may be
connected from the SCL bus time to V
DD
to act as a pullup.
V
DDSPD
Supply
Serial EEPROM positive power supply.
REV 1.1
3
08/2002
NANYA TECHNOLOGY CORP.
NANYA TECHNOLOGY CORP. reserves the right to change Products and Specifications without notice.
NT256D64S88AMGM
256MB : 32M x 64
PC2100 / PC1600 Unbuffered DDR SO-DIMM
Functional Block Diagram
(1 Bank, 32Mx8 DDR SDRAMs)
V
DDSPD
V
SS
V
REF
V
DDID
V
DD
/V
DDQ
Strap: see Note 4
SPD
D0-D7
D0-D7
D0-D7
Serial PD
A0
A2
A1
SCL
WP
SDA
SA0
SA2
SA1
S0
DM0
DQ0
DQ1
DQ2
DQ7
DQ4
DQ6
DQ5
DQ3
DQ8
DQ9
DQ10
DQ15
DQ12
DQ14
DQ13
DQ11
DQ16
DQ17
DQ18
DQ23
DQ20
DQ22
DQ21
DQ19
DQ24
DQ25
DQ26
DQ31
DQ28
DQ30
DQ29
DQ27
I/O 0
I/O 1
I/O 6
I/O 5
I/O 4
I/O 3
I/O 2
I/O 7
DM
CS
D3
I/O 0
I/O 1
I/O 6
I/O 5
I/O 4
I/O 3
I/O 2
I/O 7
DM
CS
D2
I/O 0
I/O 1
I/O 6
I/O 5
I/O 4
I/O 3
I/O 2
I/O 7
DM
CS
D4
DQS0
DM4
DQS4
DQS
I/O 0
I/O 1
I/O 6
I/O 5
I/O 4
I/O 3
I/O 2
I/O 7
DM
CS
D0
DQS
DM1
DQS1
DQS
DM2
DQS2
DM3
DQS3
DQS
DQ32
DQ33
DQ34
DQ39
DQ36
DQ38
DQ37
DQ35
DQ40
DQ41
DQ42
DQ47
DQ44
DQ46
DQ45
DQ43
I/O 0
I/O 1
I/O 6
I/O 5
I/O 4
I/O 3
I/O 2
I/O 7
DM
CS
D1
DQS
I/O 0
I/O 1
I/O 6
I/O 5
I/O 4
I/O 3
I/O 2
I/O 7
DM
CS
D5
DQS
DQS5
DM5
DQ48
DQ49
DQ50
DQ55
DQ52
DQ54
DQ53
DQ51
I/O 0
I/O 1
I/O 6
I/O 5
I/O 4
I/O 3
I/O 2
I/O 7
DM
CS
D6
DQS
DQ56
DQ57
DQ58
DQ63
DQ60
DQ62
DQ61
DQ59
I/O 0
I/O 1
I/O 6
I/O 5
I/O 4
I/O 3
I/O 2
I/O 7
DM
CS
D7
DQS
DQS6
DM6
DQS7
DM7
A0-A12
RAS
BA0-BA1
BA0-BA1 : SDRAMs D0-D7
A0-A12 : SDRAMs D0-D7
RAS : SDRAMs D0-D7
CKE0
CAS
CAS : SDRAMs D0-D7
CKE : SDRAMs D0-D7
WE
WE : SDRAMs D0-D7
120 ohm
SDRAM x 4
CK0
CK0
120 ohm
SDRAM x 4
CK1
CK1
120 ohm
SDRAM x 0
CK2
CK2
Notes :
1. DQ-to-I/O wring may be changed within a byte.
2. DQ/DQS/DM/CKE/S relationships are maintained as shown.
3. DQ/DQS/DM/DQS resistors are 22 Ohms.
4. V
DDID
strap connections (for memory device V
DD
, V
DDQ
):
STRAP OUT (OPEN): V
DD
= V
DDQ
STRAP IN (V
SS
): V
DD
is not equal to V
DDQ
.
REV 1.1
4
08/2002
NANYA TECHNOLOGY CORP.
NANYA TECHNOLOGY CORP. reserves the right to change Products and Specifications without notice.
NT256D64S88AMGM
256MB : 32M x 64
PC2100 / PC1600 Unbuffered DDR SO-DIMM
Serial Presence Detect --
Part 1 of 2
32Mx64 SDRAM DIMM based on 32Mx8, 4Banks, 8K Refresh, 2.5V DDR SDRAMs with SPD
REV 1.1
5
08/2002
NANYA TECHNOLOGY CORP.
NANYA TECHNOLOGY CORP. reserves the right to change Products and Specifications without notice.
SPD Entry Value
Serial PD Data Entry (Hexadecimal) Note
Byte
Description
DDR266A
-7K
DDR266B
-75B
DDR200
-8B
DDR266A
-7K
DDR266B
-75B
DDR200
-8B
0
Number of Serial PD Bytes Written during
Production
128 80
1
Total Number of Bytes in Serial PD device
256
08
2
Fundamental Memory Type
SDRAM DDR
07
3
Number of Row Addresses on Assembly
13
0D
4
Number of Column Addresses on Assembly
10
0A
5
Number of DIMM Bank
1
01
6
Data Width of Assembly
X64
40
7
Data Width of Assembly (cont')
X64
00
8
Voltage Interface Level of this Assembly
SSTL 2.5V
04
9
DDR SDRAM Device Cycle Time at CL=2.5
7ns
7.5ns
8ns
70
75
80
10
DDR SDRAM Device Access Time from
Clock at CL=2.5
0.75ns
0.75ns
0.8ns
75 75 80
11 DIMM
Configuration
Type
Non-Parity
00
12 Refresh
Rate/Type
SR/1x(7.8us)
82
13
Primary DDR SDRAM Width
X8
08
14
Error Checking DDR SDRAM Device Width
N/A
00
15
DDR SDRAM Device Attr: Min CLk Delay,
Random Col Access
1 Clock
01
16
DDR SDRAM Device Attributes:
Burst Length Supported
2,4,8 0E
17
DDR SDRAM Device Attributes: Number of
Device Banks
4 04
18
DDR SDRAM Device Attributes: CAS
Latencies Supported
2/2.5 2/2.5 2/2.5 0C 0C 0C
19
DDR SDRAM Device Attributes: CS Latency
0
01
20
DDR SDRAM Device Attributes: WE Latency
1
02
21 DDR
SDRAM
Device
Attributes: Differential
Clock
20
22
DDR SDRAM Device Attributes: General
+/-0.2V Voltage Tolerance
00
23
Minimum Clock Cycle at CL=2
7.5ns
10ns
10ns
75
A0
A0
24
Maximum Data Access Time from Clock at
CL=2
0.75ns
0.75ns
0.8ns
75 75 80
25
Minimum Clock Cycle Time at CL=1
N/A
00
26
Maximum Data Access Time from Clock at
CL=1
N/A 00
27
Minimum Row Precharge Time(t
RP
)
20ns 20ns 20ns 50 50 50
28
Minimum Row Active to Row Active delay
(t
RRD
)
15ns 15ns 15ns 3C 3C 3C
29
Minimum RAS to CAS delay (t
RCD
)
20ns 20ns 20ns 50 50 50
30
Minimum RAS Pulse Width (t
RAS
)
45ns 45ns 50ns 2D 2D 32
31
Module Bank Density
256MB
40
32
Address and Command Setup Time Before
Clock
0.9ns 0.9ns 1.1ns 90
90
B0
33
Address and Command Hold Time After
Clock
0.9ns 0.9ns 1.1ns 90
90
B0
34
Data Input Setup Time Before Clock
0.5ns
0.5ns
0.6ns
50
50
60
35
Data Input Hold Time After Clock
0.5ns
0.5ns
0.6ns
50
50
60
36-61 Reserved
Undefined
00
62
SPD
Revision
Initial Initial Initial 00
00
00
63
Checksum
Data
8F
BF
45
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