NT512D64S8HBAFM

512MB : 64M x 64
PC2700 / PC2100 Unbuffered DDR SO-DIMM

REV 1.1

07/2003

© NANYA TECHNOLOGY CORP.

NANYA TECHNOLOGY CORP. reserves the right to change Products and Specifications without notice.

200pin Unbuffered DDR SO-DIMM

Based on DDR333/266 32Mx8 SDRAM

Features

· 200-Pin Small Outline Dual In-Line Memory Module (SO-DIMM)
· 64Mx64 Double Unbuffered DDR SO-DIMM based on 32Mx8
DDR SDRAM.
· Performance:

PC2700 PC2100

Speed Sort

-6K

-75B

DIMM

CAS

Latency

2.5

Unit

Clock Frequency

166

133

MHz

Clock Cycle

7.5

DQ Burst Frequency

333

266

MHz

· Intended for 133 MHz and 166 MHz applications

· Inputs and outputs are SSTL-2 compatible
· V

= 2.5Volt ±

0.2, V

DDQ

= 2.5Volt ± 0.2

· SDRAMs have 4 internal banks for concurrent operation
· Module has two physical bank s

· Differential clock inputs
· Data is read or written on both clock edges

· DRAM DLL aligns DQ and DQS transitions with clock

transitions.

· Address and control signals are fully synchronous to positive

clock edge

· Programmable Operation:

- DIMM

CAS

Latency: 2, 2.5

- Burst Type: Sequential or Interleave
- Burst Length: 2, 4, 8
- Operation: Burst Read and Write

· Auto Refresh (CBR) and Self Refresh Modes
· Automatic and controlled precharge commands
· 13/10/2 Addressing (row/column/bank)
· 7.8

s Max. Average Periodic Refresh Interval

· Serial Presence Detect
· Gold contacts
· SDRAMs in 60-ball CSP Package

Description

NT512D64S8HBAFM is an unbuffered 200-Pin Double Data Rate (DDR) Synchronous DRAM Small Outline Dual In-Line Memory Module

(SO-DIMM), organized as a two-bank 64Mx64 high-speed memory array. The module uses sixteen 32Mx8 DDR SDRAMs in 60-ball CSP

packages. All NANYA DDR SDRAM DIMMs provide a high-performance, flexible 8-byte interface in a 2.66" long space-saving footprint.

The DIMM is intended for use in applications operating up to 166 MHz clock speeds and achieves high-speed data transfer rates of up to

333 MHz. Prior to any access operation, the device

CAS

latency and burst type/ length/operation type must be programmed into the

DIMM by address inputs A0-A12 and I/O inputs BA0 and BA1 using the mode register set cycle.

The DIMM uses serial presence-detect implemented via a serial 2,048-bit EEPROM using a standard IIC protocol. The first 128 bytes of

serial PD data are programmed and locked during module assembly. The remaining 128 bytes are available for use by the customer.

Ordering Information

Part Number

Speed

Organization

Leads

Power

166MHz (6ns @ CL = 2.5)

NT512D64S8HBAFM-6K

133MHz (7.5ns @ CL = 2)

DDR333

PC2700

133MHz (7.5ns @ CL = 2.5)

NT512D64S8HBAFM-75B

100MHz (10ns @ CL = 2)

DDR266B

PC2100

64Mx64

Gold

2.5V

NT512D64S8HBAFM

512MB : 64M x 64
PC2700 / PC2100 Unbuffered DDR SO-DIMM

REV 1.1

07/2003

© NANYA TECHNOLOGY CORP.

NANYA TECHNOLOGY CORP. reserves the right to change Products and Specifications without notice.

Pin Description

CK0, CK1, CK2,

CK0

CK1

CK2

Differential Clock Inputs.

DQ0-DQ63

Data input/output

CKE0, CKE1

Clock Enable

RAS

Row Address Strobe

DQS0-DQS7,

DQS9-DQS16

Bidirectional data strobes

CAS

Column Address Strobe

Power (2.5V)

Write Enable

DDQ

Supply voltage for DQs (2.5V)

Chip Selects

Ground

A0-A9, A11, A12

Address Inputs

No Connect

A10/AP

Address Input/Aut oprecharge

SCL

Serial Presence Detect Clock Input

BA0, BA1

SDRAM Bank Address Inputs

SDA

Serial Presence Detect Data input/output

REF

Ref. Voltage for SSTL_2 inputs

SA0-2

Serial Presence Detect Address Inputs

DDID

Identification flag.

DDSPD

Serial EEPROM positive power supply (2.5V)

Pinout

Front

Back

Front

Back

Front

Back

Front

Back

REF

101

102

151

DQ42

152

DQ46

DQ19

DQ23

103

104

153

DQ43

154

DQ47

DQ0

DQ4

DQ24

DQ28

105

106

155

156

DQ1

DQ5

107

108

157

158

CK1

DQ25

DQ29

109

110

159

160

CK1

DQS0

DM0

DQS3

DM3

111

112

161

162

DQ2

DQ6

113

114

163

DQ48

164

DQ52

DQ26

DQ30

115 A10/AP

116

BA1

165

DQ49

166

DQ53

DQ3

DQ7

DQ27

DQ31

117

118

RAS

167

168

DQ8

DQ12

119

120

CAS

169

DQS6

170

DM6

121

122

171

DQ50

172

DQ54

DQ9

DQ13

123

124

173

174

DQS1

DM1

125

126

175

DQ51

176

DQ55

DQS8

127

DQ32

128

DQ36 177

DQ56

178

DQ60

DQ10

DQ14

129

DQ33

130

DQ37 179

180

DQ11

DQ15

131

132

181

DQ57

182

DQ61

133

DQS4

134

DM4

183

DQS7

184

DM7

CK0

135

DQ34

136

DQ38 185

186

CK0

137

138

187

DQ58

188

DQ62

CK2

139

DQ35

140

DQ39 189

DQ59

190

DQ63

DQ16

DQ20

CK2

141

DQ40

142

DQ44 191

192

DQ17

DQ21

143

144

193

SDA

194

SA0

CKE1

CKE0

145

DQ41

146

DQ45 195

SCL

196

SA1

DQS2

DM2

147

DQS5

148

DM5

197 V

DDSPD

198

SA2

DQ18

DQ22

A12

100

A11

149

150

199

DDID

200

Note: All pin assignments are consistent for all 8-byte unbuffered versions.

NT512D64S8HBAFM

512MB : 64M x 64
PC2700 / PC2100 Unbuffered DDR SO-DIMM

REV 1.1

07/2003

© NANYA TECHNOLOGY CORP.

NANYA TECHNOLOGY CORP. reserves the right to change Products and Specifications without notice.

Input/Output Function al Description

Symbol

Type

Polarity

Function

CK0, CK1, CK2,

CK0

CK1

CK2

(SSTL)

Cross

point

The system clock inputs. All address and command lines are sampled on the cross point
of the rising edge of CK and falling edge of CK. A Delay Locked Loop (DLL) circuit is

driven from the clock inputs and output timing for read operations is synchronized to the
input clock.

CKE0, CKE1

(SSTL)

Active

High

Activates the DDR SDRAM CK signal when high and deactivates the CK signal when low.
By deactivating the clocks, CKE low initiates the Power Down mode or the Self Refresh
mode.

(SSTL)

Active

Low

Enables the associated DDR SDRAM command decoder when low and disables the
command decoder when high. When the command decoder is disabled, new commands
are ignored but previous operations continue. Physical Bank 0 is selected by S0; Bank 1 is
selected by S1.

RAS

CAS

(SSTL)

Active

Low

When sampled at the positive rising edge of the clock,

RAS

CAS

define the operation

to be executed by the SDRAM.

REF

Supply

Reference voltage for SSTL-2 inputs

DDQ

Supply

Isolated power supply for the DDR SDRAM output buffers to provide improved noise
immunity

BA0, BA1

(SSTL)

Selects which SDRAM bank is to be active.

A0 - A9

A10/AP

A11, A12

(SSTL)

During a Bank Activate command cycle, A0-A12 defines the row address (RA0-RA12)
when sampled at the rising clock edge.
During a Read or Write command cycle, A0-A9 defines the column address (CA0-CA9)
when sampled at the rising clock edge. In addition to the column address, AP is used to
invoke autoprecharge operation at the end of the Burst Read or Write cycle. If AP is high,
autoprecharge is selected and BA0/BA1 define the bank to be precharged. If AP is low,
autoprecharge is disabled.
During a Precharge command cycle, AP is used in conjunction with BA0/BA1 to control
which bank(s) to precharge. If AP is high all 4 banks will be precharged regardless of the
state of BA0/BA1. If AP is low, then BA0/BA1 are used to define which bank to pre -charge.

DQ0 - DQ63

(SSTL)

Data and Check Bit input/output pins operate in the same manner as on conventional
DRAMs.

DQS0 - DQS7,

DQS9 DQS16

(SSTL)

Active

High

Data strobes: Output with read data, input with write data. Edge aligned with read data,
centered on write data. Used to capture write data.

DD,

Supply

Power and ground for the DDR SDRAM input buffers and core logic

SA0 SA2

Address inputs. Connected to either V

or V

on the system board to configure the

Serial Presence Detect EEPROM address.

SDA

This bi-directional pin is used to transfer data into or out of the SPD EEPROM. A resistor
must be connected from the SDA bus line to V

to act as a pullup.

SCL

This signal is used to clock data into and out of the SPD EEPROM. A resistor may be
connected from the SCL bus time to V

to act as a pullup.

DDSPD

Supply

Serial EEPROM positive power supply.

NT512D64S8HBAFM

512MB : 64M x 64
PC2700 / PC2100 Unbuffered DDR SO-DIMM

REV 1.1

07/2003

© NANYA TECHNOLOGY CORP.

NANYA TECHNOLOGY CORP. reserves the right to change Products and Specifications without notice.

Functional Block Diagram

(2 Bank, 32Mx8 DDR SDRAMs)

Serial PD

SCL

SDA

SA0

SA2

SA1

DM0

DQ0
DQ1
DQ2

DQ7

DQ4

DQ6

DQ5

DQ3

DQ8
DQ9

DQ10

DQ15

DQ12

DQ14

DQ13

DQ11

DQ16
DQ17
DQ18

DQ23

DQ20

DQ22

DQ21

DQ19

DQ24
DQ25
DQ26

DQ31

DQ28

DQ30

DQ29

DQ27

I/O 0
I/O 2

I/O 5

I/O 3

I/O1

I/O 6

I/O 4

I/O 7

I/O 0
I/O 2

I/O 5

I/O 3

I/O 1

I/O 6

I/O 4

I/O 7

DQS0

DM4

DQS4

I/O 0
I/O 2

I/O 5

I/O 3

I/O 1

I/O 6

I/O 4

I/O 7

DM1

DQS1

DQS

DM2

DQS2

DM3

DQS3

DQS

DQ32
DQ33
DQ34

DQ39

DQ36

DQ38

DQ37

DQ35

DQ40
DQ41
DQ42

DQ47

DQ44

DQ46

DQ45

DQ43

I/O 4
I/O 5

I/O 1

I/O 2

I/O 3

I/O 7

I/O 6

I/O 0

DQS

DQS5

DM5

DQ48
DQ49
DQ50

DQ55

DQ52

DQ54

DQ53

DQ51

DQ56
DQ57
DQ58

DQ63

DQ60

DQ62

DQ61

DQ59

DQS6

DM6

DQS7

DM7

DQS

I/O 7
I/O 5

I/O 2

I/O 4

I/O 6

I/O 1

I/O 3

I/O 0

DQS

I/O 3
I/O 2

I/O 6

I/O 5

I/O 4

I/O 0

I/O 1

I/O 7

DQS

I/O 7
I/O 5

I/O 2

I/O 4

I/O 6

I/O 1

I/O 3

I/O 0

D10

DQS

I/O 7
I/O 5

I/O 2

I/O 4

I/O 6

I/O 1

I/O 3

I/O 0

D11

DQS

I/O 0
I/O 3

I/O 4

I/O 2

I/O 1

I/O 7

I/O 5

I/O 6

I/O 7
I/O 0

I/O 2

I/O 1

I/O 6

I/O 4

I/O 5

I/O 3

I/O 0
I/O 2

I/O 5

I/O 3

I/O 1

I/O 6

I/O 4

I/O 7

DQS

I/O 0
I/O 2

I/O 6

I/O 3

I/O 1

I/O 5

I/O 4

I/O 7

DQS

I/O 7
I/O 5

I/O 2

I/O 4

I/O 6

I/O 1

I/O 3

I/O 0

D12

DQS

I/O 7
I/O 5

I/O 1

I/O 4

I/O 6

I/O 2

I/O 3

I/O 0

D13

DQS

I/O 0
I/O 7

I/O 5

I/O 6

I/O 1

I/O 3

I/O 2

I/O 4

D14

DQS

I/O 7
I/O 4

I/O 3

I/O 5

I/O 6

I/O 0

I/O 2

I/O 1

D15

DQS

A0-A12

RAS

BA0-BA1

BA0-BA1 : SDRAMs D0-D15

A0-A12 : SDRAMs D0-D15

RAS

: SDRAMs D0-D15

CKE0

CAS

: SDRAMs D0-D15

CKE : SDRAMs D0-D7

CKE : SDRAMs D8-D15

: SDRAMs D0-D15

CKE1

DDSPD

DDID

DDQ

Strap: see Note 4

SPD
D0-D15
D0-D15
D0-D15

Notes :

1. DQ-to-I/O wring may be changed within a byte.
2. DQ/DQS/DM/CKE/S relationships are maintained as shown.
3. DQ/DQS/DM/DQS resistors are 22 Ohms.
4. V

DDID

strap connections (for memory device V

, V

DDQ

) :

STRAP OUT (OPEN): V

= V

DDQ

STRAP IN (V

): V

is not equal to V

DDQ

NT512D64S8HBAFM

512MB : 64M x 64
PC2700 / PC2100 Unbuffered DDR SO-DIMM

REV 1.1

07/2003

© NANYA TECHNOLOGY CORP.

NANYA TECHNOLOGY CORP. reserves the right to change Products and Specifications without notice.

Serial Presence Detect --

Part 1 of 2

64Mx64 SDRAM DIMM based on 32Mx8, 4Banks, 8K Refresh, 2.5V DDR SDRAMs with SPD

SPD Entry Value

Serial PD Data Entry

(Hexadecimal)

Note

Byte

Description

DDR333

-6K

DDR266B

-75B

DDR333

-6K

DDR266B

-75B

Number of Serial PD Bytes Written during Production

128

Total Number of Bytes in Serial PD device

256

Fundamental Memory Type

SDRAM DDR

Number of Row Addresses on Assembly

Number of Column Addresses on Assembly

Number of DIMM Bank

Data Width of Assembly

X64

Data Width of Assembly (cont')

X64

Voltage Interface Level of this Assembly

SSTL 2.5V

DDR SDRAM Device Cycle Time at CL=2.5

6ns

7.5ns

DDR SDRAM Device Access Time from Clock at CL=2.5

0.7ns

0.75ns

DIMM Configuration Type

Non-Parity

Refresh Rate/Type

SR/1x(7.8us)

Primary DDR SDRAM Width

Error Checking DDR SDRAM Device Width

N/A

DDR SDRAM Device Attr: Min CLK Delay, Random Col
Access

1 Clock

DDR SDRAM Device Attributes: Burst Length Supported

2,4,8

DDR SDRAM Device Attributes: Number of Device Banks

DDR SDRAM Device Attributes: CAS Latencies Supported

2/2.5

DDR SDRAM Device Attributes: CS Latency

DDR SDRAM Device Attributes: WE Latency

DDR SDRAM Device Attributes:

Differential Clock

DDR SDRAM Device Attributes: General

+/-0.2V Voltage Tolerance

Minimum Clock Cycle at CL=2

7.5ns

10ns

Maximum Data Access Time from Clock at CL=2

0.70ns

0.75ns

Minimum Clock Cycle Time at CL=1

N/A

Maximum Data Access Time from Clock at CL=1

N/A

Minimum Row Precharge Time (t

)

18ns

20ns

Minimum Row Active to Row Active delay (t

RRD

)

12ns

15ns

Minimum RAS to CAS delay (t

RCD

)

18ns

20ns

Minimum RAS Pulse Width (t

RAS

)

42ns

45ns

Module Bank Density

256MB

Address and Command Setup Time Before Clock

0.75ns

0.9ns

Address and Command Hold Time After Clock

0.75ns

0.9ns

Data Input Setup Time Before Clock

0.45ns

0.5ns

Data Input Hold Time After Clock

0.45ns

0.5ns

36-61 Reserved

Undefined

SPD Revision

Initial

Checksum Data

NT512D64S8HBAFM

512MB : 64M x 64
PC2700 / PC2100 Unbuffered DDR SO-DIMM

REV 1.1

07/2003

© NANYA TECHNOLOGY CORP.

NANYA TECHNOLOGY CORP. reserves the right to change Products and Specifications without notice.

Serial Presence Detect --

Part 2 of 2

64Mx64 SDRAM DIMM based on 32Mx8, 4Banks, 8K Refresh, 2.5V DDR SDRAMs with SPD

SPD Entry Value

Serial PD Data Entry

(Hexadecimal)

Byte

Description

DDR333

-6K

DDR266B

-75B

DDR333

-6K

DDR266B

-75B

Note

64-71 Manufacturer's JEDEC ID Code

NANYA

7F7F7F0B00000000

Module Manufacturing Location

N/A

73-90 Module Part number

N/A

91-92 Module Revision Code

N/A

93-94 Module Manufacturing Data

Year/Week Code

yy/ww

1, 2

95-98 Module Serial Number

Serial Number

99-255 Reserved

Undefined

yy= Binary coded decimal year code, 0-99(Decimal), 00-63(Hex)

ww= Binary coded decimal year code, 01-52(Decimal), 01-34(Hex)

NT512D64S8HBAFM

512MB : 64M x 64
PC2700 / PC2100 Unbuffered DDR SO-DIMM

REV 1.1

07/2003

© NANYA TECHNOLOGY CORP.

NANYA TECHNOLOGY CORP. reserves the right to change Products and Specifications without notice.

Absolute Maximum Ratings

Symbol

Parameter

Rating

Units

, V

OUT

Voltage on I/O pins relative to Vss

-0.5 to V

DDQ

+0.5

Voltage on Input relative to Vss

-0.5 to +3.6

Voltage on VDD supply relative to Vss

-0.5 to +3.6

DD Q

Voltage on VDDQ supply relative to Vss

-0.5 to +3.6

Operating Temperature (Ambient)

0 to +70

°C

STG

Storage Temperature (Plastic)

-55 to +150

°C

Power Dissipation

OUT

Short Circuit Output Current

Note: Stresses greater than those listed under "Absolute Maximum Ratings" may cause permanent damage to the device. This is
stress rating only, and functional operation of the device at these or any other conditions above those indicated in the operational
sec tions of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect reliability.

Capacitance

Parameter

Symbol

Max.

Units

Notes

Input Capacitance: CK0,

CK0

, CK1,

CK1

, CK2,

CK2

Input Capacitance: A0-A11, BA0, BA1,

RAS

CAS

CKE0,

Input Capacitance: SA0-SA2, SCL

Input Capacitance: CKE0, CKE1,

Input/Output Capacitance DQ0-63; DQS0-7, 9-16

IO1

1, 2

Input/Output Capacitance: SDA

IO3

1. V

DDQ

= V

= 2.5V ± 0.2V, f = 100 MHz, T

= 25 °C, V

OUT

(DC) = V

DDQ

/2, V

OUT

(Peak to Peak) = 0.2V.

2. DQS inputs are grouped with I/O pins reflecting the fact that they are matched in loading to DQ and DQS to facilitate trace matching at

the board level.

NT512D64S8HBAFM

512MB : 64M x 64
PC2700 / PC2100 Unbuffered DDR SO-DIMM

REV 1.1

07/2003

© NANYA TECHNOLOGY CORP.

NANYA TECHNOLOGY CORP. reserves the right to change Products and Specifications without notice.

DC Electrical Characteristics and Operating Conditions

(TA = 0 °C ~ 70 °C; V

DDQ

= 2.5V ± 0.2V; V

= 2.5V ± 0.2V, See AC Characteristics)

Symbol

Parameter

Min

Max

Units

Notes

Supply Voltage

2.3

2.7

DDQ

I/O Supply Voltage

2.3

2.7

SS,

SSQ

Supply Voltage, I/O Supply Voltage

REF

I/O Reference Voltage

0.49 x

DDQ

0.51 x

DDQ

1, 2

I/O Termination Voltage (System)

REF

0.04

REF

+ 0.04

1, 3

IH (DC)

Input High (Logic1) Voltage

REF

+ 0.15

DDQ

+ 0.3

IL (DC)

Input Low (Logic0) Voltage

-0.3

REF

- 0.15

IN (DC)

Input Voltage Level, CK and

Inputs

-0.3

DDQ

+ 0.3

ID (DC)

Input Differential Voltage, CK and

Inputs

0.30

DDQ

+ 0.6

1, 4

Input Leakage Current

Any input 0V

DD;

(All other pins not under test = 0V)

-10

Output Leakage Current

(DQs are disabled; 0V

out

DDQ

-10

Output High Current

OUT =

DDQ

-0.373V, min V

REF,

min V

TT)

-16.8

Output Low Current

OUT

= 0.373, max V

REF,

max V

TT)

16.8

1. Inputs are not recognized as valid until V

REF

stabilizes.

2. V

REF

is expected to be equal to 0.5 V

DDQ

of the transmitting device, and to track variations in the DC level of the same. Peak -to-peak

noise on V

REF

may not exceed 2% of the DC value.

3. V

is not applied directly to the DIMM. V

is a system supply for signal term ination resistors, is expected to be set equal to V

REF,

and must track variations in the DC level of V

REF

4. V

is the magnitude of the difference between the input level on CK and the input level on

NT512D64S8HBAFM

512MB : 64M x 64
PC2700 / PC2100 Unbuffered DDR SO-DIMM

REV 1.1

07/2003

© NANYA TECHNOLOGY CORP.

NANYA TECHNOLOGY CORP. reserves the right to change Products and Specifications without notice.

AC Characteristics

(Notes 1-5 apply to the following Tables; Electrical Characteristics and DC Operating Conditions, AC Operating
Conditions, Operating, Standby, and Refresh Currents, and Electrical Characteristics and AC Timing.)
1. All voltages referenced to V

2. Tests for AC timing, I

, and electrical, AC and DC characteristics, may be conducted at nominal reference/supply voltage levels, but

the related specifications and device operation are guaranteed for the full voltage range specified.

3. Outputs measured with equivalent load. Refer to the AC Output Load Circuit below.
4. AC timing and I

tests may use a V

to V

swing of up to 1.5V in the test environment, but input timing is still referenced to V

REF

(or

to the crossing point for CK,

), and parameter specifications are guaranteed for the specified AC input levels under normal use

conditions. The minimum slew rate for the input signals is 1V/ns in the range between V

IL (AC)

and V

IH (AC)

unless otherwise specified.

5. The AC and DC input level specifications are as defined in the SSTL_2 Standard (i.e. the receiver effectively switches as a result of the

signal crossing the AC input level, and remains in that state as long as the signal does not ring back above (below) the DC input LOW
(HIGH) level.

AC Output Load Circuits

Timing Reference Point

50 ohms

30 pF

Output

OUT

AC Operating Conditions

(TA = 0 °C ~ 70 °C; V

DDQ

= 2.5V ± 0.2V; V

= 2.5V ± 0.2V, See AC Characteristics)

Symbol

Parameter/Condition

Min

Max

Unit

Notes

IH (AC)

Input High (Logic 1) Voltage.

REF

+ 0.31

1, 2

IL (AC)

Input Low (Logic 0) Voltage.

REF

?
- 0.31

1, 2

ID (AC)

Input Differential Voltage, CK and

Inputs

0.62

DDQ

+ 0.6

1, 2, 3

IX (AC)

Input Differential Pair Cross Point Voltage, CK and

Inputs

(0.5*V

DDQ)

- 0.2

(0.5*V

DDQ)

+ 0.2

1, 2, 4

1. Input slew rate = 1V/ ns.
2. Inputs are not recognized as valid until V

REF

stabilizes.

3. V

is the magnitude of the difference between the input level on CK and the input level on

4. The value of V

is expected to equal 0.5*V

DDQ

of the transmitting device and must track variations i n the DC level of the same.

NT512D64S8HBAFM

512MB : 64M x 64
PC2700 / PC2100 Unbuffered DDR SO-DIMM

REV 1.1

07/2003

© NANYA TECHNOLOGY CORP.

NANYA TECHNOLOGY CORP. reserves the right to change Products and Specifications without notice.

Operating, Standby, and Refresh Currents

(TA = 0 °C ~ 70 °C; V

DDQ

= 2.5V ± 0.2V; V

= 2.5V ± 0.2V, See AC Characteristics)

Symbol

Parameter/Condition

PC2700

(-6K)

PC2100

(-75B)

Unit

Notes

DD0

Operating Current: one bank; active/precharge; t

= t

RC (MIN);

= t

(MIN);

DQ, DM, and DQS inputs changing twice per clock cycle; address and

control inputs changing once per clock cycle

1100

920

1, 2

DD1

Operating Current: one bank; active/read/precharge; Burst = 2; t

= t

(MIN);

CL=2.5; t

= t

CK (MIN);

OUT

= 0mA; address and control inputs

changing once per clock cycle

1250

1080

1, 2

DD2P

Precharge Power-Down Standby Current: all banks idle; power-down
mode; CKE

IL (MAX);

= t

CK (MIN )

210

180

1, 2

DD2N

Idle Standby Current: CS

IH (MIN);

all banks idle; CKE

IH (MIN)

; t

CK (MIN);

address and control inputs changing once per clock cycle

550

480

1, 2

DD3P

Active Power-Down Standby Current: one bank active; power-down mode;
CKE

IL (MAX);

= t

CK (MIN )

220

190

1, 2

DD3N

Active Standby Current: one bank; active/precharge; CS

IH (MIN);

CKE

IH (MIN);

= t

RAS (MAX)

; t

= t

CK (MIN)

; DQ, DM, and DQS inputs

changing twice per clock cycle; address and control inputs changing once
per clock cycle

720

620

1, 2

DD4R

Operating Current: one bank; Burst = 2; reads; continuous burst; address
and control inputs changing once per clock cycle; DQ and DQS outputs
changing twice per clock cycle; CL = 2.5; t

= t

CK (MIN);

OUT

= 0mA

1900

1700

1, 2

DD4W

Operating Current: one bank; Burst = 2; writes; continuous burst; address
and control inputs changing once per clock cycle; DQ and DQS inputs
changing twice per clock cycle; CL=2.5; t

= t

CK (MIN)

1460

1200

1, 2

DD5

Auto-Refresh Current:

= t

RFC (MIN )

2100

1800

1, 2, 4

DD6

Self -Refresh Current: CKE

0.2V

1, 2

DD7

Operating Current: four bank; four bank interleaving with BL = 4, address
and control inputs randomly changing; 50% of data changing at every
transfer; t

= t

(min); I

OUT

= 0mA.

3100

2500

1, 2

1. I

specifications are tested after the device is properly initialized.

2. Input slew rate = 1V/ ns.
3. Enables on-chip refresh and address counters.
4. Current at 7.8 µs is time averaged value of I

DD5

at t

RFC (MIN)

and I

DD2P

over 7.8 µs.

NT512D64S8HBAFM

512MB : 64M x 64
PC2700 / PC2100 Unbuffered DDR SO-DIMM

REV 1.1

07/2003

NANYA TECHNOLOGY CORP. reserves the right to change Products and Specifications without notice.

AC Timing Specifications for DDR SDRAM Devices Used on Module

(TA = 0 °C ~ 70 °C; V

DDQ

= 2.5V ± 0.2V; V

= 2.5V ± 0.2V, See AC Characteristics) (Part 1 of 2)

-6K

-75B

Symbol

Parameter

Min.

Max.

Min.

Max.

Unit

Notes

DQ output access time from CK/

-0.7

+0.7

-0.75

+0.75

1-4

DQSCK

DQS output access time from CK/

-0.7

+0.7

-0.75

+0.75

1-4

CK high-level width

0.45

0.55

0.45

0.55

1-4

CK low-level width

0.45

0.55

0.45

0.55

1-4

CL=2.5

7.5

1-4

Clock cycle time

CL=2

7.5

1-4

DQ and DM input hold time

0.45

0.5

1-4,

15, 16

DQ and DM input setup time

0.45

0.5

1-4,

15, 16

DIPW

DQ and DM input pulse width (each input)

1.75

1-4

Data-out high-impedance time from CK/

-0.7

+0.7

-0.75

+0.75

1-4, 5

Data-out low-impedance time from CK/

-0.7

+0.7

-0.75

+0.75

1-4, 5

DQSQ

DQS-DQ skew (DQS & associated DQ signals)

0.45

0.5

1-4

Minimum half clk period for any given cycle;
defined by clk high (t

CH)

or clk low (t

) time

or t

1-4

Data output hold time from DQS

QHS

1-4

QHS

Data hold Skew Factor

0.55ns

0.75ns

1-4

DQSS

Write command to 1st DQS latching transition

0.75

1.25

0.75

1.25

1-4

DQSL,H

DQS input low (high) pulse width
(write cycle)

0.35

1-4

DSS

DQS falling edge to CK setup time
(write cycle)

0.2

1-4

DSH

DQS falling edge hold time from CK
(write cycle)

0.2

1-4

MRD

Mode register set command cycle time

1-4

WPRES

Write preamble setup time

1-4, 7

WPST

Write postamble

0.40

0.60

0.40

0.60

1-4, 6

WPRE

Write preamble

0.25

1-4

Address and control input hold time
(fast slew rate)

0.75

0.9

2-4, 9,
11, 12

Address and control input setup time
(fast slew rate)

0.75

0.9

2-4, 9,
11, 12

Address and control input hold time
(slow slew rate)

0.8

1.0

2-4,

10, 11,

12, 14

NT512D64S8HBAFM

512MB : 64M x 64
PC2700 / PC2100 Unbuffered DDR SO-DIMM

REV 1.1

07/2003

NANYA TECHNOLOGY CORP. reserves the right to change Products and Specifications without notice.

AC Timing Specifications for DDR SDRAM Devices Used on Module

(TA = 0 °C ~ 70 °C; V

DDQ

= 2.5V ± 0.2V; V

= 2.5V ± 0.2V, See AC Characteristics) (Part 2 of 2)

-6K

-75B

Symbol

Parameter

Min.

Max.

Min.

Max.

Unit

Notes

Address and control input setup time

(slow slewrate)

0.8

1.0

2-4,

10-12,

IPW

Input pulse width

2.2

2-4, 12

RPRE

Read preamble

0.9

1.1

0.9

1.1

1-4

RPST

Read postamble

0.40

0.60

0.40

0.60

1-4

RAS

Active to Precharge command

120,000

1-4

Active to Active/Auto-refresh command period

1-4

RFC

Auto-refresh to Active/Auto-refresh command

period

1-4

RCD

Active to Read or Write delay

1-4

RAP

Active to Read Command with Autoprecharge

1-4

Precharge command period

1-4

RRD

Active bank A to Active bank B command

1-4

Write recovery time

1-4

DAL

Auto precharge write recovery + precharge time

)

1-4, 13

WTR

Internal write to read command delay

1-4

PDEX

Power down ex it time

7.5

1-4

XSNR

Exit self -refresh to non-read command

1-4

XSRD

Exit self -refresh to read command

200

1-4

REFI

Average Periodic Refresh Interval

7.8

µs

1-4, 8

NT512D64S8HBAFM

512MB : 64M x 64
PC2700 / PC2100 Unbuffered DDR SO-DIMM

REV 1.1

07/2003

NANYA TECHNOLOGY CORP. reserves the right to change Products and Specifications without notice.

AC Timing Specification Notes

1. Input slew rate = 1V/ns.
2. The CK/

input reference level (for timing reference to CK/

) is the point at which CK and

cross: the input reference level for

signals other than CK/

is V

REF

3. Inputs are not recognized as valid until V

REF

stabilizes.

4. The Output tim ing reference level, as measured at the timing reference point indicated in AC Characteristics (Note 3) is V

TT.

5. t

and t

transitions occur in the same access time windows as valid data transitions. These parameters are not referred to a

specific voltage level, but specify when the device is no longer driving (HZ), or begins driving (LZ).

6. The maximum limit for this parameter is not a device limit. The device operates with a greater value for this parameter, but system

performance (bus turnaround) degrades accordingly.

7. The specific requirement is that DQS be valid (high, low, or some point on a valid transition) on or before this CK edge. A valid

transition is defined as monotonic and meeting the input slew rate specifications of the device. When no writes were previously in
progress on the bus, DQS will be transitioning from Hi -Z to logic LOW. If a previous write was in progress, DQS could be HIGH, LOW,
or transitioning from high to low at this time, depending on t DQSS.

8. A maximum of eight Auto refresh commands can be posted to any given DDR SDRAM device.
9. For command/address input slew rate >= 1.0 V/ns. Slew rate is measured between V

(AC) and V

(AC).

10. For command/address input slew rate >= 0.5 V/ns and < 1.0 V/ns. Slew rate is measured between V

(AC) and V

(AC).

11. CK/

slew rates are >= 1.0 V/ns.

12. These parameters guarantee device timing, but they are not necessarily tested on each device, and they may be guaranteed by

design or tester characterization.

13. For each of the terms in parentheses, if not already an in teger, round to the next highest integer. t CK is equal to the actual system

clock cycle time. For example, for PC2100 at CL= 2.5, t DAL = (15ns/7.5ns) +(20ns/7.0ns) = 2 + 3 = 5.

14. An input setup and hold time derating table is used to increase t IS and t IH in the case where the input slew rate is below 0.5 V/ns.

Input Slew Rate

Delta (tIS

)

Delta (tIH

)

Unit

Note

0.5 V/ns

1, 2

0.4 V/ns

+50

1, 2

0.3 V/ns

+100

1, 2

Input slew rate is based on the lesser of the slew rates determined by either V

IH (AC)

to V

IL (AC)

or V

IH (DC)

to V

IL (DC),

similarly for

rising transitions.

These derating parameters may be guaranteed by design or tester characterization and are not necessarily tested on each device.

15. An input setup and hold time derating table is used to increase t DS and t DH in the case where the I/O slew rate is below 0.5 V/ns.

Input Slew Rate

Delta (tDS

)

Delta (tDH

)

Unit

Note

0.5 V/ns

1, 2

0.4 V/ns

+75

1, 2

0.3 V/ns

+150

1, 2

I/O slew rate is based on the lesser of the slew rates determined by either V

IH (AC)

to V

IL (AC)

or V

IH (DC)

to V

IL (DC),

similarly for

rising transitions.

These derating parameters may be guaranteed by design or tester characterization and are not necessarily tested on each device.

16. An I/O Delta Rise, Fall Derating table is used to increase t DS and t DH in the case where DQ, DM, and DQS slew rates differ.

Delta Rise and Fall Rate

Delta (tDS

)

Delta (tDH

)

Unit

Note

0.0 ns/V

1-4

0.25 ns/V

+50

1-4

0.5 ns/V

+100

1-4

Input slew rate is based on the lesser of the slew rates determined by either V

IH (AC)

to V

IL (AC)

or V

IH (DC)

to V

IL (DC),

similarly for

rising transitions.

Input slew rate is based on the larger of AC to AC delta rise, fall rate and DC to DC delta rise, fall rate.

The delta rise, fall rate is calculated as: [1/(slew rate 1)] - [1/(slew rate 2)]
For example: slew rate 1 = 0.5 V/ns; slew rate 2 = 0.4 V/ns . Delta rise, fall = (1/0.5) - (1/0.4) [ns/V] = -0.5 ns/V

Using the table above, this would result in an increase in t

and t

of 100 ps.

These derating parameters may be guaranteed by design or tester characterization and are not necessarily tested on each device.

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