NT512S64V8HA0G
512MB : 64M x 64
Unbuffered SDRAM Module

64Mx64 bit Two Bank Unbuffered SDRAM Module
based on 32Mx8, 4Banks, 8K Refresh, 3.3V Synchronous DRAMs with SPD

Features

168-Pin Unbuffered 8-Byte Dual In-Line Memory Module

Intended for PC133 applications
- Clock Frequency: 133MHz
- Clock Cycle: 7.5ns
- Clock Assess Time: 5.4ns

Inputs and outputs are LVTTL (3.3V) compatible

Single 3.3V

0.3V Power Supply

Single Pulsed RAS interface

SDRAMs have 4 internal banks

Module has 2 physical banks

Fully Synchronous to positive Clock Edge

Data Mask for Byte Read/Write control

Auto Refresh (CBR) and Self Refresh

Automatic and controlled Precharge commands

Programmable Operation:
- CAS Latency: 2, 3
- Burst Type: Sequential or Interleave
- Burst Length: 1, 2, 4, 8
- Operation: Burst Read and Write or Multiple Burst Read with

Single Write

Suspend Mode and Power Down Mode

8K Refresh cycles distributed across 64ms

Gold contacts

SDRAMs in TSOP Type II Package

Serial Presence Detect with Write Protect

Description

NT512S64V8HA0G is unbuffered 168-pin Synchronous DRAM Dual In-Line Memory Modules (DIMMs) which is organized as 64Mx64
high-speed memory arrays and is configured as two 32M x 64 physical bank. The DIMM uses sixteen 32Mx8 SDRAMs in 400mil TSOP II
packages. The DIMM achieves high-speed data transfer rates of up to 133MHz by employing a prefetch / pipeline hybrid architecture that
supports the JEDEC 1N rule while allowing very low burst power.

All control, address, and data input/output circuits are synchronized with the positive edge of the externally supplied clock inputs.
All inputs are sampled at the positive edge of each externally supplied clock (CK0 - CK3). Internal operating modes are defined by combinations
of RAS , CAS ,

WE , S0 - S3 , DQMB, and CKE0 CKE1 signals. A command decoder initiates the necessary timings for each operation. A

14-bit address bus accepts address information in a row / column multiplexing arrangement.

Prior to any Access operation, the CAS latency, burst type, burst length, and Burst operation type must be programmed into the DIMM by
address inputs A0-A9 during the Mode Register Set cycle. The DIMM uses serial presence detects implemented via a serial EEPROM using
the two-pin IIC protocol. The first 128 bytes of serial PD data are used by the DIMM manufacturer. The last 128 bytes are available to the
customer.

Ordering Information

Speed

Part Number

MHz. CL

RCD

Organization

Leads

Power

143MHz 3 3 3

NT512S64V8HA0G-7K

133MHz 2 2 2

133MHz 3 3 3

NT512S64V8HA0G-75B

100MHz 2 2 2

125MHz 3 3 3

NT512S64V8HA0G-8B

100MHz 2 2 2

64Mx64 Gold 3.3V

* CL =

CAS Latency

REV 1.0

08/2002

© NANYA TECHNOLOGY CORP.

NANYA TECHNOLOGY CORP. reserves the right to change Products and Specifications without notice.

NT512S64V8HA0G
512MB : 64M x 64
Unbuffered SDRAM Module

Pin Description

DQ0-DQ63 Data

input/output

CK0, CK1

CK2, CK3

Clock Inputs

CB0-CB7

Check Bit Data input/output

CKE0 CKE1

Clock Enable

DQMB0-DQMB7

Data Mask

RAS Row

Address

Strobe V

Power

(3.3V)

CAS Column

Address

Strobe V

Ground

Write Enable

No Connect

S0 , S1, S2 , S3

Chip Selects

SCL

Serial Presence Detect Clock Input

A0-A9, A12

Address Inputs

SDA

Serial Presence Detect Data input/output

A10 / AP

Address Input/Autoprecharge

SA0-2

Serial Presence Detect Address Inputs

BA0, BA1

SDRAM Bank Address Inputs

Serial Presence Detect Write Protect Input

Pinout

Pin Front Pin Back Pin Front Pin Back Pin Front Pin Back

1 V

85 V

DQMB1

113

DQMB5

57 DQ18

141

DQ50

2 DQ0 86 DQ32

30 S0 114 S1 58 DQ19

142

DQ51

3 DQ1 87 DQ33

31 NC 115

RAS 59 V

143 V

4 DQ2 88 DQ34

32 V

116 V

60 DQ20

144

DQ52

5 DQ3 89 DQ35

33 A0 117 A1 61 NC 145 NC

6 V

90 V

34 A2 118 A3 62 NC 146 NC

7 DQ4 91 DQ36

35 A4 119 A5 63

CKE1*

147 NC

8 DQ5 92 DQ37

36 A6 120 A7 64 V

148 V

9 DQ6 93 DQ38 37 A8 121 A9 65 DQ21 149 DQ53

10 DQ7 94 DQ39 38 A10/AP

122 BA0 66 DQ22 150 DQ54

11 DQ8 95 DQ40 39 BA1 123 A11 67 DQ23 151 DQ55

12 V

96 V

40 V

124 V

68 V

152 V

13 DQ9 97 DQ41 41 V

125 CK1 69 DQ24 153 DQ56

14 DQ10 98 DQ42 42 CK0 126 A12 70 DQ25 154 DQ57

15 DQ11 99 DQ43 43 V

127 V

71 DQ26

155

DQ58

16 DQ12 100 DQ44 44 NC 128 CKE0 72 DQ27 156 DQ59

17 DQ13 101 DQ45 45 S2 129 S3 73 V

157 V

18 V

102 V

DQMB2

130

DQMB6

74 DQ28

158

DQ60

19 DQ14 103 DQ46 47 DQMB3

131 DQMB7

75 DQ29 159 DQ61

20 DQ15 104 DQ47 48 NC 132 NC 76 DQ30 160 DQ62

21 CB0 105 CB4 49 V

133 V

77 DQ31

161

DQ63

22 CB1 106 CB5

50 NC 134 NC 78 V

162 V

23 V

107 V

51 NC 135 NC 79 CK2 163 CK3

24 NC 108 NC 52 CB2 136 CB6 80 NC 164 NC

25 NC 109 NC 53 CB3 137 CB7 81 WP 165 SA0

26 V

110 V

54 V

138 V

82 SDA 166 SA1

WE 111 CAS 55 DQ16 139 DQ48 83 SCL 167 SA2

28 DQMB0 112 DQMB4

56 DQ17 140 DQ49 84 V

168 V

Note: All pin assignments are consistent for all 8-byte unbuffered versions.
*CKE1 is terminated with a 10k ohm pullup resistor.

REV 1.0

08/2002

© NANYA TECHNOLOGY CORP.

NANYA TECHNOLOGY CORP. reserves the right to change Products and Specifications without notice.

NT512S64V8HA0G
512MB : 64M x 64
Unbuffered SDRAM Module

SDRAM DIMM Block Diagram

(2 Bank, 32Mx8 SDRAMs)

NOTE : Exact DQ wiring may differ from that shown above

A0 - A12

A0 - A12 : SDRAMs D0 - D15
A13/BS0 : SDRAMs D0 - D15
A12/BS1 : SDRAMs D0 - D15

BA0
BA1

*All resistor values are 10 ohms except as shown.

RAS : SDRAMs D0- D15

CKE : SDRAMs D0- D7

CAS : SDRAMs D0- D15

WE : SDRAMs D0- D15

DQMB0

DQ0
DQ1
DQ2

DQ7

DQ4

DQ6

DQ5

DQ3

DQMB4

DQ32
DQ33
DQ34

DQ39

DQ36

DQ38

DQ37

DQ35

DQMB1

DQ8
DQ9

DQ10

DQ15

DQ12

DQ14

DQ13

DQ11

DQMB5

DQ40
DQ41
DQ42

DQ47

DQ44

DQ46

DQ45

DQ43

CK0

CK2

CK3

CK1

CLK : SDRAMs D0 -D1, D4 - D5, 3.3pF Cap

CLK : SDRAMs D8 - D9,D12 - D13, 3.3pF Cap

CLK : SDRAMs D2 - D3,D6 -D7, 3.3pF Cap

CLK : SDRAMs D10 - D11, D14 -D15, 3.3pF Cap

DQMB2

DQ16
DQ17
DQ18

DQ23

DQ20

DQ22

DQ21

DQ19

DQMB6

DQ48
DQ49
DQ50

DQ55

DQ52

DQ54

DQ53

DQ51

DQMB3

DQMB7

DQ56
DQ57
DQ58

DQ63

DQ60

DQ62

DQ61

DQ59

I/O 0
I/O 1

I/O 6

I/O 5

I/O 4

I/O 3

I/O 2

I/O 7

DQM

I/O 0
I/O 1

I/O 6

I/O 5

I/O 4

I/O 3

I/O 2

I/O 7

DQM

D15

DQ24
DQ25
DQ26

DQ31

DQ28

DQ30

DQ29

DQ27

RAS
CAS

CKE0

I/O 0
I/O 1

I/O 6

I/O 5

I/O 4

I/O 3

I/O 2

I/O 7

DQM

I/O 0
I/O 1

I/O 6

I/O 5

I/O 4

I/O 3

I/O 2

I/O 7

DQM

D11

I/O 0
I/O 1

I/O 6

I/O 5

I/O 4

I/O 3

I/O 2

I/O 7

DQM

I/O 0
I/O 1

I/O 6

I/O 5

I/O 4

I/O 3

I/O 2

I/O 7

DQM

D10

I/O 0
I/O 1

I/O 6

I/O 5

I/O 4

I/O 3

I/O 2

I/O 7

DQM

I/O 0
I/O 1

I/O 6

I/O 5

I/O 4

I/O 3

I/O 2

I/O 7

DQM

D14

I/O 0
I/O 1

I/O 6

I/O 5

I/O 4

I/O 3

I/O 2

I/O 7

DQM

I/O 0
I/O 1

I/O 6

I/O 5

I/O 4

I/O 3

I/O 2

I/O 7

DQM

D13

I/O 0
I/O 1

I/O 6

I/O 5

I/O 4

I/O 3

I/O 2

I/O 7

DQM

I/O 0
I/O 1

I/O 6

I/O 5

I/O 4

I/O 3

I/O 2

I/O 7

DQM

I/O 0
I/O 1

I/O 6

I/O 5

I/O 4

I/O 3

I/O 2

I/O 7

DQM

I/O 0
I/O 1

I/O 6

I/O 5

I/O 4

I/O 3

I/O 2

I/O 7

DQM

D12

I/O 0
I/O 1

I/O 6

I/O 5

I/O 4

I/O 3

I/O 2

I/O 7

DQM

I/O 0
I/O 1

I/O 6

I/O 5

I/O 4

I/O 3

I/O 2

I/O 7

DQM

VDD

10K

CKE : SDRAMs D8- D15

CKE1

VDD

VSS

D0 - D15

0.1 uF

.33uF

Serial PD

SCL

SDA

SA0

SA2

SA1

47K

REV 1.0

08/2002

© NANYA TECHNOLOGY CORP.

NANYA TECHNOLOGY CORP. reserves the right to change Products and Specifications without notice.

NT512S64V8HA0G
512MB : 64M x 64
Unbuffered SDRAM Module

Input/Output Functional Description

Symbol

Type

Signal

Polarity

Function

CK0 ~ CK3

Input

Pulse

Positive

Edge

The system clock inputs. All of the SDRAM inputs are sampled on the rising edge of
their associated clock.

CKE0, CKE1

Input

Level

Active

High

Activates the SDRAM CK0 ~ CK3 signals when high and deactivates them when low. By
deactivating the clocks, CKE0 low initiates the Power Down mode, Suspend mode, or the
Self-Refresh mode.

S0 ~ S3

Input

Pulse

Active

Low

Enables the associated SDRAM command decoder when low and disables the
command decoder when high. When the command decoder is disabled, new commands
are ignored but previous operations continue.

RAS

CAS

Input

Pulse

Active

Low

When sampled at the positive rising edge of the clock, RAS

CAS

WE define the

operation to be executed by the SDRAM.

BA0, BA1

Input

Level

Selects which SDRAM bank is to be active.

A0 - A9

A10/AP

A12

Input

Level

During a Bank Activate command cycle, A0-A12 defines the row address (RA0-RA12)
when sampled at the rising clock edge.
During a Read or Write command cycle, A0-A9 defines the column address (CA0-CA9)
when sampled at the rising clock edge. In addition to the column address, AP is used to
invoke Autoprecharge operation at the end of the Burst Read or Write cycle. If AP is high,
autoprecharge is selected and BA0/BA1 define the bank to be precharged. If AP is low,
autoprecharge is disabled.
During a Precharge command cycle, AP is used in conjunction with BA0/BA1 to control
which bank(s) to precharge. If AP is high all 4 banks will be precharged regardless of the
state of BA0/BA1. If AP is low, then BA0/BA1 are used to define which bank to
pre-charge.

DQ0 - DQ63,

CB0 - CB7

Input

/Output

Level

Data and Check Bit input/output pins operate in the same manner as on conventional
DRAMs.

DQMB0 -DQMB7

Input

Pulse

Active

High

The Data input/output mask places the DQ buffers in a high impedance state when
sampled high. In Read mode, DQM has a latency of two clock cycles and controls the
output buffers like an output enable. In Write mode, DQM has a latency of zero and
operates as a byte mask by allowing input data to be written if it is low but blocks the
Write operation if DQM is high.

SA0 SA2

Input

Level

Address inputs. Connected to either V

or V

on the system board to configure the

Serial Presence Detect EEPROM address.

SDA

Input

/Output

Level

Serial Data. Bi-directional signal used to transfer data into and out of the Serial Presence
Detect EEPROM. Since the SDA signal is Open Drain/Open Collector at the EEPROM, a
pull-up resistor is required on the system board.

SCL

Input

Pulse

Serial Clock. Used to clock all Serial Presence Detect data into and out of the EEPROM.
Since the SCL signal is inactive in the "high" state, a pull-up resistor is recommended on
the system board.

Input

Level

Active

High

Hardware Write Protect. When WP is active, writing to the EEPROM array is inhibited.
On the DIMM, this input is connected to the EEPROM Write Protect input and is also tied
to ground through a 47K ohm pull-down resistor.

, V

Supply

Power and ground for the module.

REV 1.0

08/2002

© NANYA TECHNOLOGY CORP.

NANYA TECHNOLOGY CORP. reserves the right to change Products and Specifications without notice.

NT512S64V8HA0G
512MB : 64M x 64
Unbuffered SDRAM Module

Absolute Maximum Ratings

Symbol

Parameter

Rating

Units

Notes

Power Supply Voltage

-0.3 to +4.6

Input Voltage

-0.3 to V

+0.3

OUT

Output Voltage

-0.3 to V

+0.3

Operating Temperature (ambient)

0 to +70

°C

STG

Storage Temperature

-55 to +125

°C

Power Dissipation

16 W

OUT

Short Circuit Output Current

50 mA

1. Stresses greater than those listed under "Absolute Maximum Ratings" may cause permanent damage to the device.
This is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operational

sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect reliability.

Recommended DC Operating Conditions

=0 to 70

°C)

Rating

Symbol

Parameter

Min.

Typ. Max.

Units Notes

Power

Voltage

3.0 3.3 3.6 V 1

Input High Voltage

2.0

+ 0.3

1,2

Input

Low

Voltage

-0.3 - 0.8 V 1,3

Output

High

Voltage

2.4 -

- V

Output

Low

Voltage

- 0.4 V

Input Leakage current

-10

1. All voltages referenced to V

2. V

(max) = V

/ V

DDQ

+ 1.2V for pulse width

5ns

(min) = V

/ V

SSQ

- 1.2V for pulse width

5ns .

Capacitance

=25 °C, f =1MHz, V

=3.3 ± 0.3V)

Symbol Parameter

Max.

Unit

Input Capacitance (A0-A12, BA0, BA1, RAS

CAS

WE ) 100

Input Capacitance (CKE0 ~ CKE1)

Input Capacitance ( S0 , S2 ) 30

Input Capacitance (CK0 - CK3)

Input Capacitance (DQMB0 - DQMB7)

Input Capacitance (SA0 - SA2, SCL, WP)

IO1

Input/Output Capacitance (DQ0 - DQ63, CB0 - CB7)

IO2

Input/Output

Capacitance

(SDA)

DC Output Load Circuit

VOH(DC) = 2.4V,IOH= -2mA

VOL(DC) = 0.4V,IOL= -2mA

3.3 V

1200 ohms

870 ohms

50 pF

Output

REV 1.0

08/2002

© NANYA TECHNOLOGY CORP.

NANYA TECHNOLOGY CORP. reserves the right to change Products and Specifications without notice.

NT512S64V8HA0G
512MB : 64M x 64
Unbuffered SDRAM Module

Operating, Standby, and Refresh Currents

=0 to 70 °C , V

=3.3 ± 0.3V)

Speed

Parameter

Symbol

Test condition

- 7K

- 75B

- 8B

Unit Note

Operating current

CC1

1 bank operation , t

= t

(mim), t

= min

Active-Precharge Command cycling

without burst operation

1200 1080 1080 mA 1,

3,4

CC2P

CKE0

(max), t

= min,

S0 , S2 = V

(min)

32 32 32 mA 2

Precharge

standby current

in power-down mode

CC2PS

CKE0

(max), t

=oo ,

S0 , S2 = V

(min)

32 32 32 mA 2

CC2N

CKE0

(min), t

= min

S0 , S2 = V

(min)

800 720 720 mA 2,5

Precharge

standby current in non

power-down mode

CC2NS

CKE0

(min), t

=oo,

S0 , S2 = V

(min)

144 144 144 mA 2,6

CC3P

CKE0

(max), t

=min.

S0 , S2 = V

(min) (Power Down Mode)

144 144 144 mA 2,7

No Operating current

( Active state : 4 bank)

CC3N

CKE0

(min), t

=min

S0 , S2 = V

(min)

960 800 800 mA 2,5

Operating current

( Burst mode )

CC4

=min , Read/ Write command cycling,

Multiple banks active, gapless data, BL=4

1560 1360 1360 mA 1,4,8

Auto(CBR)

refresh current

CC5

=min, CBR command cycling

2000 1920 1920 mA

Self refresh current

CC6

CKE0

0.2V

48 48 48 mA 2

Serial PD Device

Standby Current

= GND or V

30 30 30

A 9

Serial PD Device Active

Power Supply Current

CCA

SCL Clock Frequency=100 MHz

1 1 1

A 10

1. The specified values are for one DIMM bank in the specified mode, and the other DIMM bank in Active Standby (I

CC3N

2. The specified values are for both DIMM banks operating in the specified mode.
3. These parameters depend on the cycle rate and are measured with the cycle determined by the minimum value of t

and t

Input signals are changed up to three times during t

(min).

4. The specified values are obtained with the output open.
5. Input signals are changed once during three clock cycles.
6. Input signals are stable.
7. Active Standby current will be higher if clock suspend is entered during a Burst Read cycle (add 1mA per DQ).
8. Input signals are changed once during t

CK(min)

9. V

=3.3V.

10. As follows:

· Input pulse levels V

x 0.1 to V

x 0.9

· Input rise and fall times 10ns
· Input and output timing levels V

x 0.5

· Output load 1 TTL gate and CL=100pF

REV 1.0

08/2002

© NANYA TECHNOLOGY CORP.

NANYA TECHNOLOGY CORP. reserves the right to change Products and Specifications without notice.

NT512S64V8HA0G
512MB : 64M x 64
Unbuffered SDRAM Module

AC Characteristics

=0 to 70

C , V

=3.3 ± 0.3V)

1. An initial pause of 200us,with DQMB0-7 and CKE0 held high, is required after power-up. A Precharge All Banks command must be given

followed by a minimum of eight Auto (CBR) Refresh cycles before or after the Mode Register Set operation.

2. The Transition time is measured between

and

(or between V

and

3. In addition to meeting the transition rate specification, the CK0, CK2, and CKE0 signals must transit between V

and V

(or between V

and V

) in a monotonic manner.

4. AC timing tests have V

=0.8Vand V

= 2.0 V with the timing referenced to the 1.40V crossover point.

5. AC measurements assume t T =1.2 ns.

AC Output Load Circuits

Clock

Input

Output

HOLD

SETUP

CKL

CKH

1.4V

tOH

1.4V

Output

Zo = 50 ohm

50 pF

AC Output Load Circuit

REV 1.0

08/2002

NANYA TECHNOLOGY CORP. reserves the right to change Products and Specifications without notice.

NT512S64V8HA0G
512MB : 64M x 64
Unbuffered SDRAM Module

AC Timing Parameters
Clock and Clock Enable Parameters

- 7K

- 75B

- 8B

Symbol Parameter

Min. Max. Min. Max. Min. Max.

Unit Note

tCK3 Clock

Cycle

Time,

CAS

Latency

3 7 1000

7.5 1000

8 1000 ns

tCK2 Clock

Cycle

Time,

CAS

Latency

2 7.5 1000

10 1000

10 1000 ns

tAC3(B) Clock

Access

Time, CAS

Latency

3 - 5.4 - 5.4 - 6 ns

tAC2(B) Clock

Access

Time, CAS

Latency

2 - 5.4 - 6 - 6 ns 1

tCKH

Clock High Pulse Width

2.5

tCKL Clock

Low

Pulse

Width

2.5 - 2.5 - 3 - ns

tCES

Clock Enable Set-up Time

1.5

tCEH

Clock Enable Hold Time

0.8

tSB

Power down mode Entry Time

7.5

Transition

Time

(Rise

and

Fall)

0.5 10 0.5 10 0.5 10 ns

Access time is measured at 1.4V. In AC Characteristics section, see notes.

2. t

CKH

is the pulse width of CLK measured from the positive edge to the negative edge referenced to V

(min). t

CKL

is the pulse width of

CLK measured from the negative edge to the positive edge referenced to V

(max).

Common Parameters

- 7K

- 75B

- 8B

Symbol Parameter

Min. Max. Min. Max. Min. Max.

Unit Note

tCS Command

Setup

Time

1.5 - 1.5 - 2 - ns

tCH Command

Hold

Time

0.8 - 0.8 - 1 - ns

tAS

Address and Bank Select Set-up Time

1.5

tAH

Address and Bank Select Hold Time

0.8

tRCD

RAS to CAS

Delay

20 - 20 - 20 - ns 1

tRC Bank

Cycle

Time

60 - 67.5 - 70 - ns 1

tRFC Auto

Refresh

Active/Auto

Refresh 60 - 67.5 - 70 -

tRAS Active

Command

Period

45 100K

50 100K ns

tRP Precharge

Time

20 - 20 - 20 - ns 1

tRRD

Bank

Delay

Time

15 - 15 - 20 - ns 1

tCCD

CAS to CAS Delay

Time

1 - 1 - 1 - CLK

1.These parameters account for the number of clock cycle and depend on the operating frequency of the clock, as follows: the num
ber of clock cycles = specified value of timing / clock period (count fractions as a whole number).

Mode Register Set Cycle

- 7K

- 75B

- 8B

Symbol Parameter

Min. Max. Min. Max. Min. Max.

Unit Note

tRSC

Mode

Set

Cycle

Time

2 - 2 - 2 - CLK 1

REV 1.0

08/2002

NANYA TECHNOLOGY CORP. reserves the right to change Products and Specifications without notice.

NT512S64V8HA0G
512MB : 64M x 64
Unbuffered SDRAM Module

Read Cycle

- 7K

- 75B

- 8B

Symbol Parameter

Min. Max. Min. Max. Min. Max.

Unit Note

- - - - 2.5 - ns

tOH

Data Out Hold Time

2.7 - 2.7 - 3 - ns

tLZ Data

Out

Low

Impedance

Time

0 - 0 - 0 - ns

tHZ3

Data Out to High Impedance Time

5.4

tDQZ

DQM

Data

Out

Disable

Latency

2 - 2 - 2 - CLK

1. Referenced to the time at which the output achieves the open circuit condition, not to output voltage levels.

Refresh Cycle

- 7K

- 75B

- 8B

Symbol Parameter

Min. Max. Min. Max. Min. Max.

Unit Note

tREF Refresh

Period

- 64 - 64 - 64 ms

tSREX

Self

Refresh

Exit

Time

10 - 10 - 10 - ns

Write Cycle

- 7K

- 75B

- 8B

Symbol Parameter

Min. Max. Min. Max. Min. Max.

Unit Note

tDS

Data In Set-up Time

1.5

tDH

Data In Hold Time

0.8

tDPL Data

input

Precharge

15 - 15 - 15 - ns

tDAL3

Data In to Active Delay

CAS Latency = 3

5 - 5 - 5 - CLK

tDAL2

Data In to Active Delay

CAS Latency = 2

5 - - - - - CLK

tDQW

DQM

Write

Mask

Latency

0 - 0 - 0 - ns

REV 1.0

08/2002

NANYA TECHNOLOGY CORP. reserves the right to change Products and Specifications without notice.

NT512S64V8HA0G
512MB : 64M x 64
Unbuffered SDRAM Module

REV 1.0

08/2002

NANYA TECHNOLOGY CORP. reserves the right to change Products and Specifications without notice.

Package Dimensions

Note : All dimensions are typical unless otherwise stated.

133.35

127.33

1.660

2.625

Detail B

0.079

Detail B

1
.
375

0.157

0.700

FRONT VIEW

Side

pin 1

0.118

0.050

6.35

0.250

0.079

Detail A

Detail C

489

0.050

Detail C

0.039

0.0

0.170 MAX.

Unit : Millimeters

BACK VIEW

5.250

5.013

4.00

17.78

3
4

.925

3.0

66.67

0.250

42.17

6.35

4.318

1.27

3
.
124

0
.
123

2.006

123

124

0.2

1.0

098

1.27

Inches

Document Outline

Ð­Ð»ÐµÐºÑ‚Ñ€Ð¾Ð½Ð½Ñ‹Ð¹ ÐºÐ¾Ð¼Ð¿Ð¾Ð½ÐµÐ½Ñ‚: NT512S64V8HA0G-8B

Document Outline

ÐÐ»ÐµÐºÑ‚Ñ€Ð¾Ð½Ð½Ñ‹Ð¹ ÐºÐ¾Ð¼Ð¿Ð¾Ð½ÐµÐ½Ñ‚: NT512S64V8HA0G-8B