NT5DS64M4AT NT5DS64M4AW
NT5DS32M8AT NT5DS32M8AW

256Mb Double Data Rate SDRAM

REV 1.3

08/2002

NANYA TECHNOLOGY CORP

NANYA TECHNOLOGY CORP. reserves the right to change Products and Specifications without notice.

Features

Double data rate architecture: two data transfers per
clock cycle

Bidirectional data strobe (DQS) is transmitted and
received with data, to be used in capturing data at the
receiver

DQS is edge-aligned with data for reads and is center-
aligned with data for writes

Differential clock inputs (CK and CK)

Four internal banks for concurrent operation

Data mask (DM) for write data

DLL aligns DQ and DQS transitions with CK transitions

Commands entered on each positive CK edge; data and
data mask referenced to both edges of DQS

Burst lengths: 2, 4, or 8

CAS Latency: 2, 2.5

Auto Precharge option for each burst access

Auto Refresh and Self Refresh Modes

7.8

s Maximum Average Periodic Refresh Interval

2.5V (SSTL_2 compatible) I/O

DDQ

= 2.5V

0.2V

= 2.5V

0.2V

-7K parts support PC2100 modules.
-75B parts support PC2100 modules
-8B parts support PC1600 modules

Description

The 256Mb DDR SDRAM is a high-speed CMOS, dynamic
random-access memory containing 268,435,456 bits. It is

internally configured as a quad-bank DRAM.

The 256Mb DDR SDRAM uses a double-data-rate architec-

ture to achieve high-speed operation. The double data rate
architecture is essentially a 2n prefetch architecture with an

interface designed to transfer two data words per clock cycle

at the I/O pins. A single read or write access for the 256Mb
DDR SDRAM effectively consists of a single 2n-bit wide, one

clock cycle data transfer at the internal DRAM core and two

corresponding n-bit wide, one-half-clock-cycle data transfers
at the I/O pins.

A bidirectional data strobe (DQS) is transmitted externally,

along with data, for use in data capture at the receiver. DQS

is a strobe transmitted by the DDR SDRAM during Reads
and by the memory controller during Writes. DQS is edge-

aligned with data for Reads and center-aligned with data for

Writes.

The 256Mb DDR SDRAM operates from a differential clock
(CK and CK; the crossing of CK going high and CK going

LOW is referred to as the positive edge of CK). Commands

(address and control signals) are registered at every positive
edge of CK. Input data is registered on both edges of DQS,

and output data is referenced to both edges of DQS, as well

as to both edges of CK.

Read and write accesses to the DDR SDRAM are burst ori-
ented; accesses start at a selected location and continue for

a programmed number of locations in a programmed

sequence. Accesses begin with the registration of an Active
command, which is then followed by a Read or Write com-

mand. The address bits registered coincident with the Active

command are used to select the bank and row to be
accessed. The address bits registered coincident with the

Read or Write command are used to select the bank and the

starting column location for the burst access.

The DDR SDRAM provides for programmable Read or Write
burst lengths of 2, 4 or 8 locations. An Auto Precharge func-

tion may be enabled to provide a self-timed row precharge

that is initiated at the end of the burst access.

As with standard SDRAMs, the pipelined, multibank architec-
ture of DDR SDRAMs allows for concurrent operation,

thereby providing high effective bandwidth by hiding row pre-

charge and activation time.

An auto refresh mode is provided along with a power-saving
Power Down mode. All inputs are compatible with the JEDEC

Standard for SSTL_2. All outputs are SSTL_2, Class II com-

patible.

The functionality described and the timing specifications
included in this data sheet are for the DLL Enabled mode
of operation.

CAS Latency and Frequency

CAS Latency

Maximum Operating Frequency (MHz)*

DDR266A

(-7K)

DDR266B

(-75B)

DDR200

(-8B)

133

100

2.5

143

133

125

* Values are nominal (exact tCK should be used).

NT5DS64M4AT NT5DS64M4AW
NT5DS32M8AT NT5DS32M8AW

256Mb Double Data Rate SDRAM

REV 1.3

08/2002

NANYA TECHNOLOGY CORP

NANYA TECHNOLOGY CORP. reserves the right to change Products and Specifications without notice.

Pin Configuration - 256Mb DDR SDRAM (x4 / x8)

2
3
4

9
10

13
14

7
8

16
17
18
19

21
22

65
64
63

58
57

60
59

51
50
49
48

46
45

24
25

43
42

26
27

41
40

28
29

30
31
32
33

39
38

36
35
34

DQ0

DDQ

DQ1

SSQ

DDQ

DQ3

SSQ

NC
NC

DQ2

DDQ

NU
NC

CAS

RAS

BA0

BA1

DQ7
V

SSQ

NC
DQ6

DDQ

SSQ

DQ4

DDQ

NC
DQ5

SSQ

DQS
NC
V

REF

DM*

CK
CK
CKE

NC
A12

A11
A9

DDQ

DQ0

SSQ

DDQ

DQ1

SSQ

NC
NC

DDQ

NC
NC

CAS
RAS

BA0
BA1

NC
V

SSQ

NC
DQ3

DDQ

SSQ

DQ2

DDQ

NC
NC

SSQ

DQS
NC
V

REF

DM*

CK
CK
CKE

NC
A12

A11
A9

A10/AP

A0
A1
A2

A10/AP

A0
A1
A2

A6
A5

A4
V

A6
A5

A4
V

Column Address Table

Organization

Column Address

64Mb x 4

A0-A9, A11

32Mb x 8

A0-A9

*DM is internally loaded to match DQ and DQS identically

NT5DS64M4AT

NT5DS32M8AT

64Mb x 4

32Mb x 8

66-pin Plastic TSOP-II 400mil

NT5DS64M4AT NT5DS64M4AW
NT5DS32M8AT NT5DS32M8AW

256Mb Double Data Rate SDRAM

REV 1.3

08/2002

NANYA TECHNOLOGY CORP

NANYA TECHNOLOGY CORP. reserves the right to change Products and Specifications without notice.

Pin Configuration - 60 balls 0.8mmx1.0mm Pitch CSP Package

See the balls through the package.

64 X 4

32 X 8

VSSQ

VREF

VDDQ

VSSQ

VDDQ

VSSQ

VSS

CLK

A12

A11

VSS

DQ3

DQ2

DQS

DQM

CLK

CKE

VSS

VDD

DQ0

DQ1

QFC

RAS

BA1

VDD

VSSQ

VDDQ

VSSQ

VDDQ

VDD

CAS

BA0

A10/AP

VDDQ

VSSQ

VREF

DQ7

VDDQ

VSSQ

VDDQ

VSSQ

VSS

CLK

A12

A11

VSS

DQ6

DQ5

DQ4

DQS

DQM

CLK

CKE

VSS

VDD

DQ1

DQ2

DQ3

QFC

RAS

BA1

VDD

DQ0

VSSQ

VDDQ

VSSQ

VDDQ

VDD

CAS

BA0

A10/AP

VDDQ

NT5DS64M4AT NT5DS64M4AW
NT5DS32M8AT NT5DS32M8AW

256Mb Double Data Rate SDRAM

REV 1.3

08/2002

NANYA TECHNOLOGY CORP

NANYA TECHNOLOGY CORP. reserves the right to change Products and Specifications without notice.

Input/Output Functional Description

Symbol

Type

Function

CK, CK

Input

Clock: CK and CK are differential clock inputs. All address and control input signals are sampled
on the crossing of the positive edge of CK and negative edge of CK. Output (read) data is refer-
enced to the crossings of CK and CK (both directions of crossing).

CKE, CKE0, CKE1

Input

Clock Enable: CKE HIGH activates, and CKE Low deactivates, internal clock signals and device
input buffers and output drivers. Taking CKE Low provides Precharge Power Down and Self
Refresh operation (all banks idle), or Active Power Down (row Active in any bank). CKE is syn-
chronous for power down entry and exit, and for self refresh entry. CKE is asynchronous for self
refresh exit. CKE must be maintained high throughout read and write accesses. Input buffers,
excluding CK, CK and CKE are disabled during Power Down. Input buffers, excluding CKE, are
disabled during self refresh. The standard pinout includes one CKE pin. Optional pinouts might
include CKE1 on a different pin, in addition to CKE0, to facilitate independent Power Down control
of stacked devices.

CS, CS0, CS1

Input

Chip Select: All commands are masked when CS is registered high. CS provides for external
bank selection on systems with multiple banks. CS is considered part of the command code. The
standard pinout includes one CS pin. Optional pinouts might include CS1 on a different pin, in
addition to CS0, to allow upper or lower deck selection on stacked devices.

RAS, CAS , WE

Input

Command Inputs: RAS, CAS and WE (along with CS) define the command being entered.

Input

Input Data Mask: DM is an input mask signal for write data. Input data is masked when DM is
sampled high coincident with that input data during a Write access. DM is sampled on both edges
of DQS. Although DM pins are input only, the DM loading matches the DQ and DQS loading. Dur-
ing a Read, DM can be driven high, low, or floated.

BA0, BA1

Input

Bank Address Inputs: BA0 and BA1 define to which bank an Active, Read, Write or Precharge
command is being applied. BA0 and BA1 also determines if the mode register or extended mode
register is to be accessed during a MRS or EMRS cycle.

A0 - A12

Input

Address Inputs: Provide the row address for Active commands, and the column address and
Auto Precharge bit for Read/Write commands, to select one location out of the memory array in
the respective bank. A10 is sampled during a Precharge command to determine whether the Pre-
charge applies to one bank (A10 low) or all banks (A10 high). If only one bank is to be precharged,
the bank is selected by BA0, BA1. The address inputs also provide the op-code during a Mode
Register Set command.

Input/Output

Data Input/Output: Data bus.

DQS

Input/Output

Data Strobe: Output with read data, input with write data. Edge-aligned with read data, centered
in write data. Used to capture write data.

No Connect: No internal electrical connection is present.

Electrical connection is present. Should not be connected at second level of assembly.

DDQ

Supply

DQ Power Supply: 2.5V

0.2V.

SSQ

Supply

DQ Ground

Supply

Power Supply: 2.5V

0.2V.

Supply

Ground

REF

Supply

SSTL_2 reference voltage: (V

DDQ

/ 2)

1%.

NT5DS64M4AT NT5DS64M4AW
NT5DS32M8AT NT5DS32M8AW

256Mb Double Data Rate SDRAM

REV 1.3

08/2002

NANYA TECHNOLOGY CORP

NANYA TECHNOLOGY CORP. reserves the right to change Products and Specifications without notice.

Block Diagram (64Mb x 4)

c
e
i
v
e
r
s

DQS

CK, CK

DLL

RAS

CAS

CK
CS
WE

n
t
r
o
l

L

o
g

i
c

Column-Address

Counter/Latch

Mode

o
m

n
d

c
o
d

A0-A12,

BA0, BA1

CKE

I/O Gating

DM Mask Logic

Bank0

Memory

Array

(8192 x 1024 x 8)

Sense Amplifiers

Bank1

Bank2

Bank3

f
r
e
s
h

o
u

n
t
e

Input

clk

out

Data

Mask

Data

CK,

COL0

clk

DQS

Generator

4
4

DQ0-DQ3,
DM

DQS

e
a
d

a
t
c
h

Write

FIFO

Drivers

Note: This Functional Block Diagram is intended to facilitate user understanding of the operation of
the device; it does not represent an actual circuit implementation.

Note: DM is a unidirectional signal (input only), but is internally loaded to match the load of the bidi-
rectional DQ and DQS signals.

Column

Decoder

1024

(x8)

o
w

-
A

d
d

r
e

s
s

M

Registers

8
1

9
2

a
n
k
0

-
A

d
d

r
e

s
s

L
a

t
c
h

e
c
o

d
e

8192

d
r
e
s
s

R

g
i
s
t
e
r

r
i
v
e

r
s

a
n
k

C

n
t
r
o

l

L
o

g
i
c

NT5DS64M4AT NT5DS64M4AW
NT5DS32M8AT NT5DS32M8AW

256Mb Double Data Rate SDRAM

REV 1.3

08/2002

NANYA TECHNOLOGY CORP

NANYA TECHNOLOGY CORP. reserves the right to change Products and Specifications without notice.

Block Diagram (32Mb x 8)

c
e
i
v
e
r
s

DQS

CK, CK

DLL

RAS

CAS

CK
CS
WE

n
t
r
o
l

L

o
g

i
c

Column-Address

Counter/Latch

Mode

n
d

e
c
o

d
e

A0-A12,

BA0, BA1

CKE

I/O Gating

DM Mask Logic

Bank0

Memory

Array

(8192 x 512 x 16)

Sense Amplifiers

Bank1

Bank2

Bank3

f
r
e
s
h

C

u
n

t
e
r

Input

clk

out

Data

Mask

Data

CK,

COL0

clk

DQS

Generator

8
8

DQ0-DQ7,

DQS

a
d

L
a

t
c
h

Write

FIFO

Drivers

Note: This Functional Block Diagram is intended to facilitate user understanding of the operation of
the device; it does not represent an actual circuit implementation.

Note: DM is a unidirectional signal (input only), but is internally loaded to match the load of the bidi-
rectional DQ and DQS signals.

Column

Decoder

512

(x16)

-
A

d
d

r
e

s
s

M

Registers

8
1

9
2

n
k
0

-
A

d
r
e
s
s

L
a

t
c
h

e
c
o

d
e

8192

d
d

r
e

s
s

R

e
g

i
s
t
e
r

r
i
v
e

r
s

n
k

C

n
t
r
o
l

L

o
g

i
c

NT5DS64M4AT NT5DS64M4AW
NT5DS32M8AT NT5DS32M8AW

256Mb Double Data Rate SDRAM

REV 1.3

08/2002

NANYA TECHNOLOGY CORP

NANYA TECHNOLOGY CORP. reserves the right to change Products and Specifications without notice.

Functional Description

The 256Mb DDR SDRAM is a high-speed CMOS, dynamic random-access memory containing 268, 435, 456 bits. The 256Mb
DDR SDRAM is internally configured as a quad-bank DRAM.

The 256Mb DDR SDRAM uses a double-data-rate architecture to achieve high-speed operation. The double-data-rate architec-
ture is essentially a 2n prefetch architecture, with an interface designed to transfer two data words per clock cycle at the I/O
pins. A single read or write access for the 256Mb DDR SDRAM consists of a single 2n-bit wide, one clock cycle data transfer at
the internal DRAM core and two corresponding n-bit wide, one-half clock cycle data transfers at the I/O pins.

Read and write accesses to the DDR SDRAM are burst oriented; accesses start at a selected location and continue for a pro-
grammed number of locations in a programmed sequence. Accesses begin with the registration of an Active command, which is
then followed by a Read or Write command. The address bits registered coincident with the Active command are used to select
the bank and row to be accessed (BA0, BA1 select the bank; A0-A12 select the row). The address bits registered coincident
with the Read or Write command are used to select the starting column location for the burst access.

Prior to normal operation, the DDR SDRAM must be initialized. The following sections provide detailed infor-mation covering
device initialization, register definition, command descriptions and device operation.

Initialization

Only one of the following two conditions must be met.
· No power sequencing is specified during power up or power down given the following criteria:

and V

DDQ

are driven from a single power converter output

meets the specification

A minimum resistance of 42 ohms limits the input current from the VTT supply into any pin and
V

REF

tracks V

DDQ

or
· The following relationships must be followed:

DDQ

is driven after or with V

such that V

DDQ

< V

+ 0.3V

is driven after or with V

DDQ

such that V

< V

DDQ

+ 0.3V

REF

is driven after or with V

DDQ

such that V

REF

< V

DDQ

+ 0.3V

The DQ and DQS outputs are in the High-Z state, where they remain until driven in normal operation (by a read access). After-
all power supply and reference voltages are stable, and the clock is stable, the DDR SDRAM requires a 200

s delay prior to

applying an executable command.

Once the 200

s delay has been satisfied, a Deselect or NOP command should be applied, and CKE must be brought HIGH.

Following the NOP command, a Precharge ALL command must be applied. Next a Mode Register Set command must be
issued for the Extended Mode Register, to enable the DLL, then a Mode Register Set command must be issued for the Mode
Register, to reset the DLL, and to program the operating parameters. 200 clock cycles are required between the DLL reset and
any read command. A Precharge ALL command should be applied, placing the device in the "all banks idle" state

Once in the idle state, two auto refresh cycles must be performed. Additionally, a Mode Register Set command for the Mode
Register, with the reset DLL bit deactivated (i.e. to program operating parameters without resetting the DLL) must be performed.
Following these cycles, the DDR SDRAM is ready for normal operation.

DDR SDRAM's may be reinitialized at any time during normal operation by asserting a valid MRS command to either the base
or extended mode registers without affecting the contents of the memory array. The contents of either the mode register or
extended mode register can be modified at any valid time during device operation without affecting the state of the internal
address refresh counters used for device refresh.

NT5DS64M4AT NT5DS64M4AW
NT5DS32M8AT NT5DS32M8AW

256Mb Double Data Rate SDRAM

REV 1.3

08/2002

NANYA TECHNOLOGY CORP

NANYA TECHNOLOGY CORP. reserves the right to change Products and Specifications without notice.

Register Definition

Mode Register

The Mode Register is used to define the specific mode of operation of the DDR SDRAM. This definition includes the selection of
a burst length, a burst type, a CAS latency, and an operating mode. The Mode Register is programmed via the Mode Register
Set command (with BA0 = 0 and BA1 = 0) and retains the stored information until it is programmed again or the device loses
power (except for bit A8, which is self-clearing).

Mode Register bits A0-A2 specify the burst length, A3 specifies the type of burst (sequential or interleaved), A4-A6 specify the
CAS latency, and A7-A12 specify the operating mode.

The Mode Register must be loaded when all banks are idle, and the controller must wait the specified time before initiating the
subsequent operation. Violating either of these requirements results in unspecified operation.

Burst Length

Read and write accesses to the DDR SDRAM are burst oriented, with the burst length being programmable. The burst length
determines the maximum number of column locations that can be accessed for a given Read or Write command. Burst lengths
of 2, 4, or 8 locations are available for both the sequential and the interleaved burst types.

Reserved states should not be used, as unknown operation or incompatibility with future versions may result.

When a Read or Write command is issued, a block of columns equal to the burst length is effectively selected. All accesses for
that burst take place within this block, meaning that the burst wraps within the block if a boundary is reached. The block is
uniquely selected by A1-Ai when the burst length is set to two, by A

-Ai when the burst length is set to four and by A

-Ai when

the burst length is set to eight (where Ai is the most significant column address bit for a given configuration). The remaining
(least significant) address bit(s) is (are) used to select the starting location within the block. The programmed burst length
applies to both Read and Write bursts.

NT5DS64M4AT NT5DS64M4AW
NT5DS32M8AT NT5DS32M8AW

256Mb Double Data Rate SDRAM

REV 1.3

08/2002

NANYA TECHNOLOGY CORP

NANYA TECHNOLOGY CORP. reserves the right to change Products and Specifications without notice.

Mode Register Operation

CAS Latency

Burst Length

Address Bus

CAS Latency

Latency

Reserved

2.5

Reserved

Burst Length

Burst Length

Reserved

BA1

BA0

A11 A10

A 9

Mode Register

Operating Mode

* BA0 and BA1 must be 0, 0 to select the Mode Register

(vs. the Extended Mode Register).

A12

- A9

A 7

A6 - A0

Operating Mode

Valid

Normal operation

Do not reset DLL

Valid

Normal operation

in DLL Reset

VS**

Vendor-Specific

Test Mode

Reserved

A 3

Burst

Type

Sequential

Interleave

VS ** Vendor Specific

A12

NT5DS64M4AT NT5DS64M4AW
NT5DS32M8AT NT5DS32M8AW

256Mb Double Data Rate SDRAM

REV 1.3

08/2002

NANYA TECHNOLOGY CORP

NANYA TECHNOLOGY CORP. reserves the right to change Products and Specifications without notice.

Notes:

1. For a burst length of two, A1-A i selects the two-data-element block; A0 selects the first access within the block.
2. For a burst length of four, A2-A i selects the four-data-element block; A0-A1 selects the first access within the block.
3. For a burst length of eight, A3-A i selects the eight-data- element block; A0-A2 selects the first access within the block.
4. Whenever a boundary of the block is reached within a given sequence above, the following access wraps within the block.

Burst Type

Accesses within a given burst may be programmed to be either sequential or interleaved; this is referred to as the burst type
and is selected via bit A3. The ordering of accesses within a burst is determined by the burst length, the burst type and the start-
ing column address, as shown in Burst Definition on page 11.

Read Latency

The Read latency, or CAS latency, is the delay, in clock cycles, between the registration of a Read command and the availability
of the first burst of output data. The latency can be programmed 2 or 2.5 clocks.

If a Read command is registered at clock edge n, and the latency is m clocks, the data is available nominally coincident with
clock edge n + m.

Reserved states should not be used as unknown operation or incompatibility with future versions may result.

Burst Definition

Burst Length

Starting Column Address

Order of Accesses Within a Burst

Type = Sequential

Type = Interleaved

0-1

1-0

0-1-2-3

1-2-3-0

1-0-3-2

2-3-0-1

3-0-1-2

3-2-1-0

0-1-2-3-4-5-6-7

1-2-3-4-5-6-7-0

1-0-3-2-5-4-7-6

2-3-4-5-6-7-0-1

2-3-0-1-6-7-4-5

3-4-5-6-7-0-1-2

3-2-1-0-7-6-5-4

4-5-6-7-0-1-2-3

5-6-7-0-1-2-3-4

5-4-7-6-1-0-3-2

6-7-0-1-2-3-4-5

6-7-4-5-2-3-0-1

7-0-1-2-3-4-5-6

7-6-5-4-3-2-1-0

NT5DS64M4AT NT5DS64M4AW
NT5DS32M8AT NT5DS32M8AW

256Mb Double Data Rate SDRAM

REV 1.3

08/2002

NANYA TECHNOLOGY CORP

NANYA TECHNOLOGY CORP. reserves the right to change Products and Specifications without notice.

Operating Mode

The normal operating mode is selected by issuing a Mode Register Set Command with bits A7-A12 to zero, and bits A0-A6 set
to the desired values. A DLL reset is initiated by issuing a Mode Register Set command with bits A7 and A9-A12 each set to
zero, bit A8 set to one, and bits A0-A6 set to the desired values. A Mode Register Set command issued to reset the DLL should
always be followed by a Mode Register Set command to select normal operating mode.

All other combinations of values for A7-A12 are reserved for future use and/or test modes. Test modes and reserved states
should not be used as unknown operation or incompatibility with future versions may result.

CAS Latencies

NOP

Read

CAS Latency = 2, BL = 4

Shown with nominal t

, t

DQSCK

, and t

DQSQ

CK
CK

Command

DQS

Don't Care

CL=2

NOP

Read

CAS Latency = 2.5, BL = 4

CK
CK

Command

DQS

CL=2.5

NT5DS64M4AT NT5DS64M4AW
NT5DS32M8AT NT5DS32M8AW

256Mb Double Data Rate SDRAM

REV 1.3

08/2002

NANYA TECHNOLOGY CORP

NANYA TECHNOLOGY CORP. reserves the right to change Products and Specifications without notice.

Extended Mode Register

The Extended Mode Register controls functions beyond those controlled by the Mode Register; these additional functions
include DLL enable/disable, bit A0; output drive strength selection, bit A1; and QFC output enable/disable, bit A2 (NTC
optional). These functions are controlled via the bit settings shown in the Extended Mode Register Definition. The Extended
Mode Register is programmed via the Mode Register Set command (with BA0 = 1 and BA1 = 0) and retains the stored informa-
tion until it is programmed again or the device loses power. The Extended Mode Register must be loaded when all banks are
idle, and the controller must wait the specified time before initiating any subsequent operation. Violating either of these require-
ments result in unspecified operation.

DLL Enable/Disable

The DLL must be enabled for normal operation. DLL enable is required during power up initialization, and upon returning to nor-
mal operation after having disabled the DLL for the purpose of debug or evaluation. The DLL is automatically disabled when
entering self refresh operation and is automatically re-enabled upon exit of self refresh operation. Any time the DLL is enabled,
200 clock cycles must occur to allow time for the internal clock to lock to the externally applied clock before a Read command
can be issued. This is the reason for introducing timing parameter t

XSRD

for DDR SDRAM's (Exit Self Refresh to Read Com-

mand). Non- Read commands can be issued 2 clocks after the DLL is enabled via the EMRS command (t

MRD

) or 10 clocks after

the DLL is enabled via self refresh exit command (t

XSNR

, Exit Self Refresh to Non-Read Command).

Output Drive Strength

The normal drive strength for all outputs is specified to be SSTL_2, Class II.

QFC Enable/Disable

The QFC signal is an optional DRAM output control used to isolate module loads (DIMMs) from the system memory bus by
means of external FET switches when the given module (DIMM) is not being accessed. The QFC function is an optional feature
for NTC and is not included on all DDR SDRAM devices. Refer to the DDR SDRAM Device Labeling Table for proper differenti-
ation when ordering DDR devices with or without the QFC function. The QFC output is an open drain driver and must be con-
nected to V

DDQ

through a pull up resistor at the board level if the QFC function is enabled. The recommended pull up resistance

is 150 ohms.

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Commands

Truth Tables 1a and 1b provide a reference of the commands supported by DDR SDRAM devices. A verbal description of each
commands follows.

Truth Table 1a: Commands

Name (Function)

RAS

CAS

Address

MNE

Notes

Deselect (Nop)

NOP

1, 9

No Operation (Nop)

NOP

1, 9

Active (Select Bank And Activate Row)

Bank/Row

ACT

1, 3

Read (Select Bank And Column, And Start Read Burst)

Bank/Col

Read

1, 4

Write (Select Bank And Column, And Start Write Burst)

Bank/Col

Write

1, 4

Burst Terminate

BST

1, 8

Precharge (Deactivate Row In Bank Or Banks)

Code

PRE

1, 5

Auto Refresh Or Self Refresh (Enter Self Refresh Mode)

AR / SR

1, 6, 7

Mode Register Set

Op-Code

MRS

1, 2

1. CKE is high for all commands shown except Self Refresh.
2. BA0, BA1 select either the Base or the Extended Mode Register (BA0 = 0, BA1 = 0 selects Mode Register; BA0 = 1, BA1 = 0 selects

Extended Mode Register; other combinations of BA0-BA1 are reserved; A0-A12 provide the op-code to be written to the selected Mode
Register.)

3. B A0-BA1 provide bank address and A0-A 12 provide row address.
4. BA0, BA1 provide bank address; A0-Ai provide column address (where i = 9 for x8 and 9, 11 for x4); A10 high enables the Auto Pre-

charge feature (nonpersistent), A10 low disables the Auto Precharge feature.

5. A10 LOW: BA0, BA1 determine which bank is precharged.

A10 HIGH: all banks are precharged and BA0, BA1 are "Don't Care."

6. This command is auto refreshif CKE is high; Self Refresh if CKE is low.
7. Internal refresh counter controls row and bank addressing; all inputs and I/Os are "Don't Care" except for CKE.
8. Applies only to read bursts with Auto Precharge disabled; this command is undefined (and should not be used) for read bursts with Auto

Precharge enabled or for write bursts

9. Deselect and NOP are functionally interchangeable.

Truth Table 1b: DM Operation

Name (Function)

DQs

Notes

Write Enable

Valid

Write Inhibit

1. Used to mask write data; provided coincident with the corresponding data.

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Deselect

The Deselect function prevents new commands from being executed by the DDR SDRAM. The DDR SDRAM is
effectively deselected. Operations already in progress are not affected.

No Operation (NOP)

The No Operation (NOP) command is used to perform a NOP to a DDR SDRAM. This prevents unwanted commands from
being registered during idle or wait states. Operations already in progress are not affected.

Mode Register Set

The mode registers are loaded via inputs A0-A12, BA0 and BA1 while issuing the Mode Register Set Command. See mode reg-
ister descriptions in the Register Definition section. The Mode Register Set command can only be issued when all banks are idle
and no bursts are in progress. A subsequent executable command cannot be issued until t

MRD

is met.

Active

The Active command is used to open (or activate) a row in a particular bank for a subsequent access. The value on the BA0,
BA1 inputs selects the bank, and the address provided on inputs A0-A12 selects the row. This row remains active (or open) for
accesses until a Precharge (or Read or Write with Auto Precharge) is issued to that bank. A Precharge (or Read or Write with
Auto Precharge) command must be issued and completed before opening a different row in the same bank.

Read

The Read command is used to initiate a burst read access to an active (open) row. The value on the BA0, BA1 inputs selects
the bank, and the address provided on inputs A0-Ai, Aj (where [i = 9, j = don't care] for x8; where [i = 9, j = 11] for x4) selects the
starting column location. The value on input A10 determines whether or not Auto Precharge is used. If Auto Precharge is
selected, the row being accessed is precharged at the end of the Read burst; if Auto Precharge is not selected, the row remains
open for subsequent accesses.

Write

The Write command is used to initiate a burst write access to an active (open) row. The value on the BA0, BA1 inputs selects
the bank, and the address provided on inputs A0-Ai, Aj (where [i = 9, j = don't care] for x8; where [i = 9, j = 11] for x4) selects the
starting column location. The value on input A10 determines whether or not Auto Precharge is used. If Auto Precharge is
selected, the row being accessed is precharged at the end of the Write burst; if Auto Precharge is not selected, the row remains
open for subsequent accesses. Input data appearing on the DQs is written to the memory array subject to the DM input logic
level appearing coincident with the data. If a given DM signal is registered low, the corresponding data is written to memory; if
the DM signal is registered high, the corresponding data inputs are ignored, and a Write is not executed to that byte/column
location.

Precharge

The Precharge command is used to deactivate (close) the open row in a particular bank or the open row(s) in all banks. The
bank(s) will be available for a subsequent row access a specified time (t

) after the Precharge command is issued. Input A10

determines whether one or all banks are to be precharged, and in the case where only one bank is to be precharged, inputs
BA0, BA1 select the bank. Otherwise BA0, BA1 are treated as "Don't Care." Once a bank has been precharged, it is in the idle
state and must be activated prior to any Read or Write commands being issued to that bank. A precharge command is treated
as a NOP if there is no open row in that bank, or if the previously open row is already in the process of precharging.

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Auto Precharge

Auto Precharge is a feature which performs the same individual-bank precharge function described above, but without requiring
an explicit command. This is accomplished by using A10 to enable Auto Precharge in conjunction with a specific Read or Write
command. A precharge of the bank/row that is addressed with the Read or Write command is automatically performed upon
completion of the Read or Write burst. Auto Precharge is nonpersistent in that it is either enabled or disabled for each individual
Read or Write command. Auto Precharge ensures that the precharge is initiated at the earliest valid stage within a burst. This is
determined as if an explicit Precharge command was issued at the earliest possible time without violating t

RAS

(min). The user

must not issue another command to the same bank until the precharge (t

) is completed.

The NTC DDR SDRAM devices supports the optional t

RAS

lockout feature. This feature allows a Read command with Auto Pre-

charge to be issued to a bank that has been activated (opened) but has not yet satisfied the t

RAS

(min) specification. The t

RAS

lockout feature essentially delays the onset of the auto precharge operation until two conditions occur. One, the entire burst
length of data has been successfully prefetched from the memory array; and two, t

RAS

(min) has been satisfied.

As a means to specify whether a DDR SDRAM device supports the t

RAS

lockout feature, a new parameter has been defined,

RAP

(RAS Command to Read Command with Auto Precharge or better stated Bank Activate to Read Command with Auto Pre-

charge). For devices that support the t

RAS

lockout feature, t

RAP

= t

RCD

(min). This allows any Read Command (with or without

Auto Precharge) to be issued to an open bank once t

RCD

(min) is satisfied.

Burst Terminate

The Burst Terminate command is used to truncate read bursts (with Auto Precharge disabled). The most re-cently registered
Read command prior to the Burst Terminate command is truncated, as shown in the Operation section of this data sheet. Write
burst cycles are not to be terminated with the Burst Terminate command.

RAP

Definition

CK
CK

Command

DQ (BL=2)

RAPmin

NOP

ACT

NOP

RD A

NOP

ACT

NOP

RCDmin

RASmin

DQ0

DQ1

The above timing diagrams show the effects of t

RAP

for devices that support t

RAS

lockout. In these cases, the Read

with Auto Precharge command (RDA) is issued with t

RCD

(min) and dataout is available with the shortest latency from the

Bank Activate command (ACT). The internal precharge operation, however, does not begin until after t

RAS

(min) is satisfied.

CL=2, t

=10ns

Command

DQ (BL=4)

NOP

ACT

NOP

RD A

NOP

ACT

NOP

DQ0

DQ1

DQ2

DQ3

Command

DQ (BL=8)

NOP

ACT

NOP

RD A

NOP

ACT

NOP

DQ0

DQ1

DQ2

DQ3

DQ4

DQ5

DQ6

DQ7

Indicates Auto Precharge begins here

RPmin

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Auto Refresh

Auto Refresh is used during normal operation of the DDR SDRAM and is analogous to CAS Before RAS (CBR) Refresh in pre-
vious DRAM types. This command is nonpersistent, so it must be issued each time a refresh is required.

The refresh addressing is generated by the internal refresh controller. This makes the address bits "Don't Care" during an Auto
Refresh command. The 256Mb DDR SDRAM requires Auto Refresh cycles at an average periodic interval of 7.8

s (maximum).

Self Refresh

The Self Refresh command can be used to retain data in the DDR SDRAM, even if the rest of the system is powered down.
When in the self refresh mode, the DDR SDRAM retains data without external clocking. The Self Refresh command is initiated
as an Auto Refresh command coincident with CKE transitioning low. The DLL is automatically disabled upon entering Self
Refresh, and is automatically enabled upon exiting Self Refresh (200 clock cycles must then occur before a Read command can
be issued). Input signals except CKE (low) are "Don't Care" during Self Refresh operation.

The procedure for exiting self refresh requires a sequence of commands. CK (and CK) must be stable prior to CKE returning
high. Once CKE is high, the SDRAM must have NOP commands issued for t

XSNR

because time is required for the completion of

any internal refresh in progress. A simple algorithm for meeting both refresh and DLL requirements is to apply NOPs for 200
clock cycles before applying any other command.

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Operations

Bank/Row Activation

Before any Read or Write commands can be issued to a bank within the DDR SDRAM, a row in that bank must be "opened"
(activated). This is accomplished via the Active command and addresses A0-A12, BA0 and BA1 (see Activating a Specific Row
in a Specific Bank), which decode and select both the bank and the row to be activated. After opening a row (issuing an Active
command), a Read or Write command may be issued to that row, subject to the t

RCD

specification. A subsequent Active com-

mand to a different row in the same bank can only be issued after the previous active row has been "closed" (precharged). The
minimum time interval between successive Active commands to the same bank is defined by t

. A subsequent Active com-

mand to another bank can be issued while the first bank is being accessed, which results in a reduction of total row-access
overhead. The minimum time interval between successive Active commands to different banks is defined by t

RRD

Activating a Specific Row in a Specific Bank

HIGH

RA = row address.
BA = bank address.

CKE

RAS

CAS

A0-A12

BA0, BA1

Don't Care

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Reads

Subsequent to programming the mode register with CAS latency, burst type, and burst length, Read bursts are initiated with a
Read command.

The starting column and bank addresses are provided with the Read command and Auto Precharge is either enabled or dis-
abled for that burst access. If Auto Precharge is enabled, the row that is accessed starts precharge at the completion of the
burst, provided t

RAS

has been satisfied. For the generic Read commands used in the following illustrations, Auto Precharge is

disabled.

During Read bursts, the valid data-out element from the starting column address is available following the CAS latency after the
Read command. Each subsequent data-out element is valid nominally at the next positive or negative clock edge (i.e. at the
next crossing of CK and CK). The following timing figure entitled "Read Burst: CAS Latencies (Burst Length=4)" illustrates the
general timing for each supported CAS latency setting. DQS is driven by the DDR SDRAM along with output data. The initial low
state on DQS is known as the read preamble; the low state coincident with the last data-out element is known as the read post-
amble. Upon completion of a burst, assuming no other commands have been initiated, the DQs and DQS goes High-Z. Data
from any Read burst may be concatenated with or truncated with data from a subsequent Read command. In either case, a con-
tinuous flow of data can be maintained. The first data element from the new burst follows either the last element of a completed
burst or the last desired data element of a longer burst which is being truncated. The new Read command should be issued x
cycles after the first Read command, where x equals the number of desired data element pairs (pairs are required by the 2n
prefetch architecture). This is shown in timing figure entitled "Consecutive Read Bursts: CAS Latencies (Burst Length =4 or 8)".
A Read command can be initiated on any positive clock cycle following a previous Read command. Nonconsecutive Read data
is shown in timing figure entitled "Non-Consecutive Read Bursts: CAS Latencies (Burst Length = 4)". Full-speed Random Read
Accesses: CAS Latencies (Burst Length = 2, 4 or 8) within a page (or pages) can be performed as shown on page 25.

RCD

and t

RRD

Definition

ROW

ACT

NOP

COL

ROW

BA y

BA x

ACT

NOP

CK
CK

Command

A0-A12

BA0, BA1

Don't Care

RD/WR

RCD

RRD

RD/WR

NOP

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Consecutive Read Bursts: CAS Latencies (Burst Length = 4 or 8)

CAS Latency = 2

NOP

Read

NOP

Read

CK
CK

Command

Address

DQS

CL=2

BAa, COL n

BAa, COL b

Don't Care

DO a-n (or a-b) = data out from bank a, column n (or bank a, column b).
When burst length = 4, the bursts are concatenated.
When burst length = 8, the second burst interrupts the first.
3 subsequent elements of data out appear in the programmed order following DO a-n.
3 (or 7) subsequent elements of data out appear in the programmed order following DO a-b.
Shown with nominal t

, t

DQSCK

, and t

DQSQ

CAS Latency = 2.5

NOP

Read

NOP

Read

CK
CK

Command

Address

DQS

CL=2.5

BAa, COL n

BAa,COL b

DOa-n

DOa- n

DOa- b

DOa-b

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Data from any Read burst may be truncated with a Burst Terminate command, as shown in timing figure entitled Terminating a
Read Burst: CAS Latencies (Burst Length = 8) on page 27. The Burst Terminate latency is equal to the read (CAS) latency, i.e.
the Burst Terminate command should be issued x cycles after the Read command, where x equals the number of desired data
element pairs.

Data from any Read burst must be completed or truncated before a subsequent Write command can be issued. If truncation is
necessary, the Burst Terminate command must be used, as shown in timing figure entitled Read to Write: CAS Latencies (Burst
Length = 4 or 8) on page 28. The example is shown for t

DQSS

(min). The t

DQSS

(max) case, not shown here, has a longer bus idle

time. t

DQSS

(min) and t

DQSS

(max) are defined in the section on Writes.

A Read burst may be followed by, or truncated with, a Precharge command to the same bank (provided that Auto Precharge
was not activated). The Precharge command should be issued x cycles after the Read command, where x equals the number of
desired data element pairs (pairs are required by the 2n prefetch architecture). This is shown in timing figure Read to Pre-
charge: CAS Latencies (Burst Length = 4 or 8) on page 29 for Read latencies of 2 and 2.5. Following the Precharge command,
a subsequent command to the same bank cannot be issued until t

is met. Note that part of the row precharge time is hidden

during the access of the last data elements.

In the case of a Read being executed to completion, a Precharge command issued at the optimum time (as described above)
provides the same operation that would result from the same Read burst with Auto Precharge enabled. The disadvantage of the
Precharge command is that it requires that the command and address busses be available at the appropriate time to issue the
command. The advantage of the Precharge command is that it can be used to truncate bursts.

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Writes

Write bursts are initiated with a Write command, as shown in timing figure Write Command on page 31.

The starting column and bank addresses are provided with the Write command, and Auto Precharge is either enabled or dis-
abled for that access. If Auto Precharge is enabled, the row being accessed is precharged at the completion of the burst. For
the generic Write commands used in the following illustrations, Auto Precharge is disabled.

During Write bursts, the first valid data-in element is registered on the first rising edge of DQS following the write command, and
subsequent data elements are registered on successive edges of DQS. The Low state on DQS between the Write command
and the first rising edge is known as the write preamble; the Low state on DQS following the last data-in element is known as
the write postamble. The time between the Write command and the first corresponding rising edge of DQS (t

DQSS

) is specified

with a relatively wide range (from 75% to 125% of one clock cycle), so most of the Write diagrams that follow are drawn for the
two extreme cases (i.e. t

DQSS

(min) and t

DQSS

(max)). Timing figure Write Burst (Burst Length = 4) on page 32 shows the two

extremes of t

DQSS

for a burst of four. Upon completion of a burst, assuming no other commands have been initiated, the DQs

and DQS enters High-Z and any additional input data is ignored.

Data for any Write burst may be concatenated with or truncated with a subsequent Write command. In either case, a continuous
flow of input data can be maintained. The new Write command can be issued on any positive edge of clock following the previ-
ous Write command. The first data element from the new burst is applied after either the last element of a completed burst or
the last desired data element of a longer burst which is being truncated. The new Write command should be issued x cycles
after the first Write command, where x equals the number of desired data element pairs (pairs are required by the 2n prefetch
architecture). Timing figure Write to Write (Burst Length = 4) on page 33 shows concatenated bursts of 4. An example of non-
consecutive Writes is shown in timing figure Write to Write: Max DQSS, Non-Consecutive (Burst Length = 4) on page 34. Full-
speed random write accesses within a page or pages can be performed as shown in timing figure Random Write Cycles (Burst
Length = 2, 4 or 8) on page 35. Data for any Write burst may be followed by a subsequent Read command. To follow a Write
without truncating the write burst, t

WTR

(Write to Read) should be met as shown in timing figure Write to Read: Non-Interrupting

(CAS Latency = 2; Burst Length = 4) on page 36.

Data for any Write burst may be truncated by a subsequent (interrupting) Read command. This is illustrated in timing figures
"Write to Read: Interrupting (CAS Latency =2; Burst Length = 8)", "Write to Read: Minimum D

QSS

, Odd Number of Data (3 bit

Write), Interrupting (CAS Latency = 2; Burst Length = 8)", and "Write to Read: Nominal D

QSS

, Interrupting (CAS Latency = 2;

Burst Length = 8)". Note that only the data-in pairs that are registered prior to the t

WTR

period are written to the internal array,

and any subsequent data-in must be masked with DM, as shown in the diagrams noted previously.

Data for any Write burst may be followed by a subsequent Precharge command. To follow a Write without truncating the write
burst, t

should be met as shown in timing figure Write to Precharge: Non-Interrupting (Burst Length = 4) on page 40.

Data for any Write burst may be truncated by a subsequent Precharge command, as shown in timing figures Write to Pre-
charge: Interrupting (Burst Length = 4 or 8) on page 41 to Write to Precharge: Nominal DQSS (2 bit Write), Interrupting (Burst
Length = 4 or 8) on page 43. Note that only the data-in pairs that are registered prior to the t

period are written to the internal

array, and any subsequent data in should be masked with DM. Following the Precharge command, a subsequent command to
the same bank cannot be issued until t

is met.

In the case of a Write burst being executed to completion, a Precharge command issued at the optimum time (as described
above) provides the same operation that would result from the same burst with Auto Precharge. The disadvantage of the Pre-
charge command is that it requires that the command and address busses be available at the appropriate time to issue the com-
mand. The advantage of the Precharge command is that it can be used to truncate bursts.

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Write Burst (Burst Length = 4)

DQSS

(max)

NOP

Write

DI a-b = data in for bank a, column b.
3 subsequent elements of data in are applied in the programmed order following DI a- b.
A non-interrupted burst is shown.
A10 is Low with the Write command (Auto Precharge is disabled).

CK
CK

Command

Address

DQS

Don't Care

Maximum D

QSS

BA a, COL b

DQSS

(min)

NOP

Write

CK
CK

Command

Address

DQS

Minimum D

QSS

BA a, COL b

Dla-b

QFC

QCSW

(max)

QCHW

(min)

(Optional)

QFC

QCSW

(max)

QCHW

(max)

QFC is an open drain driver. Its output high level is achieved through an externally connected pull up resistor connected to V

DDQ

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Random Write Cycles (Burst Length = 2, 4 or 8)

DQSS

(max)

Maximum D

QSS

Write

DI a-b

DI a-n

DI a-b, etc. = data in for bank a, column b, etc.
b', etc. = odd or even complement of b, etc. (i.e., column address LSB inverted).
Each Write command may be to any bank.

DI a-b'

DI a-x

DI a-x'

DI a-n'

DI a-a

DI a-a'

CK
CK

Command

Address

DQS

Don't Care

BAa, COL b

BAa, COL x

BAa, COL n

BAa, COL a

BAa, COL g

Minimum D

QSS

Write

DI a-b

DI a-n

DI a-b'

DI a-x

DI a-x'

DI a-n'

DI a-a

DI a-a'

CK
CK

Command

Address

DQS

BAa, COL b

BAa, COL x

BAa, COL n

BAa, COL a

BAa, COL g

DQSS

(min)

DI a-g

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Write to Read: Non-Interrupting (CAS Latency = 2; Burst Length = 4)

CL = 2

WTR

NOP

Read

Write

DI a- b

NOP

DI a-b = data in for bank a, column b.
3 subsequent elements of data in are applied in the programmed order following DI a-b.
A non-interrupted burst is shown.
t

WTR

is referenced from the first positive CK edge after the last data in pair.

A10 is Low with the Write command (Auto Precharge is disabled).
The Read and Write commands may be to any bank.

Command

Address

DQS

Don't Care

Maximum D

QSS

BAa, COL b

BAa, COL n

WTR

NOP

Read

Write

NOP

Command

Address

Minimum D

QSS

BAa, COL b

BAa, COL n

DQSS

(max)

DI a- b

DQS

DQSS

(min)

CL = 2

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Write to Read: Interrupting (CAS Latency = 2; Burst Length = 8)

DQSS

(max)

Maximum D

QSS

NOP

Read

Write

NOP

DI a-b = data in for bank a, column b.
An interrupted burst is shown, 4 data elements are written.
3 subsequent elements of data in are applied in the programmed order following DI a-b.
t

WTR

is referenced from the first positive CK edge after the last data in pair.

The Read command masks the last 2 data elements in the burst.
A10 is Low with the Write command (Auto Precharge is disabled).
The Read and Write commands are not necessarily to the same bank.

DIa- b

CK
CK

Command

Address

DQS

Don't Care

BAa, COL b

BAa, COL n

W T R

CL = 2

Minimum D

QSS

NOP

Read

Write

NOP

CK
CK

Command

Address

BAa, COL b

BAa, COL n

WTR

DI a-b

DQS

CL = 2

DQSS

(min)

1 = These bits are incorrectly written into the memory array if DM is low.

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Write to Read: Minimum DQSS, Odd Number of Data (3 bit Write), Interrupting (CAS
Latency = 2; Burst Length = 8)

DI a-b = data in for bank a, column b.
An interrupted burst is shown, 3 data elements are written.
2 subsequent elements of data in are applied in the programmed order following DI a-b .
t

WTR

is referenced from the first positive CK edge after the last desired data in pair (not the last desired data in element)

The Read command masks the last 2 data elements in the burst.
A10 is Low with the Write command (Auto Precharge is disabled).
The Read and Write commands are not necessarily to the same bank.

Don't Care

NOP

Read

Write

NOP

CK
CK

Command

Address

BAa, COL b

BAa, COL n

W T R

DI a-b

DQS

CL = 2

DQSS

(min)

1 = This bit is correctly written into the memory array if DM is low.
2 = These bits are incorrectly written into the memory array if DM is low.

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Write to Read: Nominal DQSS, Interrupting (CAS Latency = 2; Burst Length = 8)

DQSS

(nom)

NOP

Read

Write

NOP

DI a-b = data in for bank a, column b.
An interrupted burst is shown, 4 data elements are written.
3 subsequent elements of data in are applied in the programmed order following DI a-b.
t

WTR

is referenced from the first positive CK edge after the last desired data in pair.

The Read command masks the last 2 data elements in the burst.
A10 is Low with the Write command (Auto Precharge is disabled).
The Read and Write commands are not necessarily to the same bank.

DI a- b

Command

Address

DQS

Don't Care

BAa, COL b

BAa, COL n

WTR

CL = 2

1 = These bits are incorrectly written into the memory array if DM is low.

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Write to Precharge: Non-Interrupting (Burst Length = 4)

DQSS

(max)

NOP

Write

DI a-b

PRE

DI a-b = data in for bank a, column b.
3 subsequent elements of data in are applied in the programmed order following DI a-b.
A non-interrupted burst is shown.

is referenced from the first positive CK edge after the last data in pair.

A10 is Low with the Write command (Auto Precharge is disabled).

Command

Address

DQS

Don't Care

BA a, COL b

BA (a or all)

Maximum D

QSS

NOP

Write

PRE

Command

Address

BA a, COL b

BA (a or all)

Minimum D

QSS

DI a-b

DQS

DQSS

(min)

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Write to Precharge: Interrupting (Burst Length = 4 or 8)

DI a- b = data in for bank a, column b.
An interrupted burst is shown, 2 data elements are written.
1 subsequent element of data in is applied in the programmed order following DI a-b.
t

is referenced from the first positive CK edge after the last desired data in pair.

The Precharge command masks the last 2 data elements in the burst, for burst length = 8.
A10 is Low with the Write command (Auto Precharge is disabled).

1 = Can be don't care for programmed burst length of 4.
2 = For programmed burst length of 4, DQS becomes don't care at this point.

Don't Care

NOP

PRE

Write

NOP

Command

Address

Maximum D

QSS

DI a-b

DQS

DQSS

(max)

R P

NOP

PRE

Write

NOP

Command

Address

BA a, COL b

BA (a or all)

Minimum D

QSS

R P

DI a-b

DQS

DQSS

(min)

BA a, COL b

BA (a or all)

3 = These bits are incorrectly written into the memory array if DM is low.

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Write to Precharge: Minimum DQSS, Odd Number of Data (1 bit Write), Interrupting
(Burst Length = 4 or 8)

DI a-b = data in for bank a, column b.
An interrupted burst is shown, 1 data element is written.
t

is referenced from the first positive CK edge after the last desired data in pair.

The Precharge command masks the last 2 data elements in the burst.
A10 is Low with the Write command (Auto Precharge is disabled).
1 = Can be don't care for programmed burst length of 4.
2 = For programmed burst length of 4, DQS becomes don't care at this point.

Don't Care

NOP

PRE

Write

NOP

Command

Address

BA a, COL b

BA (a or all)

DI a-b

DQS

DQSS

(min)

3 = This bit is correctly written into the memory array if DM is low.
4 = These bits are incorrectly written into the memory array if DM is low.

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Write to Precharge: Nominal DQSS (2 bit Write), Interrupting (Burst Length = 4 or 8)

DI a-b = Data In for bank a, column b.
An interrupted burst is shown, 2 data elements are written.
1 subsequent element of data in is applied in the programmed order following DI a-b.
t

is referenced from the first positive CK edge after the last desired data in pair.

Don't Care

NOP

PRE

Write

NOP

Command

Address

BA a, COL b

BA (a or all)

DQSS

(nom)

DI a-b

DQS

3 = These bits are incorrectly written into the memory array if DM is low.

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Precharge

The Precharge command is used to deactivate the open row in a particular bank or the open row in all banks. The
bank(s) is available for a subsequent row access some specified time (t

) after the Precharge command is

issued. Input A10 determines whether one or all banks are to be precharged, and in the case where only one bank
is to be precharged, inputs BA0, BA1 select the bank. When all banks are to be precharged, inputs BA0, BA1 are
treated as "Don't Care." Once a bank has been precharged, it is in the idle state and must be activated prior to any
Read or Write commands being issued to that bank.

Precharge Command

HIGH

BA = bank address

CKE

RAS

CAS

A10

BA0, BA1

Don't Care

All Banks

One Bank

(if A10 is Low, otherwise Don't Care).

A0-A9, A11, A12

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Power Down

Power Down mode is entered when CKE is registered low (no accesses can be in progress). If power down occurs when all
banks are idle, this mode is referred to as Precharge Power Down; if power down occurs when there is a row active in any bank,
this mode is referred to as Active Power Down. Entering Power Down deactivates the input and output buffers, excluding CK,
CK and CKE. The DLL is still running in Power Down mode, so for maximum power savings, the user has the option of disabling
the DLL prior to entering Power Down. In that case, the DLL must be enabled after exiting Power Down, and 200 clock cycles
must occur before a Read command can be issued. In Power Down mode, CKE Low and a stable clock signal must be main-
tained at the inputs of the DDR SDRAM, and all other input signals are "Don't Care". However, power down duration is limited
by the refresh requirements of the device, so in most applications, the self refresh mode is preferred over the DLL-disabled
Power Down mode.

The Power Down state is synchronously exited when CKE is registered high (along with a Nop or Deselect command). A valid,
executable command may be applied one clock cycle later.

Power Down

CK
CK

CKE

Command

No column

access in

progress

VALID

NOP

VALID

Don't Care

Exit

power down

mode

Enter Power Down mode

(Burst Read or Write operation

must not be in progress)

NOP

XARD

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Truth Table 2: Clock Enable (CKE)

1. CKE n is the logic state of CKE at clock edge n: CKE n-1 was the state of CKE at the previous clock edge.
2. Current state is the state of the DDR SDRAM immediately prior to clock edge n.
3. Command n is the command registered at clock edge n, and action n is a result of command n.
4. All states and sequences not shown are illegal or reserved.

Current State

CKE n-1

CKEn

Command n

Action n

Notes

Cycle

Current

Cycle

Self Refresh

Maintain Self-Refresh

Self Refresh

Deselect or NOP

Exit Self-Refresh

Power Down

Maintain Power Down

Power Down

Deselect or NOP

Exit Power Down

All Banks Idle

Deselect or NOP

Precharge Power Down Entry

All Banks Idle

Auto Refresh

Self Refresh Entry

Bank(s) Active

Deselect or NOP

Active Power Down Entry

See "Truth Table 3: Current State

Bank n - Command to Bank n (Same

Bank) " on page 47

1. Deselect or NOP commands should be issued on any clock edges occurring during the Self Refresh Exit (t

XSNR

) period. A minimum of

200 clock cycles are needed before applying a read command to allow the DLL to lock to the input clock.

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Truth Table 3: Current State Bank n - Command to Bank n (Same Bank)

Current State

RAS

CAS

Command

Action

Notes

Any

Deselect

NOP. Continue previous operation

1-6

No Operation

NOP. Continue previous operation

1-6

Idle

Active

Select and activate row

1-6

Auto Refresh

1-7

Mode Register Set

1-7

Row Active

Read

Select column and start Read burst

1-6, 10

Write

Select column and start Write burst

1-6, 10

Precharge

Deactivate row in bank(s)

1-6, 8

Read

(Auto Precharge

Disabled)

Read

Select column and start new Read burst

1-6, 10

Precharge

Truncate Read burst, start Precharge

1-6, 8

Burst Terminate

1-6, 9

Write

(Auto Precharge

Disabled)

Read

Select column and start Read burst

1-6, 10, 11

Write

Select column and start Write burst

1-6, 10

Precharge

Truncate Write burst, start Precharge

1-6, 8, 11

1. This table applies when CKE n-1 was high and CKE n is high (see Truth Table 2: Clock Enable (CKE) and after t

XSNR /

XSRD

has been

met (if the previous state was self refresh).

2. This table is bank-specific, except where noted, i.e., the current state is for a specific bank and the commands shown are those allowed

to be issued to that bank when in that state. Exceptions are covered in the notes below.

3. Current state definitions:

Idle:

The bank has been precharged, and t

has been met.

Row Active:

A row in the bank has been activated, and t

RCD

has been met. No data bursts/accesses and no register accesses are in

progress.

Read:

A Read burst has been initiated, with Auto Precharge disabled, and has not yet terminated or been terminated.

Write:

A Write burst has been initiated, with Auto Precharge disabled, and has not yet terminated or been terminated.

4. The following states must not be interrupted by a command issued to the same bank.

Precharging:

Starts with registration of a Precharge command and ends when t

R P

is met. Once t

is met, the bank is in the idle

state.

Row Activating: Starts with registration of an Active command and ends when t

RCD

is met. Once t

RCD

is met, the bank is in the "row

active" state.

Read w/Auto Precharge Enabled: Starts with registration of a Read command with Auto Precharge enabled and ends when t

has been

met. Once t

is met, the bank is in the idle state.

Write w/Auto Precharge Enabled: Starts with registration of a Write command with Auto Precharge enabled and ends when t

has been

met. Once t

is met, the bank is in the idle state.

Deselect or NOP commands, or allowable commands to the other bank should be issued on any clock edge occurring during these

states. Allowable commands to the other bank are determined by its current state and according to Truth Table 4.

5. The following states must not be interrupted by any executable command; Deselect or NOP commands must be applied on each positive

clock edge during these states.
Refreshing:

Starts with registration of an Auto Refresh command and ends when t

RFC

is met. Once t

RFC

is met, the DDR SDRAM is

in the "all banks idle" state.

Accessing Mode Register: Starts with registration of a Mode Register Set command and ends when t

MRD

has been met. Once t

MRD

met, the DDR SDRAM is in the "all banks idle" state.

Precharging All: Starts with registration of a Precharge All command and ends when t

is met. Once t

is met, all banks is in the idle

state.

6. All states and sequences not shown are illegal or reserved.
7. Not bank-specific; requires that all banks are idle.
8. May or may not be bank-specific; if all/any banks are to be precharged, all/any must be in a valid state for precharging.
9. Not bank-specific; Burst terminate affects the most recent Read burst, regardless of bank.

10. Reads or Writes listed in the Command/Action column include Reads or Writes with Auto Precharge enabled and Reads or Writes with

Auto Precharge disabled.

11. Requires appropriate DM masking.

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Truth Table 4: Current State Bank n - Command to Bank m (Different bank)

(Part 1 of 2)

Current State

RAS

CAS

Command

Action

Notes

Any

Deselect

NOP/continue previous operation

1-6

No Operation

NOP/continue previous operation

1-6

Idle

Any Command Otherwise

Allowed to Bank m

1-6

Row Activating,

Active, or

Precharging

Active

Select and activate row

1-6

Read

Select column and start Read burst

1-7

Write

Select column and start Write burst

1-7

Precharge

1-6

Read

(Auto Precharge

Disabled)

Active

Select and activate row

1-6

Read

Select column and start new Read burst

1-7

Precharge

1-6

Write

(Auto Precharge

Disabled)

Active

Select and activate row

1-6

Read

Select column and start Read burst

1-8

Write

Select column and start new Write burst

1-7

Precharge

1-6

1. This table applies when CKE n-1 was high and CKE n is high (see Truth Table 2: Clock Enable (CKE) and after t

XSNR /

XSRD

has been

met (if the previous state was self refresh).

2. This table describes alternate bank operation, except where noted, i.e., the current state is for bank n and the commands shown are

those allowed to be issued to bank m (assuming that bank m is in such a state that the given command is allowable). Exceptions are cov-
ered in the notes below.

3. Current state definitions:

Idle:

The bank has been precharged, and t

has been met.

Row Active:

A row in the bank has been activated, and t

RCD

has been met. No data bursts/accesses and no register accesses are

in progress.

Read:

A Read burst has been initiated, with Auto Precharge disabled, and has not yet terminated or been terminated.

Write:

A Write burst has been initiated, with Auto Precharge disabled, and has not yet terminated or been terminated.

Read with Auto Precharge Enabled: See note 10.
Write with Auto Precharge Enabled: See note 10.

4. Auto Refresh and Mode Register Set commands may only be issued when all banks are idle.
5. A Burst Terminate command cannot be issued to another bank; it applies to the bank represented by the current state only.
6. All states and sequences not shown are illegal or reserved.
7. Reads or Writes listed in the Command/Action column include Reads or Writes with Auto Precharge enabled and Reads or Writes with

Auto Precharge disabled.

8. Requires appropriate DM masking.
9. A Write command may be applied after the completion of data output.

10. The Read with Auto Precharge enabled or Write with Auto Precharge enabled states can each be broken into two parts: the access

period and the precharge period. For Read with Auto Precharge, the precharge period is defined as if the same burst was executed with
Auto Precharge disabled and then followed with the earliest possible Precharge command that still accesses all of the data in the burst.
For Write with Auto Precharge, the precharge period begins when t

ends, with t

measured as if Auto Precharge was disabled. The

access period starts with registration of the command and ends where the precharge period (or t

R P

) begins. During the precharge period

of the Read with Auto Precharge Enabled or Write with Auto Precharge Enabled states, Active, Precharge, Read, and Write commands
to the other bank may be applied; during the access period, only Active and Precharge commands to the other bank may be applied. In
either case, all other related limitations apply (e.g. contention between Read data and Write data must be avoided).

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Read (With

Auto Precharge)

Active

Select and activate row

1-6

Read

Select column and start new Read burst

1-7,10

Write

Select column and start Write burst

1-7,9,10

Precharge

1-6

Write (With

Auto Precharge)

Active

Select and activate row

1-6

Read

Select column and start Read burst

1-7,10

Write

Select column and start new Write burst

1-7,10

Precharge

1-6

Truth Table 4: Current State Bank n - Command to Bank m (Different bank)

(Part 2 of 2)

Current State

RAS

CAS

Command

Action

Notes

1. This table applies when CKE n-1 was high and CKE n is high (see Truth Table 2: Clock Enable (CKE) and after t

XSNR /

XSRD

has been

met (if the previous state was self refresh).

2. This table describes alternate bank operation, except where noted, i.e., the current state is for bank n and the commands shown are

those allowed to be issued to bank m (assuming that bank m is in such a state that the given command is allowable). Exceptions are cov-
ered in the notes below.

3. Current state definitions:

Idle:

The bank has been precharged, and t

has been met.

Row Active:

A row in the bank has been activated, and t

RCD

has been met. No data bursts/accesses and no register accesses are

in progress.

Read:

A Read burst has been initiated, with Auto Precharge disabled, and has not yet terminated or been terminated.

Write:

A Write burst has been initiated, with Auto Precharge disabled, and has not yet terminated or been terminated.

Read with Auto Precharge Enabled: See note 10.
Write with Auto Precharge Enabled: See note 10.

Auto Precharge disabled.

8. Requires appropriate DM masking.
9. A Write command may be applied after the completion of data output.

10. The Read with Auto Precharge enabled or Write with Auto Precharge enabled states can each be broken into two parts: the access

ends, with t

measured as if Auto Precharge was disabled. The

access period starts with registration of the command and ends where the precharge period (or t

R P

) begins. During the precharge period

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Simplified State Diagram

Self

Auto

Idle

MRS

EMRS

Row

Precharge

Power

Write

Power

ACT

Read A

Read

REFS

REFSX

REFA

CKEL

MRS

CKEH

CKEL

Write

Power

Applied

Automatic Sequence

Command Sequence

Read A

Write A

Read

PRE

Refresh

Down

Power

Down

Active

Read

Write A

Burst Stop

Preall

Active

Precharge

Preall

Read

Write

PREALL = Precharge All Banks

MRS = Mode Register Set

EMRS = Extended Mode Register Set

REFS = Enter Self Refresh

REFSX = Exit Self Refresh

REFA = Auto Refresh

CKEL = Enter Power Down

CKEH = Exit Power Down

ACT = Active

Write A = Write with Autoprecharge

Read A = Read with Autoprecharge

PRE = Precharge

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Absolute Maximum Ratings

Symbol

Parameter

Rating

Units

, V

OUT

Voltage on I/O pins relative to V

0.5 to V

DDQ

0.5

I N

Voltage on Inputs relative to V

0.5 to

3.6

Voltage on V

D D

supply relative to V

0.5 to

3.6

DDQ

Voltage on V

DDQ

supply relative to V

0.5 to

3.6

Operating Temperature (Ambient)

0 to

STG

Storage Temperature (Plastic)

55 to

150

Power Dissipation

1.0

OUT

Short Circuit Output Current

Note: Stresses greater than those listed under "Absolute Maximum Ratings" may cause permanent damage to the device. This is a stress rat-
ing only, and functional operation of the device at these or any other conditions above those indicated in the operational sections of this speci-
fication is not implied. Exposure to absolute maximum rating conditions for extended periods may affect reliability.

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Capacitance

Parameter

Symbol

Min.

Max.

Units

Notes

Input Capacitance: CK, CK

2.0

3.0

Delta Input Capacitance: CK, CK

delta CI

0.25

Input Capacitance: All other input-only pins (except DM)

2.0

3.0

Delta Input Capacitance: All other input-only pins (except DM)

delta CI

0.5

Input/Output Capacitance: DQ, DQS, DM

4.0

5.0

1, 2

Delta Input/Output Capacitance: DQ, DQS, DM

delta C

0.5

1. V

DDQ

= V

D D

= 2.5V ±

0.2V (minimum range to maximum range), f = 100MHz, T

= 25

C, VO

= V

DDQ/2

, VO

Peak -Peak

=0.2V.

2. Although DM is an input-only pin, the input capacitance of this pin must model the input capacitance of the DQ and DQS pins. This is

required to match input propagation times of DQ, DQS and DM in the system.

DC Electrical Characteristics and Operating Conditions

(0°C

= 2.5V

0.2V,

2.5V

0.2V, see AC Characteristics)

Symbol

Parameter

Min

Max

Units

Notes

Supply Voltage

2.3

2.7

DDQ

I/O Supply Voltage

2.3

2.7

, V

SSQ

Supply Voltage
I/O Supply Voltage

REF

I/O Reference Voltage

0.49 x V

DDQ

0.51 x V

DDQ

1, 2

I/O Termination Voltage (System)

REF

0.04

REF

0.04

1, 3

IH(DC)

Input High (Logic1) Voltage

REF

0.15

DDQ

0.3

IL(DC)

Input Low (Logic0) Voltage

0.3

REF

0.15

IN(DC)

Input Voltage Level, CK and CK Inputs

0.3

DDQ

0.3

ID(DC)

Input Differential Voltage, CK and CK Inputs

0.30

DDQ

0.6

1, 4

Ratio

V-I Matching Pullup Current to Pulldown Current Ratio

0.71

1.4

Input Leakage Current
Any input 0V

D D

; (All other pins not under test

0V)

Output Leakage Current
(DQs are disabled; 0V

out

DDQ

O H

Output Current: Nominal Strength Driver
High current (V

OUT

= V

DDQ

-0.373V, min V

REF

, min V

)

Low current (V

OUT

= 0.373V, max V

REF

, max V

)

16.8

OHW

Output Current: Half- Strength Driver
High current (V

OUT

= V

DDQ

-0.763V, min V

REF

, min V

)

Low current (V

OUT

= 0.763V, max V

REF

, max V

)

9.0

OLW

9.0

1. Inputs are not recognized as valid until V

REF

stabilizes.

2. V

REF

is expected to be equal to 0.5 V

DDQ

of the transmitting device, and to track variations in the DC level of the same. Peak-to-peak

noise on V

REF

may not exceed ± 2% of the DC value.

3. V

is not applied directly to the device. V

is a system supply for signal termination resistors, is expected to be set equal to V

REF

, and

must track variations in tHalf-he DC level of V

REF

4. V

is the magnitude of the difference between the input level on CK and the input level on CK .

5. The ratio of the pullup current to the pulldown current is specified for the same temperature and voltage, over the entire tempera-ture and

voltage range, for device drain to source voltages for 0.25 volts to 1.0 volts. For a given output, it represents the maximum difference
between pullup and pulldown drivers due to process variation.

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Normal Strength Driver Pulldown and Pullup Characteristics

1. The full variation in driver pulldown current from minimum to maximum process, temperature and voltage will lie within the

outer bounding lines of the V-I curve.

2. It is recommended that the "typical" IBIS pulldown V-I curve lie within the shaded region of the V-I curve.

3. The full variation in driver pullup current from minimum to maximum process, temperature and voltage will lie within the

outer bounding lines of the V-I curve.

4. It is recommended that the "typical" IBIS pullup V-I curve lie within the shaded region of the V-I curve.

5. The full variation in the ratio of the maximum to minimum pullup and pulldown current will not exceed 1.7, for device

drain to source voltages from 0.1 to 1.0.

6. The full variation in the ratio of the "typical" IBIS pullup to "typical" IBIS pulldown current should be unity + 10%, for device

drain to source voltages from 0.1 to 1.0. This specification is a design objective only. It is not guaranteed.

7. These characteristics are intended to obey the SSTL_2 class II standard.
8. This specification is intended for DDR SDRAM only.

Normal Strength Driver Pulldown Characteristics

Normal Strength Driver Pullup Characteristics

2.7

140

(
m

)

OUT

(V)

Maximum

Typical High

Typical Low

Minimum

Maximum

Typical High

Typical Low

Minimum

OUT

(V)

2.7

-200

(
m

)

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Normal Strength Driver Pulldown and Pullup Currents

Pulldown Current (mA)

Pullup Current (mA)

Voltage (V)

Typical

Low

Typical

High

Min

Max

Typical

Low

Typical

High

Min

Max

0.1

6.0

6.8

4.6

9.6

-6.1

-7.6

-4.6

-10.0

0.2

12.2

13.5

9.2

18.2

-12.2

-14.5

-9.2

-20.0

0.3

18.1

20.1

13.8

26.0

-18.1

-21.2

-13.8

-29.8

0.4

24.1

26.6

18.4

33.9

-24.0

-27.7

-18.4

-38.8

0.5

29.8

33.0

23.0

41.8

-29.8

-34.1

-23.0

-46.8

0.6

34.6

39.1

27.7

49.4

-34.3

-40.5

-27.7

-54.4

0.7

39.4

44.2

32.2

56.8

-38.1

-46.9

-32.2

-61.8

0.8

43.7

49.8

36.8

63.2

-41.1

-53.1

-36.0

-69.5

0.9

47.5

55.2

39.6

69.9

-43.8

-59.4

-38.2

-77.3

1.0

51.3

60.3

42.6

76.3

-46.0

-65.5

-38.7

-85.2

1.1

54.1

65.2

44.8

82.5

-47.8

-71.6

-39.0

-93.0

1.2

56.2

69.9

46.2

88.3

-49.2

-77.6

-39.2

-100.6

1.3

57.9

74.2

47.1

93.8

-50.0

-83.6

-39.4

-108.1

1.4

59.3

78.4

47.4

99.1

-50.5

-89.7

-39.6

-115.5

1.5

60.1

82.3

47.7

103.8

-50.7

-95.5

-39.9

-123.0

1.6

60.5

85.9

48.0

108.4

-51.0

-101.3

-40.1

-130.4

1.7

61.0

89.1

48.4

112.1

-51.1

-107.1

-40.2

-136.7

1.8

61.5

92.2

48.9

115.9

-51.3

-112.4

-40.3

-144.2

1.9

62.0

95.3

49.1

119.6

-51.5

-118.7

-40.4

-150.5

2.0

62.5

97.2

49.4

123.3

-51.6

-124.0

-40.5

-156.9

2.1

62.9

99.1

49.6

126.5

-51.8

-129.3

-40.6

-163.2

2.2

63.3

100.9

49.8

129.5

-52.0

-134.6

-40.7

-169.6

2.3

63.8

101.9

49.9

132.4

-52.2

-139.9

-40.8

-176.0

2.4

64.1

102.8

50.0

135.0

-52.3

-145.2

-40.9

-181.3

2.5

64.6

103.8

50.2

137.3

-52.5

-150.5

-41.0

-187.6

2.6

64.8

104.6

50.4

139.2

-52.7

-155.3

-41.1

-192.9

2.7

65.0

105.4

50.5

140.8

-52.8

-160.1

-41.2

-198.2

Normal Strength Driver Evaluation Conditions

Typical

Minimum

Maximum

Temperature (T

ambient

)

DDQ

2.5V

2.3V

2.7V

Process conditions

typical process

slow-slow process

fast-fast process

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AC Characteristics

(Notes 1-5 apply to the following Tables; Electrical Characteristics and DC Operating Conditions, AC Operating Conditions, I

Specifications and Conditions, and Electrical Characteristics and AC Timing.)

1. All voltages referenced to V

2. Tests for AC timing, I

, and electrical, AC and DC characteristics, may be conducted at nominal reference/supply voltage

levels, but the related specifications and device operation are guaranteed for the full voltage range specified.

3. Outputs measured with equivalent load. Refer to the AC Output Load Circuit below.
4. AC timing and I

tests may use a V

to V

swing of up to 1.5V in the test environment, but input timing is still referenced

to V

REF

(or to the crossing point for CK, CK), and parameter specifications are guaranteed for the specified AC input levels

under normal use conditions. The minimum slew rate for the input signals is 1V/ns in the range between V

IL(AC)

and

IH(AC)

5. The AC and DC input level specifications are as defined in the SSTL_2 Standard (i.e. the receiver effectively switches as a

result of the signal crossing the AC input level, and remains in that state as long as the signal does not ring back above
(below) the DC input low (high) level.

AC Output Load Circuit Diagrams

Timing Reference Point

Output

OUT

)

30pF

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AC Input Operating Conditions

(0 °C

;

DDQ

= 2.5V

0.2V; V

= 2.5V

0.2V, See AC

Characteristics)

Symbol

Parameter/Condition

Min

Max

Unit

Notes

IH(AC)

Input High (Logic 1) Voltage, DQ, DQS, and DM Signals

REF

+ 0.31

1, 2

IL(AC)

Input Low (Logic 0) Voltage, DQ, DQS, and DM Signals

REF

0.31

1, 2

ID(AC)

Input Differential Voltage, CK and CK Inputs

0.62

DDQ

+ 0.6

1, 2, 3

IX(AC)

Input Crossing Point Voltage, CK and CK Inputs

0.5*V

DDQ

0.2 0.5*V

DDQ

0.2

1, 2, 4

1. Input slew rate = 1V/ns

2. Inputs are not recognized as valid until V

REF

stabilizes.

3. V

is the magnitude of the difference between the input level on CK and the input level on CK .

4. The value of V

is expected to equal 0.5*V

DDQ

of the transmitting device and must track variations in the DC level of the same.

Specifications and Conditions

(0 °C

;

DDQ

= 2.5V

0.2V; V

= 2.5V

0.2V, See AC

Characteristics)

Symbol

Parameter/Condition

DDR200

(8B)

=10ns

DDR266A/B

(7K/75B)

=7.5ns

Unit

Notes

D D 0

Operating Current: one bank; active / precharge; t

= t

(min); DQ, DM, and

DQS inputs changing twice per clock cycle; address and control inputs changing
once per clock cycle

D D 1

Operating Current: one bank; active / read / precharge; Burst = 2; t

= t

R C

(min); CL = 2.5;

OUT

= 0mA; address and control inputs changing once per clock

cycle

110

120

DD2P

Precharge Power Down Standby Current: all banks idle; Power Down mode;
CKE

(max)

DD2N

Idle Standby Current: CS

(min); all banks idle; CKE

(min);

address and control inputs changing once per clock cycle

DD3P

Active Power Down Standby Current: one bank active; Power Down mode;
CKE

(max)

DD3N

Active Standby Current: one bank; active / precharge; CS

I H

(min);

CKE

I H

(min); t

= t

RAS

(max); DQ, DM, and DQS inputs changing twice per

clock cycle; address and control inputs changing once per clock cycle

DD4R

Operating Current: one bank; Burst = 2; reads; continuous burst; address and
control inputs changing once per clock cycle; DQ and DQS outputs changing
twice per clock cycle; CL = 2.5; I

OUT

= 0mA

130

165

DD4W

Operating Current: one bank; Burst = 2; writes; continuous burst; address and
control inputs changing once per clock cycle; DQ and DQS inputs changing twice
per clock cycle; CL = 2.5

115

150

D D 5

Auto-Refresh Current : t

= t

RFC

(min)

160

170

D D 6

Self-Refresh Current : CKE

0.2V

1, 2

D D 7

Operating current: four bank; four bank interleaving with BL = 4, address

and

control inputs randomly changing; 50% of data changing at every transfer;
t

= t

(min); I

OUT

= 0mA.

250

300

1. I

specifications are tested after the device is properly initialized.

2. Enables on-chip refresh and address counters.

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Electrical Characteristics & AC Timing for DDR266/DDR200 - Absolute Specifications

;

DDQ

= 2.5V

0.2V; V

= 2.5V

0.2V, See AC Characteristics) (Part 1 of 2)

Symbol

Parameter

DDR266A

(-7K)

DDR266B

(-75B)

DDR200

(-8B)

Unit

Notes

Min

Max

Min

Max

Min

Max

DQ output access time from CK/CK

0.75

0.8

1-4

DQSCK

DQS output access time from CK/CK

0.75

0.8

1-4

CK high-level width

0.45

0.55

0.45

0.55

0.45

0.55

C K

1-4

CK low-level width

0.45

0.55

0.45

0.55

0.45

0.55

C K

1-4

Clock cycle time

CL = 2.5

7.5

1-4

CL = 2.0

7.5

1-4

DQ and DM input hold time

0.5

0.6

1-4, 15,

DQ and DM input setup time

0.5

0.6

1-4, 15,

DIPW

DQ and DM input pulse width (each input)

1.75

1-4

Data-out high-impedance time from CK/CK

0.75

0.8

1-4, 5

Data-out low-impedance time from CK/CK

0.75

0.8

1-4, 5

DQSQ

DQS-DQ skew (DQS & associated DQ signals)

0.5

0.6

1-4

DQSQA

DQS-DQ skew (DQS & all DQ signals)

0.5

0.6

1-4

minimum half clk period for any given cycle;
defined by clk high (t

) or clk low (t

) time

C K

1-4

Data output hold time from DQS

0.75ns

1.0ns

C K

1-4

DQSS

Write command to 1st DQS latching
transition

0.75

1.25

0.75

1.25

0.75

1.25

C K

1-4

DQSL,H

DQS input low (high) pulse width (write cycle)

0.35

C K

1-4

DSS

DQS falling edge to CK setup time (write cycle)

0.2

C K

1-4

DSH

DQS falling edge hold time from CK (write cycle)

0.2

C K

1-4

MRD

Mode register set command cycle time

1-4

WPRES

Write preamble setup time

1-4, 7

WPST

Write postamble

0.40

0.60

0.40

0.60

0.40

0.60

C K

1-4, 6

WPRE

Write preamble

0.25

C K

1-4

Address and control input hold time
(fast slew rate)

0.9

1.1

2-4, 9,
11, 12

Address and control input setup time
(fast slew rate)

0.9

1.1

2-4, 9,
11, 12

Address and control input hold time
(slow slew rate)

1.0

1.1

2-4, 11,

12, 14

Address and control input setup time
(slow slew rate)

1.0

1.1

2-4, 11,

12, 14

IPW

Input pulse width

2.2

2-4, 12

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RPRE

Read preamble

0.9

1.1

0.9

1.1

0.9

1.1

C K

1-4

RPST

Read postamble

0.40

0.60

0.40

0.60

0.40

0.60

C K

1-4

RAS

Active to Precharge command

120,000

1-4

Active to Active/Auto-refresh command period

1-4

RFC

Auto-refresh to Active/Auto-refresh
command period

1-4

RCD

Active to Read or Write delay

1-4

RAP

Active to Read Command with Autoprecharge

1-4

Precharge command period

1-4

RRD

Active bank A to Active bank B command

1-4

Write recovery time

1-4

DAL

Auto precharge write recovery
+ precharge time

)

C K

1-4, 13

WTR

Internal write to read command delay

C K

1-4

XARD

Power down exit time

7.5

1-4

XSNR

Exit self-refresh to non-read command

1-4

XSRD

Exit self-refresh to read command

200

C K

1-4

REFI

Average Periodic Refresh Interval

7.8

1-4, 8

Electrical Characteristics & AC Timing for DDR266/DDR200 - Absolute Specifications

;

DDQ

= 2.5V

0.2V; V

= 2.5V

0.2V, See AC Characteristics) (Part 2 of 2)

Symbol

Parameter

DDR266A

(-7K)

DDR266B

(-75B)

DDR200

(-8B)

Unit

Notes

Min

Max

Min

Max

Min

Max

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Electrical Characteristics & AC Timing for DDR266 - Applicable Specifications
Expressed in Clock Cycles

;

DDQ

= 2.5V

0.2V; V

= 2.5V

0.2V, See AC Characteristics)

Symbol

Parameter

= 7.5ns

Units

Notes

Min

Max

MRD

Mode register set command cycle time

1-4

WPRE

Write preamble

0.25

1-4

RAS

Active to Precharge command

16000

1-4

Active to Active/Auto-refresh command period

1-4

RFC

Auto-refresh to Active/Auto-refresh
command period

1-4

RCD

Active to Read or Write delay

1-4

RAP

Active to Read Command with Autoprecharge

1-4

Precharge command period

1-4

RRD

Active bank A to Active bank B command

1-4

Write recovery time

1-4

DAL

Auto precharge write recovery + precharge time

1-5

WTR

Internal write to read command delay

1-4

XSNR

Exit self-refresh to non-read command

1-4

XSRD

Exit self-refresh to read command

200

1-4

1. Input slew rate = 1V/ns
2. The CK/CK input reference level (for timing reference to CK/CK) is the point at which CK and CK cross: the input reference level for sig-

nals other than CK/CK , is V

REF.

3. Inputs are not recognized as valid until V

REF

stabilizes.

4. The Output timing reference level, as measured at the timing reference point indicated in AC Characteristics (Note 3) is V

5. t

H Z

and t

transitions occur in the same access time windows as valid data transitions. These parameters are not referred to a specific

voltage level, but specify when the device is no longer driving (HZ), or begins driving (LZ).

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Electrical Characteristics & AC Timing for DDR266/DDR200 - Absolute Specifications
Notes

1. Input slew rate = 1V/ns.
2. The CK/CK input reference level (for timing reference to CK/CK) is the point at which CK and CK cross:
the input reference level for signals other than CK/CK, is V

REF.

3. Inputs are not recognized as valid until V

REF

stabilizes.

4. The Output timing reference level, as measured at the timing reference point indicated in AC Characteristics (Note 3) is V

5. t

and t

transitions occur in the same access time windows as valid data transitions. These parameters are not referred

to a specific voltage level, but specify when the device is no longer driving (HZ), or begins driving (LZ).
6. The maximum limit for this parameter is not a device limit. The device operates with a greater value for this parameter, but
system performance (bus turnaround) degrades accordingly.
7. The specific requirement is that DQS be valid (high, low, or some point on a valid transition) on or before this CK edge. A
valid
transition is defined as monotonic and meeting the input slew rate specifications of the device. When no writes were prev-
iously in progress on the bus, DQS will be transitioning from Hi-Z to logic LOW. If a previous write was in progress, DQS
could be HIGH, LOW, or transitioning from high to low at this time, depending on t

DQSS

8. A maximum of eight Autorefresh commands can be posted to any given DDR SDRAM device.
9. For command/address input slew rate

1.0V/ns. Slew rate is measured between V

(AC) and V

(AC).

10. For command/address input slew rate

0.5V/ns and < 1.0V/ns. Slew rate is measured between V

(AC) and V

O L

(AC)

11. CK/CK slew rates are

1.0V/ns.

12.These parameters guarantee device timing, but they are not necessarily tested on each device, and they may be guara-
nteed by design or tester characterization.
13. For each of the terms in parentheses, if not already an integer, round to the next highest integer. t

is equal to the actual

system clock cycle time.
For example, for DDR266B at CL = 2.5, t

DAL

= (15ns/7.5ns) +(20ns/7.5ns) = 2 + 3 = 5.

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14. An input setup and hold time derating table is used to increase t

and t

in the case where the input slew

rate is below 0.5 V/ns.

15. An input setup and hold time derating table is used to increase t

and t

in the case where the I/O slew rate is below

0.5 V/ns.

16. An I/O Delta Rise, Fall Derating table is used to increase t

and t

DH)

in the case where DQ, DM, and DQS slew rates

differ.

Input Slew Rate

delta

( t

IS)

delta

( t

IH)

Unit

Notes

0.5 V/ns

1,2

0.4 V/ns

+50

1,2

0.3 V/ns

+100

1,2

1. Input slew rate is based on the lesser of the slew rates determined by either V

IH (AC)

to V

IL (AC)

or V

IH (DC)

to V

IL (DC)

, similarly for rising

transitions.

2. These derating parameters may be guaranteed by design or tester characterization and are not necessarily tested on eachdevice.

Input Slew Rate

delta

( t

DS)

delta

( t

DH)

Unit

Notes

0.5 V/ns

1,2

0.4 V/ns

+75

1,2

0.3 V/ns

+150

1,2

1. I/O slew rate is based on the lesser of the slew rates determined by either V

IH (AC)

to V

IL (AC)

or V

IH (DC)

to V

IL (DC)

, similarly for rising

transitions.

2. These derating parameters may be guaranteed by design or tester characterization and are not necessarily tested on eachdevice.

Input Slew Rate

delta

( t

DS)

delta

( t

DH)

Unit

Notes

0.0 V/ns

1,2,3,4

0.25 V/ns

+50

1,2,3,4

0.5 V/ns

+100

1,2,3,4

1. Input slew rate is based on the lesser of the slew rates determined by either V

IH (AC)

to V

IL (AC)

or V

IH (DC)

to V

IL (DC)

, similarly for rising

transitions.

2. Input slew rate is based on the larger of AC to AC delta rise, fall rate and DC to DC delta rise, fall rate.

3. The delta rise, fall rate is calculated as: [1/(slew rate 1)] - [1/(slew rate 2)]

For example: slew rate 1 = 0.5 V/ns; slew rate 2 = 0.4 V/ns

Delta rise, fall = (1/0.5) - (1/0.4) [ns/V]

= -0.5 ns/V

Using the table above, this would result in an increase in t

and t

of 100 ps.

4. These derating parameters may be guaranteed by design or tester characterization and are not necessarily tested on each device.

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Data Input (Write)

(Timing Burst Length = 4)

Data Output (Read)

(Timing Burst Length = 4)

DSL

DI n = Data In for column n.
3 subsequent elements of data in are applied in programmed order following DI n.

DI n

DQS

Don't Care

DSH

DQSQ

(max)occurs when DQS is the earliest among DQS and DQ signals to transition.

DQS

DQSQ

Data Output hold time from Data Strobe is shown as t

. t

Q H

is a function of the clock high or low time (t

)

QH2

QH1

DQSQ

QH3

QH4

DQSQ

CK
CK

HP1

HP2

HP3

HP4

is the half cycle pulse width for each half cycle clock. t

is referenced to the clock duty cycle only

and not to the data strobe (DQS) duty cycle.

for that given clock cycle. Note correlation of t

H P

to t

Q H

in the diagram above (t

HP1

to t

QH1

, etc.).

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256Mb Double Data Rate SDRAM

REV 1.3

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NT5DS32M8AT NT5DS32M8AW

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08/2002

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NANYA TECHNOLOGY CORP. reserves the right to change Products and Specifications without notice.

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NT5DS32M8AT NT5DS32M8AW

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08/2002

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NT5DS32M8AT NT5DS32M8AW

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08/2002

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NT5DS32M8AT NT5DS32M8AW

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08/2002

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NT5DS32M8AT NT5DS32M8AW

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Nanya Technology Corporation.

The following are trademarks of NANYA TECHNOLOGY CORPORATION in R.O.C , or other countries, or both.
NANYA NANYA logo

Other company, product and service names may be trademarks or service marks of others.

NANYA TECHNOLOGY CORPORATION (NTC) reserves the right to make changes without notice. NTC warrants performance
of its semiconductor products and related software to the specifications applicable at the time of sale in accordance with NTC's
standard warranty. Testing and other quality control techniques are utilize to the extent NTC deems necessary to support this
warranty. Specific testing of all parameters of each device is not necessarily performed, except those mandated by government
requirements.

Certain applications using semiconductor products may involve potential risks of death, personal injury, or severe property or
environmental damage ("Critical Applications").

NTC SEMICONDUCTOR PRODUCTS ARE NOT DESIGNED, INTEND, AUTHORIZED, OR WARRANTED TO BE SUITABLE
FOR USE IN LIFE-SUPPORT APPLICATIONS, DEVICES OR SYSTEMS OR OTHER CRITICAL APPLICATIONS.

Inclusion of NTC products in such applications is understood to be fully at the risk of the customer. Use of NTC products in such
applications requires the written approval of an appropriate NTC officer. Question concerning potential risk applications should
be directed to NTC through a local sales office.

In order to minimize risks associated with the customer's applications, adequate design and operating safeguards should be
provided by customer to minimize the inherent or procedural hazards.

NTC assumes no liability of applications assistance, customer product design, software performance, or infringement of patents
or services described herein. Nor does NTC warrant or represent that any license, either express or implied, is granted under
any patent right, copyright, mask work right, or other intellectual property right of NTC covering or relating to any combination,
machine, or process in which such semiconductor products or services might be or are used.

NANYA TECHNOLOGY CORPORATION
HWA YA Technology Park
669, FU HSING 3rd Rd., Kueishan,
Taoyuan, Taiwan, R.O.C.

The NANYA TECHNOLOGY CORPORATION home page can be found at
http:\\www.nanya.com

Ð­Ð»ÐµÐºÑ‚Ñ€Ð¾Ð½Ð½Ñ‹Ð¹ ÐºÐ¾Ð¼Ð¿Ð¾Ð½ÐµÐ½Ñ‚: NT5DS32M8AT-75B

ÐÐ»ÐµÐºÑ‚Ñ€Ð¾Ð½Ð½Ñ‹Ð¹ ÐºÐ¾Ð¼Ð¿Ð¾Ð½ÐµÐ½Ñ‚: NT5DS32M8AT-75B