NT5DS4M32EF

4Mx32 Double Data Rate SDRAM

REV 0.1 (Preliminary)

06/2003

© NANYA TECHNOLOGY CORP.

NANYA TECHNOLOGY CORP. reserves the right to change Products and Specifications without notice.

TABLE OF CONTENTS

Timing

- 32

Basic Timing(@BL=2, CL=3)

- 32

Multi Bank Interleaving Read(@BL=4,CL=3)

- 33

Multi Bank Interleaving Write(@BL=4,CL=3)

- 34

Auto Precharge after Read Burst(@BL=8)

- 35

Auto Precharge after Write Burst(@BL=4)

- 36

Normal Write Burst(@BL=4)

- 37

Write Interrupt by Precharge & DM(@BL=8)

- 38

Read Interrupt by Precharge(@BL=8)

- 39

Read Interrupt by Burst Stop & Write(@BL=8,CL=3) - 40
Read Interrupt by Read(@BL=8,CL=3)

- 41

DM Function only for Write(@BL=8)

- 42

Power up Sequence & Auto Refresh(CBR)

- 43

Mode Register Set

- 44

I/V Characteristics for Input and Output Buffer

- 45

Reduced Output Driver Characteristics

- 45

Impedance Match Output Driver Characteristics

- 47

Package Dimension(FBGA)

- 48

Table of Contents

- 2

Memory Part Numbering

- 3

General Description & Device Features

- 4

Pin Configuration & Pin Description

- 5

Input/Output Functional Description

- 6

Functional Block Diagram

- 7

Simplified State Diagram

- 8

Functional Description

- 9

Power up Sequence

- 9

Mode Register Set(MRS)

- 10

Extended Mode Register Set

- 11

Burst Mode Operation

- 12

Burst Length & Sequence

- 12

Bank Activation Command

- 12

Burst Read Operation

- 13

Burst Write Operation

- 13

Burst Interruption

- 14

Read Interrupt by Read

- 14

Read Interrupt by Burst Stop & Write

- 14

Read Interrupt by Precharge

- 15

Write Interrupt by Write

- 15

Write Interrupt by Read & DM

- 16

Write Interrupt by Precharge & DM

- 17

Burst Stop Command

- 18

DM Function

- 18

Auto Precharge Operation

- 19

Read with Auto Precharge

- 19

Write with Auto Precharge

- 20

Precharge Command

- 20

Auto Refresh

- 21

Self Refresh

- 21

Power Down Mode

- 22

Absolute Maximum Ratings

- 23

Power & DC Operating Conditions

- 23

DC Characteristics

- 24

AC Input Operating Conditions

- 24

AC Operating Test Conditions

- 25

Capacitance

- 25

Decoupling Capacitance Guide Line

- 25

AC Characteristics(I)

- 26

AC Characteristics(II)

- 27

Simplified Truth Table

- 28

Functional Truth Table

- 29

Functional Truth Table for CKE

- 31

NT5DS4M32EF

4Mx32 Double Data Rate SDRAM

REV 0.1 (Preliminary)

06/2003

© NANYA TECHNOLOGY CORP.

NANYA TECHNOLOGY CORP. reserves the right to change Products and Specifications without notice.

1M x32Bit x4Banks Double Data Rate Synchronous RAM with Bi-directional Data Strobe and DLL

GENERAL DESCRIPTION

For 1M x 32Bit x 4 Bank DDR SDRAM

The NT5DT4M32EF is 134,217,728 bits of double data rate synchronous dynamic RAM organized as 4 x 1,048,576 bits by 32 I/Os.

Synchronous features with Data Strobe allow extremely high performance up to 3.2GB/s/chip. I/O transactions are possible on both

edges of the clock. Range of operating frequencies, programmable burst length and programmable latencies allow the device to be

useful for a variety of high performance memory system applications.

FEATURES

· VDD = 2.5V

5% , VDDQ = 2.5V

· SSTL_2 compatible inputs/outputs

· 4 banks operation

· MRS cycle with address key programs

-. Read latency 3, 4 (clock)

-. Burst length (2, 4, 8 and Full page)

-. Burst type (sequential & interleave)

· Full page burst length for sequential burst type only

· Start address of the full page burst should be even

· All inputs except data & DM are sampled at the rising

edge of the system clock

· Differential clock input(CK & /CK)

· Data I/O transaction on both edges of Data strobe

· 4 DQS (1 DQS/Byte)

· DLL aligns DQ and DQS transaction with Clock

transaction

· Edge aligned data & data strobe output

· Center aligned data & data strobe input

· DM for write masking only

· Auto & self refresh

· 32ms refresh period (4K cycle)

· 144-Ball FBGA package

· Maximum clock frequency up to 400MHz

· Maximum data rate up to 800Mbps/pin

ORDERING INFORMATION

Part NO.

NT5DS4M32EF-33

NT5DS4M32EF-4

NT5DS4M32EF-28

Max Freq.

300MHz

250MHz

350MHz

Max Data Rate

600Mbps/pin

500Mbps/pin

700Mbps/pin

Interface

Package

NT5DS4M32EF-25

400MHz

800Mbps/pin

SSTL_2

144-Ball FBGA

NT5DS4M32EF

4Mx32 Double Data Rate SDRAM

REV 0.1 (Preliminary)

06/2003

© NANYA TECHNOLOGY CORP.

NANYA TECHNOLOGY CORP. reserves the right to change Products and Specifications without notice.

PIN CONFIGURATION (Top View)

DQS0

DM0

VSSQ

DQ3

DQ2

DQ0

DQ31

DQ29

DQ28

VSSQ

DM3

DQS3

VSS

Thermal

VSS

Thermal

VSS

Thermal

VSS

Thermal

VSS

Thermal

VSS

Thermal

VSS

Thermal

VSS

Thermal

VSS

Thermal

VSS

Thermal

VSS

Thermal

VSS

Thermal

VSS

Thermal

VSS

Thermal

VSS

Thermal

VSS

Thermal

DQ4

VDDQ

DQ1

VDDQ

DQ30

VDDQ

DQ27

DQ6

DQ5

VSSQ

VDD

VSSQ

DQ26

DQ25

DQ7

VDDQ

VDD

VSS

VSSQ

VSS

VSSQ

VSS

VDD

VDDQ

DQ24

DQ17

DQ16

VDDQ

VSSQ

DQ19

DQ18

VDDQ

VSSQ

DQS2

DM2

VSSQ

DQ21

DQ20

VDDQ

VSSQ

VDDQ

DQ15

DQ14

VSSQ

VDDQ

DQ13

DQ12

VSSQ

DM1

DQS1

VSSQ

VDDQ

DQ11

DQ10

DQ22

DQ23

VDDQ

VSSQ

VSS

VSSQ

VDDQ

DQ9

DQ8

/CAS

/WE

VDD

VSS

A10

VDD

RFU1

VSS

VDD

/RAS

BA1

A11

RFU2

/CK

MCL

/CS

BA0

A8/AP

CKE

VREF

10 11 12

NOTE :

1. RFU1 is reserved for A12
2. RFU2 is reserved for BA2
3. VSS Thermal balls are optional

PIN Description

Bank Select Address
Address Input
Data Input/Output
Power
Ground
Power for DQ's
Ground for DQ's
Must Connect Low

, BA

~ A

0 ~

DDQ

SSQ

MCL

Differential Clock Input
Clock Enable
Chip Select

Row Address Strobe
Column Address Strobe
Write Enable
Data Strobe
Data Mask
Reserved for Future Use

CK, /CK

CKE

/CS

/RAS

/CAS

/WE

DQS

DM
RFU

NT5DS4M32EF

4Mx32 Double Data Rate SDRAM

REV 0.1 (Preliminary)

06/2003

© NANYA TECHNOLOGY CORP.

NANYA TECHNOLOGY CORP. reserves the right to change Products and Specifications without notice.

INPUT/OUTPUT FUNCTIONAL DESCRIPTION

This pin is recommended to be left "No Connection" on the device

No Connection/

Reserved for future use

NC/RFU

Must Connect Low

MCL

Reference voltage for inputs, used for SSTL interface.

Power Supply

REF

Isolated power supply and ground for the output buffers to provide improved
noise immunity.

Power Supply

DDQ

SSQ

Power and ground for the input buffers and core logic.

Power Supply

Row,Column addresses are multiplexed on the same pin. Row address : RA

~ RA

Column address : CA

~ CA

. Column address CA

is used for auto precharge.

Input

~ A

Select which bank is to be active.

Input

, BA

Data inputs and outputs are multiplexed on the same pins.

Input,Output

~ DQ

Data-In mask. Data-In is masked by DM Latency=0 when DM is high in burst write. DM

for DQ

~ DQ

for DQ

~ DQ

, DM

for DQ

~ DQ

, DM

for DQ

~ DQ

Input

~ DM

Data inputs and outputs are synchronized with both edge of DQS.
DQS

for DQ

~DQ

, DQS

for DQ

~DQ

, DQS

for DQ

~DQ

, DQS

for DQ

~DQ

Input,Output

DQS

~DQS

Enables write operation and row precharge.
Latches data in starting from /CAS, /WE active.

Input

/WE

Latches Column addresses on the positive going edge of the CK with /CAS
low. Enables column access.

Input

/CAS

Latches row addresses on the positive going edge of the CK with /RAS low.
Enables row access & precharge.

Input

/RAS

/CS enables(registered Low) and disables(registered High) the command decoder. When /CS is
registered High,new commands are ignored but previous operations are continued.

Input

/CS

CKE high activates and CKE low deactivates the internal clock,input buffers and output drivers. By
deactivating the clock, CKE low indicates the Power down mode or Self refresh mode.

The differential system clock inputs.
All of the input are sampled on the rising edge of the clock except DQ's and
DM's that are sampled on both edges of the DQS.

Function

Input

Type

CKE

CK, /CK

Symbol

: The timing reference point for the differential clocking is the cross point of CK and /CK.

For any applications using the single ended clocking, apply V

REF

to /CK pin.

NT5DS4M32EF

4Mx32 Double Data Rate SDRAM

REV 0.1 (Preliminary)

06/2003

© NANYA TECHNOLOGY CORP.

NANYA TECHNOLOGY CORP. reserves the right to change Products and Specifications without notice.

FUNCTIONAL BLOCK DIAGRAM (1Mbit x 32 I/O x 4 Bank)

Sen

s
e A
M

Column Decoder

Latency & Burst Length

bit pr

t
ch

Ou
t
p

De
code

o
lu

Bu
ffe
r

e
f
r
e
s
h
Counte

Bu
ffe
r

dress R

giste

LRA

LCBR

LCKE

LRAS LCBR

LWE

LCAS

O C

ntrol

CK,/CK

ADDR

DQi

Input Buffer

LWE

CK, /CK

Data Input Register

Serial to parallel

LDMi

Bank Select

1M x 32

x32

1M x 32

Gen.

robe

Data Strobe

(DQS0~DQS3)

Programming Register

DLL

LDMi

LWCBR

CK,/CK

Timing Register

CK,/CK

CKE

/CS

/RAS

/CAS

/WE

DMi

NT5DS4M32EF

4Mx32 Double Data Rate SDRAM

REV 0.1 (Preliminary)

06/2003

© NANYA TECHNOLOGY CORP.

NANYA TECHNOLOGY CORP. reserves the right to change Products and Specifications without notice.

FUNCTIONAL DESCRIPTION

Power-Up Sequence

DDR SDRAMs must be powered up and initialized in a predefined manner to prevent undefined operations.

1. Apply power and keep CKE at low state (All other inputs may be undefined)

- Apply VDD before or at the same time as VDDQ.
- Apply VDDQ before or at the same time as VREF & VTT

2. Start clock and maintain stable condition for minimum 200µs
3. The minimum of 200µs after stable power and clock (CK,/CK), apply NOP and CKE to be high.
4. Issue precharge command for all banks of the device.
5. Issue a EMRS command to enable DLL

6. Issue a MRS command to reset DLL. The additional 200 clock cycles are required to lock the DLL.

*1,2

7. Issue precharge command for all banks of the device.
8. Issue at least 2 or more auto-refresh commands.
9. Issue a mode register set command with A8 to low to initialize the mode register.

*1 Every "DLL Enable" command resets DLL. Therefore sequence 6 can be skipped during power-up.

Instead of it, the additional 200cycles of clock input is required to lock the DLL after enabling DLL.

*2 Sequence of 6 & 7 is regardless of the order.

Power-Up & Initialization Sequence

/CK

2Clock

min.

2Clock

min.

tRFC

2Clock

min.

Precharge

ALL Banks

EMRS

MRS

DLL Reset

Precharge

ALL Banks

1st Auto

Refresh

2nd Auto

Refresh

Mode

Register Set

Any

Command

200 Clock min.

Command

Input must be

stable for 200us

NT5DS4M32EF

4Mx32 Double Data Rate SDRAM

REV 0.1 (Preliminary)

06/2003

© NANYA TECHNOLOGY CORP.

NANYA TECHNOLOGY CORP. reserves the right to change Products and Specifications without notice.

Mode Register Set (MRS)

The mode register stores the data for controlling the various operating modes of DDR SDRAM. It programs /CAS latency, address

mode, burst length, test mode, DLL reset and various vendor specific option to make DDR SDRAM useful for variety of different

applications. The default value of the mode register is not defined, therefore the mode register must be written after EMRS setting for

proper operation. The mode register is written by asserting low on /CS, /RAS, /CAS and WE (The DDR SDRAM should be in active

mode with CKE already high prior to writing into the mode register). The state of address pins A

~ A

and BA

,BA

in the same cycle

as /CS, /RAS, /CAS and /WE going low is written in the mode register. Minimum two clock cycles are requested to complete the write

operation in the mode register. The mode register contents can be changed using the same command and clock cycle requirements

during operation as long as all banks are in the idle state. The mode register is divided into various fields depending on functionality.

The burst length uses A

, address mode uses A

, /CAS latency(read latency from column address) uses A

~ A

. A

is used for test

mode. A

is used for DLL for DLL reset. A

, A

, and BA

must be set to low for normal MRS operation. Refer to the table for

specific codes for various burst length, address modes and /CAS latencies.

Address Bus

RFU

DLL

RFU

/CAS Latency

Burst Length

Mode

DLL Reset

Mode

Type

Burst Type

Test Mode

DLL

Normal

Yes

Test

Sequential

Interleave

Mode

MRS

EMRS

Latency

Reserved

Interleave

Reserve

Sequential

Reserve

Full page

Burst Type

Burst Length

/CAS Latency

* RFU(Reserved for future use)

should stay "0" during MRS cycle.

NOP

Precharge

All Banks

NOP

MRS

NOP

Any

Command

NOP

MRD

= 2 t

MRS Cycle

/CK

Command

* 1 : MRS can be issued only at all banks precharge state.
* 2 : Minimum t

is required to issue MRS command.

NT5DS4M32EF

4Mx32 Double Data Rate SDRAM

REV 0.1 (Preliminary)

06/2003

© NANYA TECHNOLOGY CORP.

NANYA TECHNOLOGY CORP. reserves the right to change Products and Specifications without notice.

Extended Mode Register Set (EMRS)

The extended mode register stores the data for enabling or disabling DLL and selecting output driver strength. The default value of

the extended mode register is not defined, therefore the extended mode register must be written after power up for enabling or

disabling DLL. The extended mode register is written by asserting low on /CS, /RAS, /CAS, /WE and high on BA

(The DDR SDRAM

should be in all bank precharge with CKE already high prior to writing into the extended mode register). The state of address pins

, A

and BA1 in the same cycle as /CS,/RAS,/CAS and /WE going low are written in the extended mode register. A

and

are used for setting driver strength to weak or matched impedance. Two clock cycles are required to complete the write operation

in the extended mode register. The mode register contents can be changed using the same command and clock cycle requirements

during operation as long as all banks are in the idle state A

is used for DLL enable or disable."High"on BA

is used for EMRS. All the

other address pins except A

and BA

must be set to low for proper EMRS operation. Refer to the table for specific codes.

Address Bus

RFU

Extended

Mode Register

Mode

MRS

EMRS

· RFU(Reserved for Future Use) should stay "0" during MRS cycle.

DIC

RFU

DIC

DLL

Output Driver Impedance Control

60% of full drive strength

DLL Enable

30% of full drive strength

Enable

Disable

Weak

Matched impedance

DLL DISABLE MODE

/CK

2Clock

min.

2Clock

min.

Precharge

ALL Banks

EMRS

MRS*1

CMD

MRS

Active

Read*2

200 Clock min.

Command

Enter DLL

Disable

Mode

2Clock

min.

EMRS

2Clock

min.

DLL Disable

Mode

Precharge

ALL Banks

Exit DLL

Disable

Mode

MRS

DLL RESET

2Clock

min.

CL=2 Only,

BL=FREE

Notes:

- DLL disable mode is operating mode for low operating frequency between 66MHz and 100MHz without DLL.
- This DLL disable mode is useful for power saving.
- All banks precharge or a bank precharge command can omit before entering and exiting DLL disable mode.

: CL=2 only and BL can set any burst length at DLL disable mode.

: A write command can be applied as far as tRCD is satisfied after any bank active command.

And it needs an additional 200 clock cycles for read operation after exiting DLL disable mode.

NT5DS4M32EF

4Mx32 Double Data Rate SDRAM

REV 0.1 (Preliminary)

06/2003

© NANYA TECHNOLOGY CORP.

NANYA TECHNOLOGY CORP. reserves the right to change Products and Specifications without notice.

Burst Mode Operation

Burst mode operation is used to provide a constant flow of data to memory location (write cycle), or from memory location (read

cycle). There are two parameters that define how the burst mode operates. These parameters including burst sequence and burst

length are programmable and determined by address A

~ A

during the Mode Register Set command. The burst type is used to

define the sequence in which the burst data will be delivered or stored to the DDR SDRAM. Two types of burst sequences are

supported, sequential and interleaved. See the below table. The burst length controls the number of bits that will be output after a

read command, or the number of bits to be input after a write command. The burst length can be programmed to have values of 2,4,8

or full page. For the full page operation, the starting address must be an even number and the burst stop at the end of burst.

Burst Length and Sequence

Burst Length

xx0

Starting Address(A

)

Sequential Mode

Interleave Mode

xx1

x00

x01

x10

x11

000

001

010

011

100

101

110

111

0-1

1-0

0-1-2-3

1-2-3-0

2-3-0-1

3-0-1-2

0-1-2-3-4-5-6-7

3-4-5-6-7-0-1-2

4-5-6-7-0-1-2-3

5-6-7-0-1-2-3-4

6-7-0-1-2-3-4-5

7-0-1-2-3-4-5-6

0-1

1-0

0-1-2-3

1-0-3-2

2-3-0-1

3-2-1-0

0-1-2-3-4-5-6-7

1-0-3-2-5-4-7-6

2-3-0-1-6-7-4-5

3-2-1-0-7-6-5-4

4-5-6-7-0-1-2-3

5-4-7-6-1-0-3-2

6-7-4-5-2-3-0-1

7-6-5-4-3-2-1-0

1-2-3-4-5-6-7-0

2-3-4-5-6-7-0-1

n = A

- A

, A

= 0

Cn, Cn+1, Cn+2, ..., Cn-1

Not supported

Full Page (256)

Bank Activation Command

The Bank Activation command is issued by holding /CAS and /WE high with /CS and /RAS low at the rising edge of the clock. The

DDR SDRAM has four independent Banks, so two Bank Select Addresses(BA

, BA

) are supported. The Bank Activation command

must be applied before any Read or Write operation is executed.The delay from the Bank Activation command to the first read or write

command must meet or exceed the minimum of /RAS to /CAS delay time(tRCDR/tRCDW min). Once a bank has been activated, it

must be precharged before another Bank Activation command can be applied to the same bank. The minimum time interval between

interleaved Bank Activation commands(Bank A to B and vice versa) is the Bank to Bank delay time (t

RRD

min).

Bank Activation Command Cycle ( /CAS Latency = 3 )

n+1

n+2

Bank A

Row Addr.

Bank A

Col. Addr.

Bank A

Row Addr.

Bank B

Row Addr.

Bank A

Activate

NOP

READ A

with Auto

Bank A

Activate

NOP

Bank B

Activate

/RAS-/CAS delay time(tRCDR for READ)

/RAS-/RAS delay time(t

RRD

)

Precharge

Row cycle Time (t

)

: Don't care

/CK

Address

Command

NT5DS4M32EF

4Mx32 Double Data Rate SDRAM

REV 0.1 (Preliminary)

06/2003

© NANYA TECHNOLOGY CORP.

NANYA TECHNOLOGY CORP. reserves the right to change Products and Specifications without notice.

Burst Read Operation

Burst Read operation in DDR SDRAM is in the same manner as the current SDRAM such that the burst read command is issued

by asserting /CS and /CAS low while holding /RAS and /WE high at the rising edge of the clock after t

RCD

from the bank activation.

The address inputs (A

) determine the starting address for the Burst. The Mode Register sets type of burst (Sequential or

interleave) and burst length(2,4,8, Full page). The first output data is available after the /CAS Latency from the READ command,

and the consecutive data are presented on the falling and rising edge of Data Strobe adopted by DDR SDRAM until the burst length

is completed.

< Burst Length = 4, /CAS Latency = 3,4 >

NOP

/CK

Command

NOP

READ

RPRE

RPST

DQS

Dout 0 Dout 1 Dout 2 Dout 3

DQ's

RPRE

RPST

Dout 0 Dout 1 Dout 2 Dout 3

DQS

DQ's

/CAS Latency = 3

/CAS Latency = 4

Burst Write Operation

The Burst Write command is issued by having /CS, /CAS and /WE low while holding /RAS high at the rising edge of the clock. The

address inputs determine the starting column address. There is no real write latency required for burst write cycle. The first data for

burst write cycle must be applied at the first rising edge of the data strobe enabled after t

DQSS

from the rising edge of the clock that

the write command is issued.The remaining data inputs must be supplied on each subsequent falling and rising edge of Data Strobe

until the burst length is completed. When the burst has been finished, any additional data supplied to the DQ pins will be ignored.

< Burst Length = 4 >

WRITEA

/CK

Command

NOP

WRITEB

NOP

DQSSmax

WPST

DQS

Din a2 Din a3 Din b0 Din b1

DQ's

Din b2 Din b3

Din a0 Din a1

WPREH

WPRES

NT5DS4M32EF

4Mx32 Double Data Rate SDRAM

REV 0.1 (Preliminary)

06/2003

© NANYA TECHNOLOGY CORP.

NANYA TECHNOLOGY CORP. reserves the right to change Products and Specifications without notice.

Burst Interruption

Read Interrupted by Read

Burst Read can be interrupted before completion of the burst by new Read command of any bank. When the previous burst is

interrupted, the remaining address are overridden by the new address with the full burst length. The data from the previous Read

command continues to appear on the outputs until the /CAS latency from the interrupting Read command is satisfied. Read to

Read interval is minimum 1 tCK.

< Burst Length = 4, /CAS Latency = 3 >

READ B

/CK

Command

NOP

READ A

DQS

Douta0 Douta1 Doutb0 Doutb1

DQ's

Doutb2 Doutb3

/CAS Latency = 3

Read Interrupted by Burst stop & Write

To interrupt Burst Read with a write command, Burst stop command must be asserted to avoid data contention on the I/O bus

by placing the DQ's(Output drivers) in a high impedance state at least one clock cycle before the Write Command is initiated.

Once the burst stop command has been issued, the minimum delay to a write command is CL(RU). [CL is /CAS Latency and RU

means round up to the nearest integer.]

< Burst Length = 4, /CAS Latency = 3 >

Burst

stop

/CK

Command

NOP

WRITE

NOP

READ

DQS

Dout0 Dout1

Din 0

Din 1

DQ's

Din 2

Din 3

/CAS Latency = 3

RPRE

Preamble

WPREH

DQSS

WPRES

NT5DS4M32EF

4Mx32 Double Data Rate SDRAM

REV 0.1 (Preliminary)

06/2003

© NANYA TECHNOLOGY CORP.

NANYA TECHNOLOGY CORP. reserves the right to change Products and Specifications without notice.

Read Interrupted by Precharge

Burst Read can be interrupted by precharge of the same bank. The minimum 1 clock cycle is required for the read precharge

interval. Precharge command to output disable latency is equivalent to the /CAS latency.

< Burst Length = 8, /CAS Latency = 3 >

Precharge

/CK

Command

NOP

READ

DQS

DQ's

Dout 0 Dout 1 Dout 2 Dout 3 Dout 4 Dout 5

/CAS Latency = 3

1tCK

Dout 6 Dout 7

Interrupted by prechagre

RPRE

RPST

NOP

Write Interrupted by Write

Burst Write can be interrupted by the new Write Command before completion of the previous burst write, with the onlyrestriction

being that the interval that separates the commands must be at least one clock cycle. When the previous burst is interrupted, the

remaining addresses are overridden by the new addresses and data will be written into the device until the programmed burst

length is satisfied.

< Burst Length = 4 >

WRITEA

/CK

Command

WRITEB

NOP

DQS

DQ's

Din a0 Din a1 Din b0 Din b1 Din b2 Din b3

/CAS Latency = 3

1tCK

WPREH

WPRES

NT5DS4M32EF

4Mx32 Double Data Rate SDRAM

REV 0.1 (Preliminary)

06/2003

© NANYA TECHNOLOGY CORP.

NANYA TECHNOLOGY CORP. reserves the right to change Products and Specifications without notice.

Write Interrupted by Read & DM

A burst write can be interrupted by a read command of any bank. The DQ's must be in the high impedance state at least one

clock cycle before the interrupting read data appear on the outputs to avoid data contention. When the read command is
registered, any residual data from the burst write cycle must be masked by DM. The delay from the last data to read command
(tWTR) is required to avoid the data contention DRAM inside. Data that are presented on the DQ pins before the read command is
initiated will actually be written to the memory. Read command interrupting write can not be issued at the next clock edge of the
write command.

< Burst Length = 8 >

WRITE

/CK

Command

NOP

READ

NOP

DQS

DQ's

Din 0

Din 1

Din 2

Din 3

Din 4

Din 5

/CAS
Latency=3

DQSSmax

WPRES

WTR

Din 6

Din 7

DQS

DQ's

Din 0

Din 1

Din 2

Din 4

Din 5

Din 6

Din 7

Din 3

/CAS
Latency=3

Dout0 Dout1

DQSSmin

WPRES

WTR

Dout0 Dout1

NOP

NT5DS4M32EF

4Mx32 Double Data Rate SDRAM

REV 0.1 (Preliminary)

06/2003

© NANYA TECHNOLOGY CORP.

NANYA TECHNOLOGY CORP. reserves the right to change Products and Specifications without notice.

Write Interrupted by Precharge & DM

A burst Write can be interrupted by a precharge of the same bank before completion of the previous burst. A write recovery

time(t

) is required from the last data to precharge command. When Precharge command is asserted, any residual data from the

burst write cycle must be masked by DM.

< Burst Length = 8 >

WRITE A

/CK

Command

NOP

Precharge

WRITE B

NOP

DQS

DQ's

Din a0 Din a1 Din a2 Din a3 Din a4 Din a5

Max t

DQSS

DQSSmax

WPREH

WPRES

WPREH

DQSSmax

WPRES

Din a6 Din a7

Din a0 Din a1

DQS

DQ's

Din a0 Din a1 Din a2

Din a4 Din a5

Min t

DQSS

DQSSmin

WPREH

WPRES

WPREH

DQSSmin

WPRES

Din a6 Din a7

Din b0 Din b1

Din b2

Din a3

NT5DS4M32EF

4Mx32 Double Data Rate SDRAM

REV 0.1 (Preliminary)

06/2003

© NANYA TECHNOLOGY CORP.

NANYA TECHNOLOGY CORP. reserves the right to change Products and Specifications without notice.

BURST STOP COMMAND

The Burst stop command is initiated by having /RAS and /CAS high with /CS and /WE low at the rising edge of the clock only. The

Burst Stop command has the fewest restrictions making it the easiest method to use when terminating a burst operation before it

has been completed. When the Burst Stop command is issued during a burst read cycle, both the data and DQS(Data Strobe) go to a

high impedance state after a delay which is equal to the /CAS Latency set in the Mode Register. The Burst Stop command, however,

is not supported during a write burst operation.

< Burst Length = 4, /CAS Latency = 3,4 >

Burst

Stop

/CK

Command

NOP

READ

DQS

DQ's

Dout 0 Dout 1

/CAS Latency = 3

1tCK

The burst ends after a delay equal to the /CAS Latency

Dout 0 Dout 1

DQS

DQ's

/CAS Latency = 4

The burst ends after a delay equal to the /CAS Latency

DM FUNCTION

The DDR SDRAM has a Data mask function that can be used in conjunction with data Write cycle only, not Read cycle. When the

Data Mask is activated (DM high) during write operation, the write data is masked immediately (DM to Data-mask Latency is Zero).

DM must be issued at the rising edge or the falling edge of Data Strobe instead of a clock edge.

< Burst Length = 8 >

NOP

/CK

Command

NOP

WRITE

DQS

DQ's

Din 0

DQSS

WPREH

WPRES

Din 1 Din 2

Din 3

Din 4

Din 5

Din 6

Din 7

Masked by DM=H

NT5DS4M32EF

4Mx32 Double Data Rate SDRAM

REV 0.1 (Preliminary)

06/2003

© NANYA TECHNOLOGY CORP.

NANYA TECHNOLOGY CORP. reserves the right to change Products and Specifications without notice.

AUTO-PRECHARGE OPERATION

The Auto precharge command can be issued by having column address A

High when a Read or a Write command is asserted into

the DDR SDRAM. If A

is low when Read or Write command is issued, normal Read or Write burst operation is asserted and the bank

remains active after the completion of the burst sequence. When the Auto precharge command is activated, the active bank

automatically begins to precharge at the earliest possible moment during read or write cycle after t

RAS(min)

is satisfied.

Read with Auto Precharge

If a Read with Auto-precharge command is initiated, the DDR SDRAM automatically starts the precharge operation on 2 clock

previous to the end of burst from a Read with Auto-Precharge command when t

RAS(min)

is satisfied. If not, the start point of

precharge operation will be delayed until t

RAS(min)

is satisfied. The bank started the Precharge operation once cannot be

reactivated and the new command can not be asserted until the Precharge time(t

) is satisfied.

< Burst Length = 4, /CAS Latency = 3 >

NOP

/CK

Command

NOP

READ A

Auto Precharge

NOP

BANK A

ACTIVE

DQS

DQ's

Douta0 Douta1

/CAS Latency = 3

* Bank can be reactivated at

completion of t

RCDR(min)

RAS(min)

Douta2 Douta3

Auto-Precharge start point

RC(min)

When the Read with Auto precharge command is issued, new command can be asserted at T5,T6 and T7 respectively as follows.

: AP = Auto Precharge

For same Bank

For Different Bank

Asserted

command

READ

READ+AP

Active

Precharge

READ +
No AP

READ +

Illegal

Legal

READ +

No AP

READ +

Illegal

Legal

Illegal

Legal

NT5DS4M32EF

4Mx32 Double Data Rate SDRAM

REV 0.1 (Preliminary)

06/2003

© NANYA TECHNOLOGY CORP.

NANYA TECHNOLOGY CORP. reserves the right to change Products and Specifications without notice.

Write with Auto Precharge

If A

is high when Write command is issued, the write with Auto-Precharge function is performed. Any new command to the same

bank should not be issued until the internal precharge is completed. The internal precharge begins after keeping t

WR(min)

< Burst Length = 4, /CAS Latency = 3 >

WRITE A

Auto Precharge

/CK

Command

NOP

BANK A

ACTIVE

DQS

DQ's

Din a0 Din a1

/CAS Latency = 3

* Bank can be reactivated at

completion of t

WPREH

Din a2 Din a3

Internal precharge starts

WPRES

Legal

Illegal

Precharge

Legal

Illegal

Active

Legal

Illegal

READ +

READ + AP

+ DM

READ + AP

+ DM

Illegal

READ + AP

Legal

Illegal

READ +

No AP

READ +

No AP

READ + No

AP + DM

READ + No

AP + DM

Illegal

READ

Legal

Illegal

WRITE+AP

WRITE + AP

Legal

Illegal

WRITE + No

WRITE

For Different Bank

For same Bank

Asserted

command

AP = Auto Precharge

DM : Refer to "Write Interrupted by Rean & DM" in page 16.

NT5DS4M32EF

4Mx32 Double Data Rate SDRAM

REV 0.1 (Preliminary)

06/2003

© NANYA TECHNOLOGY CORP.

NANYA TECHNOLOGY CORP. reserves the right to change Products and Specifications without notice.

PRECHARGE COMMAND

The precharge command is issued when /CS, /RAS, and /WE are low and /CAS is high at the rising edge of the clock, CK. The

precharge command can be used to precharge each bank respectively or all banks simultaneously. The Bank select addresses(BA

) are used to define which bank is precharged when the command is initiated. For write cycle, tWR(min.) must be satisfied from

the start of the last burst write cycle until the precharge command can be issued. After t

from the precharge, an active command to

the same bank can be initiated.

< Bank Selection for Precharge by Bank address bits >

Bank A Only

All Banks

Bank D Only

Bank C Only

Bank B Only

Precharge

BA0

BA1

A8/AP

AUTO REFRESH

An Auto Refresh command is issued by having /CS, /RAS and /CAS held low with CKE and /WE high at the rising edge of the clock,

CK. All banks must be precharged and idle for a t

RP(min)

before the Auto Refresh command is applied. The refresh addressing is

generated by the internal refresh address counter. This makes the address bits "Don't care" during an Auto Refresh command. When

the refresh cycle has completed, all banks will be in the idle state. A delay between the Auto Refresh command and the next Activate

Command or subsequent Auto Refresh Command must be greater than or equal to the tRFC

(min)

/CK

Command

PRE

tRFC

Auto

Refresh

CMD

CKE=High

NT5DS4M32EF

4Mx32 Double Data Rate SDRAM

REV 0.1 (Preliminary)

06/2003

© NANYA TECHNOLOGY CORP.

NANYA TECHNOLOGY CORP. reserves the right to change Products and Specifications without notice.

SELF REFRESH

A self refresh command is defined by having /CS, /RAS, /CAS and CKE low with /WE high at the rising edge of the clock (CK). Once

the self refresh command is initiated, CKE must be held low to keep the device in self refresh mode. During the self refresh operation,

all inputs except CKE are ignored. The clock is internally disabled during self refresh operation to reduce power consumption. The

self refresh is exited by supplying stable clock input before returning CKE high, asserting deselect or NOP command and then

asserting CKE high for longer than tXSR for locking of DLL.

/CK

Command

Self

Refresh

XSA

XSR

CKE

Active

Read

Exit self refresh to bank active command, a write command can be applied as far as tRCD is satisfied after any bank active command.

Exit self refresh to read command.

POWER DOWN MODE

The power down is entered when CKE Low, and exited when CKE High. Once the power down mode is initiated, all of the receiver

circuits except CK and CKE are gated off to reduce power consumption. The all banks should be in idle state prior to entering the

precharge power down mode and CKE should be set high at least 1tCK+tIS prior to Row active command. During power down mode,

refresh operations can't be performed, therefore the device cannot remain in power down mode longer than the refresh period(t

REF

) of

the device.

/CK

Command

CKE

Precharge

power

down

Entry

Precharge

power

down

Exit

Active

power

down

Entry

Active

power

down

Exit

Read

NOP

PDEX

NT5DS4M32EF

4Mx32 Double Data Rate SDRAM

REV 0.1 (Preliminary)

06/2003

© NANYA TECHNOLOGY CORP.

NANYA TECHNOLOGY CORP. reserves the right to change Products and Specifications without notice.

ABSOLUTE MAXIMUM RATINGS

Parameter

Voltage on any pin relative to Vss

Voltage on VDD supply relative to Vss

Storage Temperature

Power dissipation

Short circuit current

Symbol

, V

OUT

STG

Value

-0.5 ~ 3.6

-1.0 ~ 3.6

-55 ~ +150

2.0

Unit

Voltage on VDDQ supply relative to Vss

DDQ

-0.5 ~ 3.6

Note :

Permanent device damage may occur if ABSOLUTE MAXIMUM RATING are exceeded.
Functional operation should be restricted to recommended operating condition.
Exposure to higher than recommended voltage for extended periods of time could affect device reliability.

POWER & DC OPERATING CONDITIONS (SSTL_2 In/Out)

Recommended operating conditions (Voltage referenced to Vss=0V, TA=0 to 70

Parameter

Device supply Voltage

Output supply Voltage

Reference Voltage

Termination Voltage

Input logic high Voltage

Symbol

DDQ

REF

Vtt

Min

2.375

0.49* V

DDQ

REF

-0.04

REF

+0.15

Unit

Input logic low Voltage

-0.30

Output logic high Voltage

Vtt+0.76

Output logic low Voltage

Input leakage current

-5

Output leakage current

-5

Typ

2.50

VREF

Max

2.625

0.51* V

DDQ

REF

+0.04

DDQ

+0.30

REF

-0.15

Vtt-0.76

Note

= -15.2mA

= +15.2mA

Note :

1. For -25/28/-33/-36/-40/-45/-50, V

/ V

DDQ

= 2.5V

5% / 2.5V

2. V

REF

is expected to equal 0.50* V

DDQ

of the transmitting device and to track variations in the DC level of the same. Peak to peak noise on the V

REF

may not exceed

2% of the DC value. Thus, from 0.50* V

DDQ

, V

REF

is allowed

25mV for DC error and an additional

25mV for AC noise.

3. Vtt of the transmitting device must track V

REF

of the receiving device.

4. V

(max.) = V

DDQ

+1.5V for a pulse and it which can not be greater than 1/3 of the cycle rate.

5. V

(mim.) =-1.5V for a pulse width and it can not be greater than 1/3 of the cycle rate.

6. For any pin under test input of 0V

is acceptable. For all other pins that are not under test V

= 0V.

NT5DS4M32EF

4Mx32 Double Data Rate SDRAM

REV 0.1 (Preliminary)

06/2003

© NANYA TECHNOLOGY CORP.

NANYA TECHNOLOGY CORP. reserves the right to change Products and Specifications without notice.

DC CHARACTERISTICS

Recommended operating conditions (Voltage referenced to Vss=0V, V

DDQ

=2.5V

5%/ 2.5V

5%,, TA=0 to 70

Parameter

Operating current
(One Bank Active)

Symbol

Icc1

Test Condition

Burst Length=2, tRC

tRC(min)

IOL=0mA, tCK=tCK(min)

Unit

Precharge Standby Current
in Power-down mode

Icc2P

CKE

VIL(max), tCK=tCK(min)

Precharge Standby Current
in Non Power-down mode

Icc2N

CKE

VIH(min), /CS

VIH(min),

tCK=tCK(min).

Active Standby Current
in Power-down mode

Icc3P

CKE

VIL(max), tCK=tCK(min)

Active Standby Current
in Non Power-down mode

Icc3N

CKE

VIH(min), /CS

VIH(min),

tCK=tCK(min).

Operating Current
(Burst mode)

Icc4

IOL=0mA, tCK=tCK(min), Page Burst,
All Banks activated.

Refresh current

Icc5

tRC

tRFC(min)

Self Refresh current

Icc6

CKE

0.2V

Note

170 165 160 155 150

480 450 420 380 350

210 200 200 190 190

-40

-45

-50

-55

-60

Version

185 180 175

620 570 530

240 230 220

-28

-33

-36

Operating Current
(4Bank Interleaving)

Icc7

Burst Length=4, tRC

tRC(min)

IOL=0mA, tCK=tCK(min)

600 580 560 540 520

720 660 630

200

670

250

-25

770

100

Notes :

1. Measured with outputs open.
2. Refresh period is 32ms.

AC INPUT OPERATING CONDITIONS

Recommended operating conditions (Voltage referenced to Vss=0V, V

DDQ

=2.5V

5%/ 2.5V

5%,, TA=0 to 70

Parameter

Input High (Logic1) Voltage : DQ

Input Low (Logic0) Voltage : DQ

Clock input Differential Voltage ; CK and /CK

Clock input Crossing point Voltage ; CK and /CK

Symbol

VIH

VIL

VID

VIX

Min

REF

+0.35

0.7

0.5* V

DDQ

-0.2

Unit

Typ

Max

REF

-0.35

DDQ

+0.6

0.5* V

DDQ

+0.2

Note

Note :

1. VID is the magnitude of the difference between the input level on CK and the input level on /CK
2. The value of VIX is expected to equal 0.5* V

DDQ

of the transmitting device and must track variation in the DC level of the same

NT5DS4M32EF

4Mx32 Double Data Rate SDRAM

REV 0.1 (Preliminary)

06/2003

© NANYA TECHNOLOGY CORP.

NANYA TECHNOLOGY CORP. reserves the right to change Products and Specifications without notice.

AC OPERATING TEST CONDITIONS

=2.5V

0.125V, TA=0 to 70

Parameter

Input reference voltage for CK (for signal ended)

Value

0.50*

DDQ

Unit

CK and /CK signal maximum peak swing

1.5

CK signal minimum slew rate

1.0

V/ns

Input levels (VIH/VIL)

REF

+0.35 / V

REF

-0.35

Input timing measurement refrence level

REF

Output timing measurement refrence level

Vtt

Output load condition

See Fig.1

Note

Output

Z0=50

LOAD

=20pF

REF

=0.5*V

DDQ

=50

Vtt=0.5*V

DDQ

Fig.1) Output Load Circuit

CAPACITANCE

=2.5V, TA=25

C, f=1MHz)

Parameter

Input capacitance (A0~A11, BA0~BA1)

Input capacitance (CKE, /CS, /RAS, /CAS, /WE)

Data & DQS input/output capacitance (DQ0~DQ31)

Input capacitance (DM0 ~ DM3)

Symbol

CIN2

CIN3

COUT

CIN4

Min

2.0

4.0

Unit

Max

3.0

5.0

Input capacitance(CK, /CK,)

CIN1

2.0

3.0

DECOUPLING CAPACITANCE GUIDE LINE

Recommended decoupling capacitance added to power line at board.

Parameter

Decoupling Capacitance between VDD and VSS

Decoupling Capacitance between VDDQ and VSSQ

Symbol

CDC1

CDC2

Value

0.1+0.01

Unit

Note :

1. VDD and VDDQ pins are separated each other.

All VDD pins are connected in chip. All VDDQ pins are connected in chip.

2. VSS and VSSQ pins are separated each other.

All VSS pins are connected in chip. All VSSQ pins are connected in chip.

NT5DS4M32EF

4Mx32 Double Data Rate SDRAM

REV 0.1 (Preliminary)

06/2003

© NANYA TECHNOLOGY CORP.

NANYA TECHNOLOGY CORP. reserves the right to change Products and Specifications without notice.

AC CHARACTERISTICS(I)

Parameter

Symbol

-40

Unit Note

Min Max

-45

Min Max

-50

Min Max

-55

Min Max

-60

Min Max

CK cycle time

4.0

4.5

CK high level width

0.45

tCK

0.55

tCH

CK low level width

0.45

tCK

0.55

tCL

DQS out access time from CK

-0.6

-0.7

-0.75

+0.6

+0.7

+0.75

DQSCK

Output access time from CK

Data strobe edge to Dout edge

+0.40

+0.45

+0.5

DQSQ

Read preamble

0.9

tCK

1.1

RPRE

Read postamble

0.4

tCK

0.6

RPST

CK to valid DQS-in

0.8

0.75

tCK

1..2

1.25

DQSS

DQS-in setup time

WPRES

DQS-in hold time

0.35

0.30

0.25

tCK

WPREH

DQS write postamble

WPST

DQS-in high level width

DQSH

DQS-in low level width

DQSL

Address and Control input setup

0.9

1.0

1.1

Address and Control input hold

DQ and DM setup time to DQS

0.40

0.45

0.5

DQ and DM hold time to DQS

Clock half period

tCLmin

tCHmin

CL=3

CL=4

0.4

tCK

0.6

0.4

tCK

0.6

0.4

tCK

0.6

0.9

1.0

1.1

0.40

0.45

0.5

Data output hold time from DQS

tHP

-0.40

tCLmin

tCHmin

tCLmin

tCHmin

tCLmin

tCHmin

tCLmin

tCHmin

tHP

-0.45

tHP

-0.45

tHP
-0.5

-0.6

-0.7

-0.75

+0.6

+0.7

+0.75

-28

Min Max

-33

Min Max

-36

Min Max

2.8

3.3

3.6

0.45

0.55

0.45

0.55

-0.6

+0.6

+0.35

+0.40

0.9

1.1

0.4

0.6

0.85

1.15

0.35

035

0.9

0.35

0.40

tCLmin

tCHmin

0.4

0.6

0.4

0.6

0.4

0.6

0.9

0.35

0.40

tHP

-0.35

tCLmin

tCHmin

tCLmin

tCHmin

tHP

-0.35

tHP

-0.40

-0.6

-0.7

+0.6

+0.7

CL=2

3.6

4.0

4.5

5.0

5.5

6.0

0.85

1.15

0.85

1.15

0.85

1.15

3.6

5.5

-25

Min Max

2.5

0.45

0.55

0.45

0.55

-0.6

+0.6

+0.35

0.9

1.1

0.4

0.6

0.85

1.15

0.35

0.9

0.35

tCLmin

tCHmin

0.4

0.6

0.4

0.6

0.4

0.6

0.9

0.35

tHP

-0.35

-0.6

+0.6

3.6

Note 1:
-. Can support from -4 to -6 in CL2 with DLL enable.
-. Can support from -7 to -15 in CL2 with DLL disable set by EMRS.

Under set DLL disable by EMRS,

The tDQSCK can be 0.0ns in 100MHz operation. (-10)
The tDQSCK can be +1.5ns in 143MHz operation. (-7)
The tDQSCK can be -2.5ns in 66MHz operation. (-15)

- The JEDEC DDR specification currently defines the output data valid window(tDV) as the period when the data strobe and all data associated with that

data strobe are coincidentally valid.

-. The previously used definition of tDV(=0.35tDK) artificially penalizes system timing budgets by assuming the worst case output valid window even then

the clock duty cycle applied to the device is better than 45/55%

-. A new AC timing term,tQH which stands for data output hold time from DQS is defined to account for clock duty cycle variation and replaces

tDV - tQHmin = tHP-X

where . tHP=Minimum half clock period for any given cycle and is defined by clock high or clock low time(tCH,tCL)

. X=A frequency dependent timing allowance account for tDQSQmax

NT5DS4M32EF

4Mx32 Double Data Rate SDRAM

REV 0.1 (Preliminary)

06/2003

NANYA TECHNOLOGY CORP. reserves the right to change Products and Specifications without notice.

AC CHARACTERISTICS(II)

Parameter

Symbol

tRC

Refresh cycle time

tCK

Row active time

tCK

100K

tRAS

tCK

tRCDR

tRCDW

Row precharge time

tCK

tRP

Row active to Row active

tCK

tRRD

Last data in to Row precharge(@Normal)

tWR

tWTR

Col. address to Col. address

tCCD

Mode register set cycle time

tMRD

Auto precharge write recovery
+ Precharge

tDAL

tCK

tXSR

Power down exit time

tPDEX

Refresh interval time

tREF

Row cycle time

tCK

tRFC

/RAS to /CAS delay for Write

/RAS to /CAS delay for Read

Internal Write in to Read command

Exit self refresh to read command

100K

tCK

200

1tCK +

tIS

7.8

200

1tCK +

tIS

7.8

200

1tCK +

tIS

7.8

200

1tCK +

tIS

7.8

200

1tCK +

tIS

7.8

-40

Unit Note

Min Max

-45

Min Max

-50

Min Max

-55

Min Max

-60

Min Max

-28

Min Max

-33

Min Max

-36

Min Max

100K

200

1tCK +

tIS

7.8

200

1tCK +

tIS

7.8

200

1tCK +

tIS

7.8

Last data in to Row precharge(@Auto)

tWR_A

tCK

-25

Min Max

100K

200

1tCK +

tIS

7.8

tXSA

Exit self refresh to active command

Note

1. For normal write operation, even numbers of Din are to be written inside DRAM
2. A write command can be applied with tRCD satisfied after this command.

-. AC parameters for DLL Disable Mode(66MHz ~ 100MHz, CL2 only) : Same as "-60" AC parameters except tCK.

NT5DS4M32EF

4Mx32 Double Data Rate SDRAM

REV 0.1 (Preliminary)

06/2003

NANYA TECHNOLOGY CORP. reserves the right to change Products and Specifications without notice.

SIMPLIFIED TRUTH TABLE

COMMAND

CKEn-1

CKEn

/CS

/RAS /CAS

/WE

0,1

/AP

, A

Note

Extended Mode Register

Mode Register Set

OP CODE

1,2

Auto Refresh

Entry

Exit

Self
Refresh

Refresh

Bank Active & Row Address

Row Address

Auto Precharge Disable

Auto Precharge Enable

Read &
Column Addr.

Column
Address

Auto Precharge Disable

Auto Precharge Enable

Write &
Column Addr.

Column
Address

4,6

Burst Stop

Bank Selection

All Banks

Precharge

Entry

Exit

Entry

Exit

Active Power Down

Precharge Power Down
Mode

No Operation Command

( V=Valid, X=Don't care, H=Logic High, L=Logic Low )

Note : 1. OP CODE : Operand Code.

~ A

& BA

~ BA

: Program Keys. (@EMRS/MRS)

2. EMRS/MRS can be issued only at all banks precharge state

A new command can be issued after 2 clock cycle of EMRS/MRS

3. Auto refresh function are as same as CBR refresh of DRAM.

The automatic precharge without row precharge command is meant by "Auto".
Auto/Self refresh can be issued only at all banks precharge state.

4. BA

~ BA

: Bank select addresses.

If both BA

and BA

are "Low" at read, write, row active and precharge, bank A is selected.

If BA

is "High" and BA

is "Low" at read, write, row active and precharge, bank B is selected.

If BA

is "Low" and BA

is "High" at read, write, row active and precharge, bank C is selected.

If both BA

and BA

are "High" at read, write, row active and precharge, bank D is selected.

5. If A

AP is "high" at row precharge ,BA

and BA

are ignored and all banks are selected.

6. During burst write with auto precharge, new read/write command cannot be issued.

Another bank read/write command can be issued after the end of burst.
New row active of the associated bank can be issued at t

after the end of burst.

7. Burst stop command is valid at every burst length.
8. DM sampled at the rising and falling edges of the DQS and Data-in are masked at the both edges(Write DM latency is 0).

NT5DS4M32EF

4Mx32 Double Data Rate SDRAM

REV 0.1 (Preliminary)

06/2003

NANYA TECHNOLOGY CORP. reserves the right to change Products and Specifications without notice.

FUNCTION TRUTH TABLE

Current State

/CS

/RAS /CAS

/WE

Address

Command

Action

DESEL

NOP

TERM

NOP

, CA, A

READ/WRITE

ILLEGAL*2

BA, RA

ACT

Bank Active, Latch RA

BA, A

PRE/PREA

NOP*4

REFA

AUTO-Refresh*5

Op-Code, Mode-Add

MRS

Mode Register Set*5

IDLE

DESEL

NOP

TERM

NOP

BA, CA, A

READ/READA

Begin Read, Latcch CA,

Determine Auto-Precharge

BA, CA, A

WRITE/WRITEA

Begin Write, Latch CA,

Determine Auto-Precharge

BA, RA

ACT

ILLEGAL*2

BA, A

PRE/PREA

Precharge/Precharge All

REFA

ILLEGAL

Op-Code, Mode-Add

MRS

ILLEGAL

ROW ACTIVE

DESEL

NOP(Continue Burst to END)

NOP

NOP(Continue Burst to END)

TERM

Terminate Burst

BA, CA, A

READ/READA

Terminate Burst, Latch CA,

Begin New Read, Determine

Auto-Precharge*3

BA, CA, A

WRITE/WRITEA

ILLEGAL

BA, RA

ACT

ILLEGAL*2

BA, A

PRE/PREA

Terminate Burst, Precharge

REFA

ILLEGAL

Op-Code, Mode-Add

MRS

ILLEGAL

READ

DESEL

NOP(Continue Burst to END)

NOP

NOP(Continue Burst to END)

TERM

ILLEGAL

BA, CA, A

READ/READA

ILLEGAL

BA, CA, A

WRITE/WRITEA

Terminate Burst, Latch CA,
Begin new Write, Determine
Precharge*3

BA, RA

ACT

ILLEGAL*2

BA, A

PRE/PREA

Terminate Burst with DM=high
precharge

REFA

ILLEGAL

Op-Code, Mode-Add

MRS

ILLEGAL

WRITE

DESEL

NOP(Continue Burst to END)

NOP

NOP(Continue Burst to END)

TERM

ILLEGAL

BA, CA, A

READ/WRITE

ILLEGAL*2

BA, RA

ACT

ILLEGAL*2

BA, A

PRE/PREA

ILLEGAL*2

REFA

ILLEGAL

Op-Code, Mode-Add

MRS

ILLEGAL

READ with AUTO

PRECHARGE

NT5DS4M32EF

4Mx32 Double Data Rate SDRAM

REV 0.1 (Preliminary)

06/2003

NANYA TECHNOLOGY CORP. reserves the right to change Products and Specifications without notice.

FUNCTION TRUTH TABLE (continued)

Current State

/CS

/RAS /CAS

/WE

Address

Command

Action

DESEL

NOP(Continue Burst to END)

NOP

NOP(Continue Burst to END)

TERM

ILLEGAL

BA, CA, A

READ/WRITE

ILLEGAL*2

BA, RA

ACT

ILLEGAL*2

BA, A

PRE/PREA

ILLEGAL*2

REFA

ILLEGAL

Op-Code, Mode-Add

MRS

ILLEGAL

WRITE with AUTO

PRECHARGE

DESEL

NOP(Idle after tRP)

NOP

NOP(Idle after tRP)

TERM

NOP

BA, CA, A

READ/WRITE

ILLEGAL*2

BA, RA

ACT

ILLEGAL*2

BA, A

PRE/PREA

NOP*4(Idle after tRP)

REFA

ILLEGAL

Op-Code, Mode-Add

MRS

ILLEGAL

PRECHARGING

DESEL

NOP(ROW Active after tRCD)

NOP

NOP(ROW Active after tRCD)

TERM

NOP

BA, CA, A

READ/WRITE

ILLEGAL*2

BA, RA

ACT

ILLEGAL*2

BA, A

PRE/PREA

ILLEGAL*2

REFA

ILLEGAL

Op-Code, Mode-Add

MRS

ILLEGAL

ROW

ACTIVATING

WRITE

RECOVERING

RE-

FRESHING

BA, CA, A8

BA, RA

BA, A8

Op-Code, Mode-Add

BA, CA, A8

BA, RA

BA, A8

Op-Code, Mode-Add

DESEL

NOP

TERM

READ

WRITE/WRITEA

ACT

PRE/PREA

REFA

MRS

READ/WRITE

ACT

PRE/PREA

REFA

MRS

NOP

DESEL

TERM

NOP

ILLEGAL*2

New Write, Determine AP.

ILLEGAL*2

ILLEGAL

NOP(Idle after tRP)

NOP

ABBREVIATIONS :

H=High Level, L=Low Level, V=Valid, X=Don't care
BA=Bank Address, RA=Row Address, CA=Column Address, NOP=No Operation

Note :

1. All entries assume that CKE was High during the preceding clock cycle and the current clock cycle.
2. ILLEGAL to bank in specified state ; function may be legal in the bank indicated by BA, depending on the state of that bank.
3. Must satisfy bus contention, bus turn around, write recovery requirements.
4. NOP to bank precharging or in idle state, May precharge bank indicated by BA.
5. ILLEGAL if any bank is not idle.
6. Same bank's previous Auto precharge will not be performed. But if Bank is different, previous Auto precharge will be performed.

ILLEGAL = Device operation and/or data-integrity are not guaranteed.

NT5DS4M32EF

4Mx32 Double Data Rate SDRAM

REV 0.1 (Preliminary)

06/2003

NANYA TECHNOLOGY CORP. reserves the right to change Products and Specifications without notice.

FUNCTION TRUTH TABLE for CKE

Current State

SELF-

REFRESHING

Both Bank

Precharge

POWER

DOWN

/CS

/RAS

/CAS

/WE

Add

Action

INVALID

Exit Self-Refresh*1

ILLEGAL

NOP(Maintain Self-Refresh)

INVALID

Exit Power Down*2

ILLEGAL

NOP(Maintain Power Down)

Refer to Function True Table

Enter Power Down*3

ILLEGAL

Exit Power Down*2

ILLEGAL

CKE

n-1

CKE

Any State

other than

listed above

ALL BANKS

IDLE

OP Code

ILLEGAL

Row(& Bank) Active

Enter Self-Refresh *3

Begin Clock Suspend next cycle *4

Exit Clock Suspend next cycle *4

Maintain Clock Suspend

Refer to Current State=Power Down

Mode Register Access

Refer to Function True Table

ABBREVIATIONS :

H=High Level, L=Low Level, V=Valid, X=Don't care

Note :

1. After CKE's low to high transition to exist self refresh mode. And a time of tRC(min) has to be elapse after CKE's low to high

transition to issue a new command.

2. CKE low to high transition is asynchronous as if restarts internal clock.

A minimum setup time "tIS + one clock" must be satisfied before any command other than exit.

3. Power-down and self-refresh can be entered only from the all banks idle state.
4. Must be a legal command.

NT5DS4M32EF

4Mx32 Double Data Rate SDRAM

REV 0.1 (Preliminary)

06/2003

NANYA TECHNOLOGY CORP. reserves the right to change Products and Specifications without notice.

IBIS : I/V CHARACTERISTICS FOR INPUT AND OUTPUT BUFFERS

Reduced Output Driver Characteristics.

1. The nominal pulldown V-I curve for DDR SDRAM devices will be within the inner bounding lines of the V-I curve of below figure.

2. The full variation in driver pulldown current from minimum to maximum process, temperature and voltage will lie within the outer

bounding lines of the V-I curve of below figure

Maximum

Typical High

Typical Low

Minimum

0.0

10.0

20.0

30.0

40.0

50.0

60.0

70.0

80.0

0.1

0.6

1.1

1.6

2.1

Iout(mA)

Vout(V)

3. The nominal pullup V-I curve for DDR SDRAM devices will be within the inner bounding lines of the V-I curve of below figure.

4. The full variation in driver pullup current from minimum to maximum process, temperature and voltage will lie within the outer

bounding lines of the V-I curve of below figure

Maximum

Typical High

Typical Low

Minimum

-110.0

-100.0

-90.0

-80.0

-70.0

-60.0

-50.0

-40.0

-30.0

-20.0

-10.0

0.0

0.1

0.6

1.1

1.6

2.1

Iout(mA)

Vout(V)

5. The full variation in the ratio of the maximum to minimum pullup and pulldown current will not exceed 1.7, for device drain to

source voltage from 0 to VDDQ/2

6. The full variation in the ratio of the nominal pullup to pulldown current should be unity ±0%, for device drain to source voltages

from 0 to VDDQ/2

NT5DS4M32EF

4Mx32 Double Data Rate SDRAM

REV 0.1 (Preliminary)

06/2003

NANYA TECHNOLOGY CORP. reserves the right to change Products and Specifications without notice.

Pulldown Current(mA)

Pullup Current(mA)

Ty pical

Low

Ty pical

High

Minimum

Maximum

Ty pical

Low

Ty pical

High

Minimum

Maximum

0.1

3.3

3.7

2.5

4.8

-3.3

-4.1

-2.5

-4.9

0.2

6.6

7.3

5.0

9.4

-6.6

-7.8

-5.0

-9.7

0.3

9.8

10.9

7.4

14.0

-9.8

-11.4

-7.4

-14.5

0.4

13.0

14.4

10.0

18.3

-12.9

-14.9

-10.0

-19.2

0.5

16.1

17.8

12.4

22.6

-16.1

-18.4

-12.4

-23.9

0.6

18.7

21.1

14.9

26.7

-18.5

-21.9

-14.9

-28.4

0.7

21.3

23.9

17.4

30.7

-20.5

-25.3

-17.4

-32.9

0.8

23.6

26.9

19.9

34.1

-22.2

-28.7

-19.5

-37.3

0.9

25.6

29.8

21.4

37.7

-23.6

-32.1

-20.6

-41.7

1.0

27.7

32.6

23.0

41.2

-24.8

-35.4

-20.9

-46.0

1.1

29.2

35.2

24.2

44.5

-25.8

-38.6

-21.1

-50.7

1.2

30.3

37.7

25.0

47.7

-26.6

-41.9

-21.2

-54.3

1.3

31.3

40.1

25.4

50.7

-27.0

-45.2

-21.3

-58.4

1.4

32.0

42.4

25.6

53.5

-27.2

-48.4

-21.4

-62.4

1.5

32.5

44.4

25.8

56.0

-27.4

-51.6

-21.5

-66.4

1.6

32.7

46.4

25.9

58.6

-27.5

-54.7

-21.6

-70.4

1.7

32.9

48.1

26.2

60.6

-27.6

-57.8

-21.7

-73.8

1.8

33.2

49.8

26.4

62.6

-27.7

-60.7

-21.8

-77.8

1.9

33.5

51.5

26.5

64.6

-27.8

-64.1

-21.8

-81.3

2.0

33.8

52.5

26.7

66.6

-27.9

-67.0

-21.9

-84.7

2.1

33.9

53.5

26.8

68.3

-28.0

-69.8

-21.9

-88.1

2.2

34.2

54.5

26.9

69.9

-28.1

-72.7

-22.0

-91.6

2.3

34.5

55.0

27.0

71.5

-28.2

-75.6

-22.0

-95.0

2.4

34.6

55.5

27.0

72.9

-28.2

-78.4

-22.1

-97.0

2.5

34.9

56.0

27.1

74.1

-28.3

-81.3

-22.2

-101.3

Voltage

(V)

Temperature (Ambient)

Typical 25

Minimum

Maximum

Vdd/Vddq

Typical

2.50V / 2.50V

Minimum

2.375V / 2.375V

Maximum

2.625V / 2.625V

The above characteristics are specified under best, worst and normal process variation/conditions

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