1
REV 0.0 (Preliminary)
08/2002
NANYA TECHNOLOGY CORP.
NANYA TECHNOLOGY CORP. reserves the right to change Products and Specifications without notice.
NT5DU4M32EF
4Mx32 Double Data Rate SDRAM
128Mbit DDR SDRAM
1M x 32Bit x 4 Banks
Double Data Rate Synchronous RAM
With Bi-directional Data Strobe and DLL
(144-Ball FBGA)
Nanya Technology Corp.
Nanya Technology Corp.
NTC reserves the right to change products or specification without notice.
2
REV 0.0 (Preliminary)
08/2002
NANYA TECHNOLOGY CORP.
NANYA TECHNOLOGY CORP. reserves the right to change Products and Specifications without notice.
NT5DU4M32EF
4Mx32 Double Data Rate SDRAM
TABLE OF CONTENTS
Timing
- 32
Basic Timing(@BL=2, CL=3)
- 32
Multi Bank Interleaving Read(@BL=4,CL=3)
- 33
Multi Bank Interleaving Write(@BL=4,CL=3)
- 34
Auto Precharge after Read Burst(@BL=8)
- 35
Auto Precharge after Write Burst(@BL=4)
- 36
Normal Write Burst(@BL=4)
- 37
Write Interrupt by Precharge & DM(@BL=8)
- 38
Read Interrupt by Precharge(@BL=8)
- 39
Read Interrupt by Burst Stop & Write(@BL=8,CL=3) - 40
Read Interrupt by Read(@BL=8,CL=3)
- 41
DM Function only for Write(@BL=8)
- 42
Power up Sequence & Auto Refresh(CBR)
- 43
Mode Register Set
- 44
I/V Characteristics for Input and Output Buffer
- 45
Reduced Output Driver Characteristics
- 45
Impedance Match Output Driver Characteristics
- 47
Package Dimension(FBGA)
- 48
Table of Contents
- 2
Memory Part Numbering
- 3
General Description & Device Features
- 4
Pin Configuration & Pin Description
- 5
Input/Output Functional Description
- 6
Functional Block Diagram
- 7
Simplified State Diagram
- 8
Functional Description
- 9
Power up Sequence
- 9
Mode Register Set(MRS)
- 10
Extended Mode Register Set
- 11
Burst Mode Operation
- 12
Burst Length & Sequence
- 12
Bank Activation Command
- 12
Burst Read Operation
- 13
Burst Write Operation
- 13
Burst Interruption
- 14
Read Interrupt by Read
- 14
Read Interrupt by Burst Stop & Write
- 14
Read Interrupt by Precharge
- 15
Write Interrupt by Write
- 15
Write Interrupt by Read & DM
- 16
Write Interrupt by Precharge & DM
- 17
Burst Stop Command
- 18
DM Function
- 18
Auto Precharge Operation
- 19
Read with Auto Precharge
- 19
Write with Auto Precharge
- 20
Precharge Command
- 20
Auto Refresh
- 21
Self Refresh
- 21
Power Down Mode
- 22
Absolute Maximum Ratings
- 23
Power & DC Operating Conditions
- 23
DC Characteristics
- 24
AC Input Operating Conditions
- 24
AC Operating Test Conditions
- 25
Capacitance
- 25
Decoupling Capacitance Guide Line
- 25
AC Characteristics(I)
- 26
AC Characteristics(II)
- 27
Simplified Truth Table
- 28
Functional Truth Table
- 29
Functional Truth Table for CKE
- 31
3
REV 0.0 (Preliminary)
08/2002
NANYA TECHNOLOGY CORP.
NANYA TECHNOLOGY CORP. reserves the right to change Products and Specifications without notice.
NT5DU4M32EF
4Mx32 Double Data Rate SDRAM
1M x32Bit x4Banks Double Data Rate Synchronous RAM with Bi-directional Data Strobe and DLL
GENERAL DESCRIPTION
For 1M x 32Bit x 4 Bank DDR SDRAM
The NT5DU4M32EF is 134,217,728 bits of double data rate synchronous dynamic RAM organized as 4 x 1,048,576 bits by 32 I/Os.
Synchronous features with Data Strobe allow extremely high performance up to 2.4GB/s/chip. I/O transactions are possible on both
edges of the clock. Range of operating frequencies, programmable burst length and programmable latencies allow the device to be
useful for a variety of high performance memory system applications.
FEATURES
VDD = 1.8V
5% , VDDQ = 1.8V
5%
SSTL_18 compatible inputs/outputs
4 banks operation
MRS cycle with address key programs
-. Read latency 3, 4 (clock)
-. Burst length (2, 4, 8 and Full page)
-. Burst type (sequential & interleave)
Full page burst length for sequential burst type only
Start address of the full page burst should be even
All inputs except data & DM are sampled at the rising
edge of the system clock
Differential clock input(CK & /CK)
Data I/O transaction on both edges of Data strobe
4 DQS (1 DQS/Byte)
DLL aligns DQ and DQS transaction with Clock
transaction
Edge aligned data & data strobe output
Center aligned data & data strobe input
DM for write masking only
Auto & self refresh
32ms refresh period (4K cycle)
144-Ball FBGA package
Maximum clock frequency up to 300MHz
Maximum data rate up to 600Mbps/pin
ORDERING INFORMATION
Part NO.
NT5DU4M32EF-33
NT5DU4M32EF-4
NT5DU4M32EF-5
Max Freq.
300MHz
250MHz
200MHz
Max Data Rate
600Mbps/pin
500Mbps/pin
400Mbps/pin
Interface
Package
SSTL_18
144-Ball FBGA
NT5DU4M32EF-6
166MHz
332Mbps/pin
4
REV 0.0 (Preliminary)
08/2002
NANYA TECHNOLOGY CORP.
NANYA TECHNOLOGY CORP. reserves the right to change Products and Specifications without notice.
NT5DU4M32EF
4Mx32 Double Data Rate SDRAM
PIN CONFIGURATION (Top View)
DQS0
DM0
VSSQ
DQ3
DQ2
DQ0
DQ31
DQ29
DQ28
VSSQ
DM3
DQS3
VSS
Thermal
VSS
Thermal
VSS
Thermal
VSS
Thermal
VSS
Thermal
VSS
Thermal
VSS
Thermal
VSS
Thermal
VSS
Thermal
VSS
Thermal
VSS
Thermal
VSS
Thermal
VSS
Thermal
VSS
Thermal
VSS
Thermal
VSS
Thermal
DQ4
VDDQ
NC
VDDQ
DQ1
VDDQ
VDDQ
DQ30
VDDQ
NC
VDDQ
DQ27
DQ6
DQ5
VSSQ
VSSQ
VSSQ
VDD
VDD
VSSQ
VSSQ
VSSQ
DQ26
DQ25
DQ7
VDDQ
VDD
VSS
VSSQ
VSS
VSS
VSSQ
VSS
VDD
VDDQ
DQ24
DQ17
DQ16
VDDQ
VSSQ
DQ19
DQ18
VDDQ
VSSQ
DQS2
DM2
NC
VSSQ
DQ21
DQ20
VDDQ
VSSQ
VSSQ
VDDQ
DQ15
DQ14
VSSQ
VDDQ
DQ13
DQ12
VSSQ
NC
DM1
DQS1
VSSQ
VDDQ
DQ11
DQ10
DQ22
DQ23
VDDQ
VSSQ
VSS
VSS
VSS
VSS
VSSQ
VDDQ
DQ9
DQ8
/CAS
/WE
VDD
VSS
A10
VDD
VDD
RFU1
VSS
VDD
NC
NC
/RAS
NC
NC
BA1
A2
A11
A9
A5
RFU2
CK
/CK
MCL
/CS
NC
BA0
A0
A1
A3
A4
A6
A7
A8/AP
CKE
VREF
1
2
3
4
5
6
7
8
9
10 11 12
A
B
C
D
E
F
G
H
J
K
L
M
NOTE :
1. RFU1 is reserved for A12
2. RFU2 is reserved for BA2
3. VSS Thermal balls are optional
PIN Description
Bank Select Address
Address Input
Data Input/Output
Power
Ground
Power for DQ's
Ground for DQ's
Must Connect Low
BA
0
, BA
1
A
0
~ A
11
DQ
0 ~
DQ
31
V
DD
V
SS
V
DDQ
V
SSQ
MCL
Differential Clock Input
Clock Enable
Chip Select
Row Address Strobe
Column Address Strobe
Write Enable
Data Strobe
Data Mask
Reserved for Future Use
CK, /CK
CKE
/CS
/RAS
/CAS
/WE
DQS
DM
RFU
5
REV 0.0 (Preliminary)
08/2002
NANYA TECHNOLOGY CORP.
NANYA TECHNOLOGY CORP. reserves the right to change Products and Specifications without notice.
NT5DU4M32EF
4Mx32 Double Data Rate SDRAM
INPUT/OUTPUT FUNCTIONAL DESCRIPTION
This pin is recommended to be left "No Connection" on the device
No Connection/
Reserved for future use
NC/RFU
Must Connect Low
Must Connect Low
MCL
Reference voltage for inputs, used for SSTL interface.
Power Supply
V
REF
Isolated power supply and ground for the output buffers to provide improved
noise immunity.
Power Supply
V
DDQ
,V
SSQ
Power and ground for the input buffers and core logic.
Power Supply
V
DD
,V
SS
Row,Column addresses are multiplexed on the same pin. Row address : RA
0
~ RA
11
,
Column address : CA
0
~ CA
7
. Column address CA
8
is used for auto precharge.
Input
A
0
~ A
11
Select which bank is to be active.
Input
BA
0
, BA
1
Data inputs and outputs are multiplexed on the same pins.
Input,Output
DQ
0
~ DQ
31
Data-In mask. Data-In is masked by DM Latency=0 when DM is high in burst write. DM
0
for DQ
0
~ DQ
7
,
DM
1
for DQ
8
~ DQ
15
, DM
2
for DQ
16
~ DQ
23
, DM
3
for DQ
24
~ DQ
31
.
Input
DM
0
~ DM
3
Data inputs and outputs are synchronized with both edge of DQS.
DQS
0
for DQ
0
~DQ
7
, DQS
1
for DQ
8
~DQ
15
, DQS
2
for DQ
16
~DQ
23
, DQS
3
for DQ
24
~DQ
31
Input,Output
DQS
0
~DQS
3
Enables write operation and row precharge.
Latches data in starting from /CAS, /WE active.
Input
/WE
Latches Column addresses on the positive going edge of the CK with /CAS
low. Enables column access.
Input
/CAS
Latches row addresses on the positive going edge of the CK with /RAS low.
Enables row access & precharge.
Input
/RAS
/CS enables(registered Low) and disables(registered High) the command decoder. When /CS is
registered High,new commands are ignored but previous operations are continued.
Input
/CS
CKE high activates and CKE low deactivates the internal clock,input buffers and output drivers. By
deactivating the clock, CKE low indicates the Power down mode or Self refresh mode.
The differential system clock inputs.
All of the input are sampled on the rising edge of the clock except DQ's and
DM's that are sampled on both edges of the DQS.
Function
Input
Input
Type
CKE
CK, /CK
#
Symbol
#
: The timing reference point for the differential clocking is the cross point of CK and /CK.
For any applications using the single ended clocking, apply V
REF
to /CK pin.
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