NT5SV16M4DT
NT5SV8M8DT
NT5SV4M16DT
64Mb Synchronous DRAM
REV 1.1
10/01
1
NANYA TECHNOLOGY CORP
. All rights reserved.
NANYA TECHNOLOGY CORP. reserves the right to change Products and Specifications without notice.
Features
High Performance:
Single Pulsed RAS Interface
Fully Synchronous to Positive Clock Edge
Four Banks controlled by BS0/BS1 (Bank Select)
Programmable CAS Latency: 2, 3
Programmable Burst Length: 1, 2, 4, 8, Full page
Programmable Wrap: Sequential or Interleave
Multiple Burst Read with Single Write Option
Automatic and Controlled Precharge Command
Data Mask for Read/Write control (x4, x8)
Dual Data Mask for byte control (x16)
Auto Refresh (CBR) and Self Refresh
Suspend Mode and Power Down Mode
Standard Power operation
4096 refresh cycles/64ms
Random Column Address every CK (1-N Rule)
Single 3.3V
0.3V Power Supply
LVTTL compatible
Package:
54-pin 400 mil TSOP-Type II
Description
The NT5SV16M4DT, NT5SV8M8DT, and NT5SV4M16DT
are four-bank Synchronous DRAMs organized as 4Mbit x 4
I/O x 4 Bank, 2Mbit x 8 I/O x 4 Bank, and 1Mbit x 16 I/O x 4
Bank, respectively. These synchronous devices achieve
high-speed data transfer rates of up to 200MHz by employing
a pipeline chip architecture that synchronizes the output data
to a system clock. The chip is fabricated with NTC's
advanced 64Mbit single transistor CMOS DRAM process
technology.
The device is designed to comply with all JEDEC standards
set for synchronous DRAM products, both electrically and
mechanically. All of the control, address, and data input/out-
put (I/O or DQ) circuits are synchronized with the positive
edge of an externally supplied clock.
RAS, CAS, WE, and CS are pulsed signals which are exam-
ined at the positive edge of each externally applied clock
(CK). Internal chip operating modes are defined by combina-
tions of these signals and a command decoder initiates the
necessary timings for each operation. A fourteen bit address
bus accepts address data in the conventional RAS/CAS mul-
tiplexing style. Twelve row addresses (A0-A11) and two bank
select addresses (BS0, BS1) are strobed with RAS. Eleven
column addresses (A0-A9) plus bank select addresses and
A10 are strobed with CAS. Column address A9 is dropped on
the x8 device, and column addresses A8 and A9 are dropped
on the x16 device.
Prior to any access operation, the CAS latency, burst length,
and burst sequence must be programmed into the device by
address inputs A0-A11, BS0, BS1 during a mode register set
cycle. In addition, it is possible to program a multiple burst
sequence with single write cycle for write through cache oper-
ation.
Operating the four memory banks in an interleave fashion
allows random access operation to occur at a higher rate
than is possible with standard DRAMs. A sequential and gap-
less data rate of up to 200MHz is possible depending on
burst length, CAS latency, and speed grade of the device.
Simultaneous operation of both decks of a stacked device is
allowed, depending on the operation being done. Auto
Refresh (CBR) and Self Refresh operation are supported.
-6K
-7K
-7
Units
f
CK
Clock
Frequency
166
133
143
133
143
MHz
t
CK
Clock Cycle
6
7.5
7
7.5
7
ns
CL CAS Latency CL=3 CL=2 CL=3 CL=2
CL=3
CKs
t
AC
Clock Access
Time
1
---
--
---
--
--
ns
t
AC
Clock Access
Time
2
5.4
5.4
5.4
5.4
5.4
ns
1. Terminated load. See AC Characteristics on page 16.
2. Unterminated load. See AC Characteristics on page 16.
NT5SV16M4DT
NT5SV8M8DT
NT5SV4M16DT
64Mb Synchronous DRAM
REV 1.1
10/01
2
NANYA TECHNOLOGY CORP
. All rights reserved.
NANYA TECHNOLOGY CORP. reserves the right to change Products and Specifications without notice.
Pin Assignments for Planar Components
(Top View)
54-pin Plastic TSOP(II) 400 mil
4Mbit x 4 I/O x 4 Bank
NT5SV16M4DT
1
2
3
4
5
6
9
10
11
12
13
14
7
8
15
16
17
18
19
20
21
22
54
53
52
51
50
49
46
45
44
43
42
41
48
47
40
39
38
37
36
35
34
33
V
DD
NC
V
DDQ
NC
DQ0
V
SSQ
V
DDQ
NC
DQ1
V
SSQ
NC
V
DD
NC
NC
NC
WE
CAS
RAS
CS
BS0
BS1
V
SS
NC
V
SSQ
NC
DQ3
V
DDQ
V
SSQ
NC
DQ2
V
DDQ
NC
V
SS
NC
NC
NC
DQM
CK
CKE
NC
A11
A9
23
24
25
32
31
30
A10/AP
A0
A1
A2
A8
A7
A6
A5
26
27
29
28
A3
V
DD
A4
V
SS
V
DD
DQ0
V
DDQ
NC
DQ1
V
SSQ
V
DDQ
NC
DQ3
V
SSQ
NC
V
DD
NC
DQ2
NC
WE
CAS
RAS
CS
BS0
BS1
A10/AP
A0
A1
A2
A3
V
DD
V
SS
DQ7
V
SSQ
NC
DQ6
V
DDQ
V
SSQ
NC
DQ4
V
DDQ
NC
V
SS
NC
DQ5
NC
DQM
CK
CKE
NC
A11
A9
A8
A7
A6
A5
A4
V
SS
V
DD
DQ0
V
DDQ
DQ1
DQ2
V
SSQ
V
DDQ
DQ5
DQ6
V
SSQ
DQ7
V
DD
DQ3
DQ4
LDQM
WE
CAS
RAS
CS
BS0
BS1
A10/AP
A0
A1
A2
A3
V
DD
V
SS
DQ15
V
SSQ
DQ14
DQ13
V
DDQ
V
SSQ
DQ10
DQ9
V
DDQ
DQ8
V
SS
DQ12
DQ11
NC
UDQM
CK
CKE
NC
A11
A9
A8
A7
A6
A5
A4
V
SS
1Mbit x 16 I/O x 4 Bank
NT5SV4M16DT
2Mbit x 8 I/O x 4 Bank
NT5SV8M8DT
NT5SV16M4DT
NT5SV8M8DT
NT5SV4M16DT
64Mb Synchronous DRAM
REV 1.1
10/01
3
NANYA TECHNOLOGY CORP
. All rights reserved.
NANYA TECHNOLOGY CORP. reserves the right to change Products and Specifications without notice.
Pin Description
CK
Clock Input
DQ0-DQ15
Data Input/Output
CKE
Clock Enable
DQM, LDQM, UDQM
Data Mask
CS
Chip Select
V
DD
Power (+3.3V)
RAS
Row Address Strobe
V
SS
Ground
CAS
Column Address Strobe
V
DDQ
Power for DQs (+3.3V)
WE
Write Enable
V
SSQ
Ground for DQs
BS1, BS0
Bank Select
NC
No Connection
A0 - A11
Address Inputs
--
--
Input/Output Functional Description
Symbol
Type
Polarity
Function
CLK
Input
Positive
Edge
The system clock input. All of the SDRAM inputs are sampled on the rising edge of the clock.
CKE
Input
Active High
Activates the CLK signal when high and deactivates the CLK signal when low. By deactivating the
clock, CKE low initiates the Power Down mode, Suspend mode, or the Self Refresh mode.
CS
Input
Active Low
CS enables the command decoder when low and disables the command decoder when high. When the
command decoder is disabled, new commands are ignored but previous operations continue.
RAS, CAS,
WE
Input
Active Low
When sampled at the positive rising edge of the clock, CAS, RAS, and WE define the operation to be
executed by the SDRAM.
BS0, BS1
Input
--
Selects which bank is to be active.
A0 - A11
Input
--
During a Bank Activate command cycle, A0-A11 defines the row address (RA0-RA11) when sampled at
the rising clock edge.
During a Read or Write command cycle, A0-A9 defines the column address (CA0-CA9) when sampled
at the rising clock edge.
A10 is used to invoke auto-precharge operation at the end of the burst read or write cycle. If A10 is
high, auto-precharge is selected and BS0, BS1 defines the bank to be precharged. If A10 is low, auto-
precharge is disabled.
During a Precharge command cycle, A10 is used in conjunction with BS0, BS1 to control which bank(s)
to precharge. If A10 is high, all banks will be precharged regardless of the state of BS. If A10 is low,
then BS0 and BS1 are used to define which bank to precharge.
DQ0 - DQ15
Input-
Output
--
Data Input/Output pins operate in the same manner as on conventional DRAMs.
DQM
LDQM
UDQM
Input
Active High
The Data Input/Output mask places the DQ buffers in a high impedance state when sampled high. In
x16 products, LDQM and UDQM control the lower and upper byte I/O buffers, respectively. In Read
mode, DQM has a latency of two clock cycles and controls the output buffers like an output enable.
DQM low turns the output buffers on and DQM high turns them off. In Write mode, DQM has a latency
of zero and operates as a word mask by allowing input data to be written if it is low but blocks the write
operation if DQM is high.
V
DD
, V
SS
Supply
--
Power and ground for the input buffers and the core logic.
V
DDQ
V
SSQ
Supply
--
Isolated power supply and ground for the output buffers to provide improved noise immunity.
NT5SV16M4DT
NT5SV8M8DT
NT5SV4M16DT
64Mb Synchronous DRAM
REV 1.1
10/01
4
NANYA TECHNOLOGY CORP
. All rights reserved.
NANYA TECHNOLOGY CORP. reserves the right to change Products and Specifications without notice.
Ordering Information
Organization
Part Number
Speed Grade
Power
Supply
Package
Clock Frequency@CAS Latency
Note
16M x 4
NT5SV16M4DT-6K
166MHz@CL3
133MHz@CL2
PC133 , PC100
3.3 V
400mil 54-PIN
TSOP II
NT5SV16M4DT-7K
143MHz@CL3
133MHz@CL2
NT5SV16M4DT-7
143MHz@CL3
100MHz@CL2
8M x 8
NT5SV8M8DT-6K
166MHz@CL3
133MHz@CL2
NT5SV8M8DT-7K
143MHz@CL3
133MHz@CL2
NT5SV8M8DT-7
143MHz@CL3
100MHz@CL2
4M x 16
NT5SV4M16DT
-
6K
166MHz@CL3
133MHz@CL2
NT5SV4M16DT-7K
143MHz@CL3
133MHz@CL2
NT5SV4M16DT-7
143MHz@CL3
100MHz@CL2
NT5SV16M4DT
NT5SV8M8DT
NT5SV4M16DT
64Mb Synchronous DRAM
REV 1.1
10/01
5
NANYA TECHNOLOGY CORP
. All rights reserved.
NANYA TECHNOLOGY CORP. reserves the right to change Products and Specifications without notice.
Block Diagram
DQ
0
DQ
X
D
a
t
a
I
n
p
u
t
/
O
u
t
p
u
t
B
u
f
f
e
r
s
CKE Buffer
CLK Buffer
CKE
CLK
CS
RAS
CAS
DQM
WE
C
o
m
m
a
n
d
D
e
c
o
d
e
r
M
o
d
e
R
e
g
i
s
t
e
r
C
o
u
n
t
e
r
C
o
l
u
m
n
A
d
d
r
e
s
s
C
o
u
n
t
e
r
R
e
f
r
e
s
h
A1
A2
A3
A4
A5
A6
A7
A10
A8
A9
A0
A11
Sense Amplifiers
Memory Bank 1
Cell Array
R
o
w
D
e
c
o
d
e
r
A
d
d
r
e
s
s
B
u
f
f
e
r
s
(
1
4
)
Column Decoder
Sense Amplifiers
Memory Bank 3
Cell Array
R
o
w
D
e
c
o
d
e
r
Column Decoder
Sense Amplifiers
Memory Bank 0
Cell Array
R
o
w
D
e
c
o
d
e
r
Column Decoder
Sense Amplifiers
Memory Bank 2
Cell Array
R
o
w
D
e
c
o
d
e
r
Column Decoder
D
a
t
a
C
o
n
t
r
o
l
C
i
r
c
u
i
t
r
y
BS1
BS0
C
o
n
t
r
o
l
S
i
g
n
a
l
G
e
n
e
r
a
t
o
r
Cell Array, per bank, for 4Mb x 4 DQ: 4096 Row x 1024 Col x 4 DQ (DQ0-DQ3).
Cell Array, per bank, for 2Mb x 8 DQ: 4096 Row x 512 Col x 8 DQ (DQ0-DQ7)
.
Cell Array, per bank, for 1Mb x 16 DQ: 4096 Row x 256 Col x 16 DQ (DQ0-DQ15).
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