Document Outline
- COVER
- Features
- Ordering Information
- Pin Configuration
- Block Diagram
- Electrical Specifications
- Package Drawing
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1999
MOS INTEGRATED CIRCUIT
PD448012-X
8M-BIT CMOS STATIC RAM
512K-WORD BY 16-BIT
EXTENDED TEMPERATURE OPERATION
Document No. M14466EJ5V0DS00 (5th edition)
Date Published July 2001 NS CP (K)
Printed in Japan
DATA SHEET
The mark
5
5
5
5
shows major revised points.
Description
The
PD448012-X is a high speed, low power, 8,388,608 bits (524,288 words by 16 bits) CMOS static RAM.
The
PD448012-X has two chip enable pins (/CE1, CE2) to extend the capacity.
The
PD448012-X is packed in 48-pin PLASTIC TSOP (I) (Normal bent).
Features
524,288 words by 16 bits organization
Fast access time: 55, 70, 85, 100, 120 ns (MAX.)
Byte data control: /LB (I/O1 - I/O8), /UB (I/O9 - I/O16)
Low voltage operation
(B version: V
CC
= 2.7 to 3.6 V, C version: V
CC
= 2.2 to 3.6 V)
Low V
CC
data retention : 1.0 V (MIN.)
Operating ambient temperature: T
A
= 25 to +85C
Output Enable input for easy application
Two Chip Enable inputs: /CE1, CE2
Part number
Access time
Operating supply Operating ambient
Supply current
ns (MAX.)
voltage
temperature
At operating
At standby
At data retention
V
C
mA (MAX.)
A (MAX.)
A (MAX.)
PD448012-BxxX
55, 70, 85, 100
2.7 to 3.6
-
25 to +85
45
Note
15
6
PD448012-CxxX
70, 85, 100, 120
2.2 to 3.6
45
Note Cycle time
70 ns,
PD448012-B55X : 50 mA
Data Sheet M14466EJ5V0DS
2
PD448012-X
Ordering Information
Part number
Package
Access time
Operating
Operating
Remark
ns (MAX.)
supply voltage
temperature
V
C
PD448012GY-B55X-MJH
48-pin PLASTIC TSOP (I)
55
2.7 to 3.6
-
25 to +85
B version
PD448012GY-B70X-MJH
(12x18) (Normal bent)
70
PD448012GY-B85X-MJH
85
PD448012GY-B10X-MJH
100
PD448012GY-C70X-MJH
70
2.2 to 3.6
C version
PD448012GY-C85X-MJH
85
PD448012GY-C10X-MJH
100
PD448012GY-C12X-MJH
120
Data Sheet M14466EJ5V0DS
3
PD448012-X
Pin Configuration (Marking Side)
/xxx indicates active low signal.
48-pin PLASTIC TSOP (I) (12x18) (Normal bent)
[
PD448012GY-BxxX-MJH ]
[
PD448012GY-CxxX-MJH ]
A15
A14
A13
A12
A11
A10
A9
A8
NC
NC
/WE
CE2
NC
/UB
/LB
A18
A17
A7
A6
A5
A4
A3
A2
A1
A16
NC
GND
I/O16
I/O8
I/O15
I/O7
I/O14
I/O6
I/O13
I/O5
V
CC
I/O12
I/O4
I/O11
I/O3
I/O10
I/O2
I/O9
I/O1
/OE
GND
/CE1
A0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
A0 - A18
: Address inputs
I/O1 - I/O16 : Data inputs / outputs
/CE1, CE2
: Chip Enable 1, 2
/WE
: Write Enable
/OE
: Output Enable
/LB, /UB
: Byte data select
V
CC
: Power supply
GND
: Ground
NC
: No Connection
Remark Refer to Package Drawing for the 1-pin index mark.
Data Sheet M14466EJ5V0DS
4
PD448012-X
Block Diagram
Address buffer
Address
buffer
Row
decoder
Memory cell array
8,388,608 bits
Input data
controller
A0
A18
I/O9 - I/O16
/CE1
/WE
/OE
CE2
/UB
/LB
Output data
controller
I/O1 - I/O8
V
CC
GND
Sense amplifier /
Switching circuit
Column decoder
Truth Table
/CE1
CE2
/OE
/WE
/LB
/UB
Mode
I/O
Supply current
I/O1 - I/O8
I/O9 - I/O16
H
Not selected
High impedance
High impedance
I
SB
L
L
H
H
H
Output disable
High impedance
High impedance
I
CCA
L
H
L
L
Word read
D
OUT
D
OUT
L
H
Lower byte read
D
OUT
High impedance
H
L
Upper byte read
High impedance
D
OUT
L
L
L
Word write
D
IN
D
IN
L
H
Lower byte write
D
IN
High impedance
H
L
Upper byte write
High impedance
D
IN
H
H
Not selected
High impedance
High impedance
I
SB
Remark
: V
IH
or V
IL
Data Sheet M14466EJ5V0DS
5
PD448012-X
Electrical Specifications
Absolute Maximum Ratings
Parameter
Symbol
Condition
Rating
Unit
Supply voltage
V
CC
0.5
Note
to +4.0
V
Input / Output voltage
V
T
0.5
Note
to V
CC
+ 0.4 (4.0 V MAX.)
V
Operating ambient temperature
T
A
25 to +85
C
Storage temperature
T
stg
55 to +125
C
Note 3.0 V (MIN.) (Pulse width : 30 ns)
Caution Exposing the device to stress above those listed in Absolute Maximum Rating could cause
permanent damage. The device is not meant to be operated under conditions outside the limits
described in the operational section of this specification. Exposure to Absolute Maximum Rating
conditions for extended periods may affect device reliability.
Recommended Operating Conditions
Parameter
Symbol
Condition
PD448012-BxxX
PD448012-CxxX
Unit
MIN.
MAX.
MIN.
MAX.
Supply voltage
V
CC
2.7
3.6
2.2
3.6
V
High level input voltage
V
IH
2.7 V
V
CC
3.6 V
2.4
V
CC
+ 0.4
2.4
V
CC
+ 0.4
V
2.2 V
V
CC
< 2.7 V
2.0
V
CC
+ 0.3
Low level input voltage
V
IL
0.3
Note
+0.5
0.3
Note
+0.3
V
Operating ambient temperature
T
A
25
+85
25
+85
C
Note 1.5 V (MIN.) (Pulse width: 30 ns)
Capacitance (T
A
= 25
C, f = 1 MHz)
Parameter
Symbol
Test condition
MIN.
TYP.
MAX.
Unit
Input capacitance
C
IN
V
IN
= 0 V
8
pF
Input / Output capacitance
C
I/O
V
I/O
= 0 V
10
pF
Remarks 1. V
IN
: Input voltage, V
I/O
: Input / Output voltage
2. These parameters are not 100% tested.
Data Sheet M14466EJ5V0DS
6
PD448012-X
DC Characteristics (Recommended Operating Conditions Unless Otherwise Noted) (1/2)
Parameter
Symbol
Test condition
V
CC
2.7 V
Unit
PD448012-BxxX
MIN.
TYP.
MAX.
Input leakage current
I
LI
V
IN
= 0 V to V
CC
1.0
+1.0
A
I/O leakage current
I
LO
V
I/O
= 0 V to V
CC
, /CE1 = V
IH
or
1.0
+1.0
A
CE2 = V
IL
or /WE = V
IL
or /OE = V
IH
Operating supply current
I
CCA1
/CE1 = V
IL
, CE2 = V
IH
,
Cycle time = 55 ns
50
mA
Minimum cycle time,
Cycle time
70 ns
45
I
I/O
= 0 mA
I
CCA2
/CE1 = V
IL
, CE2 = V
IH
, I
I/O
= 0 mA,
4
Cycle time =
I
CCA3
/CE1
0.2 V, CE2
V
CC
0.2 V,
6
Cycle time = 1
s, I
I/O
= 0 mA,
V
IL
0.2 V, V
IH
V
CC
0.2 V
Standby supply current
I
SB
/CE1 = V
IH
or CE2 = V
IL
or /LB = /UB = V
IH
0.6
mA
I
SB1
/CE1
V
CC
-
0.2 V, CE2
V
CC
-
0.2 V
1.0
15
A
I
SB2
CE2
0.2 V
1.0
15
I
SB3
/LB = /UB
V
CC
-
0.2 V,
1.0
15
/CE1
0.2 V, CE2
V
CC
-
0.2 V
High level output voltage
V
OH
I
OH
= 0.5 mA
2.4
V
Low level output voltage
V
OL
I
OL
= 1.0 mA
0.4
V
Remarks 1. V
IN
: Input voltage, V
I/O
: Input / Output voltage
2. These DC characteristics are in common regardless of product classification.
Data Sheet M14466EJ5V0DS
7
PD448012-X
DC Characteristics (Recommended Operating Conditions Unless Otherwise Noted) (2/2)
Parameter
Symbol
Test condition
V
CC
2.2 V
Unit
PD448012-CxxX
MIN.
TYP.
MAX.
Input leakage current
I
LI
V
IN
= 0 V to V
CC
1.0
+1.0
A
I/O leakage current
I
LO
V
I/O
= 0 V to V
CC
, /CE1 = V
IH
or
1.0
+1.0
A
CE2 = V
IL
or /WE = V
IL
or /OE = V
IH
Operating supply current
I
CCA1
/CE1 = V
IL
, CE2 = V
IH
, Minimum cycle time,
45
mA
I
I/O
= 0 mA
V
CC
2.7 V
30
I
CCA2
/CE1 = V
IL
, CE2 = V
IH
, I
I/O
= 0 mA,
4
Cycle time =
V
CC
2.7 V
2
I
CCA3
/CE1
0.2 V, CE2
V
CC
0.2 V,
6
Cycle time = 1
s, I
I/O
= 0 mA, V
IL
0.2 V,
V
IH
V
CC
0.2 V
V
CC
2.7 V
5
Standby supply current
I
SB
/CE1 = V
IH
or CE2 = V
IL
or
0.6
mA
/LB = /UB = V
IH
V
CC
2.7 V
0.6
I
SB1
/CE1
V
CC
-
0.2 V,
1.0
15
A
CE2
V
CC
-
0.2 V
V
CC
2.7 V
0.9
13
I
SB2
CE2
0.2 V
1.0
15
V
CC
2.7 V
0.9
13
I
SB3
/LB = /UB
V
CC
-
0.2 V, /CE1
0.2 V,
1.0
15
CE2
V
CC
-
0.2 V
V
CC
2.7 V
0.9
13
High level output voltage
V
OH
I
OH
= 0.5 mA
2.4
V
V
CC
2.7 V
1.8
Low level output voltage
V
OL
I
OL
= 1.0 mA
0.4
V
Remarks 1. V
IN
: Input voltage, V
I/O
: Input / Output voltage
2. These DC characteristics are in common regardless of product classification.
Data Sheet M14466EJ5V0DS
8
PD448012-X
AC Characteristics (Recommended Operating Conditions Unless Otherwise Noted)
AC Test Conditions
[
PD448012-B55X,
PD448012-B70X,
PD448012-B85X,
PD448012-B10X ]
Input Waveform (Rise and Fall Time
5 ns)
0.1
V
CC
0.9
V
CC
Test points
V
CC
/2
V
CC
/2
Output Waveform
Test points
V
CC
/2
V
CC
/2
Output Load
1TTL + 50 pF
[
PD448012-C70X,
PD448012-C85X,
PD448012-C10X,
PD448012-C12X ]
Input Waveform (Rise and Fall Time
5 ns)
0.1
V
CC
0.9
V
CC
Test points
V
CC
/2
V
CC
/2
Output Waveform
Test points
V
CC
/2
V
CC
/2
Output Load
1TTL + 30 pF
Data Sheet M14466EJ5V0DS
9
PD448012-X
Read Cycle (1/2) (B version)
Parameter
Symbol
V
CC
2.7 V
Unit
Condition
PD448012
PD448012
PD448012
PD448012
-B55X
-B70X
-B85X
-B10X
MIN.
MAX.
MIN.
MAX.
MIN.
MAX.
MIN.
MAX.
Read cycle time
t
RC
55
70
85
100
ns
Address access time
t
AA
55
70
85
100
ns
Note 1
/CE1 access time
t
CO1
55
70
85
100
ns
CE2 access time
t
CO2
55
70
85
100
ns
/OE to output valid
t
OE
30
35
40
50
ns
/LB, /UB to output valid
t
BA
55
70
85
100
ns
Output hold from address change
t
OH
10
10
10
10
ns
/CE1 to output in low impedance
t
LZ1
10
10
10
10
ns
Note 2
CE2 to output in low impedance
t
LZ2
10
10
10
10
ns
/OE to output in low impedance
t
OLZ
0
0
0
0
ns
/LB, /UB to output in low impedance
t
BLZ
10
10
10
10
ns
/CE1 to output in high impedance
t
HZ1
20
25
30
35
ns
CE2 to output in high impedance
t
HZ2
20
25
30
35
ns
/OE to output in high impedance
t
OHZ
20
25
30
35
ns
/LB, /UB to output in high impedance
t
BHZ
20
25
30
35
ns
Notes 1. The output load is 1TTL + 50 pF.
2. The output load is 1TTL + 5 pF.
Read Cycle (2/2) (C version)
Parameter
Symbol
V
CC
2.2 V
Unit
Condition
PD448012
PD448012
PD448012
PD448012
-C70X
-C85X
-C10X
-C12X
MIN.
MAX.
MIN.
MAX.
MIN.
MAX.
MIN.
MAX.
Read cycle time
t
RC
70
85
100
120
ns
Address access time
t
AA
70
85
100
120
ns
Note 1
/CE1 access time
t
CO1
70
85
100
120
ns
CE2 access time
t
CO2
70
85
100
120
ns
/OE to output valid
t
OE
35
40
50
60
ns
/LB, /UB to output valid
t
BA
70
85
100
120
ns
Output hold from address change
t
OH
10
10
10
10
ns
/CE1 to output in low impedance
t
LZ1
10
10
10
10
ns
Note 2
CE2 to output in low impedance
t
LZ2
10
10
10
10
ns
/OE to output in low impedance
t
OLZ
0
0
0
0
ns
/LB, /UB to output in low impedance
t
BLZ
10
10
10
10
ns
/CE1 to output in high impedance
t
HZ1
25
30
35
40
ns
CE2 to output in high impedance
t
HZ2
25
30
35
40
ns
/OE to output in high impedance
t
OHZ
25
30
35
40
ns
/LB, /UB to output in high impedance
t
BHZ
25
30
35
40
ns
Notes 1. The output load is 1TTL + 30 pF.
2. The output load is 1TTL + 5 pF.
Data Sheet M14466EJ5V0DS
10
PD448012-X
Read Cycle Timing Chart
t
HZ2
t
RC
t
OH
t
HZ1
t
BLZ
t
BA
t
LZ2
t
CO2
t
LZ1
t
CO1
t
BHZ
t
AA
High impedance
Data out
/LB, /UB (Input)
CE2 (Input)
/CE1 (Input)
Address (Input)
I/O (Output)
t
OLZ
t
OE
t
OHZ
/OE (Input)
Remark
In read cycle, /WE should be fixed to high level.
Data Sheet M14466EJ5V0DS
11
PD448012-X
Write Cycle (1/2) (B version)
Parameter
Symbol
V
CC
2.7 V
Unit
Condition
PD448012
PD448012
PD448012
PD448012
-B55X
-B70X
-B85X
-B10X
MIN.
MAX.
MIN.
MAX.
MIN.
MAX.
MIN.
MAX.
Write cycle time
t
WC
55
70
85
100
ns
/CE1 to end of write
t
CW1
50
55
70
80
ns
CE2 to end of write
t
CW2
50
55
70
80
ns
/LB, /UB to end of write
t
BW
50
55
70
80
ns
Address valid to end of write
t
AW
50
55
70
80
ns
Address setup time
t
AS
0
0
0
0
ns
Write pulse width
t
WP
45
50
55
60
ns
Write recovery time
t
WR
0
0
0
0
ns
Data valid to end of write
t
DW
25
30
35
40
ns
Data hold time
t
DH
0
0
0
0
ns
/WE to output in high impedance
t
WHZ
20
25
30
35
ns
Note
Output active from end of write
t
OW
5
5
5
5
ns
Note The output load is 1TTL + 5 pF.
Write Cycle (2/2) (C version)
Parameter
Symbol
V
CC
2.2V
Unit
Condition
PD448012
PD448012
PD448012
PD448012
-C70X
-C85X
-C10X
-C12X
MIN.
MAX.
MIN.
MAX.
MIN.
MAX.
MIN.
MAX.
Write cycle time
t
WC
70
85
100
120
ns
/CE1 to end of write
t
CW1
55
70
80
100
ns
CE2 to end of write
t
CW2
55
70
80
100
ns
/LB, /UB to end of write
t
BW
55
70
80
100
ns
Address valid to end of write
t
AW
55
70
80
100
ns
Address setup time
t
AS
0
0
0
0
ns
Write pulse width
t
WP
50
55
60
85
ns
Write recovery time
t
WR
0
0
0
0
ns
Data valid to end of write
t
DW
30
35
40
60
ns
Data hold time
t
DH
0
0
0
0
ns
/WE to output in high impedance
t
WHZ
25
30
35
40
ns
Note
Output active from end of write
t
OW
5
5
5
5
ns
Note The output load is 1TTL + 5 pF.
Data Sheet M14466EJ5V0DS
12
PD448012-X
Write Cycle Timing Chart 1 (/WE Controlled)
t
WC
t
CW1
t
BW
t
WHZ
t
DW
t
DH
t
OW
Indefinite data out
High
impe-
dance
High
impe-
dance
Data in
Indefinite data out
Address (Input)
/CE1 (Input)
/LB, /UB (Input)
I/O (Input / Output)
CE2 (Input)
t
CW2
t
AW
t
WP
t
AS
t
WR
/WE (Input)
Cautions 1. During address transition, at least one of pins /CE1, CE2, /WE should be inactivated.
2. Do not input data to the I/O pins while they are in the output state.
Remarks 1. Write operation is done during the overlap time of a low level /CE1, /WE, /LB and/or /UB, and a
high level CE2.
2. If /CE1 changes to low level at the same time or after the change of /WE to low level, or if CE2
changes to high level at the same time or after the change of /WE to low level, the I/O pins will
remain high impedance state.
3. When /WE is at low level, the I/O pins are always high impedance. When /WE is at high level,
read operation is executed. Therefore /OE should be at high level to make the I/O pins high
impedance.
Data Sheet M14466EJ5V0DS
13
PD448012-X
Write Cycle Timing Chart 2 (/CE1 Controlled)
t
WC
t
AS
t
CW1
t
DW
t
DH
Data in
High impedance
Address (Input)
/CE1 (Input)
/LB, /UB (Input)
I/O (Input)
High
impedance
CE2 (Input)
t
CW2
t
AW
t
WP
t
WR
/WE (Input)
t
BW
Cautions 1. During address transition, at least one of pins /CE1, CE2, /WE should be inactivated.
2. Do not input data to the I/O pins while they are in the output state.
Remark Write operation is done during the overlap time of a low level /CE1, /WE, /LB and/or /UB, and a high
level CE2.
Data Sheet M14466EJ5V0DS
14
PD448012-X
Write Cycle Timing Chart 3 (CE2 Controlled)
t
WC
t
AS
t
CW2
t
BW
t
DW
t
DH
Data in
High impedance
Address (Input)
CE2 (Input)
/LB, /UB (Input)
I/O (Input)
High
impedance
/CE1 (Input)
t
CW1
t
AW
t
WP
t
WR
/WE (Input)
Cautions 1. During address transition, at least one of pins /CE1, CE2, /WE should be inactivated.
2. Do not input data to the I/O pins while they are in the output state.
Remark Write operation is done during the overlap time of a low level /CE1, /WE, /LB and/or /UB, and a high
level CE2.
Data Sheet M14466EJ5V0DS
15
PD448012-X
Write Cycle Timing Chart 4 (/LB, /UB Controlled)
t
WC
t
DW
t
DH
Data in
High impedance
Address (Input)
/LB, /UB (Input)
I/O (Input)
High
impedance
CE2 (Input)
t
CW2
t
AW
t
WP
t
WR
/WE (Input)
t
AS
t
BW
/CE1 (Input)
t
CW1
Cautions 1. During address transition, at least one of pins /CE1, CE2, /WE should be inactivated.
2. Do not input data to the I/O pins while they are in the output state.
Remark Write operation is done during the overlap time of a low level /CE1, /WE, /LB and/or /UB, and a high
level CE2.
Data Sheet M14466EJ5V0DS
16
PD448012-X
Low V
CC
Data Retention Characteristics (T
A
= 25 to +85
C)
Parameter
Symbol
Test Condition
V
CC
2.7 V
V
CC
2.2 V
Unit
PD448012
PD448012
-B
X
-C
X
MIN.
TYP.
MAX.
MIN.
TYP.
MAX.
Data retention
V
CCDR1
/CE1
V
CC
-
0.2 V, CE2
V
CC
-
0.2 V
1.0
3.6
1.0
3.6
V
supply voltage
V
CCDR2
CE2
0.2 V
1.0
3.6
1.0
3.6
V
CCDR3
/LB = /UB
V
CC
-
0.2 V,
1.0
3.6
1.0
3.6
/CE1
0.2 V, CE2
V
CC
-
0.2 V
Data retention
I
CCDR1
V
CC
= 1.5 V, /CE1
V
CC
-
0.2 V,
0.5
6.0
0.5
6.0
A
supply current
CE2
V
CC
-
0.2 V
I
CCDR2
V
CC
= 1.5 V, CE2
0.2 V
0.5
6.0
0.5
6.0
I
CCDR3
V
CC
= 1.5 V, /LB = /UB
V
CC
-
0.2 V,
0.5
6.0
0.5
6.0
/CE1
0.2 V, CE2
V
CC
-
0.2 V
Chip deselection
t
CDR
0
0
ns
to data retention
mode
Operation
t
R
t
RC
Note
t
RC
Note
ns
recovery time
Note t
RC
: Read cycle time
Data Sheet M14466EJ5V0DS
17
PD448012-X
Data Retention Timing Chart
(1) /CE1 Controlled
V
IH
(MIN.)
V
CCDR
(MIN.)
V
IL
(MAX.)
V
CC
/CE1
/CE1
V
CC
0.2 V
GND
V
CC
(MIN.)
Note
t
CDR
Data retention mode
t
R
Note B version : 2.7 V, C version : 2.2 V
Remark On the data retention mode by controlling /CE1, the input level of CE2 must be
V
CC
-
0.2 V or
0.2 V.
The other pins (Address, I/O, /WE, /OE, /LB, /UB) can be in high impedance state.
(2) CE2 Controlled
V
IH
(MIN.)
V
CCDR
(MIN.)
V
IL
(MAX.)
V
CC
CE2
CE2
0.2 V
GND
V
CC
(MIN.)
Note
t
CDR
Data retention mode
t
R
Note B version : 2.7 V, C version : 2.2 V
Remark On the data retention mode by controlling CE2, the other pins (/CE1, Address, I/O, /WE, /OE, /LB, /UB) can
be in high impedance state.
Data Sheet M14466EJ5V0DS
18
PD448012-X
(3) /LB, /UB Controlled
t
CDR
Data retention mode
V
IH
(MIN.)
V
CCDR
(MIN.)
V
IL
(MAX.)
t
R
V
CC
/LB, /UB
/LB, /UB
V
CC
0.2 V
GND
V
CC
(MIN.)
Note
Note B version : 2.7 V, C version : 2.2 V
Remark On the data retention mode by controlling /LB and /UB, the input level of /CE1 and CE2 must be
V
CC
-
0.2 V or
0.2 V. The other pins (Address, I/O, /WE, /OE) can be in high impedance state.
Data Sheet M14466EJ5V0DS
19
PD448012-X
Package Drawing
NOTES
48-PIN PLASTIC TSOP(
I
) (12x18)
ITEM
MILLIMETERS
A
B
C
E
I
12.0
0.1
0.5 (T.P.)
0.1
0.05
0.45 MAX.
K
1.2 MAX.
16.4
0.1
0.145
0.05
F
0.10
M
D
0.22
0.05
1. Each lead centerline is located within 0.10 mm of
its true position (T.P.) at maximum material condition.
2. "A" excludes mold flash. (Includes mold flash : 12.4 mm MAX.)
R
K
L
1.0
0.05
G
L
0.5
0.10
N
P
18.0
0.2
Q
3
+
5
-
3
0.25
R
S48GY-50-MJH1-1
S
0.60
0.15
J
0.8
0.2
S
Q
S
N
E
G
F
J
detail of lead end
C
D
M
M
B
A
I
P
1
24
48
25
S
Data Sheet M14466EJ5V0DS
20
PD448012-X
Recommended Soldering Conditions
Please consult with our sales offices for soldering conditions of the
PD448012-X.
Types of Surface Mount Device
PD448012GY-BxxX-MJH : 48-pin PLASTIC TSOP (I) (12x18) (Normal bent)
PD448012GY-CxxX-MJH : 48-pin PLASTIC TSOP (I) (12x18) (Normal bent)
Data Sheet M14466EJ5V0DS
21
PD448012-X
[ MEMO ]
Data Sheet M14466EJ5V0DS
22
PD448012-X
[ MEMO ]
Data Sheet M14466EJ5V0DS
23
PD448012-X
NOTES FOR CMOS DEVICES
1
PRECAUTION AGAINST ESD FOR SEMICONDUCTORS
Note:
Strong electric field, when exposed to a MOS device, can cause destruction of the gate oxide and
ultimately degrade the device operation. Steps must be taken to stop generation of static electricity
as much as possible, and quickly dissipate it once, when it has occurred. Environmental control
must be adequate. When it is dry, humidifier should be used. It is recommended to avoid using
insulators that easily build static electricity. Semiconductor devices must be stored and transported
in an anti-static container, static shielding bag or conductive material. All test and measurement
tools including work bench and floor should be grounded. The operator should be grounded using
wrist strap. Semiconductor devices must not be touched with bare hands. Similar precautions need
to be taken for PW boards with semiconductor devices on it.
2
HANDLING OF UNUSED INPUT PINS FOR CMOS
Note:
No connection for CMOS device inputs can be cause of malfunction. If no connection is provided
to the input pins, it is possible that an internal input level may be generated due to noise, etc., hence
causing malfunction. CMOS devices behave differently than Bipolar or NMOS devices. Input levels
of CMOS devices must be fixed high or low by using a pull-up or pull-down circuitry. Each unused
pin should be connected to V
DD
or GND with a resistor, if it is considered to have a possibility of
being an output pin. All handling related to the unused pins must be judged device by device and
related specifications governing the devices.
3
STATUS BEFORE INITIALIZATION OF MOS DEVICES
Note:
Power-on does not necessarily define initial status of MOS device. Production process of MOS
does not define the initial operation status of the device. Immediately after the power source is
turned ON, the devices with reset function have not yet been initialized. Hence, power-on does
not guarantee out-pin levels, I/O settings or contents of registers. Device is not initialized until the
reset signal is received. Reset operation must be executed immediately after power-on for devices
having reset function.
PD448012-X
M8E 00. 4
The information in this document is current as of July, 2001. The information is subject to change
without notice. For actual design-in, refer to the latest publications of NEC's data sheets or data
books, etc., for the most up-to-date specifications of NEC semiconductor products. Not all products
and/or types are available in every country. Please check with an NEC sales representative for
availability and additional information.
No part of this document may be copied or reproduced in any form or by any means without prior
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Descriptions of circuits, software and other related information in this document are provided for illustrative
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Customers must check the quality grade of each semiconductor product before using it in a particular
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The quality grade of NEC semiconductor products is "Standard" unless otherwise expressly specified in NEC's
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(Note)
(1) "NEC" as used in this statement means NEC Corporation and also includes its majority-owned subsidiaries.
(2) "NEC semiconductor products" means any semiconductor product developed or manufactured by or for
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