Document Outline
- COVER
- Features
- Ordering Information
- Pin Configurations
- Block Diagrams
- Electrical Specifications
- Package Drawing
The information in this document is subject to change without notice. Before using this document, please
confirm that this is the latest version.
Not all products and/or types are available in every country. Please check with an NEC Electronics
sales representative for availability and additional information.
MOS INTEGRATED CIRCUIT
PD4482162, 4482182, 4482322, 4482362
8M-BIT CMOS SYNCHRONOUS FAST SRAM
PIPELINED OPERATION
SINGLE CYCLE DESELECT
Document No. M14522EJ3V0DS00 (3rd edition)
Date Published December 2002 NS CP(K)
Printed in Japan
DATA SHEET
The mark shows major revised points.
2000
Description
The
PD4482162 is a 524,288-word by 16-bit, the PD4482182 is a 524,288-word by 18-bit, PD4482322 is a 262,144-
word by 32-bit and the
PD4482362 is a 262,144-word by 36-bit synchronous static RAM fabricated with advanced CMOS
technology using Full-CMOS six-transistor memory cell.
The
PD4482162, PD4482182, PD4482322 and PD4482362 integrates unique synchronous peripheral circuitry, 2-
bit burst counter and output buffer as well as SRAM core. All input registers are controlled by a positive edge of the single
clock input (CLK).
The
PD4482162, PD4482182, PD4482322 and PD4482362 are suitable for applications which require synchronous
operation, high speed, low voltage, high density and wide bit configuration, such as cache and buffer memory.
ZZ has to be set LOW at the normal operation. When ZZ is set HIGH, the SRAM enters Power Down State ("Sleep"). In
the "Sleep" state, the SRAM internal state is preserved. When ZZ is set LOW again, the SRAM resumes normal operation.
The
PD4482162, PD4482182, PD4482322 and PD4482362 are packaged in 100-pin PLASTIC LQFP with a 1.4
mm package thickness for high density and low capacitive loading.
Features
3.3 V or 2.5 V core supply
Synchronous operation
Operating temperature : T
A
= 0 to 70
C (-A44, -A50, -A60, -C60)
T
A
=
-40 to +85 C (-A44Y, -A50Y, -A60Y, -C60Y)
Internally self-timed write control
Burst read / write : Interleaved burst and linear burst sequence
Fully registered inputs and outputs for pipelined operation
Single-Cycle deselect timing
All registers triggered off positive clock edge
3.3 V or 2.5 V LVTTL Compatible : All inputs and outputs
Fast clock access time : 2.8 ns (225 MHz), 3.1 ns (200 MHz), 3.5 ns (167 MHz)
Asynchronous output enable : /G
Burst sequence selectable : MODE
Sleep mode : ZZ (ZZ = Open or Low : Normal operation)
Separate byte write enable : /BW1 to /BW4, /BWE (
PD4482322, PD4482362)
/BW1, /BW2, /BWE (
PD4482162, PD4482182)
Global write enable : /GW
Three chip enables for easy depth expansion
Common I/O using three state outputs
2
Data Sheet M14522EJ3V0DS
PD4482162, 4482182, 4482322, 4482362
Ordering Information
Part number
Access
Clock
Core Supply
I/O Interface
Operating
Package
Time
Frequency
Voltage
Temperature
ns
MHz
V
C
PD4482162GF-A44
2.8
225
3.3 0.165
3.3 V LVTTL
Note
0 to 70
100-pin PLASTIC
PD4482162GF-A50
3.1
200
LQFP (14
20)
PD4482162GF-A60
3.5
167
3.3 V or 2.5 V LVTTL
PD4482182GF-A44
2.8
225
3.3 V LVTTL
Note
PD4482182GF-A50
3.1
200
PD4482182GF-A60
3.5
167
3.3 V or 2.5 V LVTTL
PD4482322GF-A44
2.8
225
3.3 V LVTTL
Note
PD4482322GF-A50
3.1
200
PD4482322GF-A60
3.5
167
3.3 V or 2.5 V LVTTL
PD4482362GF-A44
2.8
225
3.3 V LVTTL
Note
PD4482362GF-A50
3.1
200
PD4482362GF-A60
3.5
167
3.3 V or 2.5 V LVTTL
PD4482162GF-C60
3.5
167
2.5 0.125
2.5 V LVTTL
PD4482182GF-C60
3.5
167
PD4482322GF-C60
3.5
167
PD4482362GF-C60
3.5
167
PD4482162GF-A44Y
2.8
225
3.3 0.165
3.3 V LVTTL
Note
-40 to +85
PD4482162GF-A50Y
3.1
200
PD4482162GF-A60Y
3.5
167
3.3 V or 2.5 V LVTTL
PD4482182GF-A44Y
2.8
225
3.3 V LVTTL
Note
PD4482182GF-A50Y
3.1
200
PD4482182GF-A60Y
3.5
167
3.3 V or 2.5 V LVTTL
PD4482322GF-A44Y
2.8
225
3.3 V LVTTL
Note
PD4482322GF-A50Y
3.1
200
PD4482322GF-A60Y
3.5
167
3.3 V or 2.5 V LVTTL
PD4482362GF-A44Y
2.8
225
3.3 V LVTTL
Note
PD4482362GF-A50Y
3.1
200
PD4482362GF-A60Y
3.5
167
3.3 V or 2.5 V LVTTL
PD4482162GF-C60Y
3.5
167
2.5 0.125
2.5 V LVTTL
PD4482182GF-C60Y
3.5
167
PD4482322GF-C60Y
3.5
167
PD4482362GF-C60Y
3.5
167
Note Although 2.5V LVTTL interface can also be used, a performance becomes equivalent to 167 MHz.
3
Data Sheet M14522EJ3V0DS
PD4482162, 4482182, 4482322, 4482362
Pin Configurations
/
indicates active low signal.
100-pin PLASTIC LQFP (14 x 20)
[
PD4482162GF, PD4482182GF]
Marking Side
NC
NC
NC
V
DD
Q
V
SS
Q
NC
NC
I/O9
I/O10
V
SS
Q
V
DD
Q
I/O11
I/O12
NC
V
DD
NC
V
SS
I/O13
I/O14
V
DD
Q
V
SS
Q
I/O15
I/O16
I/OP2, NC
NC
V
SS
Q
V
DD
Q
NC
NC
NC
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
80
79
78
77
76
75
74
73
72
71
70
69
68
67
66
65
64
63
62
61
60
59
58
57
56
55
54
53
52
51
A18
NC
NC
V
DD
Q
V
SS
Q
NC
I/OP1, NC
I/O8
I/O7
V
SS
Q
V
DD
Q
I/O6
I/O5
V
SS
NC
V
DD
ZZ
I/O4
I/O3
V
DD
Q
V
SS
Q
I/O2
I/O1
NC
NC
V
SS
Q
V
DD
Q
NC
NC
NC
100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81
31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50
A6
A7
/CE
CE2
NC
NC
/BW2
/BW1
/CE2
V
DD
V
SS
CLK
/GW
/BWE
/G
/AC
/AP
/ADV
A8
A9
MODE
A5
A4
A3
A2
A1
A0
NC
NC
V
SS
V
DD
NC
A17
A10
A11
A12
A13
A14
A15
A16
Remark Refer to Package Drawing for the 1-pin index mark.
4
Data Sheet M14522EJ3V0DS
PD4482162, 4482182, 4482322, 4482362
Pin Identification (
PD4482162GF, PD4482182GF)
Symbol
Pin No.
Description
A0 to A18
37, 36, 35, 34, 33, 32, 100, 99, 82, 81, 44, 45, 46, 47, 48,
49, 50, 43, 80
Synchronous Address Input
I/O1 to I/O16
58, 59, 62, 63, 68, 69, 72, 73, 8, 9, 12, 13, 18, 19, 22, 23
Synchronous Data In,
Synchronous / Asynchronous Data Out
I/OP1, NC
Note
74
Synchronous Data In (Parity),
I/OP2, NC
Note
24
Synchronous / Asynchronous Data Out (Parity)
/ADV
83
Synchronous Burst Address Advance Input
/AP
84
Synchronous Address Status Processor Input
/AC
85
Synchronous Address Status Controller Input
/CE,CE2, /CE2
98, 97, 92
Synchronous Chip Enable Input
/BW1, /BW2, /BWE
93, 94, 87
Synchronous Byte Write Enable Input
/GW
88
Synchronous Global Write Input
/G
86
Asynchronous Output Enable Input
CLK
89
Clock Input
MODE
31
Asynchronous Burst Sequence Select Input
Do not change state during normal operation
ZZ
64
Asynchronous Power Down State Input
V
DD
15, 41, 65, 91
Power Supply
V
SS
17, 40, 67, 90
Ground
V
DD
Q
4, 11, 20, 27, 54, 61, 70, 77
Output Buffer Power Supply
V
SS
Q
5, 10, 21, 26, 55, 60, 71, 76
Output Buffer Ground
NC
1, 2, 3, 6, 7, 14, 16, 25, 28, 29, 30, 38, 39, 42, 51, 52, 53,
56, 57, 66, 75, 78, 79, 95, 96
No Connection
Note NC (No Connection) is used in the
PD4482162GF.
I/OP1 and I/OP2 are used in the
PD4482182GF.
5
Data Sheet M14522EJ3V0DS
PD4482162, 4482182, 4482322, 4482362
100-pin PLASTIC LQFP (14 x 20)
[
PD4482322GF, PD4482362GF]
Marking Side
I/OP3, NC
I/O17
I/O18
V
DD
Q
V
SS
Q
I/O19
I/O20
I/O21
I/O22
V
SS
Q
V
DD
Q
I/O23
I/O24
NC
V
DD
NC
V
SS
I/O25
I/O26
V
DD
Q
V
SS
Q
I/O27
I/O28
I/O29
I/O30
V
SS
Q
V
DD
Q
I/O31
I/O32
I/OP4, NC
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
80
79
78
77
76
75
74
73
72
71
70
69
68
67
66
65
64
63
62
61
60
59
58
57
56
55
54
53
52
51
I/OP2, NC
I/O16
I/O15
V
DD
Q
V
SS
Q
I/O14
I/O13
I/O12
I/O11
V
SS
Q
V
DD
Q
I/O10
I/O9
V
SS
NC
V
DD
ZZ
I/O8
I/O7
V
DD
Q
V
SS
Q
I/O6
I/O5
I/O4
I/O3
V
SS
Q
V
DD
Q
I/O2
I/O1
I/OP1, NC
100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81
31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50
A6
A7
/CE
CE2
/BW4
/BW3
/BW2
/BW1
/CE2
V
DD
V
SS
CLK
/GW
/BWE
/G
/AC
/AP
/ADV
A8
A9
MODE
A5
A4
A3
A2
A1
A0
NC
NC
V
SS
V
DD
NC
A17
A10
A11
A12
A13
A14
A15
A16
Remark Refer to Package Drawing for the 1-pin index mark.
PDF 
ZIP