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2001

MOS INTEGRATED CIRCUIT

MC-222244A-X

MCP (MULTI-CHIP PACKAGE) FLASH MEMORY AND SRAM

32M-BIT FLASH MEMORY AND 4M-BIT SRAM

DATA SHEET

Document No. M15318EJ2V0DS00 (2nd edition)
Date Published July 2001 NS CP (K)
Printed in Japan

The mark

shows major revised points.

Description

The MC-222244A-X is a stacked type MCP (Multi-Chip Package) of 33,554,432 bits (BYTE mode : 4,194,304 words
by 8 bits, WORD mode : 2,097,152 words by 16 bits) flash memory and 4,194,304 bits (BYTE mode : 524,288 words
by 8 bits, WORD mode : 262,144 words by 16 bits) static RAM.
The MC-222244A-X is packaged in a 77-pin TAPE FBGA.

Features

General Features

Fast access time : t

ACC

= 85 ns (MAX.) (Flash Memory), t

= 70 ns (MAX.) (SRAM)

Supply voltage : V

f / V

s = 2.7 to 3.6 V

Wide operating temperature : T

25 to +85

Flash Memory Features

Two bank organization enabling simultaneous execution of erase / program and read

Bank organization : 2 banks (16M bits + 16M bits)

Memory organization : 4,194,304 words

8 bits (BYTE mode)

2,097,152 words

16 bits (WORD mode)

Sector organization : 71 sectors (8K bytes / 4K words

8 sectors, 64K bytes / 32K words

63 sectors)

Boot sector allocated to the highest address (sector)

3-state output

Automatic program

Program suspend / resume

Unlock bypass program

Automatic erase

Chip erase

Sector erase (sectors can be combined freely)

Erase suspend / resume

Program / Erase completion detection

Detection through data polling and toggle bits

Detection through RY (/BY) pin

Sector group protection

Any sector can be protected

Any protected sector can be temporary unprotected

Sectors can be used for boot application

Hardware reset and standby using /RESET pin

Automatic sleep mode

Boot block sector protect by /WP (ACC) pin

Conforms to common flash memory interface (CFI)

Extra One Time Protect Sector provided

Data Sheet M15318EJ2V0DS

MC-222244A-X

Pin Configuration

/xxx indicates active low signal.

77-pin TAPE FBGA (12

×
×
×
×

Top View

I/O9

I/O5

/OE

I/O7

I/O4

I/O0

A18

A11

I/O8

I/O12

A13

A17

/CEf

I/O10

/WE

A16

I/O11

RY(/BY)

/RESET

A12

I/O6

I/O13

A15

A19

I/O14

/CE1s

I/O15, A-1

I/O1

A10

CIOs

I/O2

CE2s

A20

A14

/LB

CIOf

/WP(ACC)

/UB

I/O3

Top View

Bottom View

P N M L K J H G F E D C B A

A B C D E F G H J K L M N P

Common Pins
A0 - A17

: Address inputs

I/O0 - I/O15 : Data inputs / outputs
/OE

: Output Enable

/WE

: Write Enable

: Ground

Note

: No Connection

Flash Memory Pins
A18 - A20 : Address inputs
I/O15, A

1 : Data inputs / outputs 15 (WORD mode)

LSB address input (BYTE mode)

/CEf

: Chip Enable

RY (/BY)

: Ready (Busy) output

/RESET

: Hardware reset input

: Supply Voltage

/WP(ACC) : Hardware Write Protect (Acceleration)
CIOf

: Selects 8-bit or 16-bit mode

SRAM Pins
SA

: Address input (A18 for SRAM)

/CE1s

: Chip Enable 1

CE2s

: Chip Enable 2

: Supply Voltage

/LB, /UB

: Byte data select

CIOs

: Selects 8-bit or 16-bit mode

Note Some signals can be applied because this pin is not internally connected.

Remark Refer to Package Drawing for the index mark.

Data Sheet M15318EJ2V0DS

MC-222244A-X

Bus Operations Table

Operation

Flash Memory

SRAM

Common

/RESET /CEf CIOf /WP(ACC) /CE1

CE2

/LB

/UB

CIOs /OE /WE I/O0 - I/O7 I/O8-I/O15

Full standby

Hi-Z

Output disable

Hi-Z

Read (Flash

BYTE mode

Note 2

Data Out

Hi-Z

Memory

Note 1

) WORD mode

Data Out

Write (Flash

BYTE mode

Note 2

Data In

Hi-Z

Memory)

WORD mode

Data In

Temporary sector group

Note 2

Hi-Z or

unprotect

Data In/Out Data In/Out

Boot block sector protect

Hi-Z or

Data In/Out

Hi-Z or

Data In/Out

Flash Memory hardware reset

Hi-Z

Read (SRAM)

BYTE mode

Note 3

Data Out

Hi-Z

WORD mode

Note 3

Data Out

Hi-Z

Data Out

Write (SRAM)

BYTE mode

Note 3

Data In

Hi-Z

WORD mode

Note 3

Data In

Hi-Z

Data In

Caution Other operations except for indicated in this table are inhibited.

Notes 1. When /OE = V

, V

can be applied to /WE. When /OE = V

, a write operation is started.

2. SRAM should be Standby.
3. Flash Memory should be Standby or Hardware reset.

Remarks 1. H : V

, L : V

: V

or V

2. Sector group protection and read the product ID are using a command.
3. Refer to DUAL OPERATION FLASH MEMORY 32M BITS A SERIES Information (M14914E) for the

flash memory bus operations.

Data Sheet M15318EJ2V0DS

MC-222244A-X

Sector Organization / Sector Address Table (Flash Memory)

Flash Memory top boot

(1/2)

Bank

Sector

Address

Sectors

Sector Address Table

Organization

Address

Bank Address Table

K bytes / K words

BYTE mode

WORD mode

A20 A19 A18 A17 A16 A15 A14 A13 A12

Bank 1

8/4

3FFFFFH

1FFFFFH

FSA70

3FE000H

1FF000H

8/4

3FDFFFH

1FEFFFH

FSA69

3FC000H

1FE000H

8/4

3FBFFFH

1FDFFFH

FSA68

3FA000H

1FD000H

8/4

3F9FFFH

1FCFFFH

FSA67

3F8000H

1FC000H

8/4

3F7FFFH

1FBFFFH

FSA66

3F6000H

1FB000H

8/4

3F5FFFH

1FAFFFH

FSA65

3F4000H

1FA000H

8/4

3F3FFFH

1F9FFFH

FSA64

3F2000H

1F9000H

8/4

3F1FFFH

1F8FFFH

FSA63

3F0000H

1F8000H

64/32

3EFFFFH

1F7FFFH

FSA62

3E0000H

1F0000H

64/32

3DFFFFH

1EFFFFH

FSA61

3D0000H

1E8000H

64/32

3CFFFFH

1E7FFFH

FSA60

3C0000H

1E0000H

64/32

3BFFFFH

1DFFFFH

FSA59

3B0000H

1D8000H

64/32

3AFFFFH

1D7FFFH

FSA58

3A0000H

1D0000H

64/32

39FFFFH

1CFFFFH

FSA57

390000H

1C8000H

64/32

38FFFFH

1C7FFFH

FSA56

380000H

1C0000H

64/32

37FFFFH

1BFFFFH

FSA55

370000H

1B8000H

64/32

36FFFFH

1B7FFFH

FSA54

360000H

1B0000H

64/32

35FFFFH

1AFFFFH

FSA53

350000H

1A8000H

64/32

34FFFFH

1A7FFFH

FSA52

340000H

1A0000H

64/32

33FFFFH

19FFFFH

FSA51

330000H

198000H

64/32

32FFFFH

197FFFH

FSA50

320000H

190000H

64/32

31FFFFH

18FFFFH

FSA49

310000H

188000H

64/32

30FFFFH

187FFFH

FSA48

300000H

180000H

64/32

2FFFFFH

17FFFFH

FSA47

2F0000H

178000H

64/32

2EFFFFH

177FFFH

FSA46

2E0000H

170000H

64/32

2DFFFFH

16FFFFH

FSA45

2D0000H

168000H

64/32

2CFFFFH

167FFFH

FSA44

2C0000H

160000H

64/32

2BFFFFH

15FFFFH

FSA43

2B0000H

158000H

64/32

2AFFFFH

157FFFH

FSA42

2A0000H

150000H

64/32

29FFFFH

14FFFFH

FSA41

290000H

148000H

64/32

28FFFFH

147FFFH

FSA40

280000H

140000H

64/32

27FFFFH

13FFFFH

FSA39

270000H

138000H

64/32

26FFFFH

137FFFH

FSA38

260000H

130000H

64/32

25FFFFH

12FFFFH

FSA37

250000H

128000H

64/32

24FFFFH

127FFFH

FSA36

240000H

120000H

64/32

23FFFFH

11FFFFH

FSA35

230000H

118000H

Data Sheet M15318EJ2V0DS

MC-222244A-X

(2/2)

Bank

Sector

Address

Sectors

Sector Address Table

Organization

Address

Bank Address Table

K bytes / K words

BYTE mode

WORD mode

A20 A19 A18 A17 A16 A15 A14 A13 A12

Bank 1

64/32

22FFFFH

117FFFH

FSA34

220000H

110000H

64/32

21FFFFH

10FFFFH

FSA33

210000H

108000H

64/32

20FFFFH

107FFFH

FSA32

200000H

100000H

Bank 2

64/32

1FFFFFH

0FFFFFH

FSA31

1F0000H

0F8000H

64/32

1EFFFFH

0F7FFFH

FSA30

1E0000H

0F0000H

64/32

1DFFFFH

0EFFFFH

FSA29

1D0000H

0E8000H

64/32

1CFFFFH

0E7FFFH

FSA28

1C0000H

0E0000H

64/32

1BFFFFH

0DFFFFH

FSA27

1B0000H

0D8000H

64/32

1AFFFFH

0D7FFFH

FSA26

1A0000H

0D0000H

64/32

19FFFFH

0CFFFFH

FSA25

190000H

0C8000H

64/32

18FFFFH

0C7FFFH

FSA24

180000H

0C0000H

64/32

17FFFFH

0BFFFFH

FSA23

170000H

0B8000H

64/32

16FFFFH

0B7FFFH

FSA22

160000H

0B0000H

64/32

15FFFFH

0AFFFFH

FSA21

150000H

0A8000H

64/32

14FFFFH

0A7FFFH

FSA20

140000H

0A0000H

64/32

13FFFFH

09FFFFH

FSA19

130000H

098000H

64/32

12FFFFH

097FFFH

FSA18

120000H

090000H

64/32

11FFFFH

08FFFFH

FSA17

110000H

088000H

64/32

10FFFFH

087FFFH

FSA16

100000H

080000H

64/32

0FFFFFH

07FFFFH

FSA15

0F0000H

078000H

64/32

0EFFFFH

077FFFH

FSA14

0E0000H

070000H

64/32

0DFFFFH

06FFFFH

FSA13

0D0000H

068000H

64/32

0CFFFFH

067FFFH

FSA12

0C0000H

060000H

64/32

0BFFFFH

05FFFFH

FSA11

0B0000H

058000H

64/32

0AFFFFH

057FFFH

FSA10

0A0000H

050000H

64/32

09FFFFH

04FFFFH

FSA9

090000H

048000H

64/32

08FFFFH

047FFFH

FSA8

080000H

040000H

64/32

07FFFFH

03FFFFH

FSA7

070000H

038000H

64/32

06FFFFH

037FFFH

FSA6

060000H

030000H

64/32

05FFFFH

02FFFFH

FSA5

050000H

028000H

64/32

04FFFFH

027FFFH

FSA4

040000H

020000H

64/32

03FFFFH

01FFFFH

FSA3

030000H

018000H

64/32

02FFFFH

017FFFH

FSA2

020000H

010000H

64/32

01FFFFH

00FFFFH

FSA1

010000H

008000H

64/32

00FFFFH

007FFFH

FSA0

000000H

Data Sheet M15318EJ2V0DS

MC-222244A-X

Sector Group Address Table (Flash Memory)

Sector group

A20

A19

A18

A17

A16

A15

A14

A13

A12

Size

Sector

SGA0

64 KB (1 Sector)

FSA0

SGA1

192 KB (3 Sectors)

FSA1FSA3

SGA2

256 KB (4 Sectors)

FSA4FSA7

SGA3

256 KB (4 Sectors)

FSA8FSA11

SGA4

256 KB (4 Sectors)

FSA12FSA15

SGA5

256 KB (4 Sectors)

FSA16FSA19

SGA6

256 KB (4 Sectors)

FSA20FSA23

SGA7

256 KB (4 Sectors)

FSA24FSA27

SGA8

256 KB (4 Sectors)

FSA28FSA31

SGA9

256 KB (4 Sectors)

FSA32FSA35

SGA10

256 KB (4 Sectors)

FSA36FSA39

SGA11

256 KB (4 Sectors)

FSA40FSA43

SGA12

256 KB (4 Sectors)

FSA44FSA47

SGA13

256 KB (4 Sectors)

FSA48FSA51

SGA14

256 KB (4 Sectors)

FSA52FSA55

SGA15

256 KB (4 Sectors)

FSA56FSA59

SGA16

192 KB (3 Sectors)

FSA60FSA62

SGA17

8 KB (1 Sector)

FSA63

SGA18

8 KB (1 Sector)

FSA64

SGA19

8 KB (1 Sector)

FSA65

SGA20

8 KB (1 Sector)

FSA66

SGA21

8 KB (1 Sector)

FSA67

SGA22

8 KB (1 Sector)

FSA68

SGA23

8 KB (1 Sector)

FSA69

SGA24

8 KB (1 Sector)

FSA70

Remark

: V

or V

Data Sheet M15318EJ2V0DS

MC-222244A-X

Command Sequence (Flash Memory)

Command sequence

Bus

1st bus Cycle

2nd bus Cycle

3rd bus Cycle

4th bus Cycle

5th bus Cycle

6th bus Cycle

Cycle Address Data

Address Data Address Data

Address Data

Read / Reset

Note1

×××

F0H

Read / Reset

Note1

BYTE mode

AAAH

AAH

555H

55H

AAAH

F0H

WORD mode

555H

2AAH

555H

Program

BYTE mode

AAAH

AAH

555H

55H

AAAH

A0H

WORD mode

555H

2AAH

555H

Program Suspend

Note 2

B0H

Program Resume

Note 3

30H

Chip Erase

BYTE mode

AAAH

AAH

555H

55H

AAAH

80H

AAAH

AAH

555H

55H

AAAH

10H

WORD mode

555H

2AAH

555H

2AAH

555H

Sector Erase

BYTE mode

AAAH

AAH

555H

55H

AAAH

80H

AAAH

AAH

555H

55H

FSA

30H

WORD mode

555H

2AAH

555H

2AAH

Sector Erase Suspend

Note 4

B0H

Sector Erase Resume

Note 5

30H

Unlock Bypass Set

BYTE mode

AAAH

AAH

555H

55H

AAAH

20H

WORD mode

555H

2AAH

555H

Unlock Bypass Program

Note 6

×××

A0H

Unlock Bypass Reset

Note 6

90H

×××

H 00H

Note11

Product ID

BYTE mode

AAAH

AAH

555H

55H

(BA)

90H

AAAH

WORD mode

555H

2AAH

(BA)

555H

Sector Group Protection

Note 7

×××

60H

SPA

60H

SPA

40H

SPA

Sector Group Unprotect

Note 8

×××

60H

SUA

60H

SUA

40H

SUA

Query

Note 9

BYTE mode

AAH

98H

WORD mode

55H

Extra One Time Protect

BYTE mode

AAAH

AAH

555H

55H

AAAH

88H

Sector Entry

WORD mode

555H

2AAH

555H

Extra One Time Protect

BYTE mode

AAAH

AAH

555H

55H

AAAH

A0H

Sector Program

Note 10

WORD mode

555H

2AAH

555H

Extra One Time Protect

BYTE mode

AAAH

AAH

555H

55H

AAAH

80H

AAAH

AAH

555H

55H

EOTPSA 30H

Sector Erase

Note 10

WORD mode

555H

2AAH

555H

2AAH

Extra One Time Protect

BYTE mode

AAAH

AAH

555H

55H

AAAH

90H

xxxH

00H

Sector Reset

Note 10

WORD mode

555H

2AAH

555H

Extra One Time Protect Sector

×××

60H

EOTPSA

60H

EOTPSA

40H

EOTPSA

Protection

Note 10

Data Sheet M15318EJ2V0DS

MC-222244A-X

Notes 1. Both these read / reset commands reset the device to the read mode.

2. Programming is suspended if B0H is input to the bank address being programmed to in a program

operation.

3. Programming is resumed if 30H is input to the bank address being suspended to in a program-suspend

operation.

4. Erasure is suspended if B0H is input to the bank address being erased in a sector erase operation.

5. Erasure is resumed if 30H is input to the bank address being suspended in a sector-erase-suspend

operation.

6. Valid only in the unlock bypass mode.

7. Valid only when /RESET = V

(except in the Extra One Time Protect Sector mode).

8. The command sequence that protects a sector group is excluded.

9. Only A0 to A6 are valid as an address.

10. Valid only in the Extra One Time Protect Sector mode.

11. This command can be used even if this data is F0H.

Remarks 1. Specify address 555H or 2AAH (A10 to A0) in the WORD mode, and AAAH or 555H (A10 to A0, A-1) in

the BYTE mode.

2. RA : Read address

RD : Read data
IA : Address input

xx00H (to read the manufacturer code)
xx02H (to read the device code in the BYTE mode)
xx01H (to read the device code in the WORD mode)

ID : Code output. Refer to the Product ID code (Manufacturer code / Device code) (Flash Memory).

PA : Program address
PD : Program data
FSA: Erase sector address. The sector to be erased is selected by the combination of this address.

Refer to the Sector Organization / Sector Address Table (Flash Memory).

BA : Bank address. Refer to the Sector Organization / Sector Address Table (Flash Memory).

SPA : Sector group address to be protected. Set sector group address (SGA) and (A6, A1, A0) =

, V

). For the sector group address, refer to the Sector Group Address Table (Flash

Memory).

SUA : Unprotect sector group address. Set sector group address (SGA) and (A6, A1, A0) =

, V

). For the sector group address, refer to the Sector Group Address Table (Flash

Memory).

SD : Data for verifying whether sector groups read from the address specified by SPA, SUA, and

EOTPSA are protected.

EOTPSA : Extra One Time Protect Sector area addresses.

BYTE mode : 3F0000H to 3FFFFFH, WORD mode : 1F8000H to 1FFFFFH

3. The sector group address is don't care except when a program / erase address or read address are

selected.

4. For the operation of the bus, refer to Bus Operations Table.
5.

of address bit indicates V

or V

6. Refer to DUAL OPERATION FLASH MEMORY 32M BITS A SERIES Information (M14914E) for the

flash memory commands.

Data Sheet M15318EJ2V0DS

MC-222244A-X

Product ID Code (Manufacturer Code / Device Code) (Flash Memory)

Product ID Code

Address inputs

Output

Hex

Manufacturer Code

10H

Device code

5CH (BYTE mode),

225CH (WORD mode)

Product ID Code

Code outputs

I/O

Hex

Manufacturer Code

10H

Device code BYTE mode

A-1

5CH

WORD mode

225CH

Remark H : V

, L : V

, x : Hi-Z

Hardware Sequence Flags, Hardware Data Protection (Flash Memory)

Refer to DUAL OPERATION FLASH MEMORY 32M BITS A SERIES Information (M14914E).

Data Sheet M15318EJ2V0DS

MC-222244A-X

Electrical Specifications

Before turning on power, input V

0.2 V to the /RESET pin until V

f (MIN.).

Absolute Maximum Ratings

Parameter

Symbol

Condition

Rating

Unit

Supply voltage

f, V

s with respect to V

0.5 to +4.0

Input / Output voltage

with respect /WP(ACC), /RESET

0.5

Note 1

to +13.0

to V

except /WP(ACC), /RESET

0.5

Note 1

to V

f, V

s + 0.4 (4.0 V MAX.)

Note 2

Ambient operation

25 to +85

temperature

Storage temperature

stg

55 to +125

Notes 1. 2.0 V (MIN.) (pulse width

20 ns)

2. V

f, V

s + 0.5 V (MAX.) (pulse width

20 ns)

Caution Exposing the device to stress above those listed in Absolute Maximum Rating could cause

permanent damage. The device is not meant to be operated under conditions outside the limits
described in the operational section of this specification. Exposure to Absolute Maximum Rating
conditions for extended periods may affect device reliability.

Recommended Operating Conditions

Parameter

Symbol

Condition

MIN.

TYP.

MAX.

Unit

Supply voltage

f, V

2.7

3.6

Ambient operation temperature

+85

Data Sheet M15318EJ2V0DS

MC-222244A-X

DC Characteristics (Recommended Operating Conditions Unless Otherwise Noted)

Common

Parameter

Symbol

Test condition

MIN.

TYP.

MAX.

Unit

High level input voltage

2.4

f, V

s + 0.3

Low level input voltage

0.3

+0.5

High level output voltage

500

A, V

f = V

f (MIN.),

2.4

s = V

s (MIN.)

Low level output voltage

= +1.0 mA, V

f = V

f (MIN.),

0.4

s = V

s (MIN.)

Input leakage current

1.0

+1.0

Output leakage current

1.0

+1.0

Flash Memory

Parameter

Symbol

Test condition

MIN.

TYP.

MAX.

Unit

Power

Read

BYTE mode

CC1

f = V

f (MAX.),

CYCLE

= 5 MHz

supply

/CEf = V

, /OE = V

CYCLE

= 1 MHz

current

WORD mode

CYCLE

= 5 MHz

CYCLE

= 1 MHz

Program, Erase

CC2

f = V

f (MAX.), /CEf = V

, /OE = V

Standby

CC3

f = V

f (MAX.), /CEf = /RESET =

0.2

/WP(ACC) = V

0.3 V, /OE = V

Standby / Reset

CC4

f = V

f (MAX.), /RESET = V

0.2 V

0.2

Automatic sleep mode

CC5

= V

0.2 V, V

= V

0.2 V

0.2

Read during programming

CC6

= V

0.2 V, V

= V

0.2 V

Read during erasing

CC7

= V

0.2 V, V

= V

0.2 V

Programming

CC8

/CEf = V

, /OE = V

during suspend

Automatic programming during suspend

Accelerated

ACC

/WP (ACC) pin

programming

/RESET high level input voltage

High Voltage is applied

11.5

12.5

Accelerated programming voltage

ACC

High Voltage is applied

8.5

9.5

Low V

f lock-out voltage

Note

LKO

1.7

Note When V

f is equal to or lower than V

LKO

, the device ignores all write cycles. Refer to Refer to DUAL

OPERATION FLASH MEMORY 32M BITS A SERIES Information (M14914E).

SRAM

Parameter

Symbol

Test condition

MIN.

TYP.

MAX.

Unit

Power supply current

CC1S

/CE1s = V

, CE2s = V

, Minimum cycle time, I

I/O

= 0 mA

/CE1s = V

, CE2s = V

, I

I/O

= 0 mA, Cycle time =

CC2S

/CE1s

0.2 V, CE2s

s 0.2 V, Cycle time = 1

I/O

= 0 mA, V

0.2 V, V

s 0.2 V

Standby supply current

SB1S

/CE1s = V

or CE2s = V

or /LB = /UB = V

0.6

SB2S

/CE1s

0.2 V, CE2s

0.2 V

0.5

CE2s

0.2 V

0.5

/LB = /UB

0.2 V, /CE1s

0.2 V, CE2s

0.2 V

0.5

Data Sheet M15318EJ2V0DS

MC-222244A-X

Write Cycle (Erase / Program) (Flash Memory)

Parameter

Symbol

MIN.

TYP.

MAX.

Unit

Notes

Write cycle time

Address setup time (/WE to address)

Address setup time (/CEf to address)

Address hold time (/WE to address)

Address hold time (/CEf to address)

Input data setup time

Input data hold time

/OE hold time

Read

OEH

Toggle bit, Data polling

Read recovery time before write (/OE to /CEf)

GHEL

Read recovery time before write (/OE to /WE)

GHWL

/WE setup time (/CEf to /WE)

/CEf setup time (/WE to /CEf)

/WE hold time (/CEf to /WE)

/CEf hold time (/WE to /CEf)

Write pulse width

/CEf pulse width

Write pulse width high

WPH

/CEf pulse width high

CPH

Byte programming operation time

BPG

200

Word programming operation time

WPG

200

Sector erase operation time

SER

0.7

f setup time

VCS

RY (/BY) recovery time

/RESET pulse width

500

/RESET high-voltage (V

) hold time from high of RY(/BY)

RRB

when sector group is temporarily unprotect

/RESET hold time

From completion of automatic program / erase to data

EOE

output time

RY (/BY) delay time from valid program or erase operation

BUSY

Address setup time to /OE low in toggle bit

ASO

Address hold time to /CEf or /OE high in toggle bit

AHT

/CEf pulse width high for toggle bit

CEPH

/OE pulse width high for toggle bit

OEPH

Voltage transition time

VLHT

Rise time to V

(/RESET)

VIDR

500

Rise time to V

ACC

(/WP(ACC))

VACCR

500

Erase timeout time

TOW

Erase suspend transition time

SPD

Notes 1. The preprogramming time prior to the erase operation is not included.

2. Sector group protection and accelerated mode only
3. Sector group protection only.
4. Table only.

Data Sheet M15318EJ2V0DS

MC-222244A-X

Read Cycle (SRAM)

Parameter

Symbol

MIN.

MAX.

Unit

Notes

Read cycle time

Address access time

/CE1s access time

CO1

CE2s access time

CO2

/OE to output valid

/LB, /UB to output valid

Output hold from address change

/CE1s to output in Low-Z

LZ1

CE2s to output in Low-Z

LZ2

/OE to output in Low-Z

OLZ

/LB, /UB to output in Low-Z

BLZ

/CE1s to output in Hi-Z

HZ1

CE2s to output in Hi-Z

HZ2

/OE to output in Hi-Z

OHZ

/LB, /UB to output in Hi-Z

BHZ

Write Cycle (SRAM)

Parameter

Symbol

MIN.

MAX.

Unit

Notes

Write cycle time

/CE1s to end of write

CW1

CE2s to end of write

CW2

/LB, /UB to end of write

Address valid to end of write

Address setup time

Write pulse width

Write recovery time

Data valid to end of write

Data hold time

/WE to output in Hi-Z

WHZ

Output active from end of write

Data Sheet M15318EJ2V0DS

MC-222244A-X

Low V

Data Retention Characteristics (SRAM)

Parameter

Symbol

Test Condition

MIN.

TYP.

MAX.

Unit

Data retention supply voltage

CCDR1

/CE1s

0.2 V, CE2s

0.2 V

1.0

3.6

CCDR2

CE2s

0.2 V

1.0

3.6

CCDR3

/LB = /UB

0.2 V,

1.0

3.6

/CE1s

0.2 V, CE2s

0.2 V

Data retention supply current

CCDR1

s = 1.5 V, /CE1s

0.2 V,

0.3

CE2s

0.2 V

CCDR2

s = 1.5 V, CE2s

0.2 V

0.3

CCDR3

s = 1.5 V, /LB = /UB

0.2 V,

0.3

/CE1s

0.2 V, CE2s

0.2 V

Chip deselection to data retention mode

CDR

Operation recovery time

Note

Note t

: Read cycle time

Data Sheet M15318EJ2V0DS

MC-222244A-X

Figure 4. Sector Group Protection Timing Chart (Flash Memory)

SGAx

Address (Input)

A0 (Input)

A1 (Input)

A6 (Input)

/CEf (Input)

/RESET (Input)

/OE (Input)

/WE (Input)

I/O (Input/Output)

VCS

VLHT

VIDR

TIMEOUT

SGAy

60H

40H

01H

Note

60H

Note The sector group protection verification result is output.

01H : The sector group is protected.

00H : The sector group is not protected.

Figure 5. Temporary Sector Group Unprotect Timing Chart (Flash Memory)

/RESET (Input)

/WE (Input)

/CEf (Input)

RY (/BY) (Output)

VLHT

VCS

VIDR

RRB

VLHT

(Program or erase command sequence)

Period during which

protection is canceled

Data Sheet M15318EJ2V0DS

MC-222244A-X

Figure 8. Write Cycle Timing Chart (/WE Controlled) (Flash Memory)

Address (Input)

/CEf (Input)

/OE (Input)

/WE (Input)

I/O (Input / Output)

GHWL

WPH

BPG

WPG

/I/O7

OUT

CEf

555H

A0H

(3rd and 4th write cycle)

OUT

(Data polling)

Remarks 1. This timing chart shows the last two write cycles among the program command sequence's four write

cycles, and data polling.

2. This timing chart shows the WORD mode's case. In the BYTE mode, address to be input

are different from the WORD mode. See Command Sequence (Flash Memory).

3. PA : Program address

PD : Program data
/I/O7 : The output of the complement of the data written to the device.
D

OUT

: The output of the data written to the device.

Figure 9. Write Cycle Timing Chart (/CEf Controlled) (Flash Memory)

Address (Input)

/CEf (Input)

/OE (Input)

/WE (Input)

I/O (Input / Output)

GHEL

BPG

WPG

/I/O7

OUT

CEf

555H

A0H

(3rd and 4th write cycle)

OUT

CPH

(Data polling)

Remarks 1. This timing chart shows the last two write cycles among the program command sequence's four write

cycles, and data polling.

2. This timing chart shows the WORD mode's case. In the BYTE mode, address to be input

are different from the WORD mode. See Command Sequence (Flash Memory).

3. PA : Program address

PD : Program data
/I/O7 : The output of the complement of the data written to the device.
D

OUT

: The output of the data written to the device.

Data Sheet M15318EJ2V0DS

MC-222244A-X

Figure 10. Sector / Chip Erase Timing Chart (Flash Memory)

Address (Input)

/CEf (Input)

/OE (Input)

/WE (Input)

I/O (Input)

WPH

555H

55H

AAH

80H

AAH

55H

(10H for chip erase)

30H

2AAH

555H

2AAH

FSA

Note

GHWL

VCS

Note FSA is the sector address to be erased. In the case of chip erase, input 555H (WORD mode), AAAH (BYTE

mode).

Remark This timing chart shows the WORD mode's case. In the BYTE mode, address to be input are different from

the WORD mode. See Command Sequence (Flash Memory)..

Figure 11. Data Polling Timing Chart (Flash Memory)

/CEf (Input)

OEH

BPG,

WPG,

SER

CEf

Hi-Z

/OE (Input)

/WE (Input)

I/O7 (Output)

RY (/BY) (Output)

EOE

/I/O7

Valid data

Hi-Z

I/O0 - I/O6 (Output)

BUSY

OUT

Note

Status data

Note I/O7 = D

OUT

: True value of program data (indicates completion of automatic program / erase)

Data Sheet M15318EJ2V0DS

MC-222244A-X

Figure 12. Toggle Bit Timing Chart (Flash Memory)

/OE (Input)

/WE (Input)

/CEf (Input)

Address (Input)

I/O6, I/O2 (Input / Output)

ASO

AHT

CEPH

OEPH

OEH

BUSY

OEH

CEf

Input data

Toggle

Valid

data out

Stop

toggling

Note

Toggle

RY (/BY) (Output)

Note I/O6 stops the toggle (indicates automatic program / erase completion).

Figure 13. I/O2 vs. I/O6 Timing Chart (Flash Memory)

/WE (Input)

Input of automatic

erase command

Erase

suspended

Erasure resumed

Erase suspended input

of program command

Erase suspended input

of program command

Erase suspended

read

Erase suspended

read

Erasure

Erasure Completion of

erasure

Toggle

I/O6 (Output)

I/O2 (Output)

I/O2 and I/O6 (/CEf or /OE is used for toggle)

Figure 14. RY (/BY) (Ready / Busy) Timing Chart (Flash Memory)

/CEf (Input)

/WE (Input)

RY (/BY) (Output)

BUSY

Automatic program or erase

Rising edge of the last write pulse

Figure 15. /RESET and RY (/BY) Timing Chart (Flash Memory)

/WE (Input)

/RESET (Input)

RY (/BY) (Output)

READY

Data Sheet M15318EJ2V0DS

MC-222244A-X

Figure 20. Write Cycle Timing Chart 1 (/WE Controlled) (SRAM)

CW1

WHZ

Indefinite data out

Hi-Z

Data in

Indefinite data out

Address (Input)

/CE1s (Input)

/LB, /UB (Input)

I/O (Input / Output)

CE2s (Input)

CW2

/WE (Input)

Cautions 1. During address transition, at least one of pins /CE1s, CE2s, /WE should be inactivated.

2. Do not input data to the I/O pins while they are in the output state.

Remarks 1. Write operation is done during the overlap time of a low level /CE1s, /WE, /LB and/or /UB, and a

high level CE2s.

2. If /CE1s changes to low level at the same time or after the change of /WE to low level, or if

CE2s changes to high level at the same time or after the change of /WE to low level, the I/O

pins will remain Hi-Z state.

3. When /WE is at low level, the I/O pins are always Hi-Z. When /WE is at high level, read

operation is executed. Therefore /OE should be at high level to make the I/O pins Hi-Z.

Data Sheet M15318EJ2V0DS

MC-222244A-X

Figure 24. Data Retention Timing Chart 1 (/CE1s Controlled) (SRAM)

(MIN.)

CCDR

(MIN.)

(MAX.)

/CE1s

s 0.2 V

s(MIN.)

CDR

Data retention mode

Remark

On the data retention mode by controlling /CE1s, the input level of CE2s must be

0.2 V or

0.2 V. The other pins (Address, I/O, /WE, /OE, /LB, /UB) can be in Hi-Z state.

Figure 25. Data Retention Timing Chart 2 (CE2s Controlled) (SRAM)

(MIN.)

CCDR

(MIN.)

(MAX.)

CE2s

0.2 V

CDR

Data retention mode

s(MIN.)

Remark

On the data retention mode controlling CE2s, the other pins (/CE1s, Address, I/O, /WE, /OE, /LB, /UB)

can be in Hi-Z state.

Data Sheet M15318EJ2V0DS

MC-222244A-X

CFI Code List

(1/2)

Address A6 to A0

Data I/O15 to I/O0

Description

10H

0051H

"QRY" (ASCII code)

11H

0052H

12H

0059H

13H

0002H

Main command set

14H

0000H

2 : AMD/FJ standard type

15H

0040H

Start address of PRIMARY table

16H

0000H

17H

0000H

Auxiliary command set

18H

0000H

00H : Not supported

19H

0000H

Start address of auxiliary algorithm table

1AH

0000H

1BH

0027H

Minimum V

f voltage (program / erase)

I/O7 to I/O4 : 1 V/bit

I/O3 to I/O0 : 100 mV/bit

1CH

0036H

Maximum V

f voltage (program / erase)

I/O7 to I/O4 : 1 V/bit

I/O3 to I/O0 : 100 mV/bit

1DH

0000H

Minimum V

voltage

1EH

0000H

Maximum V

voltage

1FH

0004H

Typical word program time (2

20H

0000H

Typical buffer program time (2

21H

000AH

Typical sector erase time (2

ms)

22H

0000H

Typical chip erase time (2

ms)

23H

0005H

Maximum word program time (typical time

)

24H

0000H

Maximum buffer program time (typical time

)

25H

0004H

Maximum sector erasing time (typical time

)

26H

0000H

Maximum chip erasing time (typical time

)

27H

0016H

Capacity (2

Bytes)

28H

0002H

I/O information

29H

0000H

2 :

16-bit organization

2AH

0000H

Maximum number of bytes when two banks are programmed (2

)

2BH

0000H

2CH

0002H

Type of erase block

2DH

0007H

Information about erase block 1

2EH

0000H

Bit0 to 15 : y = number of sectors

2FH

0020H

Bit16 to 31 : z = size

30H

0000H

256 Bytes)

Data Sheet M15318EJ2V0DS

MC-222244A-X

(2/2)

Address A6 to A0

Data I/O15 to I/O0

Description

31H

003EH

Information about erase block 2

32H

0000H

bit0 to 15 : y = number of sectors

33H

0000H

bit16 to 31 : z = size

34H

0001H

256 Bytes)

40H

0050H

"PRI" (ASCII code)

41H

0052H

42H

0049H

43H

0031H

Main version (ASCII code)

44H

0032H

Minor version (ASCII code)

45H

0000H

Address during command input

00H : Necessary

01H : Unnecessary

46H

0002H

Temporary erase suspend function

00H : Not supported

01H : Read only

02H : Read / Program

47H

0001H

Sector group protection

00H : Not supported

01H : Supported

48H

0001H

Temporary sector group protection

00H : Not supported

01H : Supported

49H

0004H

Sector group protection algorithm

4AH

00xxH

Number of sectors of bank 2

00H : Not supported

20H : MC-222244A-X

4BH

0000H

Burst mode

00H : Not supported

4CH

0000H

Page mode

00H : Not supported

4DH

0085H

Minimum V

ACC

voltage

I/O7 to I/O4 : 1 V/bit

I/O3 to I/O0 : 100 mV/bit

4EH

0095H

Maximum V

ACC

voltage

I/O7 to I/O4 : 1 V/bit

I/O3 to I/O0 : 100 mV/bit

4FH

00xxH

Boot organization

03H : Top boot

50H

0001H

Temporary program suspend function

00H : Not supported

01H : Supported

Data Sheet M15318EJ2V0DS

MC-222244A-X

NOTES FOR CMOS DEVICES

PRECAUTION AGAINST ESD FOR SEMICONDUCTORS

Note:

Strong electric field, when exposed to a MOS device, can cause destruction of the gate oxide and

ultimately degrade the device operation. Steps must be taken to stop generation of static electricity

as much as possible, and quickly dissipate it once, when it has occurred. Environmental control

must be adequate. When it is dry, humidifier should be used. It is recommended to avoid using

insulators that easily build static electricity. Semiconductor devices must be stored and transported

in an anti-static container, static shielding bag or conductive material. All test and measurement

tools including work bench and floor should be grounded. The operator should be grounded using

wrist strap. Semiconductor devices must not be touched with bare hands. Similar precautions need

to be taken for PW boards with semiconductor devices on it.

HANDLING OF UNUSED INPUT PINS FOR CMOS

Note:

No connection for CMOS device inputs can be cause of malfunction. If no connection is provided

to the input pins, it is possible that an internal input level may be generated due to noise, etc., hence

causing malfunction. CMOS devices behave differently than Bipolar or NMOS devices. Input levels

of CMOS devices must be fixed high or low by using a pull-up or pull-down circuitry. Each unused

pin should be connected to V

or GND with a resistor, if it is considered to have a possibility of

being an output pin. All handling related to the unused pins must be judged device by device and

related specifications governing the devices.

STATUS BEFORE INITIALIZATION OF MOS DEVICES

Note:

Power-on does not necessarily define initial status of MOS device. Production process of MOS

does not define the initial operation status of the device. Immediately after the power source is

turned ON, the devices with reset function have not yet been initialized. Hence, power-on does

not guarantee out-pin levels, I/O settings or contents of registers. Device is not initialized until the

reset signal is received. Reset operation must be executed immediately after power-on for devices

having reset function.

MC-222244A-X

Related Documents

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Document Number

DUAL OPERATION FLASH MEMORY 32M BITS A SERIES Information

M14914E

M8E 00. 4

The information in this document is current as of July, 2001. The information is subject to change
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