ChipFind - документация

Электронный компонент: M15825EJ4V0DS00

Скачать:  PDF   ZIP

Document Outline

The mark shows major revised points.
The information in this document is subject to change without notice. Before using this document, please
confirm that this is the latest version.
Not all devices/types available in every country. Please check with local NEC representative for
availability and additional information.
MOS INTEGRATED CIRCUIT



PD44165084, 44165184, 44165364
18M-BIT QDR
TM
II SRAM
4-WORD BURST OPERATION
Document No. M15825EJ4V0DS00 (4th edition)
Date Published June 2003 NS CP(K)
Printed in Japan
PRELIMINARY DATA SHEET
2001
Description
The
PD44165084 is a 2,097,152-word by 8-bit, the PD44165184 is a 1,048,576-word by 18-bit and the
PD44165364 is a 524,288-word by 36-bit synchronous quad data rate static RAM fabricated with advanced CMOS
technology using full CMOS six-transistor memory cell.
The
PD44165084, PD44165184 and PD44165364 integrates unique synchronous peripheral circuitry and a
burst counter. All input registers controlled by an input clock pair (K and /K) are latched on the positive edge of K and
/K.
These products are suitable for application which require synchronous operation, high speed, low voltage, high
density and wide bit configuration.
These products are packaged in 165-pin PLASTIC FBGA.
Features
1.8 0.1 V power supply and HSTL I/O
DLL circuitry for wide output data valid window and future frequency scaling
Separate independent read and write data ports with concurrent transactions
100% bus utilization DDR READ and WRITE operation
Four-tick burst for reduced address frequency
Two input clocks (K and /K) for precise DDR timing at clock rising edges only
Two output clocks (C and /C) for precise flight time
and clock skew matching-clock and data delivered together to receiving device
Internally self-timed write control
Clock-stop capability with
s restart
User programmable impedance output
Fast clock cycle time : 4.0 ns (250 MHz) , 5.0 ns (200 MHz) , 6.0 ns (167 MHz)
Simple control logic for easy depth expansion
JTAG boundary scan
2
Preliminary Data Sheet M15825EJ4V0DS



PD44165084, 44165184, 44165364
Ordering Information
Part number
Cycle
Clock
Organization Core Supply
I/O
Package
Time
Frequency
(word x bit)
Voltage
Interface
ns
MHz
V
PD44165084F5-E40-EQ1
4.0
250
2 M x 8-bit
1.8 0.1
HSTL
165-pin PLASTIC
PD44165084F5-E50-EQ1
5.0
200
FBGA (13 x 15)
PD44165084F5-E60-EQ1
6.0
167
PD44165184F5-E40-EQ1
4.0
250
1 M x 18-bit
PD44165184F5-E50-EQ1
5.0
200
PD44165184F5-E60-EQ1
6.0
167
PD44165364F5-E40-EQ1
4.0
250
512 K x 36-bit
PD44165364F5-E50-EQ1
5.0
200
PD44165364F5-E60-EQ1
6.0
167
3
Preliminary Data Sheet M15825EJ4V0DS



PD44165084, 44165184, 44165364
Pin Configurations
/
indicates active low signal.
165-pin PLASTIC FBGA (13 x 15)
(Top View)
[



PD44165084F5-EQ1]
1
2
3
4
5
6
7
8
9
10
11
A
/CQ
V
SS
A
/W
/NW1
/K
NC
/R
A
V
SS
CQ
B
NC
NC
NC
A
NC
K
/NW0
A
NC
NC
Q3
C
NC
NC
NC
V
SS
A
NC
A
V
SS
NC
NC
D3
D
NC
D4
NC
V
SS
V
SS
V
SS
V
SS
V
SS
NC
NC
NC
E
NC
NC
Q4
V
DD
Q
V
SS
V
SS
V
SS
V
DD
Q
NC
D2
Q2
F
NC
NC
NC
V
DD
Q
V
DD
V
SS
V
DD
V
DD
Q
NC
NC
NC
G
NC
D5
Q5
V
DD
Q
V
DD
V
SS
V
DD
V
DD
Q
NC
NC
NC
H
/DLL
V
REF
V
DD
Q
V
DD
Q
V
DD
V
SS
V
DD
V
DD
Q
V
DD
Q
V
REF
ZQ
J
NC
NC
NC
V
DD
Q
V
DD
V
SS
V
DD
V
DD
Q
NC
Q1
D1
K
NC
NC
NC
V
DD
Q
V
DD
V
SS
V
DD
V
DD
Q
NC
NC
NC
L
NC
Q6
D6
V
DD
Q
V
SS
V
SS
V
SS
V
DD
Q
NC
NC
Q0
M
NC
NC
NC
V
SS
V
SS
V
SS
V
SS
V
SS
NC
NC
D0
N
NC
D7
NC
V
SS
A
A
A
V
SS
NC
NC
NC
P
NC
NC
Q7
A
A
C
A
A
NC
NC
NC
R
TDO
TCK
A
A
A
/C
A
A
A
TMS
TDI
A
: Address inputs
TMS
: IEEE 1149.1 Test input
D0 to D7
: Data inputs
TDI
: IEEE 1149.1 Test input
Q0 to Q7
: Data outputs
TCK
: IEEE 1149.1 Clock input
/R
: Read input
TDO
: IEEE 1149.1 Test output
/W
: Write input
V
REF
: HSTL input reference input
/NW0, /NW1
: Nibble Write data select
V
DD
: Power Supply
K, /K
: Input clock
V
DD
Q
: Power Supply
C, /C
: Output clock
V
SS
: Ground
CQ, /CQ
: Echo clock
NC
: No connection
ZQ
: Output impedance matching
/DLL
: DLL disable
Remark Refer to Package Drawing for the index mark.
4
Preliminary Data Sheet M15825EJ4V0DS



PD44165084, 44165184, 44165364
165-pin PLASTIC FBGA (13 x 15)
(Top View)
[



PD44165184F5-EQ1]
1
2
3
4
5
6
7
8
9
10
11
A
/CQ
V
SS
NC
/W
/BW1
/K
NC
/R
A
V
SS
CQ
B
NC
Q9
D9
A
NC
K
/BW0
A
NC
NC
Q8
C
NC
NC
D10
V
SS
A
NC
A
V
SS
NC
Q7
D8
D
NC
D11
Q10
V
SS
V
SS
V
SS
V
SS
V
SS
NC
NC
D7
E
NC
NC
Q11
V
DD
Q
V
SS
V
SS
V
SS
V
DD
Q
NC
D6
Q6
F
NC
Q12
D12
V
DD
Q
V
DD
V
SS
V
DD
V
DD
Q
NC
NC
Q5
G
NC
D13
Q13
V
DD
Q
V
DD
V
SS
V
DD
V
DD
Q
NC
NC
D5
H
/DLL
V
REF
V
DD
Q
V
DD
Q
V
DD
V
SS
V
DD
V
DD
Q
V
DD
Q
V
REF
ZQ
J
NC
NC
D14
V
DD
Q
V
DD
V
SS
V
DD
V
DD
Q
NC
Q4
D4
K
NC
NC
Q14
V
DD
Q
V
DD
V
SS
V
DD
V
DD
Q
NC
D3
Q3
L
NC
Q15
D15
V
DD
Q
V
SS
V
SS
V
SS
V
DD
Q
NC
NC
Q2
M
NC
NC
D16
V
SS
V
SS
V
SS
V
SS
V
SS
NC
Q1
D2
N
NC
D17
Q16
V
SS
A
A
A
V
SS
NC
NC
D1
P
NC
NC
Q17
A
A
C
A
A
NC
D0
Q0
R
TDO
TCK
A
A
A
/C
A
A
A
TMS
TDI
A
: Address inputs
TMS
: IEEE 1149.1 Test input
D0 to D17
: Data inputs
TDI
: IEEE 1149.1 Test input
Q0 to Q17
: Data outputs
TCK
: IEEE 1149.1 Clock input
/R
: Read input
TDO
: IEEE 1149.1 Test output
/W
: Write input
V
REF
: HSTL input reference input
/BW0, /BW1
: Byte Write data select
V
DD
: Power Supply
K, /K
: Input clock
V
DD
Q
: Power Supply
C, /C
: Output clock
V
SS
: Ground
CQ, /CQ
: Echo clock
NC
: No connection
ZQ
: Output impedance matching
/DLL
: DLL disable
Remark Refer to Package Drawing for the index mark.
5
Preliminary Data Sheet M15825EJ4V0DS



PD44165084, 44165184, 44165364
165-pin PLASTIC FBGA (13 x 15)
(Top View)
[



PD44165364F5-EQ1]
1
2
3
4
5
6
7
8
9
10
11
A
/CQ
V
SS
NC
/W
/BW2
/K
/BW1
/R
NC
V
SS
CQ
B
Q27
Q18
D18
A
/BW3
K
/BW0
A
D17
Q17
Q8
C
D27
Q28
D19
V
SS
A
NC
A
V
SS
D16
Q7
D8
D
D28
D20
Q19
V
SS
V
SS
V
SS
V
SS
V
SS
Q16
D15
D7
E
Q29
D29
Q20
V
DD
Q
V
SS
V
SS
V
SS
V
DD
Q
Q15
D6
Q6
F
Q30
Q21
D21
V
DD
Q
V
DD
V
SS
V
DD
V
DD
Q
D14
Q14
Q5
G
D30
D22
Q22
V
DD
Q
V
DD
V
SS
V
DD
V
DD
Q
Q13
D13
D5
H
/DLL
V
REF
V
DD
Q
V
DD
Q
V
DD
V
SS
V
DD
V
DD
Q
V
DD
Q
V
REF
ZQ
J
D31
Q31
D23
V
DD
Q
V
DD
V
SS
V
DD
V
DD
Q
D12
Q4
D4
K
Q32
D32
Q23
V
DD
Q
V
DD
V
SS
V
DD
V
DD
Q
Q12
D3
Q3
L
Q33
Q24
D24
V
DD
Q
V
SS
V
SS
V
SS
V
DD
Q
D11
Q11
Q2
M
D33
Q34
D25
V
SS
V
SS
V
SS
V
SS
V
SS
D10
Q1
D2
N
D34
D26
Q25
V
SS
A
A
A
V
SS
Q10
D9
D1
P
Q35
D35
Q26
A
A
C
A
A
Q9
D0
Q0
R
TDO
TCK
A
A
A
/C
A
A
A
TMS
TDI
A
: Address inputs
TMS
: IEEE 1149.1 Test input
D0 to D35
: Data inputs
TDI
: IEEE 1149.1 Test input
Q0 to Q35
: Data outputs
TCK
: IEEE 1149.1 Clock input
/R
: Read input
TDO
: IEEE 1149.1 Test output
/W
: Write input
V
REF
: HSTL input reference input
/BW0 to /BW3
: Byte Write data select
V
DD
: Power Supply
K, /K
: Input clock
V
DD
Q
: Power Supply
C, /C
: Output clock
V
SS
: Ground
CQ, /CQ
: Echo clock
NC
: No connection
ZQ
: Output impedance matching
/DLL
: DLL disable
Remark Refer to Package Drawing for the index mark.