Document Outline

• COVER
• FEATURE
• ORDERING INFORMATION
• FUNCTION OUTLINE
• PIN CONFIGURATION (Top View)
• 1. PIN FUNCTION
  • 1.1 DESCRIPTION OF PIN FUNCTIONS
  • 1.2 PIN'S EQUIVALENT CIRCUIT
• 2. BLOCK DIAGRAM
• 3. PROGRAM MEMORY (ROM)
  • 3.1 PROGRAM MEMORY CONFIGURATIONS
  • 3.2 PROGRAM MEMORY FUNCTION
  • 3.3 PROGRAM FLOW
  • 3.4 BRANCH INSTRUCTION
  • 3.5 SUBROUTINE
  • 3.6 TABLE REFERENCE
  • 3.7 PRECAUTIONS IN ASSEMBLER DESCRIPTION
• 4. PROGRAM COUNTER (PC)
• 5. STACK
  • 5.1 CONFIGURATIONS
  • 5.2 STACK POINTER (SP)
  • 5.3 ADDRESS STACK REGISTER (ASR)
  • 5.4 INTERRUPT STACK REGISTER
• 6. DATA MEMORY (RAM)
  • 6.1 DATA MEMORY CONFIGURATIONS
  • 6.2 DATA MEMORY FUNCTION
  • 6.3 PRECAUTIONS IN USING DATA MEMORY
• 7. GENERAL REGISTER (GR)
  • 7.1 GENERAL REGISTER CONFIGURATIONS
  • 7.2 GENERAL REGISTER FUNCTION
  • 7.3 GENERAL REGISTER AND DATA MEMORY ADDRESS GENERATION IN EACH INSTRUCTION
  • 7.4 PRECAUTIONS IN USING GENERAL REGISTER
• 8. ALU
  • 8.1 ALU CONFIGURATIONS
  • 8.2 ALU FUNCTION
  • 8.3 ARITHMETIC OPERATION (BINARY AND DECIMAL ADDITION AND SUBTRACTION)
  • 8.4 LOGICAL OPERATION
  • 8.5 BIT DECISION
  • 8.6 COMPARATIVE DECISION
  • 8.7 ROTATION PROCESSING
• 9. SYSTEM REGISTER (SYSREG)
  • 9.1 ADDRESS REGISTER (AR)
  • 9.2 WINDOW REGISTER (WR)
  • 9.3 BANK REGISTER (BANK)
  • 9.4 MEMORY POINTER ENABLE FLAG (MPE)
  • 9.5 INDEX REGISTER (IX) AND DATA MEMORY ROW ADDRESS POINTER (MP)
  • 9.6 GENERAL REGISTER POINTER (RP)
  • 9.7 PROGRAM STATUS WORD (PSWORD)
• 10. REGISTER FILE (RF)
  • 10.1 IDCDMAEN
  • 10.2 SP
  • 10.3 CE
  • 10.4 SERIAL INTERFACE MODE REGISTER
  • 10.5 TMMODE
  • 10.6 INTVSYN
  • 10.7 INT
  • 10.8 HORIZONTAL SYNCHRONOUS SIGNAL COUNTER CONTROL
  • 10.9 SETTING THE PULSE WIDTH FOR ACCEPTING THE RMC PIN
  • 10.10 TIMER CARRY
  • 10.11 SERIAL INTERFACE WAIT CONTROL
  • 10.12 IEG
  • 10.13 A/D CONVERTER CONTROL
  • 10.14 SETTING PORT 1C INPUT/OUTPUT
  • 10.15 SERIAL I/O STATUS REGISTER
  • 10.16 INTERRUPT ENABLE FLAG
  • 10.17 CROM BANK SELECTION
  • 10.18 IDCEN
  • 10.19 P2ABIOn
  • 10.20 P1BBIOn
  • 10.21 P0BBIOn
  • 10.22 P0ABIOn
  • 10.23 SETTING THE INTERRUPT REQUEST GENERATION TIMING IN SERIAL INTERFACE MODE
  • 10.24 SETTING THE SHIFT CLOCK FREQUENCY
  • 10.25 IRQ
• 11. DATA BUFFER (DBF)
  • 11.1 DATA BUFFER CONFIGURATIONS
  • 11.2 DATA BUFFER FUNCTION
  • 11.3 DATA BUFFER AND TABLE REFERENCE
  • 11.4 DATA BUFFER AND PERIPHERAL HARDWARE
  • 11.5 DATA BUFFER AND EACH PERIPHERAL REGISTER
  • 11.6 PRECAUTIONS IN USING DATA BUFFER
• 12. INTERRUPT
  • 12.1 INTERRUPT BLOCK CONFIGURATIONS
  • 12.2 INTERRUPT FUNCTION
  • 12.3 INTERRUPT ACCEPTANCE OPERATION
  • 12.4 OPERATION AFTER INTERRUPT ACCEPTANCE
  • 12.5 RETURNING FROM INTERRUPT SERVICE ROUTINE
  • 12.6 INTERRUPT SERVICE ROUTINE
  • 12.7 EXTERNAL INTERRUPT (RMC PIN AND V SYNC# PIN)
  • 12.8 INTERNAL INTERRUPT (TIMER AND SERIAL INTERFACE)
  • 12.9 MULTIPLE INTERRUPT
• 13. TIMER FUNCTIONS
  • 13.1 TIMER CONFIGURATION
  • 13.2 TIMER FUNCTIONS
  • 13.3 TIMER CARRY FLIP-FLOP (TIMER CARRY FF)
  • 13.4 TIMER CARRY FF OPERATING PRECAUTIONS
  • 13.5 TIMER INTERRUPT
  • 13.6 PRECAUTIONS TIMER INTERRUPT USING
• 14. STANDBY FUNCTION
  • 14.1 STANDBY BLOCK CONFIGURATION
  • 14.2 STANDBY FUNCTION
  • 14.3 DEVICE OPERATION MODE SETTING WITH CE PIN
  • 14.4 HALT FUNCTION
  • 14.5 CLOCK STOP FUNCTION
  • 14.6 DEVICE OPERATIONS UPON HALT AND CLOCK STOP
• 15. RESET FUNCTION
  • 15.1 RESET BLOCK CONFIGURATION
  • 15.2 RESET FUNCTION
  • 15.3 CE RESET
  • 15.4 POWER-ON RESET
  • 15.5 RELATIONS BETWEEN CE RESET AND POWER-ON RESET
  • 15.6 POWER FAILURE DETECTION
• 16. GENERAL-PURPOSE PORTS
  • 16.1 GENERAL-PURPOSE PORT CONFIGURATION AND CLASSIFICATION
  • 16.2 OUTLINE OF GENRAL-PURPOSE PORT FUNCTIONS
  • 16.3 GENERAL-PURPOSE INPUT/OUTPUT PORTS (P0A, P0B, P1B, P1C, P2A)
  • 16.4 GENERAL-PURPOSE INPUT PORT (P0D)
  • 16.5 GENERAL-PURPOSE OUTPUT PORTS (P0C, P1A, P1D, P2B, P2C)
• 17. SERIAL INTERFACE
  • 17.1 SERIAL INTERFACE MODE REGISTER
  • 17.2 CLOCK COUNTER
  • 17.3 STATUS REGISTER
  • 17.4 WAIT REGISTER
  • 17.5 PRESETTABLE SHIFT REGISTER (PSR)
  • 17.6 SERIAL INTERFACE INTERRUPT SOURCE REGISTER (SIOIMD)
  • 17.7 SHIFT CLOCK FREQUENCY REGISTER (SIOCK)
• 18. D/A CONVERTER
  • 18.1 PWMRMP PIN
  • 18.2 PWM PIN
• 19. A/D CONVERTER
  • 19.1 OPERATING PRINCIPLE
  • 19.2 D/A CONVERTER CONFIGURATION
  • 19.3 COMPARE VOLTAGE SET REGISTER (ADCR)
  • 19.4 COMPARE JUDGE REGISTER (ADCCMP)
  • 19.5 ADC PIN SELECT REGISTER (ADCCHn)
  • 19.6 A/D CONVERSION PROGRAM EXAMPLE
• 20. IDC (IMAGE DISPLAY CONTROLLER)
  • 20.1 SPECIFICATIONS OUTLINE AND RESTRICTIONS
  • 20.2 DMA
  • 20.3 IDC ENABLE FLAG
  • 20.4 VRAM
  • 20.5 CROM (CHARACTER ROM)
  • 20.6 BLANK, R, G AND B PINS
  • 20.7 DISPLAY START POSITION SETTING
  • 20.8 PROGRAM EXAMPLE
• 21. HORIZONTAL SYNCHRONOUS SIGNAL COUNTER
  • 21.1 HORIZONTAL SYNCHRONOUS SIGNAL COUNTER CONFIGURATION
  • 21.2 GATE CONTROL REGISTER (HSCGT)
  • 21.3 HSYNC COUNTER (HSC)
  • 21.4 HORIZONTAL SYNCHRONOUS SIGNAL COUNTER USAGE EXAMPLE
• 22. uPD17052 INSTRUCTIONS
  • 22.1 GENERAL DESCRIPTION ON INSTRUCTION SET
  • 22.2 LEGEND
  • 22.3 INSTRUCTION SET LIST
  • 22.4 INTRINSIC MACRO INSTRUCTIONS
• 23. RESERVED SYMBOLS OF ASSEMBLER
  • 23.1 SYSTEM REGISTER (SYSREG)
  • 23.2 DATA BUFFER (DBF)
  • 23.3 GENERAL-PURPOSE PORT REGISTER
  • 23.4 REGISTER FILE (CONTROL REGISTER)
  • 23.5 PERIPHERAL HARDWARE ADDRESS
• 24. ELECTRICAL SPECIFICATIONS
• 25. PACKAGE DIMENSION
• 26. RECOMMENDED SOLDERING CONDITIONS
• APPENDIX. DEVELOPMENT TOOLS