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Электронный компонент: UPD4564323G5-A70-9JH

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availability and additional information.
1999
MOS INTEGRATED CIRCUIT






PD4564323 for Rev.
E
64M-bit Synchronous DRAM
4-bank, LVTTL
DATA SHEET
Document No.
M14376EJ2V0DS00 (2nd edition)
Date Published
December 1999 NS CP (K)
Printed in Japan
The mark
shows major revised points.
Description
The
PD4564323 is a high-speed 67,108,864-bit synchronous dynamic random-access memory, organized as
524,288 words
32 bits
4 banks.
The synchronous DRAMs achieved high-speed data transfer using the pipeline architecture.
All inputs and outputs are synchronized with the positive edge of the clock.
The synchronous DRAMs are compatible with Low Voltage TTL (LVTTL).
These products are packaged in 86-pin TSOP (II).
Features
Fully Synchronous Dynamic RAM, with all signals referenced to a positive clock edge
Pulsed interface
Possible to assert random column address in every cycle
Quad internal banks controlled by BA0 and BA1 (Bank Select)
32 organization
Byte control by DQM0, DQM1, DQM2 and DQM3
Programmable Wrap sequence (Sequential / Interleave)
Programmable burst length (1, 2, 4, 8 and full page)
Programmable /CAS latency (2 and 3)
Automatic precharge and controlled precharge
CBR (Auto) refresh and self refresh
Single 3.3 V
0.3 V power supply
LVTTL compatible inputs and outputs
4,096 refresh cycles / 64 ms
Burst termination by Burst stop command and Precharge command
Data Sheet M14376EJ2V0DS00
2



PD4564323 for Rev.
E
Ordering Information
Part number
Organization
(word
bit
bank)
Clock frequency
MHz (MAX.)
Package
PD4564323G5-A60-9JH
512K
32
4
166
86-pin Plastic TSOP (II)
PD4564323G5-A70-9JH
143
(10.16 mm (400))
PD4564323G5-A80-9JH
125
PD4564323G5-A10-9JH
100
PD4564323G5-A10B-9JH
100
5
Data Sheet M14376EJ2V0DS00
3



PD4564323 for Rev.
E
Part Number
PD4564323G5 - A60
Organization
32 : x32
Memory Density
64 : 64M bits
Synchronous
DRAM
NEC Memory
Package
G5 : TSOP(II)
Low Voltage
A : 3.3
0.3 V
Minimum Cycle Time
60 : 6 ns (166MHz)
70 : 7 ns (143MHz)
80 : 8 ns (125MHz)
10 : 10 ns (100MHz)
10B : 10 ns (100MHz)
Number of Banks
& Interface
3 : 4Bank, LVTTL
5
Data Sheet M14376EJ2V0DS00
4



PD4564323 for Rev.
E
Pin Configuration
/xxx indicates active low signal.
[



PD4564323]
86-pin Plastic TSOP (II) (10.16 mm (400))



512K words



32 bits



4 banks
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
86
85
84
83
82
81
80
79
78
77
76
75
74
73
72
71
70
69
68
67
66
65
64
63
62
61
60
59
58
57
56
55
54
53
52
51
50
49
48
47
46
45
44
V
CC
DQ0
V
CC
Q
DQ1
DQ2
V
SS
Q
DQ3
DQ4
V
CC
Q
DQ5
DQ6
V
SS
Q
DQ7
NC
V
CC
DQM0
/WE
/CAS
/RAS
/CS
NC
BA0
BA1
A10(AP)
A0
A1
A2
DQM2
V
CC
NC
DQ16
V
SS
Q
DQ17
DQ18
V
CC
Q
DQ19
DQ20
V
SS
Q
DQ21
DQ22
V
CC
Q
DQ23
V
CC
V
SS
DQ15
V
SS
Q
DQ14
DQ13
V
CC
Q
DQ12
DQ11
V
SS
Q
DQ10
DQ9
V
CC
Q
DQ8
NC
V
SS
DQM1
NC
NC
CLK
CKE
A9
A8
A7
A6
A5
A4
A3
DQM3
V
SS
NC
DQ31
V
CC
Q
DQ30
DQ29
V
SS
Q
DQ28
DQ27
V
CC
Q
DQ26
DQ25
V
SS
Q
DQ24
V
SS
A0 to A10
Note
: Address inputs
BA0, BA1
: Bank select
DQ0 to DQ31
: Data inputs / outputs
CLK
: Clock input
CKE
: Clock enable
/CS
: Chip select
/RAS
: Row address strobe
/CAS
: Column address strobe
/WE
: Write enable
DQM0 to DQM3 : DQ mask enable
V
CC
: Supply voltage
V
SS
: Ground
V
CC
Q
: Supply voltage for DQ
V
SS
Q
: Ground for DQ
NC
: No connection
Note A0 to A10 : Row address inputs
A0 to A7 : Column address inputs
Data Sheet M14376EJ2V0DS00
5



PD4564323 for Rev.
E
Block Diagram
Clock
Generator
Mode
Register
Command Decoder
Control Logic
Row
Address
Buffer
&
Refresh
Counter
Column
Address
Buffer
&
Burst
Counter
Data Control Circuit
Latch Circuit
Input & Output
Buffer
DQ
DQM
CLK
CKE
Address
/CS
/RAS
/CAS
/WE
Bank D
Bank C
Bank B
Sense Amplifier
Column Decoder &
Latch Circuit
Bank A
Row Decoder
Data Sheet M14376EJ2V0DS00
6



PD4564323 for Rev.
E
CONTENTS
1.
Input / Output Pin Function .............................................................................................................. 8
2.
Commands ......................................................................................................................................... 9
3.
Simplified State Diagram ................................................................................................................ 12
4.
Truth Table ....................................................................................................................................... 13
4.1
Command Truth Table............................................................................................................................. 13
4.2
DQM Truth Table ...................................................................................................................................... 13
4.3
CKE Truth Table....................................................................................................................................... 13
4.4
Operative Command Table .................................................................................................................... 14
4.5
Command Truth Table for CKE ............................................................................................................. 17
5.
Initialization ...................................................................................................................................... 18
6.
Programming the Mode Register ................................................................................................... 19
7.
Mode Register .................................................................................................................................. 20
7.1
Burst Length and Sequence .................................................................................................................. 21
8.
Address Bits of Bank-Select and Precharge ................................................................................ 22
9.
Precharge ......................................................................................................................................... 23
10. Auto Precharge ................................................................................................................................ 24
10.1
Read with Auto Precharge .................................................................................................................. 24
10.2
Write with Auto Precharge .................................................................................................................. 25
11. Read / Write Command Interval ..................................................................................................... 26
11.1
Read to Read Command Interval ........................................................................................................ 26
11.2
Write to Write Command Interval ....................................................................................................... 26
11.3
Write to Read Command Interval ........................................................................................................ 27
11.4
Read to Write Command Interval ........................................................................................................ 28
12. Burst Termination ........................................................................................................................... 29
12.1
Burst Stop Command .......................................................................................................................... 29
12.2
Precharge Termination ........................................................................................................................ 30
12.2.1
Precharge Termination in READ Cycle .................................................................................... 30
12.2.2
Precharge Termination in WRITE Cycle .................................................................................. 31
Data Sheet M14376EJ2V0DS00
7



PD4564323 for Rev.
E
13. Electrical Specifications ................................................................................................................. 32
13.1
AC Parameters for Read Timing ......................................................................................................... 37
13.2
AC Parameters for Write Timing ......................................................................................................... 39
13.3
Relationship between Frequency and Latency ................................................................................. 40
13.4
Mode Register Set ................................................................................................................................ 41
13.5
Power on Sequence and CBR (Auto) Refresh ................................................................................... 42
13.6
/CS Function ......................................................................................................................................... 43
13.7
Clock Suspension during Burst Read (using CKE Function) .......................................................... 44
13.8
Clock Suspension during Burst Write (using CKE Function) .......................................................... 46
13.9
Power Down Mode and Clock Mask ................................................................................................... 48
13.10 CBR (Auto) Refresh ............................................................................................................................. 49
13.11 Self Refresh (Entry and Exit) ............................................................................................................... 50
13.12 Random Column Read (Page with Same Bank) ................................................................................ 51
13.13 Random Column Write (Page with Same Bank) ................................................................................ 53
13.14 Random Row Read (Ping-Pong Banks) ............................................................................................. 55
13.15 Random Row Write (Ping-Pong Banks) ............................................................................................. 57
13.16 Read and Write ..................................................................................................................................... 59
13.17 Interleaved Column Read Cycle ......................................................................................................... 61
13.18 Interleaved Column Write Cycle ......................................................................................................... 63
13.19 Auto Precharge after Read Burst ....................................................................................................... 65
13.20 Auto Precharge after Write Burst ....................................................................................................... 67
13.21 Full Page Read Cycle ........................................................................................................................... 69
13.22 Full Page Write Cycle ........................................................................................................................... 71
13.23 Byte Write Operation ........................................................................................................................... 73
13.24 Burst Read and Single Write (Option) ................................................................................................ 74
13.25 Full Page Random Column Read ........................................................................................................ 75
13.26 Full Page Random Column Write ....................................................................................................... 76
13.27 PRE (Precharge) Termination of Burst ............................................................................................... 77
14. Package Drawing ............................................................................................................................. 79
15. Recommended Soldering Condition ............................................................................................. 80
16. Revision History .............................................................................................................................. 80
Data Sheet M14376EJ2V0DS00
8



PD4564323 for Rev.
E
1. Input / Output Pin Function
Pin name
Input / Output
Function
CLK
Input
CLK is the master clock input. Other inputs signals are referenced to the CLK rising
edge.
CKE
Input
CKE determine validity of the next CLK (clock). If CKE is high, the next CLK rising
edge is valid; otherwise it is invalid. If the CLK rising edge is invalid, the internal clock
is not issued and the
PD4564323 suspends operation.
When the
PD4564323 is not in burst mode and CKE is negated, the device enters
power down mode. During power down mode, CKE must remain low.
/CS
Input
/CS low starts the command input cycle. When /CS is high, commands are ignored
but operations continue.
/RAS, /CAS, /WE
Input
/RAS, /CAS and /WE have the same symbols on conventional DRAM but different
functions. For details, refer to the command table.
A0 - A10
Input
Row Address is determined by A0 - A10 at the CLK (clock) rising edge in the active
command cycle.
Column Address is determined by A0 - A7 at the CLK rising edge in the read or write
command cycle.
A10 defines the precharge mode. When A10 is high in the precharge command cycle,
all banks are precharged; when A10 is low, only the bank selected by BA0 and BA1 is
precharged.
When A10 is high in read or write command cycle, the precharge starts automatically
after the burst access.
BA0, BA1
Input
BA0 and BA1 are the bank select signal. In command cycle, BA0 and BA1 low select
bank A, BA0 low and BA1 high select bank C, BA0 high and BA1 low select bank B
and then BA0 and BA1 high select bank D.
DQM0 - DQM3
Input
DQM controls I/O buffers. DQM0 controls DQ0 - DQ7, DQM1 controls DQ8 - DQ15,
DQM2 controls DQ16 - DQ23, DQM3 controls DQ24 - DQ31.
In read mode, DQM controls the output buffers like a conventional /OE pin.
DQM high and DQM low turn the output buffers off and on, respectively.
The DQM latency for the read is two clocks.
In write mode, DQM controls the word mask. Input data is written to the memory cell if
DQM is low but not if DQM is high.
The DQM latency for the write is zero.
DQ0 - DQ31
Input / Output
DQ pins have the same function as I/O pins on a conventional DRAM.
V
CC
, V
SS
, V
CC
Q,
V
SS
Q
(Power supply)
V
CC
and V
SS
are power supply pins for internal circuits. V
CC
Q and V
SS
Q are power
supply pins for the output buffers.
Data Sheet M14376EJ2V0DS00
9



PD4564323 for Rev.
E
2. Commands
Mode register set command
(/CS, /RAS, /CAS, /WE = Low)
The
PD4564323 has a mode register that defines how the device
operates. In this command, A0 through A10, BA0 and BA1 are the data input
pins. After power on, the mode register set command must be executed to
initialize the device.
The mode register can be set only when all banks are in idle state.
During 2 CLK (t
RSC
) following this command, the
PD4564323 cannot
accept any other commands.
Fig.1 Mode register set command
/WE
/CAS
/RAS
/CS
CKE
CLK
H
Add
A10
BA0, BA1
(Bank select)
Activate command
(/CS, /RAS = Low, /CAS, /WE = High)
The
PD4564323 has four banks, each with 4,096 rows.
This command activates the bank selected by BA0 and BA1 and a row
address selected by A0 through A10.
This command corresponds to a conventional DRAM's /RAS falling.
Fig.2 Row address strobe and
bank activate command
/WE
/CAS
/RAS
/CS
CKE
CLK
H
Add
A10
BA0, BA1
Row
Row
(Bank select)
Precharge command
(/CS, /RAS, /WE = Low, /CAS = High)
This command begins precharge operation of the bank selected by BA0 and
BA1. When A10 is High, all banks are precharged, regardless of BA0 and
BA1. When A10 is Low, only the bank selected by BA0 and BA1 is
precharged.
After this command, the
PD4564323 can't accept the activate command to
the precharging bank during t
RP
(precharge to activate command period).
This command corresponds to a conventional DRAM's /RAS rising.
Fig.3 Precharge command
/WE
/CAS
/RAS
/CS
CKE
CLK
H
Add
A10
BA0, BA1
(Bank select)
(Precharge select)
Data Sheet M14376EJ2V0DS00
10



PD4564323 for Rev.
E
Write command
(/CS, /CAS, /WE = Low, /RAS = High)
If the mode register is in the burst write mode, this command sets the burst
start address given by the column address to begin the burst write operation.
The first write data in burst mode can input with this command with
subsequent data on following clocks.
Fig.4 Column address and write
command
/WE
/CAS
/RAS
/CS
CKE
CLK
H
Add
A10
BA0, BA1
(Bank select)
Col.
Read command
(/CS, /CAS = Low, /RAS, /WE = High)
Read data is available after /CAS latency requirements have been met.
This command sets the burst start address given by the column address.
Fig.5 Column address and read
command
/WE
/CAS
/RAS
/CS
CKE
CLK
H
Add
A10
BA0, BA1
(Bank select)
Col.
CBR (auto) refresh command
(/CS, /RAS, /CAS = Low, /WE, CKE = High)
This command is a request to begin the CBR (auto) refresh operation. The
refresh address is generated internally.
Before executing CBR (auto) refresh, all banks must be precharged.
After this cycle, all banks will be in the idle (precharged) state and ready for
a row activate command.
During t
RC
period (from refresh command to refresh or activate command),
the
PD4564323 cannot accept any other command.
Fig.6 CBR (auto) refresh command
Add
A10
BA0, BA1
/WE
/CAS
/RAS
/CS
CKE
CLK
H
(Bank select)
Data Sheet M14376EJ2V0DS00
11



PD4564323 for Rev.
E
Self refresh entry command
(/CS, /RAS, /CAS, CKE = Low, /WE = High)
After the command execution, self refresh operation continues while CKE
remains low. When CKE goes high, the
PD4564323 exits the self refresh
mode.
During self refresh mode, refresh interval and refresh operation are
performed internally, so there is no need for external control.
Before executing self refresh, all banks must be precharged.
Fig.7 Self refresh entry command
/WE
/CAS
/RAS
/CS
CKE
CLK
Add
A10
BA0, BA1
(Bank select)
Burst stop command
(/CS, /WE = Low, /RAS, /CAS = High)
This command can stop the current burst operation.
Fig.8 Burst stop command in Full
Page Mode
/WE
/CAS
/RAS
/CS
CKE
CLK
Add
A10
BA0, BA1
(Bank select)
H
No operation
(/CS = Low, /RAS, /CAS, /WE = High)
This command is not an execution command. No operations begin or
terminate by this command.
Fig.9 No operation
/WE
/CAS
/RAS
/CS
CKE
CLK
H
Add
A10
BA0, BA1
(Bank select)
Data Sheet M14376EJ2V0DS00
12



PD4564323 for Rev.
E
3. Simplified State Diagram
CKE
CKE
CKE
CKE
CKE
CKE
CKE
CKE
Precharge
Auto precharge
PRE
Read with
Auto precharge
Read
BST
BST
PRE (Precharge termination)
PRE (Precharge termination)
ACT
MRS
REF
CKE
CKE
SELF
SELF exit
IDLE
Mode
Register
Set
CBR(auto)
Refresh
ROW
ACTIVE
Self
Refresh
Power
Down
Active
Power
Down
Precharge
READ
READA
READ
SUSPEND
READA
SUSPEND
WRITE
WRITEA
WRITE
SUSPEND
WRITEA
SUSPEND
POWER
ON
Write
Read
Automatic sequence
Manual input
CKE
CKE
Read
Write
Write with
Write
Data Sheet M14376EJ2V0DS00
13



PD4564323 for Rev.
E
4. Truth Table
4.1 Command Truth Table
Function
Symbol
CKE
/CS
/RAS
/CAS
/WE
BA0,
A10
A9 - A0
n 1
n
BA1
Device deselect
DESL
H
H
No operation
NOP
H
L
H
H
H
Burst stop
BST
H
L
H
H
L
Read
READ
H
L
H
L
H
V
L
V
Read with auto precharge
READA
H
L
H
L
H
V
H
V
Write
WRIT
H
L
H
L
L
V
L
V
Write with auto precharge
WRITA
H
L
H
L
L
V
H
V
Bank activate
ACT
H
L
L
H
H
V
V
V
Precharge select bank
PRE
H
L
L
H
L
V
L
Precharge all banks
PALL
H
L
L
H
L
H
Mode register set
MRS
H
L
L
L
L
L
L
V
Remark H = High level, L = Low level,
= High or Low level (Don't care), V = Valid data input
4.2 DQM Truth Table
Function
Symbol
CKE
DQM
n-1
n
0
1
2
3
Data write/output enable
ENB
H
L
Data mask/output disable
MASK
H
H
DQ0 - DQ7 write enable/output enable
ENB0
H
L
DQ8 - DQ15 write enable/output enable
ENB1
H
L
DQ16 - DQ23 write enable/output enable
ENB2
H
L
DQ24 - DQ31 write enable/output enable
ENB3
H
L
DQ0 - DQ7 write inhibit/output disable
MASK0
H
H
DQ8 - DQ15 write inhibit/output disable
MASK1
H
H
DQ16 - DQ23 write inhibit/output disable
MASK2
H
H
DQ24 - DQ31 write inhibit/output disable
MASK3
H
H
Remark H = High level, L = Low level,
= High or Low level (Don't care)
4.3 CKE Truth Table
Current state
Function
Symbol
CKE
/CS
/RAS
/CAS
/WE
Address
n 1
n
Activating
Clock suspend mode entry
H
L
Any
Clock suspend
L
L
Clock suspend
Clock suspend mode exit
L
H
Idle
CBR (auto) refresh command
REF
H
H
L
L
L
H
Idle
Self refresh entry
SELF
H
L
L
L
L
H
Self refresh
Self refresh exit
L
H
L
H
H
H
L
H
H
Idle
Power down entry
H
L
Power down
Power down exit
L
H
H
L
H
L
H
H
H
Remark H = High level, L = Low level,
= High or Low level (Don't care)
Data Sheet M14376EJ2V0DS00
14



PD4564323 for Rev.
E
4.4 Operative Command Table
Note1
(1/3)
Current state
/CS /RAS /CAS /WE
Address
Command
Action
Notes
Idle
H
DESL
Nop or power down
2
L
H
H
NOP or BST
Nop or power down
2
L
H
L
H
BA, CA, A10
READ/READA
ILLEGAL
3
L
H
L
L
BA, CA, A10
WRIT/WRITA
ILLEGAL
3
L
L
H
H
BA, RA
ACT
Row activating
L
L
H
L
BA, A10
PRE/PALL
Nop
L
L
L
H
REF/SELF
CBR (auto) refresh or self refresh
4
L
L
L
L
Op-Code
MRS
Mode register accessing
Row active
H
DESL
Nop
L
H
H
NOP or BST
Nop
L
H
L
H
BA, CA, A10
READ/READA
Begin read : Determine AP
5
L
H
L
L
BA, CA, A10
WRIT/WRITA
Begin write : Determine AP
5
L
L
H
H
BA, RA
ACT
ILLEGAL
3
L
L
H
L
BA, A10
PRE/PALL
Precharge
6
L
L
L
H
REF/SELF
ILLEGAL
L
L
L
L
Op-Code
MRS
ILLEGAL
Read
H
DESL
Continue burst to end
Row active
L
H
H
H
NOP
Continue burst to end
Row active
L
H
H
L
BST
Burst stop
Row active
L
H
L
H
BA, CA, A10
READ/READA
Terminate burst, new read : Determine AP
7
L
H
L
L
BA, CA, A10
WRIT/WRITA
Terminate burst, start write : Determine AP
7, 8
L
L
H
H
BA, RA
ACT
ILLEGAL
3
L
L
H
L
BA, A10
PRE/PALL
Terminate burst, precharging
L
L
L
H
REF/SELF
ILLEGAL
L
L
L
L
Op-Code
MRS
ILLEGAL
Write
H
DESL
Continue burst to end
Write recovering
L
H
H
H
NOP
Continue burst to end
Write recovering
L
H
H
L
BST
Burst stop
Row active
L
H
L
H
BA, CA, A10
READ/READA
Terminate burst, start read : Determine AP
7, 8
L
H
L
L
BA, CA, A10
WRIT/WRITA
Terminate burst, new write : Determine AP
7
L
L
H
H
BA, RA
ACT
ILLEGAL
3
L
L
H
L
BA, A10
PRE/PALL
Terminate burst, precharging
9
L
L
L
H
REF/SELF
ILLEGAL
L
L
L
L
Op-Code
MRS
ILLEGAL
Data Sheet M14376EJ2V0DS00
15



PD4564323 for Rev.
E
(2/3)
Current state
/CS /RAS /CAS /WE
Address
Command
Action
Notes
Read with auto
H
DESL
Continue burst to end
Precharging
precharge
L
H
H
H
NOP
Continue burst to end
Precharging
L
H
H
L
BST
ILLEGAL
L
H
L
H
BA, CA, A10
READ/READA
ILLEGAL
3
L
H
L
L
BA, CA, A10
WRIT/WRITA
ILLEGAL
3
L
L
H
H
BA, RA
ACT
ILLEGAL
3
L
L
H
L
BA, A10
PRE/PALL
ILLEGAL
3
L
L
L
H
REF/SELF
ILLEGAL
L
L
L
L
Op-Code
MRS
ILLEGAL
Write with auto
precharge
H
DESL
Continue burst to end
Write
recovering with auto precharge
L
H
H
H
NOP
Continue burst to end
Write
recovering with auto precharge
L
H
H
L
BST
ILLEGAL
L
H
L
H
BA, CA, A10
READ/READA
ILLEGAL
3
L
H
L
L
BA, CA, A10
WRIT/WRITA
ILLEGAL
3
L
L
H
H
BA, RA
ACT
ILLEGAL
3
L
L
H
L
BA, A10
PRE/PALL
ILLEGAL
3
L
L
L
H
REF/SELF
ILLEGAL
L
L
L
L
Op-Code
MRS
ILLEGAL
Precharging
H
DESL
Nop
Enter idle after t
RP
L
H
H
H
NOP
Nop
Enter idle after t
RP
L
H
H
L
BST
ILLEGAL
L
H
L
H
BA, CA, A10
READ/READA
ILLEGAL
3
L
H
L
L
BA, CA, A10
WRIT/WRITA
ILLEGAL
3
L
L
H
H
BA, RA
ACT
ILLEGAL
3
L
L
H
L
BA, A10
PRE/PALL
Nop
Enter idle after t
RP
L
L
L
H
REF/SELF
ILLEGAL
L
L
L
L
Op-Code
MRS
ILLEGAL
Row activating
H
DESL
Nop
Enter bank active after t
RCD
L
H
H
H
NOP
Nop
Enter bank active after t
RCD
L
H
H
L
BST
ILLEGAL
L
H
L
H
BA, CA, A10
READ/READA
ILLEGAL
3
L
H
L
L
BA, CA, A10
WRIT/WRITA
ILLEGAL
3
L
L
H
H
BA, RA
ACT
ILLEGAL
3, 10
L
L
H
L
BA, A10
PRE/PALL
ILLEGAL
3
L
L
L
H
REF/SELF
ILLEGAL
L
L
L
L
Op-Code
MRS
ILLEGAL
Data Sheet M14376EJ2V0DS00
16



PD4564323 for Rev.
E
(3/3)
Current state
/CS /RAS /CAS /WE
Address
Command
Action
Notes
Write recovering
H
DESL
Nop
Enter row active after t
DPL
L
H
H
H
NOP
Nop
Enter row active after t
DPL
L
H
H
L
BST
Nop
Enter row active after t
DPL
L
H
L
H
BA, CA, A10
READ/READA
Start read, Determine AP
8
L
H
L
L
BA, CA, A10
WRIT/WRITA
New write, Determine AP
L
L
H
H
BA, RA
ACT
ILLEGAL
3
L
L
H
L
BA, A10
PRE/PALL
ILLEGAL
3
L
L
L
H
REF/SELF
ILLEGAL
L
L
L
L
Op-Code
MRS
ILLEGAL
Write recovering
H
DESL
Nop
Enter precharge after t
DPL
with auto precharge
L
H
H
H
NOP
Nop
Enter precharge after t
DPL
L
H
H
L
BST
Nop
Enter precharge after t
DPL
L
H
L
H
BA, CA, A10
READ/READA
ILLEGAL
3, 8
L
H
L
L
BA, CA, A10
WRIT/WRITA
ILLEGAL
3
L
L
H
H
BA, RA
ACT
ILLEGAL
3
L
L
H
L
BA, A10
PRE/PALL
ILLEGAL
L
L
L
H
REF/SELF
ILLEGAL
L
L
L
L
Op-Code
MRS
ILLEGAL
Refreshing
H
DESL
Nop
Enter idle after t
RC
L
H
H
NOP/BST
Nop
Enter idle after t
RC
L
H
L
READ/WRIT
ILLEGAL
L
L
H
ACT/PRE/PALL
ILLEGAL
L
L
L
REF/SELF/MRS
ILLEGAL
Mode register
H
DESL
Nop
Enter idle after t
RSC
accessing
L
H
H
H
NOP
Nop
Enter idle after t
RSC
L
H
H
L
BST
ILLEGAL
L
H
L
READ/WRIT
ILLEGAL
L
L
ACT/PRE/PALL/
REF/SELF/MRS
ILLEGAL
Notes 1.
All entries assume that CKE was active (High level) during the preceding clock cycle.
2.
If all banks are idle, and CKE is inactive (Low level),
PD4564323 will enter Power down mode.
All input buffers except CKE will be disabled.
3.
Illegal to bank in specified states; Function may be legal in the bank indicated by Bank Address (BA),
depending on the state of that bank.
4.
If all banks are idle, and CKE is inactive (Low level),
PD4564323 will enter Self refresh mode. All input
buffers except CKE will be disabled.
5.
Illegal if t
RCD
is not satisfied.
6.
Illegal if t
RAS
is not satisfied.
7.
Must satisfy burst interrupt condition.
8.
Must satisfy bus contention, bus turn around, and/or write recovery requirements.
9.
Must mask preceding data which don't satisfy t
DPL
.
10.
Illegal if t
RRD
is not satisfied.
Remark H = High level, L = Low level,
= High or Low level (Don't care), V = Valid data
Data Sheet M14376EJ2V0DS00
17



PD4564323 for Rev.
E
4.5 Command Truth Table for CKE
Current State
CKE
/CS /RAS /CAS /WE
Address
Action
Notes
n 1
n
Self refresh
H
INVALID, CLK (n-1) would exit self refresh
L
H
H
Self refresh recovery
L
H
L
H
H
Self refresh recovery
L
H
L
H
L
ILLEGAL
L
H
L
L
ILLEGAL
L
L
Maintain self refresh
Self refresh recovery
H
H
H
Idle after t
RC
H
H
L
H
H
Idle after t
RC
H
H
L
H
L
ILLEGAL
H
H
L
L
ILLEGAL
H
L
H
ILLEGAL
H
L
L
H
H
ILLEGAL
H
L
L
H
L
ILLEGAL
H
L
L
L
ILLEGAL
Power down
H
INVALID, CLK (n 1) would exit power down
L
H
H
EXIT power down
Idle
L
H
L
H
H
H
L
L
Maintain power down mode
All banks idle
H
H
H
Refer to operations in Operative Command Table
H
H
L
H
Refer to operations in Operative Command Table
H
H
L
L
H
Refer to operations in Operative Command Table
H
H
L
L
L
H
CBR (auto) refresh
H
H
L
L
L
L
Op-Code
Refer to operations in Operative Command Table
H
L
H
Refer to operations in Operative Command Table
H
L
L
H
Refer to operations in Operative Command Table
H
L
L
L
H
Refer to operations in Operative Command Table
H
L
L
L
L
H
Self refresh
1
H
L
L
L
L
L
Op-Code
Refer to operations in Operative Command Table
L
Power down
1
Row active
H
Refer to operations in Operative Command Table
L
Power down
1
Any state other than
H
H
Refer to operations in Operative Command Table
listed above
H
L
Begin clock suspend next cycle
2
L
H
Exit clock suspend next cycle
L
L
Maintain clock suspend
Notes 1. Self refresh can be entered only from the all banks idle state. Power down can be entered only from all
banks idle or row active state.
2. Must be legal command as defined in Operative Command Table.
Remark H = High level, L = Low level,
= High or Low level (Don't care)
Data Sheet M14376EJ2V0DS00
18



PD4564323 for Rev.
E
5. Initialization
The synchronous DRAM is initialized in the power-on sequence according to the following.
(1)
To stabilize internal circuits, when power is applied, a 100
s or longer pause must precede any signal toggling.
(2)
After the pause, all banks must be precharged using the Precharge command (The Precharge all banks
command is convenient).
(3)
Once the precharge is completed and the minimum t
RP
is satisfied, the mode register can be programmed. After
the mode register set cycle, t
RSC
(2 CLK minimum) pause must be satisfied as well.
(4)
Two or more CBR (Auto) refresh must be performed.
Remarks 1. The sequence of Mode register programming and Refresh above may be transposed.
2. CKE and DQM must be held high until the Precharge command is issued to ensure data-bus Hi-Z.
Data Sheet M14376EJ2V0DS00
19



PD4564323 for Rev.
E
6. Programming the Mode Register
The mode register is programmed by the Mode register set command using address bits A10 through A0, BA0 and
BA1 as data inputs. The register retains data until it is reprogrammed or the device loses power.
The mode register has four fields;
Options
: A10 through A7, BA0, BA1
/CAS latency : A6 through A4
Wrap type
: A3
Burst length
: A2 through A0
Following mode register programming, no command can be issued before at least 2 CLK have elapsed.
/CAS Latency
/CAS latency is the most critical of the parameters being set. It tells the device how many clocks must elapse
before the data will be available.
The value is determined by the frequency of the clock and the speed grade of the device. 13.3 Relationship
between Frequency and Latency shows the relationship of /CAS latency to the clock period and the speed grade of
the device.
Burst Length
Burst Length is the number of words that will be output or input in a read or write cycle. After a read burst is
completed, the output bus will become Hi-Z.
The burst length is programmable as 1, 2, 4, 8 or full page.
Wrap Type (Burst Sequence)
The wrap type specifies the order in which the burst data will be addressed. This order is programmable as either
"Sequential" or "Interleave". The method chosen will depend on the type of CPU in the system.
Some microprocessor cache systems are optimized for sequential addressing and others for interleaved
addressing. 7.1 Burst Length and Sequence shows the addressing sequence for each burst length using them.
Both sequences support bursts of 1, 2, 4 and 8. Additionally, sequence supports the full page length.
Data Sheet M14376EJ2V0DS00
20



PD4564323 for Rev.
E
7. Mode Register
WT = 1
1
2
4
8
R
R
R
R
1
0
0
0
0
A0
A1
A2
A3
A4
A5
A7
A6
A8
A9
A10
BA0
JEDEC Standard Test Set (refresh counter test)
BL
WT
LTMODE
0
0
1
x
x
A0
A1
A2
A3
A4
A5
A7
A6
A8
A9
A10
BA0
Burst Read and Single Write
(for Write Through Cache)
0
1
A0
A1
A2
A3
A4
A5
A7
A6
A8
A9
A10
BA0
Use in future
V
V
V
V
V
V
1
V
1
x
x
x
A0
A1
A2
A3
A4
A5
A7
A6
A8
A9
A10
BA0
Vender Specific
BL
WT
LTMODE
0
0
0
0
0
A0
A1
A2
A3
A4
A5
A7
A6
A8
A9
A10
BA0
Mode Register Set
V = Valid
x = Don' t care
WT = 0
1
2
4
8
R
R
R
Full page
Bits2-0
000
001
010
011
100
101
110
111
Burst length
Sequential
Interleave
0
1
Wrap type
/CAS latency
R
R
2
3
R
R
R
R
Bits6-4
000
001
010
011
100
101
110
111
Latency
mode
0
BA1
x
BA1
BA1
x
BA1
0
BA1
Remark R : Reserved
Mode Register Set Timing
CLK
CKE
/CS
/RAS
/CAS
/WE
A0 - A10,
BA0, BA1
Mode Register Set
Data Sheet M14376EJ2V0DS00
21



PD4564323 for Rev.
E
7.1 Burst Length and Sequence
[Burst of Two]
Starting address
(column address A0, binary)
Sequential addressing sequence
(decimal)
Interleave addressing sequence
(decimal)
0
0, 1
0, 1
1
1, 0
1, 0
[Burst of Four]
Starting address
(column address A1 - A0, binary)
Sequential addressing sequence
(decimal)
Interleave addressing sequence
(decimal)
00
0, 1, 2, 3
0, 1, 2, 3
01
1, 2, 3, 0
1, 0, 3, 2
10
2, 3, 0, 1
2, 3, 0, 1
11
3, 0, 1, 2
3, 2, 1, 0
[Burst of Eight]
Starting address
(column address A2 - A0, binary)
Sequential addressing sequence
(decimal)
Interleave addressing sequence
(decimal)
000
0, 1, 2, 3, 4, 5, 6, 7
0, 1, 2, 3, 4, 5, 6, 7
001
1, 2, 3, 4, 5, 6, 7, 0
1, 0, 3, 2, 5, 4, 7, 6
010
2, 3, 4, 5, 6, 7, 0, 1
2, 3, 0, 1, 6, 7, 4, 5
011
3, 4, 5, 6, 7, 0, 1, 2
3, 2, 1, 0, 7, 6, 5, 4
100
4, 5, 6, 7, 0, 1, 2, 3
4, 5, 6, 7, 0, 1, 2, 3
101
5, 6, 7, 0, 1, 2, 3, 4
5, 4, 7, 6, 1, 0, 3, 2
110
6, 7, 0, 1, 2, 3, 4, 5
6, 7, 4, 5, 2, 3, 0, 1
111
7, 0, 1, 2, 3, 4, 5, 6
7, 6, 5, 4, 3, 2, 1, 0
Full page burst is an extension of the above tables of sequential addressing, with the length being 256.
Data Sheet M14376EJ2V0DS00
22



PD4564323 for Rev.
E
8. Address Bits of Bank-Select and Precharge
A10
A9
A8
A7
A6
A4
A5
A3
A2
A1
A0
Row
(Activate command)
A10
A9
A8
A7
A6
A4
A5
A3
A2
A1
A0
(Precharge command)
disables Auto-Precharge
(End of Burst)
0
enables Auto-Precharge
(End of Burst)
1
A10
A9
A8
A7
A6
A4
A5
A3
A2
A1
A0
Col.
(/CAS strobes)
x : Don't care
BA0 BA1
BA0
BA1
BA0
BA1
Select Bank A
"Activate" command
0
Select Bank B
"Activate" command
0
1
1
0
1
0
1
BA1
BA0
Result
Select Bank C
"Activate" command
Select Bank D
"Activate" command
enables Read/Write
commands for Bank A
0
enables Read/Write
commands for Bank B
0
1
1
0
1
0
1
BA1
BA0
Result
enables Read/Write
commands for Bank C
enables Read/Write
commands for Bank D
Result
Precharge Bank A
Precharge Bank B
Precharge Bank C
Precharge Bank D
Precharge All Banks
A10
0
0
0
0
1
BA1
0
0
1
1
x
BA0
0
1
0
1
x
Data Sheet M14376EJ2V0DS00
23



PD4564323 for Rev.
E
9. Precharge
The precharge command can be issued anytime after t
RAS (MIN.)
is satisfied.
Soon after the precharge command is issued, precharge operation performed and the synchronous DRAM enters
the idle state after t
RP
is satisfied. The parameter t
RP
is the time required to perform the precharge.
The earliest timing in a read cycle that a precharge command can be issued without losing any data in the burst is
as follows.
It is depending on the /CAS latency and clock cycle time.
T0
T1
T2
T3
T4
T5
T6
T7
Burst length=4
Read
Read
Q1
Q2
Q3
Q4
PRE
Hi-Z
Q1
Q2
Q3
Q4
PRE
Hi-Z
(t
RAS
must be satisfied)
CLK
Command
/CAS latency = 2
DQ
Command
/CAS latency = 3
DQ
T8
In order to write all data to the memory cell correctly, the asynchronous parameter "t
DPL
" must be satisfied. The
t
DPL(MIN.)
specification defines the earliest time that a precharge command can be issued. Minimum number of clocks
is calculated by dividing t
DPL(MIN.)
with clock cycle time.
In summary, the precharge command can be issued relative to reference clock that indicates the last data word is
valid. In the following table, minus means clocks before the reference; plus means time after the reference.
/CAS latency
Read
Write
2
1
+t
DPL (MIN.)
3
2
+t
DPL (MIN.)
Data Sheet M14376EJ2V0DS00
24



PD4564323 for Rev.
E
10. Auto Precharge
During a read or write command cycle, A10 controls whether auto precharge is selected. A10 high in the Read or
Write command (Read with Auto precharge command or Write with Auto precharge command), auto precharge is
selected and begins automatically.
The t
RAS
must be satisfied with a read with auto precharge or a write with auto precharge operation. In addition, the
next activate command to the bank being precharged cannot be executed until the precharge cycle ends.
In read cycle, once auto precharge has started, an activate command to the bank can be issued after t
RP
has been
satisfied.
In write cycle, the t
DAL
must be satisfied to issue the next activate command to the bank being precharged.
The timing that begins the auto precharge cycle depends on both the /CAS latency programmed into the mode
register and whether read or write cycle.
10.1 Read with Auto Precharge
During a read cycle, the auto precharge begins one clock earlier (/CAS latency of 2) or two clocks earlier (/CAS
latency of 3) the last data word output.
QB1
QB2
QB3
QB4
Auto precharge starts
READA B
Hi-Z
QB1
QB2
QB3
QB4
Auto precharge starts
READA B
Hi-Z
DQ
Command
DQ
Command
/CAS latency = 2
/CAS latency = 3
CLK
T0
T2
T1
T3
T4
T5
T6
T7
T8
Burst length = 4
(t
RAS
must be satisfied)
T9
Remark READA means Read with Auto precharge
Data Sheet M14376EJ2V0DS00
25



PD4564323 for Rev.
E
10.2 Write with Auto Precharge
During a write cycle, the auto precharge starts at the timing that is equal to the value of the t
DPL (MIN.)
after the last
data word input to the device.
DB1
DB2
DB3
DB4
Auto precharge starts
WRITA B
Hi-Z
DB1
DB2
DB3
DB4
Auto precharge starts
WRITA B
Hi-Z
DQ
Command
DQ
Command
/CAS latency = 2
/CAS latency = 3
CLK
T0
T2
T1
T3
T4
T5
T6
T7
T8
Burst length = 4
(t
RAS
must be satisfied)
t
DPL(MIN.)
t
DPL(MIN.)
Remark WRITA means Write with Auto Precharge
In summary, the auto precharge begins relative to a reference clock that indicates the last data word is valid.
In the table below, minus means clocks before the reference; plus means after the reference.
/CAS latency
Read
Write
2
1
+t
DPL (MIN.)
3
2
+t
DPL (MIN.)
Data Sheet M14376EJ2V0DS00
26



PD4564323 for Rev.
E
11. Read / Write Command Interval
11.1 Read to Read Command Interval
During a read cycle, when new Read command is issued, it will be effective after /CAS latency, even if the previous
read operation does not completed. READ will be interrupted by another READ.
The interval between the commands is 1 cycle minimum. Each Read command can be issued in every clock
without any restriction.
QB1
QB2
QB3
QB4
Hi-Z
Read A
DQ
Command
CLK
T0
T2
T1
T3
T4
T5
T6
T7
T8
Burst length = 4, /CAS latency = 2
Read B
QA1
1cycle
T9
11.2 Write to Write Command Interval
During a write cycle, when a new Write command is issued, the previous burst will terminate and the new burst will
begin with a new Write command. WRITE will be interrupted by another WRITE.
The interval between the commands is minimum 1 cycle. Each Write command can be issued in every clock
without any restriction.
DB1
DB2
DB3
DB4
Hi-Z
Write A
DQ
Command
CLK
T0
T2
T1
T3
T4
T5
T6
T7
T8
Burst length = 4, /CAS latency = 2
Write B
DA1
1cycle
Data Sheet M14376EJ2V0DS00
27



PD4564323 for Rev.
E
11.3 Write to Read Command Interval
Write command and Read command interval is also 1 cycle.
Only the write data before Read command will be written.
The data bus must be Hi-Z at least one cycle prior to the first D
OUT
.
QB1
QB2
QB3
QB4
Write A
Hi-Z
QB1
QB2
QB3
QB4
Write A
Hi-Z
DQ
Command
DQ
Command
/CAS latency = 2
/CAS latency = 3
CLK
T0
T2
T1
T3
T4
T5
T6
T7
T8
Burst length = 4
DA1
DA1
Read B
Read B
Data Sheet M14376EJ2V0DS00
28



PD4564323 for Rev.
E
11.4 Read to Write Command Interval
During a read cycle, READ can be interrupted by WRITE.
The Read and Write command interval is 1 cycle minimum. There is a restriction to avoid data conflict. The Data
bus must be Hi-Z using DQM before WRITE.
D1
D2
D3
D4
Read
DQ
Command
CLK
T0
T2
T1
T3
T4
T5
T6
T7
T8
Burst length = 4
Write
DQM
Hi-Z
1cycle
READ can be interrupted by WRITE. DQM must be High at least 3 clocks prior to the Write command.
CLK
T0
T2
T1
T3
T4
T5
T6
T7
T8
Burst length = 8
T9
Q1
Q2
Q3
Read
DQ
Command
D1
D2
D3
Write
DQM
Hi-Z is
necessary
Q1
Q2
Read
DQ
Command
D1
D2
D3
Write
DQM
Hi-Z is
necessary
/CAS latency = 2
/CAS latency = 3
Data Sheet M14376EJ2V0DS00
29



PD4564323 for Rev.
E
12. Burst Termination
There are two methods to terminate a burst operation other than using a Read or a Write command. One is the
burst stop command and the other is the precharge command.
12.1 Burst Stop Command
During a read cycle, when the burst stop command is issued, the burst read data are terminated and the data bus
goes to Hi-Z after the /CAS latency from the burst stop command.
Read
Command
CLK
T0
T2
T1
T3
T4
T5
T6
T7
Burst length = X
Q1
Q2
Q3
DQ
/CAS latency = 2
Hi-Z
Q1
Q2
Q3
DQ
/CAS latency = 3
Hi-Z
BST
Remark BST: Burst stop command
During a write cycle, when the burst stop command is issued, the burst write data are terminated and data bus goes
to Hi-Z at the same clock with the burst stop command.
D2
D3
D4
Write
DQ
Command
/CAS latency = 2, 3
CLK
T0
T2
T1
T3
T4
T5
T6
T7
Burst length = X
BST
Hi-Z
D1
Remark BST: Burst stop command
Data Sheet M14376EJ2V0DS00
30



PD4564323 for Rev.
E
12.2 Precharge Termination
12.2.1 Precharge Termination in READ Cycle
During a read cycle, the burst read operation is terminated by a precharge command.
When the precharge command is issued, the burst read operation is terminated and precharge starts.
The same bank can be activated again after t
RP
from the precharge command.
To issue a precharge command, t
RAS
must be satisfied.
When /CAS latency is 2, the read data will remain valid until one clock after the precharge command.
Read
CLK
T0
T2
T1
T3
T4
T5
T6
T7
Burst length = X, /CAS latency = 2
Q1
DQ
Command
Q2
Q3
Q4
ACT
t
RP
PRE
Hi-Z
(t
RAS
must be satisfied)
When /CAS latency is 3, the read data will remain valid until two clocks after the precharge command.
Read
CLK
T0
T2
T1
T3
T4
T5
T6
T7
Burst length = X, /CAS latency = 3
DQ
Command
Q1
Q2
Q3
ACT
t
RP
PRE
Hi-Z
T8
Q4
(t
RAS
must be satisfied)
Data Sheet M14376EJ2V0DS00
31



PD4564323 for Rev.
E
12.2.2 Precharge Termination in WRITE Cycle
During a write cycle, the burst write operation is terminated by a precharge command.
When the precharge command is issued, the burst write operation is terminated and precharge starts.
The same bank can be activated again after t
RP
from the precharge command.
To issue a precharge command, t
RAS
must be satisfied.
When /CAS latency is 2, the write data written prior to the precharge command will be correctly stored. However,
invalid data may be written at the same clock as the precharge command. To prevent this from happening, DQM
must be high at the same clock as the precharge command. This will mask the invalid data.
Write
CLK
T0
T2
T1
T3
T4
T5
T6
T7
Burst length = X, /CAS latency = 2
DQ
Command
D1
D2
D3
ACT
DQM
t
RP
PRE
Hi-Z
D4
D5
(t
RAS
must be satisfied)
When /CAS latency is 3, the write data written prior to the precharge command will be correctly stored. However,
invalid data may be written at the same clock as the precharge command. To prevent this from happening, DQM
must be high at the same clock as the precharge command. This will mask the invalid data.
Write
CLK
T0
T2
T1
T3
T4
T5
T6
T7
Burst length = X, /CAS latency = 3
DQ
Command
D1
D2
D3
ACT
DQM
t
RP
PRE
Hi-Z
D5
T8
D4
(t
RAS
must be satisfied)
Data Sheet M14376EJ2V0DS00
32



PD4564323 for Rev.
E
13. Electrical Specifications
All voltages are referenced to V
SS
(GND).
After power up, wait more than 100
s and then, execute Power on sequence and CBR (auto) Refresh before
proper device operation is achieved.
Absolute Maximum Ratings
Parameter
Symbol
Condition
Rating
Unit
Voltage on power supply pin relative to GND
V
CC
, V
CC
Q
-
0.5 to +4.6
V
Voltage on input pin relative to GND
V
T
-
0.5 to +4.6
V
Short circuit output current
I
O
50
mA
Power dissipation
P
D
1
W
Operating ambient temperature
T
A
0 to 70
C
Storage temperature
T
stg
-
55 to + 125
C
Caution
Exposing the device to stress above those listed in Absolute Maximum Ratings could cause
permanent damage. The device is not meant to be operated under conditions outside the limits
described in the operational section of this specification. Exposure to Absolute Maximum
Rating conditions for extended periods may affect device reliability.
Recommended Operating Conditions
Parameter
Symbol
Condition
MIN.
TYP.
MAX.
Unit
Supply voltage
V
CC
, V
CC
Q
3.0
3.3
3.6
V
High level input voltage
V
IH
2.0
V
CC
+ 0.3
Note1
V
Low level input voltage
V
IL
-
0.3
Note 2
+0.8
V
Operating ambient temperature
T
A
0
70
C
Notes 1. V
IH(MAX.)
= V
CC
+ 1.5
V (Pulse width
5ns)
2. V
IL(MIN.)
= 1.5
V (Pulse width
5ns)
Pin Capacitance (T
A
= 25



C, f = 1 MHz)
Parameter
Symbol
Condition
MIN.
TYP.
MAX.
Unit
Input capacitance
C
I1
A0 - A10, BA0, BA1
2.5
4
pF
C
I2
CLK, CKE, /CS, /RAS, /CAS,
/WE, DQM0 - DQM3
2.5
4
Data input / output capacitance
C
I/O
DQ0 - DQ31
4
6.5
pF
Data Sheet M14376EJ2V0DS00
33



PD4564323 for Rev.
E
DC Characteristics 1 (Recommended Operating Conditions unless otherwise noted)
Parameter
Symbol
Test conditions
/CAS
latency
Grade
Maximum
Unit
Notes
Operating current
I
CC1
Burst length
=
1,
CL=2
-A60
150
mA
1
t
RC
t
RC(MIN.)
,
-A70
140
I
O
= 0
mA,
-A80
130
One bank active
-A10
130
-A10B
120
CL=3
-A60
160
-A70
150
-A80
140
-A10
140
-A10B
130
Precharge standby current
I
CC2
P
CKE
V
IL(MAX.)
, t
CK
=
15
ns
1
mA
in power down mode
I
CC2
PS
CKE
V
IL(MAX.)
, t
CK
=
1
Precharge standby current in
non power down mode
I
CC2
N
CKE
V
IH(MIN.)
, t
CK
=
15
ns, CS
V
IH(MIN.)
,
Input signals are changed one time during 30
ns
20
mA
I
CC2
NS
CKE
V
IH(MIN.)
, t
CK
=
,
Input signals are stable.
6
Active standby current in
I
CC3
P
CKE
V
IL(MAX.)
, t
CK
=
15
ns
5
mA
power down mode
I
CC3
PS
CKE
V
IL(MAX.)
, t
CK
=
4
Active standby current in
non power down mode
I
CC3
N
CKE
V
IH(MIN.)
, t
CK
=
15
ns, /CS
V
IH(MIN.)
,
Input signals are changed one time during 30
ns.
30
mA
I
CC3
NS
CKE
V
IH(MIN.)
, t
CK
=
, Input signals are stable.
20
Operating current
I
CC4
t
CK
t
CK(MIN.)
,
CL=2
-A60
170
mA
2
(Burst mode)
I
O
= 0
mA,
-A70
170
All banks active
-A80
170
-A10
140
-A10B
130
CL=3
-A60
240
-A70
220
-A80
190
-A10
180
-A10B
160
CBR (auto) refresh current
I
CC5
t
RC
t
RC(MIN.)
CL=2
-A60
160
mA
3
-A70
150
-A80
150
-A10
150
-A10B
130
CL=3
-A60
170
-A70
160
-A80
160
-A10
160
-A10B
140
Self refresh current
I
CC6
CKE
0.2
V
1
mA
Notes 1. I
CC1
depends on output loading and cycle rates. Specified values are obtained with the output open. In
addition to this, I
CC1
is measured on condition that addresses are changed only one time during t
CK(MIN.)
.
2. I
CC4
depends on output loading and cycle rates. Specified values are obtained with the output open. In
addition to this, I
CC4
is measured on condition that addresses are changed only one time during t
CK(MIN.)
.
3. I
CC5
is measured on condition that addresses are changed only one time during t
CK(MIN.)
.
5
Data Sheet M14376EJ2V0DS00
34



PD4564323 for Rev.
E
DC Characteristics 2 (Recommended Operating Conditions unless otherwise noted)
Parameter
Symbol
Test condition
MIN.
TYP.
MAX.
Unit
Notes
Input leakage current
I
I(L)
0
V
I
V
CC
Q, V
CC
Q = V
CC
,
All other pins not under test =
0 V
1.0
+1.0
A
Output leakage current
I
O(L)
0
V
O
V
CC
Q, D
OUT
is disabled
1.5
+1.5
A
High level output voltage
V
OH
I
O
= 4
mA
2.4
V
Low level output voltage
V
OL
I
O
= + 4
mA
0.4
V
AC Characteristics (Recommended Operating Conditions unless otherwise noted)
Test Conditions
Parameter
Value
Unit
Notes
AC high level input voltage / low level input voltage
2.4 / 0.4
V
Input timing measurement reference level
1.4
V
Transition time (Input rise and fall time)
1
ns
Output timing measurement reference level
1.4
V
t
CK
t
CH
t
CL
2.4 V
1.4 V
0.4 V
CLK
2.4 V
1.4 V
0.4 V
Input
t
SETUP
t
HOLD
Output
t
AC
t
OH
5
Data Sheet M14376EJ2V0DS00
35



PD4564323 for Rev.
E
Synchronous Characteristics
Parameter
/CAS Symbol
-A 60
-A 70
-A 80
-A 10
-A 10B
Unit Note
latency
MIN.
MAX.
MIN.
MAX.
MIN.
MAX.
MIN.
MAX.
MIN.
MAX.
Clock cycle time
CL = 3
t
CK3
6
(166MHz)
7
(143MHz)
8
(125MHz)
10
(100MHz)
10
(100MHz)
ns
CL = 2
t
CK2
10
(100MHz)
10
(100MHz)
10
(100MHz)
13
(77
MHz)
15
(67
MHz)
ns
Access time from CLK
CL = 3
t
AC3
5.5
5.5
6
6
7
ns
1
CL = 2
t
AC2
6
6
6
7
8
ns
1
CLK high level width
t
CH
2
2
3
3
3.5
ns
CLK low level width
t
CL
2
2
3
3
3.5
ns
Data-out hold time
t
OH
2.5
2.5
3
3
3
ns
1
Data-out low-impedance time
t
LZ
0
0
0
0
0
ns
Data-out high-impedance
CL = 3
t
HZ3
2.5
5.5
2.5
5.5
3
6
3
6
3
7
ns
time
CL = 2
t
HZ2
2.5
6
2.5
6
3
6
3
7
3
8
ns
Data-in setup time
t
DS
1.5
1.5
2
2
2.5
ns
Data-in hold time
t
DH
0.8
0.8
1
1
1
ns
Address setup time
t
AS
1.5
1.5
2
2
2.5
ns
Address hold time
t
AH
0.8
0.8
1
1
1
ns
CKE setup time
t
CKS
2
2
2
2
2.5
ns
CKE hold time
t
CKH
1
1
1
1
1
ns
CKE setup time (Power down exit)
t
CKSP
2
2
2
2
2.5
ns
Command (/CS, /RAS, /CAS,
/WE, DQM) setup time
t
CMS
1.5
1.5
2
2
2.5
ns
Command (/CS, /RAS, /CAS,
/WE, DQM) hold time
t
CMH
0.8
0.8
1
1
1
ns
Note 1. Output load
Output
Z = 50
1.4
V
50 pF
50
Data Sheet M14376EJ2V0DS00
36



PD4564323 for Rev.
E
Asynchronous Characteristics
Parameter
/CAS Symbol
-A 60
-A 70
-A 80
-A 10
-A 10B
Unit Note
latency
MIN.
MAX.
MIN.
MAX.
MIN.
MAX.
MIN.
MAX.
MIN.
MAX.
REF to REF/ACT command
period (Operation)
t
RC
60
63
70
70
90
ns
REF to REF/ACT command
period (Refresh)
t
RC1
66
70
70
70
90
ns
ACT to PRE command period
t
RAS
42
120,000
42
120,000
48
120,000
50
120,000
60
120,000
ns
PRE to ACT command period
t
RP
18
20
20
20
30
ns
Delay time ACT to READ/WRITE
command
t
RCD
18
20
20
20
30
ns
ACT(one) to ACT(another)
command period
t
RRD
12
14
16
20
20
ns
Data-in to PRE command period
t
DPL
8
8
8
10
10
ns
Data-in to ACT(REF) command
CL = 3
t
DAL3
2CLK+18
2CLK+20
1CLK+20
1CLK+20
1CLK+30
ns
period (Auto precharge)
CL = 2
t
DAL2
1CLK+18
1CLK+20
1CLK+20
1CLK+20
1CLK+30
ns
Mode register set cycle time
t
RSC
2
2
2
2
2
CLK
Transition time
t
T
0.5
30
0.5
30
0.5
30
1
30
1
30
ns
Refresh time (4,096 refresh cycles)
t
REF
64
64
64
64
64
ms
D
a
ta S
heet M14376E
J2V
0
D
S
00
37



PD4564323 for Rev
.
E
13.1 AC Parameters for Read Timing (Manual Precharge, Burst Length = 4, /CAS Latency = 3)
,
,
,
,
,
,,
,,
,,
,,
,,
,,
,,
,,
,,
,,
,,
,,
,,
,,
,,
,,
,,
,,
,,
,,
,,
,,
,
,
,
,
,
,
,
,
,
,
,
,
,
,
,
,
,
,,
,,
,,
,,
,,
,,
,,
,,
,,
,,
,,
,,
,,
,,
,,
,,
,,
,
,
,
,
,
,
,
,
,
,
,
,
,
,
,
,
,
,,
,,
,,
,,
,,
,,
,,
,,
,,
,,
,,
,,
,,
,
,
,
,
,
,
,
,
,
,
,
,
,
,
,
,
t
OH
,
,
,
,
t
LZ
t
AC
t
OH
t
AC
t
AC
t
OH
,
,
,
t
OH
t
AC
t
HZ
t
RAS
t
RC
,
,
,
,
,
,
,
,
,
,
,
,
,
,
BA0
t
CKH
t
RP
,,
,,
,,
,,
T0
T1
T2
T3
T4
T5
T6
T7
T8
T9
T10
T11
T12
T13
,,
,,
,,
,
,
,,
,,
,
,
,,
,,
,
,
CLK
CKE
/CS
/RAS
/CAS
/WE
BA1
A10
ADD
DQM
DQ
t
RCD
t
CKS
t
CH
t
CL
t
CK
t
CMS
t
CMH
t
AS
t
AH
L
Hi-Z
Activate
Command
for Bank A
Precharge
Command
for Bank A
Read
Command
for Bank A
Activate
Command
for Bank A
D
a
ta S
heet M14376E
J2V
0
D
S
00
38



PD4564323 for Rev
.
E
AC Parameters for Read Timing (Auto Precharge, Burst Length = 4, /CAS Latency = 3)
,
,
,
,
,
,
,
,
,
,
,
,
,
,
,
,
,
,
,
,
,
,
,
,
,
,
,
,
,
,
,
,
,
,
,
,
,
,
,
,
,
,
,
,
,
,
,
,
,
,
,
,
,
,
,
,
,
,
,
,
,
,
,
,
,
,
,
,
,
,
,
,
,
,
,
,
,
,
,
,
,
,
,
,
,
,
,
,
,
,
,
,
,
,
,
,
,
,
,
,
,
,
,
,
,
,
,
t
OH
,
,
,
,
,
t
LZ
t
AC
t
OH
t
AC
t
AC
t
OH
,
,
,
t
OH
t
AC
t
HZ
t
RAS
t
RRD
t
RC
,
,
,
,
,
,
,
,
,
,
,
,
,
,
BA0
t
CKH
,
,
,
,
,
T0
T1
T2
T3
T4
T5
T6
T7
T8
T9
T10
T11
T12
T13
,
,
,
,
,
,
,
,
,
,
,
CLK
CKE
/CS
/RAS
/CAS
/WE
BA1
A10
ADD
DQM
DQ
t
RCD
t
CKS
t
CH
t
CL
t
CK
t
CMS
t
CMH
t
AS
t
AH
L
Hi-Z
,
,
,
,
,
,
,
,
Auto Precharge
Start for Bank C
Activate
Command
for Bank C
Activate
Command
for Bank D
Read with
Auto Precharge
Command
for Bank C
Activate
Command
for Bank C
D
a
ta S
heet M14376E
J2V
0
D
S
00
39



PD4564323 for Rev
.
E
13.2 AC Parameters for Write Timing (Burst Length = 4, /CAS Latency = 3)
,
,
,
,
,
,
,
,
,
,
,
,
,
,
,
,
,
,
,
,
,
,
,
,
,
,
,
,
,
,
,,
,,
,,
,,
,,
,
,
,
,
,,
,,
,
,
,,
,,
,
,
,
,
,,
,,
,
,
,
,
,
,
,
,
,
,
,
,
,
,
,
,
,
,
,
,
,
,
,
,
,
,
,
,
,
,
,
,
,
,
,
,
,
T0
T1
T2
T3
T4
T5
T6
T7
T8
T9
T10
T11
T12
T13
T14
T15
T16
T17
T18
T19
T20
T21
,
,
,
,
,
,
,
,
,
CLK
CKE
BA0
A10
ADD
DQM
DQ
Hi-Z
t
AS
t
AH
t
DS
t
DH
t
RCD
t
DAL
t
RC
t
RRD
t
RCD
t
RAS
t
RC
t
DPL
t
RP
t
CKH
,
,
t
CMS
t
CMH
t
CKS
/CS
/RAS
/CAS
/WE
,
,
,
,
,
,
,
,
,
,
,
BA1
,
,
Auto Precharge
Start for Bank C
L
,
,
Activate
Command
for Bank C
Activate
Command
for Bank B
Write
Command
for Bank B
Activate
Command
for Bank B
Write with
Auto Precharge
Command
for Bank C
Precharge
Command
for Bank B
Activate
Command
for Bank C
Data Sheet M14376EJ2V0DS00
40



PD4564323 for Rev.
E
13.3 Relationship between Frequency and Latency
Speed version
-A 60
-A 70
-A 80
-A 10
-A 10B
Clock cycle time [ns]
6
10
7
10
8
10
10
13
10
15
Frequency [MHz]
166
100
143
100
125
100
100
77
100
67
/CAS latency
3
2
3
2
3
2
3
2
3
2
[t
RCD
]
3
2
3
2
3
2
2
2
3
2
/RAS latency (/CAS latency + [t
RCD
])
6
4
6
4
6
4
5
4
6
4
[t
RC
]
10
6
9
7
9
7
7
6
9
6
[t
RC1
]
11
7
10
7
9
7
7
6
9
6
[t
RAS
]
7
5
6
5
6
5
5
4
6
4
[t
RRD
]
2
2
2
2
2
2
2
2
2
2
[t
RP
]
3
2
3
2
3
2
2
2
3
2
[t
DPL
]
2
1
2
1
1
1
1
1
1
1
[t
DAL
]
5
3
5
3
4
3
3
3
4
3
[t
RSC
]
2
2
2
2
2
2
2
2
2
2
D
a
ta S
heet M14376E
J2V
0
D
S
00
41



PD4564323 for Rev
.
E
13.4 Mode Register Set (Burst Length = 4, /CAS Latency = 2)
CLK
CKE
/CS
/RAS
/CAS
/WE
BA0
A10
ADD
DQM
DQ
,
,
,
,
,
,
,
,
,
,
,
,
,
,
,
,
,
,
,
,,
,,
,,
,,
,,
,,
,,
,,
,,
,,
,,
,,
,,
,,
,,
,,
,,
,,
,,
,
,
,
,
,
,
,
,
,
,
,
,
,
,
,
,
,
,
,
,,
,,
,,
,,
,
,
,
,,
,,
,
,,
,,
,,
,,
,,
,,
,,
,,
,,
,,
,,
,,
,,
,,
,,
,,
,,
,,
,,
,,
,,
,,
,,
,,
,,
,,
,,
,,
,,
,,
,
,
,
,
,
,
,
,
,
,
,
,
,
,
,,
,,
,,
,,
,,
,,
,,
,,
,,
,,
,,
,,
,,
,,
,,
,,
,,
,,
,
,
,
,
,
,
,
,
,
,
,
,
,
,
,
,
,
,
BA1
T0
T1
T2
T3
T4
T5
T6
T7
T8
T9
T10
T11
T12
T13
T14
T15
T16
T17
T18
T19
T20
T21
Hi-Z
ADDRESS KEY
t
RP
Precharge
All Banks
Command
Mode
Register Set
Command
Activate
Command
is valid
H
t
RSC
2 CLK (MIN.)
D
a
ta S
heet M14376E
J2V
0
D
S
00
42



PD4564323 for Rev
.
E
13.5 Power On Sequence and CBR (Auto) Refresh
CLK
CKE
/CS
/RAS
/CAS
/WE
BA1
A10
ADD
DQM
DQ
,,
,,
,,
,,
,,
,,
,
,
,
,
,,
,,
,,
,,
,,
,,
,
,
,
,
,,
,,
,
,
,
,
,
,
,
,
,
,
,
,
,,
,,
,
,
,,
,,
,,
,,
,,
,,
,,
,,
,,
,,
,,
,,
,,
,,
,
,
,
,
,
,
,
,
,
,
,
,
,
,
,
,
,
,
Hi-Z
t
RSC
ADDRESS KEY
t
RP
,
,
,
,
,
,
,
,,
,,
,,
,,
,,
,,
,,
,,
,,
,,
,
,
,
,
,
,,
,,
,,
,,
,,
,,
,,
,,
,,
,,
,
,
,,
,,
,,
,,
,
,
,
,
,
,
,
,
,
,
High level is necessary
High level is necessary
Clock signal is necessary
2 refresh cycles are necessary
t
RC1
t
RC1
Precharge
All Banks
Command
is necessary
Mode
Register Set
Command
is necessary
CBR(Auto)
Refresh
Command
is necessary
Activate
Command
CBR (Auto) refresh
Command
is necessary
BA0
,
,
,
,
,
,
,
,
,
,
,
,
,
,
,
,
,
,
D
a
ta S
heet M14376E
J2V
0
D
S
00
43



PD4564323 for Rev
.
E
13.6 /CS Function (at 100 MHz, Burst Length = 4, /CAS Latency = 3)
 Only /CS signal needs to be issued at minimum rate
CLK
CKE
/CS
/RAS
/CAS
/WE
BA1
A10
ADD
DQM
DQ
T0
T1
T2
T3
T4
T5
T6
T7
T8
T9
T10
T11
T12
T13
T14
T15
T16
T17
T18
T19
T20
T21
H
L
Hi-Z
L
BA0
L
RAa
QAa1
QAa2
QAa3
QAa4
DAb1
DAb2
DAb3
DAb4
Activate
Command
for Bank A
Read
Command
for Bank A
Write
Command
for Bank A
Precharge
Command
for Bank A
RAa
CAa
CAb
D
a
ta S
heet M14376E
J2V
0
D
S
00
44



PD4564323 for Rev
.
E
13.7 Clock Suspension during Burst Read (using CKE Function) (1/2) (Burst Length = 4, /CAS Latency = 2)
CLK
CKE
/CS
/RAS
/CAS
/WE
BA1
A10
ADD
DQM
DQ
,
,
T0
T1
T2
T3
T4
T5
T6
T7
T8
T9
T10
T11
T12
T13
T14
T15
T16
T17
T18
T19
T20
T21
,,
,,
,
,
,
,
,
,
,,
,,
,,
,,
,,
,,
,,
,,
,,
,,
,,
,,
,,
,,
,,
,,
,,
,,
,,
,,
,,
,,
,,
,,
,,
,,
,,
,,
,,
,,
,,
,,
,
,
,
,
,
,
,
,
,
,
,
,
,
,
,
,
,
QAa1
QAa2
QAa3
QAa4
CAa
,
,
,
,
,
,
,
,
,
,
,
,
,
,
,
,
,
,
,
,
,,
,,
,,
,,
,,
,,
,,
,,
,,
,,
,,
,,
,,
,,
,,
,,
,,
,,
,,
,
,
,
,
,
,
,
,
,
,
,
,
,
,
,
,
,
,
,
,
,
,
,
,
,
,,
,,
,
,
BA0
,,
,,
,,
,,
,,
,,
,,
,,
,,
,,
,,
,,
,,
,,
,,
,,
,,
,,
,,
,,
,,
L
Hi-Z
RAa
RAa
Activate
Command
for Bank A
Read
Command
for Bank A
1-CLOCK
SUSPENDED
2-CLOCK
SUSPENDED
3-CLOCK
SUSPENDED
Hi-Z (turn off)
at the end of burst
D
a
ta S
heet M14376E
J2V
0
D
S
00
45



PD4564323 for Rev
.
E
Clock Suspension during Burst Read (using CKE Function) (2/2) (Burst Length = 4, /CAS Latency = 3)
CLK
CKE
/CS
/RAS
/CAS
/WE
BA1
A10
ADD
DQM
DQ
,
,
T0
T1
T2
T3
T4
T5
T6
T7
T8
T9
T10
T11
T12
T13
T14
T15
T16
T17
T18
T19
T20
T21
,,
,,
,
,
,
,
,,
,,
,,
,,
,,
,,
,,
,,
,,
,,
,,
,,
,,
,,
,,
,,
,,
,,
,,
,,
,,
,,
,,
,,
,,
,,
,,
,,
,,
,,
,
,
,
,
,
,
,
,
,
,
,
,
,
,
,
,
QAa1
QAa2
QAa3
QAa4
CAa
,
,
,
,
,
,
,
,
,
,
,
,
,
,
,
,
,
,
,
,
,
,
,
,
,,
,,
,,
,,
,,
,,
,,
,,
,,
,,
,,
,,
,,
,,
,,
,,
,,
,,
,
,
,
,
,
,
,
,
,
,
,
,
,
,
,
,
,
,
,
,
,
,
,
,
,
,
,,
,,
,
,
BA0
,,
,,
,,
,,
,,
,,
,,
,,
,,
,,
,,
,,
,,
,,
,,
,,
,,
,,
,,
,,
L
Hi-Z
RAa
RAa
Activate
Command
for Bank A
Read
Command
for Bank A
1-CLOCK
SUSPENDED
2-CLOCK
SUSPENDED
3-CLOCK
SUSPENDED
Hi-Z (turn off)
at the end of burst
D
a
ta S
heet M14376E
J2V
0
D
S
00
46



PD4564323 for Rev
.
E
13.8 Clock Suspension during Burst Write (using CKE Function) (1/2) (Burst Length = 4, /CAS Latency = 2)
CLK
CKE
/CS
/RAS
/CAS
/WE
BA1
A10
ADD
DQM
DQ
,
,
T0
T1
T2
T3
T4
T5
T6
T7
T8
T9
T10
T11
T12
T13
T14
T15
T16
T17
T18
T19
T20
T21
,
,
,
,
,
,
,
,
,
,
,
,
,
,
,
,
,
,
,
,
,
,
,
,
,
,
,
,
,
,
,
,
,
,
,
,
,
,
,
,
,
,
,
,
,
,
,
,
,
,
,
,
,
,
CAa
,
,
,
,
,
,
,
,
,
,
,
,
,
,
,
,
,
,
,
,
,
,
,
,
,
,
,
,
,
,
,
,
,
,
,
,
,
,
,
,
,
,
,
,
,
,
BA0
,
,
,
,
,
,
,
,
,
,
,
,
,
,
,
,
,
,
,
,
,
L
Hi-Z
RAa
RAa
,
,
,
,
,
,
,
,
,
,
,
,
,
,
,
,
,
,
,
,
,
,
,
,
,
,
,
,
,
,
,
,
,
,
DAa1
DAa2
DAa3
DAa4
Activate
Command
for Bank A
1-CLOCK
SUSPENDED
2-CLOCK
SUSPENDED
3-CLOCK
SUSPENDED
Write
Command
for Bank A
D
a
ta S
heet M14376E
J2V
0
D
S
00
47



PD4564323 for Rev
.
E
Clock Suspension during Burst Write (using CKE Function) (2/2) (Burst Length = 4, /CAS Latency = 3)
CLK
CKE
/CS
/RAS
/CAS
/WE
BA1
A10
ADD
DQM
DQ
,
,
T0
T1
T2
T3
T4
T5
T6
T7
T8
T9
T10
T11
T12
T13
T14
T15
T16
T17
T18
T19
T20
T21
,,
,,
,
,
,
,
,,
,,
,,
,,
,,
,,
,,
,,
,,
,,
,,
,,
,,
,,
,,
,,
,,
,,
,,
,,
,,
,,
,,
,,
,,
,,
,,
,,
,,
,,
,
,
,
,
,
,
,
,
,
,
,
,
,
,
,
,
CAa
,
,
,
,
,
,
,
,
,
,
,
,
,
,
,
,
,
,
,
,
,,
,,
,,
,,
,,
,,
,,
,,
,,
,,
,,
,,
,,
,,
,,
,,
,,
,,
,
,
,
,
,
,
,
,
,,
,,
,
,
BA0
,,
,,
,,
,,
,,
,,
,,
,,
,,
,,
,,
,,
,,
,,
,,
,,
,,
,,
,,
,,
L
Hi-Z
RAa
RAa
,
,
,
,
,
,
,
,
,
,
,
,
,
,
,
,
,
,
,
,
,
,
,,
,,
,,
,,
,,
,,
,,
,,
,,
,,
DAa1
DAa2
DAa3
DAa4
Activate
Command
for Bank A
1-CLOCK
SUSPENDED
2-CLOCK
SUSPENDED
3-CLOCK
SUSPENDED
Write
Command
for Bank A
D
a
ta S
heet M14376E
J2V
0
D
S
00
48



PD4564323 for Rev
.
E
13.9 Power Down Mode and Clock Mask (Burst Length = 4, /CAS Latency = 2)
CLK
CKE
/CS
/RAS
/CAS
/WE
BA1
A10
ADD
DQM
DQ
,
,
T0
T1
T2
T3
T4
T5
T6
T7
T8
T9
T10
T11
T12
T13
T14
T15
T16
T17
T18
T19
T20
T21
,
,
,
,
,
,
,
,,
,,
,,
,,
,,
,,
,,
,,
,,
,,
,,
,,
,,
,,
,,
,
,
,
,
QAa3
CAa
,
,
,
,
,
,
,
,
,
,
,
,
,
,
,
,
,
,
,
,
,
,
,
,
,
,
,
,
,
,
,
,
,
,,
,,
L
Hi-Z
RAa
RAa
,
,
,
,
,
,
,
,
,
,
,
,
,
,
,
,
,
,
,
,
,
,
,
,
,
,
,
,
,
,
,
,
,
,
,
,
,
BA0
,
,
,
,
,
,
,
,
,
,
,
,
,
,
,
,
,
,
,
,
,
,
,
,
,
,
,
t
CKSP
t
CKSP
QAa1 QAa2
VALID
Activate
Command
for Bank A
Power Down
Mode Entry
ACTIVE STANDBY
Power Down
Mode Exit
Read
Command
for Bank A
Clock Mask
Start
Clock Mask
End
Power Down
Mode Entry
Precharge
Command
for Bank A
PRECHARGE STANDBY
Power Down
Mode Exit
QAa4
,
,
,
,
,
,
,
,
,
,
,
,
,
,
,
,
,
,
,
,
,
D
a
ta S
heet M14376E
J2V
0
D
S
00
49



PD4564323 for Rev
.
E
13.10 CBR (Auto) Refresh
CLK
CKE
/CS
/RAS
/CAS
/WE
BA1
ADD
DQM
DQ
T0
T1
T2
T3
T4
T5
T6
Tn
Tn
+
1 Tn
+
2
Tn
+
3 Tn
+
4
Tn
+
5 Tn
+
6
Tm
Tm
+
1 Tm
+
2 Tm
+
3 Tm
+
4 Tm
+
5 Tm
+
6 Tm
+
7
,,
,,
,,
,,
,,
,,
,,
,,
,,
,,
,,
,,
,,
,,
,,
,,
,,
,,
,,
,,
,,
,,
,,
,,
,,
,,
,,
,,
,,
,,
,,
,,
,,
,,
,,
,,
,,
,,
BA0
,,
,,
,,
,,
,,
,,
,,
,,
,,
,,
,,
,,
,,
,,
,,
,,
,,
,,
,,
,
,
,
,
,
,
,
,
,
,
,
,
,
,
,
,
,
,
,
,
,
,
,
,
,
,
,
,
,,
,,
,
,
,
,,
,,
,,
,,
,,
,,
,
,
,
,
,
,,
,,
,,
,,
,,
,,
,,
,,
,
,
,
,
,
,
,
,
,
,
,
,
,
,
,
,
,
,
,
,
,
,
,
,
,,
,,
,,
,,
,,
,
,
L
Hi-Z
t
RP
H
t
RC1
t
RC1
Q1
Precharge
Command
(if necessary)
CBR (Auto)
Refresh
CBR(Auto)
Refresh
Activate
Command
Read
Command
,
,
,
A10
,
,
,
,
,
,
,
,
,
,
,
,
,
,
,
,
,
,
,
D
a
ta S
heet M14376E
J2V
0
D
S
00
50



PD4564323 for Rev
.
E
13.11 Self Refresh (Entry and Exit)
CLK
CKE
/CS
/RAS
/CAS
/WE
BA1
ADD
DQM
DQ
,
,
,,
,,
,,
,,
,
,
,
,
,,
,,
,,
,,
,
,
,
,
,
,
,
,
,
,
,
,
,
,
,
,
,
,
,
,
T0
T1
T2
T3
T4
Tn
Tn
+
1 Tn
+
2
Tm
Tm
+
1
Tk
Tk
+
1
Tk
+
2 Tk
+
3
Tk
+
4
t
RP
,
,
,
,
,
,
,,
,,
,,
,,
,,
,,
,
,
,
,
,
,,
,,
,,
,,
,,
,,
,,
,,
,,
,,
,,
,
,
,
,,
,,
,,
,,
,,
,,
,
,
,
,
,
,
,
,
,
,
,
t
RC1
t
RC1
,,
,,
,,
,,
,,
,,
,
,
,
,
,
,
,
,
,
,
,
,
,
,
,
,
,
,
,
,
,
,
BA0
,
,
,
,
,
,
,
,
,
,
,
,
,
,
,
,
,
Precharge
Command
(if necessary)
Self Refresh
Entry
Self Refresh
Exit
Next Clock
Enable
Self Refresh
Entry
(or Activate Command)
Activate
Command
Self Refresh
Exit
Next Clock
Enable
L
Hi-Z
A10
,,
,,
,,
,,
,,
,,
,,
,,
,,
,,
,,
,,
,,
,,
,,
,,
,,
D
a
ta S
heet M14376E
J2V
0
D
S
00
51



PD4564323 for Rev
.
E
13.12 Random Column Read (Page with Same Bank) (1/2) (Burst Length = 4, /CAS Latency = 2)
CLK
CKE
/CS
/RAS
/CAS
/WE
BA1
A10
ADD
DQM
DQ
,,
,,
T0
T1
T2
T3
T4
T5
T6
T7
T8
T9
T10
T11
T12
T13
T14
T15
T16
T17
T18
T19
T20
T21
,
,
,
,
,
,
,
,
,
,
,
,
,
,
,
,
,
,
,
,
,
,
,
,
,
,
,
,
,
,
,
,
,
,
,
,
,
,
,,
,,
,,
,
,
,
,,
,,
,,
,
,
,,
,,
,
,
,
,
,,
,,
,,
,,
QAa1
QAa2
,
,
,
,
,
,
,
,
,
,
,
,
,
,
,
,
,
,
,
,
,
,
,
,
,
,
,
,
,
,,
,,
,
,
,
,
,,
,,
,,
,,
,
,
,
,
,
,
,
,,
,,
,,
,
,
,
,
,
,
,,
,,
,,
,
,
,,
,,
,,
QAa3
QAa4
QAb1
QAb2
QAc1
QAc2
QAc3
QAc4
QAd1
QAd2
QAd3
,
,
,
,
,
,
,
,
,
H
RAd
RAa
CAd
CAc
CAa
RAd
CAb
,,
,,
,
,
,
,
,
,
,
,
BA0
,
,
,
,
,
,
,
,
,
,
,
,
,
,
,
,
,
,
,
,
,
,
,
,
,
,
,
,
,
,
,
,
,
,
,
,,
,,
,
,
,
,
,,
,,
,,
,,
,,
,,
,
,
,
,
,
,
,
,
,
,
,
,
RAa
Precharge
Command
for Bank A
Activate
Command
for Bank A
Read
Command
for Bank A
Read
Command
for Bank A
Read
Command
for Bank A
Activate
Command
for Bank A
Read
Command
for Bank A
L
Hi-Z
D
a
ta S
heet M14376E
J2V
0
D
S
00
52



PD4564323 for Rev
.
E
Random Column Read (Page with Same Bank) (2/2) (Burst Length = 4, /CAS Latency = 3)
CLK
CKE
/CS
/RAS
/CAS
/WE
BA1
A10
ADD
DQM
DQ
Precharge
Command
for Bank A
Activate
Command
for Bank A
Read
Command
for Bank A
Read
Command
for Bank A
Read
Command
for Bank A
Activate
Command
for Bank A
Read
Command
for Bank A
T0
T1
T2
T3
T4
T5
T6
T7
T8
T9
T10
T11
T12
T13
T14
T15
T16
T17
T18
T19
T20
T21
,
,
,
,
,
,
,
,
,
,
,
,
,
,
,
,
,
,
,
,
,
,
,
,
,
,
,
,
,
,
,
,
,
,
,
,
,
,
,
,
,
,
,
,
,
,
,
,
,
,
,
,
,
,
,
,
,
,
,
QAa1
QAa2
,
,
,
,
,
,
,
,
,
,
,
,
,
,
,
,
,
,
,
,
,
,
,
,
,
,
,
,
,
,
,
,
,
,
,
,
,
,
,
,
,
,
,
,
,
,
,
,
,
,
,
,
,
,
,
,
,
,
,
QAa3
QAa4
QAb1
QAb2
QAc1
QAc2
QAc3
QAc4
,
,
,
,
,
,
,
,
,
,
H
RAa
RAa
CAa
CAc
CAa
RAa
CAb
,
,
,
,
,
,
,
,
,
,
,
,
,
BA0
,
,
,
,
,
,
,
,
,
,
,
,
,
,
,
,
,
,
,
,
,
,
,
,
,
,
,
,
,
,
,
,
,
,
,
,
,
,
,
,
,
,
,
,
,
,
,
,
,
,
,
,
,
,
,
,
,
,
,
,
,
,
,
,
,
RAa
,
,
L
Hi-Z
D
a
ta S
heet M14376E
J2V
0
D
S
00
53



PD4564323 for Rev
.
E
13.13 Random Column Write (Page with Same Bank) (1/2) (Burst Length = 4, /CAS Latency = 2)
CLK
CKE
/CS
/RAS
/CAS
/WE
BA1
A10
ADD
DQM
DQ
,,
,,
T0
T1
T2
T3
T4
T5
T6
T7
T8
T9
T10
T11
T12
T13
T14
T15
T16
T17
T18
T19
T20
T21
,
,
,
,
,
,
,
,
,
,
,
,
,
,
,
,
,
,
,
,
,
,
,
,
,
,
,
,
,
,
,
,,
,,
,
,
,
,,
,,
,,
,
,
,
,,
,,
,,
,,
L
Hi-Z
,
,,
,
,
,
,
,,
,,
,,
,,
DDa1
DDa2
,
,
,
,
,
,
,
,
,
,
,
,
,
,
,
,
,
,,
,,
,,
,
,
,
,
,
,
,,
,,
,
,
,
,
,,
,,
,,
,,
,,
,,
,,
,
,
,
,
,
,
,,
,,
,,
,
,
,,
,,
,,
DDa3
DDa4
DDb1
DDb2
DDc1
DDc2
DDc3
DDc4
DDd1
DDd2
DDd3
,
,
,
,
,
,
,
,
,
H
RDd
RDa
CDd
CDc
CDa
RDd
CDb
,,
,,
,
,
,
,
,
,
BA0
,
,
,
,
,
,
,
,
,
,
,
,
,
,
,
,
,
,
,
,
,
,
,
,
,
,
,
,
,
,
,
,
,,
,,
,,
,,
,
,
,,
,,
,,
,,
,,
,,
,
,
,
,
,
,
,
,
,
,
,
,
RDa
,
,
,,
,,
,,
,,
,,
,,
,,
,,
,,
,,
,,
DDd4
Activate
Command
for Bank D
Write
Command
for Bank D
Write
Command
for Bank D
Write
Command
for Bank D
Precharge
Command
for Bank D
Activate
Command
for Bank D
Write
Command
for Bank D
D
a
ta S
heet M14376E
J2V
0
D
S
00
54



PD4564323 for Rev
.
E
Random Column Write (Page with Same Bank) (2/2) (Burst Length = 4, /CAS Latency = 3)
CLK
CKE
/CS
/RAS
/CAS
/WE
BA1
A10
ADD
DQM
DQ
,
,
T0
T1
T2
T3
T4
T5
T6
T7
T8
T9
T10
T11
T12
T13
T14
T15
T16
T17
T18
T19
T20
T21
,
,
,
,
,
,
,
,
,
,
,
,
,
,
,
,
,
,
,
,
,
,
,
,
,
,
,
,
,
,
,
,
,
,
,
,
,
,
,
,
,
,
,
,
,
,
,
,
L
Hi-Z
,
,
,
,
,
,
,
,
DDa1
DDa2
,
,
,
,
,
,
,
,
,
,
,
,
,
,
,
,
,
,
,
,
,
,
,
,
,
,
,
,
,
,
,
,
,
,
,
,
,
,
,
,
,
,
,
,
,
,
,
,
,
,
,
,
,
DDa3
DDa4
DDb1
DDb2
DDc1
DDc2
DDc3
DDc4
,
,
,
,
,
,
,
,
,
H
RDd
RDa
CDd
CDc
CDa
RDd
CDb
,
,
,
,
,
,
,
,
,
,
,
BA0
,
,
,
,
,
,
,
,
,
,
,
,
,
,
,
,
,
,
,
,
,
,
,
,
,
,
,
,
,
,
,
,
,
,
,
,
,
,
,
,
,
,
,
,
,
,
,
,
,
,
,
,
,
,
,
,
,
,
,
,
,
,
RDa
DDd1
,
,
,
,
,
,
,
,
,
,
,
,
,
Activate
Command
for Bank D
Write
Command
for Bank D
Write
Command
for Bank D
Write
Command
for Bank D
Precharge
Command
for Bank D
Activate
Command
for Bank D
Write
Command
for Bank D
DDd2
D
a
ta S
heet M14376E
J2V
0
D
S
00
55



PD4564323 for Rev
.
E
13.14 Random Row Read (Ping-Pong Banks) (1/2) (Burst Length = 8, /CAS Latency = 2)
CLK
CKE
/CS
/RAS
/CAS
/WE
BA1
A10
ADD
DQM
DQ
,
,
T0
T1
T2
T3
T4
T5
T6
T7
T8
T9
T10
T11
T12
T13
T14
T15
T16
T17
T18
T19
T20
T21
,
,
,
,
,
,
,
,
,
,
,
,
,
,
,
,
,
,
,
,
,
,
,
,
,
,
,
,
,
,
,
,
,
,
,
,
,
,
,
,
,
,
,
,
,
,
,
,
L
Hi-Z
,
,
,
,
,
,
QDa1 QDa2
,
,
,
,
,
,
,
,
,
,
,
,
,
,
,
,
,
,
,
,
,
,
,
,
,
,
,
,
,
,
QDa3 QDa4
QDa5 QDa6
QDa7 QDa8
QBa1
QBa2
QBa3
QBa4
QBa5
H
RDb
RDa
CDb
CBa
CDa
RDb
RBa
,
,
,
,
,
,
,
,
,
,
,
,
,
,
,
,
,
,
,
,
,
,
,
,
,
RDa
,
,
,
,
,
,
,
,
,
,
,
,
,
,
,
,
,
,
,
,
,
,
,
,
,
,
,
,
,
BA0
,
,
,
,
,
,
,
,
,
,
,
,
,
,
,
,
,
,
,
,
,
,
,
,
,
,
,
,
,
,
RBa
,
,
,
,
,
,
QBa6
QBa7
QBa8
Activate
Command
for Bank D
Read
Command
for Bank D
Activate
Command
for Bank B
Read
Command
for Bank B
Precharge
Command
for Bank D
Activate
Command
for Bank D
Read
Command
for Bank D
D
a
ta S
heet M14376E
J2V
0
D
S
00
56



PD4564323 for Rev
.
E
Random Row Read (Ping-Pong Banks) (2/2) (Burst Length = 8, /CAS Latency = 3)
CLK
CKE
/CS
/RAS
/CAS
/WE
BA0
A10
ADD
DQM
DQ
,,
,,
T0
T1
T2
T3
T4
T5
T6
T7
T8
T9
T10
T11
T12
T13
T14
T15
T16
T17
T18
T19
T20
T21
,
,
,
,
,
,
,
,
,
,
,
,
,
,
,
,
,
,
,
,
,
,
,
,
,
,
,
,
,,
,,
,
,
,
,,
,,
,,
,,
,
,
,
,
,,
,,
,,
,,
,,
L
Hi-Z
,
,
,
QBa1
QBa2
,
,
,
,
,
,
,
,
,
,
,
,
,
,
,
,
,
,,
,,
,,
,,
,
,
,
,,
,,
QBa3
QBa4
QBa5
QBa6
QBa7
QBa8
QAa1
QAa2
QAa3
QAa4
QAa5
H
RBb
RBa
CBb
CAa
CBa
RBb
RAa
,,
,,
,,
,
,
,
,
,
,
,
,,
,,
,,
,,
,,
,,
,,
,,
,
,
,
,
,
RBa
,
,,
,,
,,
,,
,,
,,
,,
,,
,,
,,
,,
,
,
,
,
,
,
,
,
,
,
,
,
,,
,,
,
,
,
,
,
,
,
,
RAa
,,
,,
,,
,,
,,
,,
,,
QAa6
QAa7
,
,
,,
,,
,
,
,,
,,
,,
,,
,,
,,
,,
,,
,
,
,,
,,
,
,
,
,
,,
,,
,
,
,
,,
,,
,,
,,
,,
,,
,
,
,
,,
,,
,,
,,
,,
,,
,,
,,
,
,
BA1
Activate
Command
for Bank B
Read
Command
for Bank B
Activate
Command
for Bank A
Read
Command
for Bank A
Precharge
Command
for Bank B
Activate
Command
for Bank B
Read
Command
for Bank B
Precharge
Command
for Bank A
,,
,,
,,
,,
D
a
ta S
heet M14376E
J2V
0
D
S
00
57



PD4564323 for Rev
.
E
13.15 Random Row Write (Ping-Pong Banks) (1/2) (Burst Length = 8, /CAS Latency = 2)
CLK
CKE
/CS
/RAS
/CAS
/WE
BA1
A10
ADD
DQM
DQ
,
T0
T1
T2
T3
T4
T5
T6
T7
T8
T9
T10
T11
T12
T13
T14
T15
T16
T17
T18
T19
T20
T21
,,
,
,
,
,
,,
,,
,,
,,
,,
,,
,,
,,
,,
,,
,,
,,
,,
,,
,,
,,
,,
,
,
,,
,
,
,
,
,
,
,
,
,
,
,,
,,
,,
,,
,,
,
,
,
L
Hi-Z
,
,
DAa5
DAa6
,
,
,
,
,
,
,
,
,
,
,
,
,
,
,
,
,
,
,
,
,
,
,,
,,
DAa7
DAa8
DDa1
DDa2
DDa3
DDa4
DDa5
DDa6
DDa7
DDa8
DAb1
H
RAa
CAb
CDa
CAa
RDa
,
,
,,
,,
,,
,,
,,
,,
,
RAa
,
,
,
,
,
,
,
,
,
,,
,,
,,
,,
,,
,,
,,
,,
,,
,
,
RDa
,
,
,
,
,
,
,
DAb2
DAb3
,,
,,
,
,
,,
,,
,
,
,
,
,
,
,
,
,
,
,
,
,
,,
,,
,
,
,
,
,,
,,
,,
,,
,,
,,
BA0
,,
,
,
,
,
,,
,,
,,
,,
,,
,,
,,
,,
,,
,
,
,,
,,
,,
,,
,,
,,
,,
,,
,
,
,
RAb
RAb
,
,
,
,
,
,
DAa1
DAa2
DAa3
DAa4
Activate
Command
for Bank A
Write
Command
for Bank A
Write
Command
for Bank D
Activate
Command
for Bank D
Precharge
Command
for Bank A
Activate
Command
for Bank A
Write
Command
for Bank A
Precharge
Command
for Bank D
D
a
ta S
heet M14376E
J2V
0
D
S
00
58



PD4564323 for Rev
.
E
Random Row Write (Ping-Pong Banks) (2/2) (Burst Length = 8, /CAS Latency = 3)
CLK
CKE
/CS
/RAS
/CAS
/WE
BA1
A10
ADD
DQM
DQ
,
,
T0
T1
T2
T3
T4
T5
T6
T7
T8
T9
T10
T11
T12
T13
T14
T15
T16
T17
T18
T19
T20
T21
,,
,,
,
,
,
,
,
,,
,,
,
,
,
,
,
,
,
,
,
,,
,,
,,
,,
,
,
,
,
,
DAa3
DAa4
,
,
,
,
,
,
,
,
,
,
,
,
,
,
,
,
,
,
,
,
,
,,
,,
,,
,,
,,
,,
DAa5
DAa6
DAa7
DAa8
DDa1
DDa2
DDa3
DDa5
DDa6
DDa7
H
RAa
CAb
CDa
RDa
,
,
,
,,
,,
,,
,,
,,
,
,
,
,
RAa
,
,
,
,
,
,
,
,
,
,,
,,
,,
,,
,,
,,
,,
,,
,,
,,
,
,
RDa
,
,
,
,
,
,
,
DDa8
DAb1
DAb2
,
,
,,
,,
,,
,,
,,
,,
,
,
,
,
,
,
,
,
,
,
,,
,,
,,
,,
,,
,,
,,
,,
,,
,,
,,
,,
,
,
,,
,,
,,
,,
,
,
,
,
,,
,,
,,
,,
,
,
,
,
,
RAb
,
,
,
,
DAa1
DAa2
,
,
BA0
,,
,,
,
,
,
,,
,,
,,
,,
,,
,,
,,
,,
,,
,,
,
,
,,
,,
,,
,,
,
,
CAa
,
,
,,
,,
,,
,,
,,
,,
,,
,,
,,
,,
,,
RAb
,,
,,
,,
,,
Activate
Command
for Bank A
Write
Command
for Bank A
Write
Command
for Bank D
Activate
Command
for Bank D
Precharge
Command
for Bank A
Activate
Command
for Bank A
Precharge
Command
for Bank D
Write
Command
for Bank A
L
Hi-Z
DDa4
D
a
ta S
heet M14376E
J2V
0
D
S
00
59



PD4564323 for Rev
.
E
13.16 Read and Write (1/2) (Burst Length = 4, /CAS Latency = 2)
CLK
CKE
/CS
/RAS
/CAS
/WE
BA1
A10
ADD
DQM
DQ
Activate
Command
for Bank A
Read
Command
for Bank A
Write
Command
for Bank A
0-Clock Latency
2-Clock Latency
Read
Command
for Bank A
,,
,,
T0
T1
T2
T3
T4
T5
T6
T7
T8
T9
T10
T11
T12
T13
T14
T15
T16
T17
T18
T19
T20
T21
,
,
,
,
,
,
,
,
,
,
,
,
,,
,,
,,
,,
,,
,
,
,
,
,
,,
,
,
,
,
,
,
,,
,,
,,
,,
,,
,,
QAa1
QAa2
,
,
,
,
,
,
,
,
,,
,,
,,
,
,
,
,
,
,
,,
,,
,,
,,
,,
,,
,
,
,
,
,
,
,
,
,
,
,
,
,,
,,
,,
,,
,,
,,
,,
,,
,
,
QAa3
QAa4
DAb1
DAb2
QAc1
QAc2
QAc4
,
,
,
,
,
,
H
RAa
CAc
CAb
,
,
,
,
,
DAb4
,
,
BA0
,
,
,
,
,
,
,
,
,
,
,
,
,
,
,
,
,
,
,
,
,
,
,
,
,
,
,,
,,
,
,
,,
,,
CAa
,
Write Latency = 0
RAa
,
,
,
,
,
,
,
,
,
,
,
,
,
,
Word Masking
L
Hi-Z
Hi-Z at the end of wrap function
D
a
ta S
heet M14376E
J2V
0
D
S
00
60



PD4564323 for Rev
.
E
Read and Write (2/2) (Burst Length = 4, /CAS Latency = 3)
CLK
CKE
/CS
/RAS
/CAS
/WE
BA1
A10
ADD
DQM
DQ
,,
,,
T0
T1
T2
T3
T4
T5
T6
T7
T8
T9
T10
T11
T12
T13
T14
T15
T16
T17
T18
T19
T20
T21
,
,
,
,
,
,
,
,
,
,
,
,
,
,
,,
,,
,,
,,
,,
,,
,
,
,
,
,
,
,,
,
,
,
,
,
,,
,,
,,
,,
,,
QAa1
QAa2
,
,
,
,
,
,
,
,
,
,
,
,
,
,
,
,
,
,
,
,
,
,
,
,
,
,
,,
,,
,,
,
,
,
,
,
,,
,,
,,
,,
,,
,
,
,
,
,
,
,
,
,
,
,
,,
,,
,,
,,
,,
,,
,,
,,
,,
,
,
,
QAa3
QAa4
DAb1
DAb2
QAc1
QAc2
,
,
H
RAa
CAc
CAb
,
,
,
,
,
,
DAb4
,
,
,
,
,
,
,,
,,
,,
,
,
,
,,
,,
,,
CAa
,
,
,
,
,
,
,
,
,
,
,
,
,
,
,
RAa
,
,
,
BA0
,
,
,
,
,
,
,
,
,
,
,
,
,
,
,
,
,
,
,
,
,
,
,
,
,
Activate
Command
for Bank A
Read
Command
for Bank A
Write
Command
for Bank A
0-Clock Latency
Read
Command
for Bank A
Word Masking
Write Latency = 0
L
Hi-Z
Hi-Z at the end of wrap function
2-Clock Latency
D
a
ta S
heet M14376E
J2V
0
D
S
00
61



PD4564323 for Rev
.
E
13.17 Interleaved Column Read Cycle (1/2) (Burst Length = 4, /CAS Latency = 2)
CLK
CKE
/CS
/RAS
/CAS
/WE
BA1
A10
ADD
DQM
DQ
,
,
T0
T1
T2
T3
T4
T5
T6
T7
T8
T9
T10
T11
T12
T13
T14
T15
T16
T17
T18
T19
T20
T21
,,
,,
,,
,,
,
,
,
,
,
,
L
Hi-Z
,
,
,
,
,
,
Aa1
Aa2
,
,
,,
,,
,
,
,
,
,
,
,
,
,
,
,
,
,
,
Aa3
Aa4
Da1
Da2
Dc1
Dc2
Dd1
Dd2
Dd3
Dd4
,
,
H
RAa
RDa
,,
,,
,,
,,
,
,
,,
,,
,
,
,
,,
,,
,
,
,,
,,
,
,
,,
,,
,
,
,
,
,
,
,
,,
,,
,,
,,
,
,
,
,
,
,
,
,
,,
,,
,
,
,,
,,
,,
,,
,,
,,
,,
,,
,
,
,
,
,
,
,
,
,
,
,
,
,,
,,
,
,
,
,
,
,
,
,
,
,
,
,
,
,
Ab1
Ab2
Db1
Db2
,
,,
,
,
,,
,,
BA0
,,
,,
,,
,,
,,
,,
,
,
,
,,
,,
,,
,,
,
,
,
,,
,,
,,
,,
,,
,,
,,
,
,
,
,,
,,
,,
RAa
,
RDa
CAa
,
,
CDa
CDb
CDc
CAb
,
,
,
,
,
,
,
CDd
,,
,,
,
,
,,
,
Activate
Command
for Bank A
Activate
Command
for bank D
Read
Command
for Bank D
Read
Command
for Bank D
Read
Command
for Bank D
Read
Command
for Bank A
Read
Command
for Bank D
Precharge
Command
for Bank A
Precharge
Command
for Bank D
Read
Command
for Bank A
D
a
ta S
heet M14376E
J2V
0
D
S
00
62



PD4564323 for Rev
.
E
Interleaved Column Read Cycle (2/2) (Burst Length = 4, /CAS Latency = 3)
CLK
CKE
/CS
/RAS
/CAS
/WE
BA1
A10
ADD
DQM
DQ
,
,
T0
T1
T2
T3
T4
T5
T6
T7
T8
T9
T10
T11
T12
T13
T14
T15
T16
T17
T18
T19
T20
T21
,,
,,
,,
,,
,
,
,
,
,
,
L
Hi-Z
,
,
,
,
,
,
,
,
Aa1
Aa2
,
,
,
,
,
,
,
,
,
,
,
,
,
,
,
,
,
,,
,
,
,
,
,
,
Aa3
Aa4
Da1
Da2
Dc1
Dc2
Ab3
Ab4
,
,
,
,
H
,,
,,
,,
,
,
,,
,,
,
,
,,
,,
,
,
,
,
,
,,
,,
,,
,
,
,
,
,
,
,
,
,
,,
,,
,
,
,,
,,
,,
,,
,,
,,
,
,
,
,
,
,
,
,
,
,
,,
,,
,
,
,
,
,
,
,
,
,
,
,
Ab1
Ab2
Db1
Db2
,
,
,
,,
,,
,
,
,,
,,
RAa
,
,
RDa
,,
,,
,
,
,,
,,
,,
,
,
,
,,
,,
,,
BA0
,,
,,
,,
,,
,,
,,
,,
,
,
,
,,
,,
,,
,,
,
,
,
,
,,
,,
,,
,,
,,
,,
,,
,,
,,
,,
,,
,,
,,
,,
,,
,,
,,
,,
,,
,,
,,
,,
,,
,,
RAa
CAb
CDc
RDa
CDa
CAa
Activate
Command
for Bank A
Activate
Command
for Bank D
Read
Command
for Bank D
Read
Command
for Bank D
Read
Command
for Bank D
Read
Command
for Bank A
Precharge
Command
for Bank D
Precharge
Command
for Bank A
Read
Command
for Bank A
CDb
D
a
ta S
heet M14376E
J2V
0
D
S
00
63



PD4564323 for Rev
.
E
13.18 Interleaved Column Write Cycle (1/2) (Burst Length = 4, /CAS Latency = 2)
CLK
CKE
/CS
/RAS
/CAS
/WE
BA0
A10
ADD
DQM
DQ
,
,
T0
T1
T2
T3
T4
T5
T6
T7
T8
T9
T10
T11
T12
T13
T14
T15
T16
T17
T18
T19
T20
T21
,
,
,
,
,
,
,
,
,
,
,
,
,
,
,
L
Hi-Z
,
,
,
,
,
,
,
,
Aa1
Aa2
,
,
,
,
,
,
,
,
,
,
,
,
,
,
,
,
,
,
,
,
,
,
,
,
,
,
,
,
,
,
,
,
,
,
Aa3
Aa4
Ba1
Ba2
Bc1
Bc2
Bd1
Bd2
Bd3
Bd4
,
,
H
RAa
RBa
,
,
,
,
,
,
,
,
,
,
,
,
,
,
,
,
,
,
,
,
,
,
,
,
,
,
,
,
,
,
,
,
,
,
,
,
,
,
,
,
,
,
,
,
,
,
,
,
,
,
,
,
,
,
,
,
,
,
,
,
,
,
,
,
Ab1
Ab2
Bb1
Bb2
,
,
,
,
RAa
,
,
RBa
CAa
,
,
CBa
CBb
CBc
CAb
,
,
,
,
,
,
,
,
CBd
,
,
,
,
,
,
,
,
,
,
,
,
,
,
,
,
,
,
,
,
,
,
,
,
,
,
BA1
,
,
,
,
,
,
,
,
,
,
,
,
,
,
,
,
,
,
,
,
,
,
,
Activate
Command
for Bank A
Write
Command
for Bank A
Activate
Command
for Bank B
Write
Command
for Bank B
Write
Command
for Bank A
Precharge
Command
for Bank A
Precharge
Command
for Bank B
Write
Command
for Bank B
Write
Command
for Bank B
Write
Command
for Bank B
t
DPL
t
DPL
D
a
ta S
heet M14376E
J2V
0
D
S
00
64



PD4564323 for Rev
.
E
Interleaved Column Write Cycle (2/2) (Burst Length = 4, /CAS Latency = 3)
CLK
CKE
/CS
/RAS
/CAS
/WE
BA0
A10
ADD
DQM
DQ
,
,
T0
T1
T2
T3
T4
T5
T6
T7
T8
T9
T10
T11
T12
T13
T14
T15
T16
T17
T18
T19
T20
T21
,,
,,
,,
,,
,
,
,
,
,
L
Hi-Z
,
,
Aa1
Aa2
,
,
,
,
,
,
,
,
,
,
,
,
,
,
,
,
,
,,
,,
,
,
,
,
,
,
Aa3
Aa4
Ba1
Ba2
Bc1
Bc2
Bd1
Bd2
,
,
H
,,
,,
,,
,,
,
,
,,
,,
,,
,,
,
,
,
,
,
,
,
,
,
,
,,
,,
,
,
,,
,,
,
,
,,
,,
,
,
,
,
Ab1
Ab2
Bb1
Bb2
,,
,,
,,
,,
,,
RAa
,
,
,
RBa
,,
,,
,,
,
,
,
,,
,,
,,
,
,
,
,,
,,
,,
,,
,,
,,
,,
,,
,,
,,
,,
,,
,,
,,
,,
,,
,,
RAa
CAb
CBc
RBa
CBa
CBb
CAa
,,
,,
,
,
,
,
,
,
,
,
,,
,,
,
,
,
,
,
,
,
,
,
,
,
,
,
,
,
,
,
,
,
,
,
CBd
Bd3
Bd4
Activate
Command
for Bank A
Write
Command
for Bank A
Activate
Command
for Bank B
Write
Command
for Bank B
Write
Command
for Bank A
Precharge
Command
for Bank A
Precharge
Command
for Bank B
Write
Command
for Bank B
Write
Command
for Bank B
Write
Command
for Bank B
,,
,,
BA1
,,
,,
,
,
,
,
,
,
,
,
,
,
,
,
,
,
,
,
,
,
,
,
,
,
,,
,,
,
,
,
,,
,,
,,
,
,
,
,
,
,
D
a
ta S
heet M14376E
J2V
0
D
S
00
65



PD4564323 for Rev
.
E
13.19 Auto Precharge after Read Burst (1/2) (Burst Length = 4, /CAS Latency = 2)
CLK
CKE
/CS
/RAS
/CAS
/WE
BA0
A10
ADD
DQM
DQ
,
,
T0
T1
T2
T3
T4
T5
T6
T7
T8
T9
T10
T11
T12
T13
T14
T15
T16
T17
T18
T19
T20
T21
,,
,,
,
,
,
,
,
,
,
,
,
,
,
L
,
,
,
,
,
,
,
,
,
,
,
,
,
,
,
,
,
,
,
,
,
,
,
,
,
,
,
,
H
,,
,
,,
,,
,,
,,
,
,
,
,,
,,
,
,
,
,
,
,
,
,
,
,,
,,
,
,
,
,
,
,,
,,
,
,
,,
,,
,
,
,
,
,
,
,
,
,
,
,
,
,
,
,,
,,
,,
,,
,,
,,
,
,,
,,
,,
,,
,,
,,
,,
,,
,,
,,
,,
,,
,,
,,
,,
,,
,,
,,
,
,
,
,
,
,,
,,
,,
,
,
BA1
,,
,,
,
,
,
,,
,,
,,
,,
,,
,
,
,
,,
,,
,
,
,
,,
,,
,,
,,
,,
,,
,,
,,
,,
,,
,,
,,
,
,
,
,
,
,
,
,
,
,
,
,
,
,
,
,
RDb
,
,
,
RAc
,
,
,
,
,
,
RDa
,
,
,
RAa
,,
,,
,,
,,
,,
,,
,,
,,
,,
,,
,,
,,
,,
,,
,,
,,
,,
RAa
CAb
CAa
RDb
CDa
RDa
CAc
CDb
RAc
Hi-Z
Activate
Command
for Bank A
Activate
Command
for Bank D
Read
Command
for Bank A
Read with
Auto Precharge
Command
for Bank D
Read with
Auto Precharge
Command
for Bank A
Auto Precharge
Start for Bank D
Read with
Auto Precharge
Command
for Bank D
Auto Precharge
Start for Bank A
Auto Precharge
Start for Bank D
Activate
Command
for Bank A
Read with
Auto Precharge
Command
for Bank A
Activate
Command
for Bank D
D
a
ta S
heet M14376E
J2V
0
D
S
00
66



PD4564323 for Rev
.
E
Auto Precharge after Read Burst (2/2) (Burst Length = 4, /CAS Latency = 3)
CLK
CKE
/CS
/RAS
/CAS
/WE
BA0
A10
ADD
DQM
DQ
,,
,,
T0
T1
T2
T3
T4
T5
T6
T7
T8
T9
T10
T11
T12
T13
T14
T15
T16
T17
T18
T19
T20
T21
,
,
,
,
L
,
,
,
,
,
,
,
,
,
,
,
,
,
,
,
,
,
,
,
,
,,
,,
,,
H
,
,
,
,
,
,
,
,
,
,
,
,
,
,
,
,
,
,
,
,
,
,
,,
,,
,,
,,
,,
,,
,,
,,
,,
,,
,,
,,
,,
,,
,
,
,
,
,
,
,
,
,
,
,
,
,
,
,
,
,
,
,
,
,
,
,
,
,
,
,
,
,
,
,
,
,
,
,
,
,
,
,
,
RDb
,
,
,
,
,
,
,
,
,
,
,
,
RAa
,
,
,
,
,
,
,
,
,
,
,
,
,
,
,
,
,
RAa
CAb
CAa
RDb
CDa
RDa
CDb
Hi-Z
,
,
,
,
,
BA1
,
,
,
,
,
,
,
,
,
,
,
,
,
,
,
,
,
,
,
,
,
,
,
,
RDa
Activate
Command
for Bank A
Activate
Command
for Bank D
Read
Command
for Bank A
Read with
Auto Precharge
Command
for Bank D
Activate
Command
for Bank D
Read with
Auto Precharge
Command
for Bank A
Auto Precharge
Start for Bank A
Read with
Auto Precharge
Command
for Bank D
Auto Precharge
Start for Bank D
D
a
ta S
heet M14376E
J2V
0
D
S
00
67



PD4564323 for Rev
.
E
13.20 Auto Precharge after Write Burst (1/2) (Burst Length = 4, /CAS Latency = 2)
CLK
CKE
/CS
/RAS
/CAS
/WE
BA0
A10
ADD
DQM
DQ
Activate
Command
for Bank A
Write
Command
for Bank A
Activate
Command
for Bank D
Activate
Command
for Bank D
Write with
Auto Precharge
Command
for Bank D
Write with
Auto Precharge
Command
for Bank D
Write with
Auto Precharge
Command
for Bank A
Auto Precharge
Start for Bank D
Auto Precharge
Start for Bank A
Auto Precharge
Start for Bank D
Activate
Command
for Bank A
Write with
Auto Precharge
Command
for Bank A
,
,
T0
T1
T2
T3
T4
T5
T6
T7
T8
T9
T10
T11
T12
T13
T14
T15
T16
T17
T18
T19
T20
T21
,,
,,
,
,
,
,
L
,
,
,
,
,
,
,
,
,
,
,
,
,
,
,
,
,
,
,
,
,
,
H
,,
,
,,
,,
,,
,,
,
,
,
,,
,,
,
,
,
,,
,,
,,
,,
,,
,,
,
,
,
,
,
,
,
,
,
,
,
,
,
,
,,
,,
,,
,,
,,
,,
,
,,
,,
,,
,,
,,
,,
,,
,,
,,
,,
,,
,,
,,
,,
,,
,,
,,
,,
,,
,,
,,
,
,
,
,
,
,
,
,
,
,
,
,
,
,
,
RDb
,
,
,
RAc
,
,
,
,
,
,
RDa
,
,
,
RAa
,,
,,
,,
,,
,,
,,
,,
,,
,,
,,
,,
,,
,,
,,
,,
,,
,,
RAa
CAb
CAa
RDb
CDa
RDa
CAc
CDb
RAc
,
,
BA1
,,
,,
,
,
,
,
,,
,,
,,
,,
,,
,
,
,
,,
,,
,
,
,
,,
,,
,,
,,
,,
,,
,,
,,
,,
,,
,,
,,
,
,
,
,
,
,
,
,
,
,
,
,
,
,
,
,
,
,
,
,
,
,
Hi-Z
D
a
ta S
heet M14376E
J2V
0
D
S
00
68



PD4564323 for Rev
.
E
Auto Precharge after Write Burst (2/2) (Burst Length = 4, /CAS Latency = 3)
CLK
CKE
/CS
/RAS
/CAS
/WE
BA0
A10
ADD
DQM
DQ
,
,
T0
T1
T2
T3
T4
T5
T6
T7
T8
T9
T10
T11
T12
T13
T14
T15
T16
T17
T18
T19
T20
T21
,,
,,
L
,
,
,
,
,
,
,
,
,
,
,
,
,
,
,
,
,
,
,
,
,
H
,,
,,
,,
,,
,,
,,
,,
,,
,,
,,
,,
,,
,,
,,
,
,
,
,
,
,
,
,
,
,
,
,
,
,
,
,,
,,
,,
,,
,,
,,
,,
,,
,,
,,
,,
,,
,,
,,
,,
,,
,,
,,
,,
,,
,,
,,
,,
,,
,
,
,
,
,
,
,
,
,
,
,
,
,
,
,
,
RDb
,
,
,
,
,
,
,
,
,
,
RAa
,
,
,
,
,
,
,
,
,
,
,
,
,
,
,
,
,
RAa
CAb
CAa
RDb
CDa
RDa
CDb
,,
,,
,,
,
RDa
,
,
BA1
,,
,,
,,
,,
,,
,,
,,
,,
,,
,,
,,
,,
,,
,,
,,
,,
,,
,,
,,
,
,
,,
,,
,,
,
,
,
,
,
,
,
,
,
,
,
,
,
,
,
,
,
,
,
,
Hi-Z
Activate
Command
for Bank A
Write
Command
for Bank A
Activate
Command
for Bank D
Write with
Auto Precharge
Command
for Bank D
Write with
Auto Precharge
Command
for Bank A
Auto Precharge
Start for Bank D
Auto Precharge
Start for Bank A
Activate
Command
for bank D
Write with
Auto Precharge
Command
for Bank D
D
a
ta S
heet M14376E
J2V
0
D
S
00
69



PD4564323 for Rev
.
E
,
,
,
,
,,
,,
,,
,,
,,
,,
,,
,,
,,
,,
,,
,,
,,
,,
,,
,,
13.21 Full Page Read Cycle (1/2) (/CAS Latency = 2)
CLK
CKE
/CS
/RAS
/CAS
/WE
BA0
A10
ADD
DQM
DQ
,
,
T0
T1
T2
T3
T4
T5
T7
Tn
Tn
+
1
Tn
+
2 Tn
+
3
Tn
+
4 Tn
+
5
Tn
+
6 Tn
+
7 Tn
+
8 Tn
+
9 Tn
+
10 Tn
+
11 Tn
+
12 Tn
+
13
,
,
,
,
,
,
,
,
,
,
,
,
,
,
,
,
,
,
,
,
,
,
,
,
,
,
,
,
,
,
,
,
,
,
,
,
,
H
,
,
,
,
,
,
,
,
,
,
,
,
,
,
,
,
,
,
,
,
,
,
,
,
,
,
,
,
,
,
,
,
,
,
,
,
,
,
,
,
,
,
,
,
,
,
,
,
RAa
RDa
,
,
,
,
,
,
,
,
,
,
,
,
,
,
,
,
,
,
,
,
,
,
,
,
,
,
,
,
,
,
RDb
,
,
,
,
,
,
,
,
,
,
,
,
,
,
,
,
,
RAa
RDa
CDa
CAa
RDb
Aa
Aa+1
Aa+2
Aa-2
Aa-1
Aa
Aa+1
Da
Da+1
Da+2
Da+3
Da+4
Da+5
Da+6
Activate
Command
for Bank A
Read
Command
for Bank A
Activate
Command
for Bank D
Read
Command
for Bank D
Burst Stop Command
Precharge
Command
for Bank D
Activate
Command
for Bank D
T6
BA1
,
,
,
,
,
,
,
,
,
,
,
,
,
,
,
,
,
,
,
,
,
,
,
,
,
,
,
,
,
L
Hi-Z
,
,
D
a
ta S
heet M14376E
J2V
0
D
S
00
70



PD4564323 for Rev
.
E
,,
,,
,,
,,
,,
,,
,,
,,
,,
,,
Full Page Read Cycle (2/2) (/CAS latency = 3)
CLK
CKE
/CS
/RAS
/CAS
/WE
BA0
A10
ADD
DQM
,,
,,
,,
,,
DQ
,
,
T0
T1
T2
T3
T4
T5
T6
T7
T8
Tn
Tn
+
1 Tn
+
2
Tn
+
3 Tn
+
4
Tn
+
5 Tn
+
6 Tn
+
7 Tn
+
8
Tn
+
9 Tn
+
10 Tn
+
11 Tn
+
12
,
,
,
,
,
,
L
,
,
,
,
,
,
,
,
,
,
,
,
,
,
,
,
,
,
,
,
,
H
,
,
,
,
,
,
,
,
,
,
,
,
,
,
,
,
,
,
,
,
,
,
,
,
,
,
,
,
,
,
,
,
,
,
,
,
,
RAa
RDa
,
,
,
,
,
,
,
,
,
,
,
,
,
,
,
,
,
,
,
,
,
,
,
RDb
,
,
,
,
,
,
,
,
,
,
,
,
,
,
,
,
,
RAa
RDa
CDa
CAa
RDb
Aa
Aa+1
Aa-3
Aa-2
Aa-1
Aa
Aa+1
Da
Da+1
Da+2
Da+3
Da+4
Da+5
Precharge
Command
for Bank D
Activate
Command
for Bank A
Read
Command
for Bank A
Activate
Command
for Bank D
Read
Command
for Bank D
Burst Stop Command
Activate
Command
for Bank D
Hi-Z
BA1
,
,
,
,
,
,
,
,
,
,
,
,
,
,
,
,
,
,
D
a
ta S
heet M14376E
J2V
0
D
S
00
71



PD4564323 for Rev
.
E
,,
,,
,,
,,
,,
,,
,,
,,
,,
,,
,,
,,
,,
,,
,,
,,
13.22 Full Page Write Cycle (1/2) (/CAS latency = 2)
CLK
CKE
/CS
/RAS
/CAS
/WE
BA0
A10
ADD
DQM
DQ
,
,
T0
T1
T2
T3
T4
T5
Tn
Tn
+
1 Tn
+
2 Tn
+
3
Tn
+
4 Tn
+
5
Tn
+
6 Tn
+
7
Tn
+
8 Tn
+
9 Tn
+
10 Tn
+
11 Tn
+
12 Tn
+
13 Tn
+
14 Tn
+
15
,,
,,
,
,
,
,,
,,
,
,
,
,
,
,
,
,
,
,
,
,
,
,
,
,
,
,
,
,
,
,
,
H
,,
,,
,,
,,
,
,
,
,
,
,
,
,,
,,
,,
,,
,,
,,
,,
,,
,,
,,
,,
,
,
,
,
,
,
,
,
,,
,,
,
,
,,
,,
,,
,,
,,
RAa
RDa
,,
,
,,
,,
,,
,,
,
,
,
,
,
,
,
,
,
,
,
,,
,,
,,
,,
,,
,,
,,
RDb
,,
,,
,,
,,
,,
,,
,,
,,
,,
,,
,,
,,
,,
,,
,,
,,
,,
RAa
RDa
CDa
CAa
RDb
Aa
Aa+1
Aa+2
Aa-2
Aa-1
Aa
Aa+1
Da
Da+1
Da+2
Da+3
Da+4
Da+5
,
,
,
,
,
,
,
BA1
,,
,,
,
,
,
,,
,,
,,
,,
,,
,,
,,
,,
,,
,,
,,
,,
,,
,,
,,
,
,
,,
,,
Precharge
Command
for Bank D
Activate
Command
for Bank A
Write
Command
for Bank A
Activate
Command
for Bank D
Write
Command
for Bank D
Burst Stop Command
Activate
Command
for Bank D
L
Hi-Z
D
a
ta S
heet M14376E
J2V
0
D
S
00
72



PD4564323 for Rev
.
E
,,
,,
,,
,,
,,
,,
,,
,,
,,
,,
,,
,,
,,
,,
Full Page Write Cycle (2/2) (/CAS Latency = 3)
CLK
CKE
/CS
/RAS
/CAS
/WE
BA0
A10
ADD
DQM
DQ
,
,
T0
T1
T2
T3
T4
T5
T6
T7
Tn
Tn
+
1
Tn
+
2 Tn
+
3
Tn
+
4 Tn
+
5
Tn
+
6 Tn
+
7 Tn
+
8 Tn
+
9 Tn
+
10 Tn
+
11 Tn
+
12 Tn
+
13
,
,
,
,
,
,
,
,
,
,
,
,
,
,
,
,
,
,
,
,
,
,
,
,
,
,
,
H
,
,
,
,
,
,
,
,
,
,
,
,
,
,
,
,
,
,
,
,
,
,
,
,
,
,
,
,
,
,
,
,
,
,
,
,
,
,
,
,
,
RAa
RDa
,
,
,
,
,
,
,
,
,
,
,
,
,
,
,
,
,
,
,
,
,
,
,
,
,
,
RDb
,
,
,
,
,
,
,
,
,
,
,
,
,
,
,
,
,
RAa
RDa
CDa
CAa
RDb
Aa
Aa+1
Aa+2
Aa+3
Aa-1
Aa
Aa+1
Da
Da+1
Da+2
Da+3
Da+4
Da+5
,
,
,
,
,
,
,
,
,
Precharge
Command
for Bank D
Activate
Command
for Bank A
Write
Command
for Bank A
Activate
Command
for Bank D
Burst is not completed
in the Full Page Mode
Write
Command
for Bank D
Burst Stop Command
Activate
Command
for Bank D
BA1
,
,
,
,
,
,
,
,
,
,
,
,
,
,
,
,
,
,
,
,
,
,
L
Hi-Z
D
a
ta S
heet M14376E
J2V
0
D
S
00
73



PD4564323 for Rev
.
E
,
,
,
,
,
,
,
,
,
,
,
,
,
,
,
,
,
,
,
,
,
,
,
,
,
,
,
,
,
,
,
,
,
,
13.23 Byte Write Operation (Burst Length = 4, /CAS Latency = 2)
CLK
CKE
/CS
/RAS
/CAS
/WE
BA0
A10
ADD
DQM0
,
T0
T1
T2
T3
T4
T5
T6
T7
T8
T9
T10
T11
T12
T13
T14
T15
T16
T17
T18
T19
T20
T21
,
,
,
,
,
,
,
,
,
,
,
,
,
DQM1
,
,
,
,
,
,
,
BA1
DQ 0-7
DQ 8-15
Activate
Command
for Bank D
Read
Command
for Bank D
,,
,,
,,
,
,
,
,
,
,
,
,
,
,
,
,
,
,
,
,
,
,
,
,
,
,
,
,
,
,
,
,
,
,
,
,
,
,
,
,
,
,
,
,
,
,
,
,
,
,
,
,
,
,
,
,
,
,
,
,
,
,
,
,
,
,
,
,
,
,
,
,
,
,
,
,
,
,
,
,
,
,
,
,
,,
,,
,,
,,
,,
,,
,,
,,
,
,
,
,
,
,
,
,
,
,
,
,
,
,
,
,
,
,
,
,
,
,
,
,
,
,
,
,
,
,
,
,
,
,
,
Byte 1
not Read
Byte 0
not Write
Byte 1
not Write
Byte 0
not Write
D
a
ta S
heet M14376E
J2V
0
D
S
00
74



PD4564323 for Rev
.
E
13.24 Burst Read and Single Write (Option) (Burst Length = 4, /CAS Latency = 2)
CLK
CKE
/CS
/RAS
/CAS
/WE
BA0
A10
ADD
DQM
,
,
T0
T1
T2
T3
T4
T5
T6
T7
T8
T9
T10
T11
T12
T13
T14
T15
T16
T17
T18
T19
T20
T21
,
,
,
,
,
,
,
,
,
,
,
,
,
,
,
,
,
,
,
,
,
,
,
,
,
,
,
,
,
,
H
Hi-Z
,
,
,
,
,
,
,
,
,
,
,
,
,
,
,
,
,
,
,
,
,
,
,
,
,
,
,
,
,
,
,
,
,
,
,
,
,
DQ
,
,
,
,
,
,
,
,
,
,
,
,
,
,
,
,
,
,
,
,
,
,
,
,
,
,
,
,
,
,
,
,
,
,
,
,
,
,
,
,
,
,
BA1
,
,
,
,
,
,
,
,
,
,
,
,
,
,
,
,
,
,
,
,
,
,
,
,
,
,
,
,
,
,
,
,
,
,
,
,
,
,
Activate
Command
for Bank D
Read
Command
for Bank D
Single
Write
Command
for Bank D
Single
Write
Command
for Bank D
Read
Command
for Bank D
Single
Write
Command
for Bank D
,
,
Qa1
Qa2
Qa3
Qa4
D1
Qb1
Qb2
Qb4
D2
D
a
ta S
heet M14376E
J2V
0
D
S
00
75



PD4564323 for Rev
.
E
13.25 Full Page Random Column Read (Burst Length = Full Page, /CAS Latency = 2)
CLK
CKE
/CS
/RAS
/CAS
/WE
BA0
A10
ADD
DQM
DQ
,
,
T0
T1
T2
T3
T4
T5
T6
T7
T8
T9
T10
T11
T12
T13
T14
T15
T16
T17
T18
T19
T20
T21
,
,
,
,
,
,
,
,
L
,
,
,
,
,
,
,
,
,
,
,
,
,
,
,
,
,
,
,
,
,
,
,
,
,
,
,
,
,
,
,
,
,
,
,
,
,
,
,
,
,
,
,
H
,
,
,
,
,
,
,
,
,
,
,
,
,
,
,
,
,
,
,
,
,
,
,
,
,
,
,
,
,
,
,
,
,
,
,
,
,
Hi-Z
,
,
,
,
,
,
,
,
,
,
,
,
,
,
,
,
,
,
,
,
,
,
,
,
,
,
,
,
,
,
,
,
,
,
,
,
,
RAa
CAc
CDb
CAb
RDa
,
,
RDa
CDc
RAa
,
,
,
,
,
,
,
,
,
,
,
,
,
,
,
,
,
BA1
,
,
,
,
,
,
,
,
,
,
,
,
,
,
,
,
,
,
,
,
,
,
,
CAa
CDa
QAa1
QDa1
QAb1
QAb2
QDb1
QDb2
QAc1
QAc2
QAc3
QDc1
QDc2
QDc3
Activate
Command
for Bank A
Activate
Command
for Bank D
Read
Command
for Bank A
Read
Command
for Bank D
Read
Command
for Bank A
Read
Command
for Bank D
Read
Command
for Bank A
Read
Command
for Bank D
Precharge
Command
for Bank D
(PRE Termination of Burst)
Hi-Z
t
RCD
t
RRD
t
RCD
D
a
ta S
heet M14376E
J2V
0
D
S
00
76



PD4564323 for Rev
.
E
13.26 Full Page Random Column Write (Burst Length = Full Page, /CAS Latency = 2)
CLK
CKE
/CS
/RAS
/CAS
/WE
BA0
A10
ADD
DQM
DQ
,
T0
T1
T2
T3
T4
T5
T6
T7
T8
T9
T10
T11
T12
T13
T14
T15
T16
T17
T18
T19
T20
T21
,
,
,
,
L
,
,
,
,
,
,
,
,
,
,
,
,
,
,
,
,
,
,
,
,
,
,
,
,
,
,
,
,
,
,
,
,
H
,
,
,
,
,
,
,
,
,
,
,
,
,
,
,
,
,
,
,
,
,
,
,
,
,
,
,
,
Hi-Z
,
,
,
,
,
,
,
,
,
,
,
,
,
,
,
,
,
,
,
,
,
,
,
,
,
RAa
CAc
CDb
CAb
RDa
,
RDa
CDc
RAa
,
,
,
,
,
,
,
,
,
,
,
,
BA1
,
,
,
,
,
,
,
,
,
,
,
,
,
,
,
,
CAa
CDa
DAa1
DDa1
DAb1
DAb2
DDb1
DDb2
DAc1
DAc2
DAc3
DDc1
DDc2
DDc3
,
,
,
,
,
,
,
,
,
,
,
,
,
,
,
DDc4
Precharge
Command
for Bank D
(PRE Termination of Burst)
Activate
Command
for Bank A
Activate
Command
for Bank D
Write
Command
for Bank A
Write
Command
for Bank D
Write
Command
for Bank A
Write
Command
for Bank D
Write
Command
for Bank A
Write
Command
for Bank D
t
RCD
t
RRD
t
RCD
D
a
ta S
heet M14376E
J2V
0
D
S
00
77



PD4564323 for Rev
.
E
,,
,,
,,
,,
,,
,,
,,
,,
,,
,,
,,
,,
13.27 PRE (Precharge) Termination of Burst (1/2) (Burst Length = 8, /CAS Latency = 2)
CLK
CKE
/CS
/RAS
/CAS
/WE
BA0
A10
ADD
DQM
DQ
,
,
T0
T1
T2
T3
T4
T5
T6
T7
T8
T9
T10
T11
T12
T13
T14
T15
T16
T17
T18
T19
T20
T21
,
,
L
,
,
,
,
,
,
,
,
,
,
,
,
,
,
,
,
,
H
,
,
,
,
,
,
,
,
,
,
,
,
,
,
,
,
,
,
,
,
,
,
,
,
,
,
,
,
,
,
,
,
,
,
,
,
,
,
,
,
,
,
,
,
,
,
,
,
,
,
,
,
,
,
,
,
,
,
,
,
,
,
,
,
,
,
,
,
,
,
BA1
,
,
,
,
,
,
,
,
,
,
,
,
,
,
,
,
,
,
,
,
,
,
,
,
,
,
,
Hi-Z
,
,
,
,
,
,
,
,
,
,
,
,
,
,
,
,
,
RAa
RAb
CAa
RAa
RAb
CAb
DAa1
DAa2
DAa3
DAa4
DAa5
QAb1
QAb2
QAb3
QAb4
QAb5
Activate
Command
for Bank A
Activate
Command
for Bank A
Write
Command
for Bank A
PRE Termination
of Burst
PRE Termination
of Burst
Precharge
Command
for Bank A
Activate
Command
for Bank A
Read
Command
for Bank A
Precharge
Command
for Bank A
Hi-Z
Write
Masking
,
,
,
,
,
RAc
RAc
t
RCD
t
DPL
t
RP
t
RAS
t
RAS
D
a
ta S
heet M14376E
J2V
0
D
S
00
78



PD4564323 for Rev
.
E
,,
,,
,,
,,
,,
,,
,,
,,
,,
,,
,,
,,
PRE (Precharge) Termination of Burst (2/2) (Burst Length = 8, /CAS Latency = 3)
CLK
CKE
/CS
/RAS
/CAS
/WE
BA0
A10
ADD
DQM
DQ
,,
,,
T0
T1
T2
T3
T4
T5
T6
T7
T8
T9
T10
T11
T12
T13
T14
T15
T16
T17
T18
T19
T20
T21
,
,
L
Hi-Z
,
,
,
,
,
,
,
,
,
,
,
,
,
,
,
,
,
H
,
,
,
,,
,,
,,
,,
,,
,,
,,
,,
,,
,,
,,
,
,
,
,
,
,
,
,
,
,
,
,
,
,,
,,
,,
,,
,,
,,
,,
,,
,,
,,
,,
,
,
,
,
,
,
,
,
,
,,
,,
,,
,
,
,
,
,
BA1
,
,
,
,
,
,
,
,
,
,
,
,
,
,
,
,
,,
,,
,,
,,
,,
,,
,
,
,
,
,
,
,
,
,
,
,
,
,
,
,
,
,
RAa
RAb
CAa
RAa
RAb
CAb
DAa1
DAa2
DAa3
QAb1 QAb2
QAb3
QAb4
Hi-Z
Activate
Command
for Bank A
Activate
Command
for Bank A
Write
Command
for Bank A
PRE Termination
of Burst
Precharge
Command
for Bank A
Precharge
Command
for Bank A
Activate
Command
for Bank A
Read
Command
for Bank A
PRE Termination
of Burst
,,
,,
,,
,,
,,
,,
DAa4
DAa5
Write
Mask
,,
,,
,,
,,
,
,
,
,
,,
,,
,,
,
,
,
,
,
,
,
,
RAc
RAc
,,
,,
t
RCD
t
RP
t
RAS
t
DPL
t
RAS
Data Sheet M14376EJ2V0DS00
79



PD4564323 for Rev.
E
14. Package Drawing
M
P
C
N
S
B
M
D
L
K
J
L
S
G
E
F
detail of lead end
NOTES
1. Each lead centerline is located within 0.08 mm of
its true position (T.P.) at maximum material condition.
R
86
44
1
43
S
H
I
2. Dimension "A" does not include mold flash, protrusions or gate
burrs. Mold flash, protrusions or gate burrs shall not exceed
0.15mm per side.
A
ITEM
B
C
I
86-PIN PLASTIC TSOP (
II
) (10.16 mm (400))
A
D
E
F
G
H
J
K
L
MILLIMETERS
0.5 (T.P.)
0.765 MAX.
10.16
0.10
22.22
0.05
0.10
0.05
0.22
1.1
0.1
11.76
0.20
1.00
+
0.08
-
0.07
0.80
0.20
0.145
+
0.025
-
0.015
0.50
0.08
M
P
R
3
+
5
-
3
0.25
0.60
0.15
S
0.10
N
S86G5-50-9JH-1
5
Data Sheet M14376EJ2V0DS00
80



PD4564323 for Rev.
E
15. Recommended Soldering Condition
Please consult with our sales offices for soldering conditions of the
PD4564323.
Type of Surface Mount Device
PD4564323G5: 86-pin Plastic TSOP (II) (10.16 mm (400))
16. Revision History
Edition /
Page
Description
Date
This
edition
Previous
edition
Type of
revision
Location
1st edition /
June 1999
2nd edition /
p.2
p.2
Deletion
PD4564323G5-A60L-9JH, 4564323G5-A70L-9JH, 4564323G5-A80L-9JH,
December 1999
PD4564323G5-A10L-9JH, 4564323G5-A10BL-9JH
p.3
p.3
Deletion
L (Low Power)
p.33
p.33
Deletion
I
CC6
(-AxxL (Maximum))
p.34
p.34
Modification
Test Conditions
p.79
p.79
Modification
Package Drawing
Data Sheet M14376EJ2V0DS00
81



PD4564323 for Rev.
E
[MEMO]
Data Sheet M14376EJ2V0DS00
82



PD4564323 for Rev.
E
[MEMO]
Data Sheet M14376EJ2V0DS00
83



PD4564323 for Rev.
E
NOTES FOR CMOS DEVICES
1
PRECAUTION AGAINST ESD FOR SEMICONDUCTORS
Note:
Strong electric field, when exposed to a MOS device, can cause destruction of the gate oxide and
ultimately degrade the device operation. Steps must be taken to stop generation of static electricity
as much as possible, and quickly dissipate it once, when it has occurred. Environmental control
must be adequate. When it is dry, humidifier should be used. It is recommended to avoid using
insulators that easily build static electricity. Semiconductor devices must be stored and transported
in an anti-static container, static shielding bag or conductive material. All test and measurement
tools including work bench and floor should be grounded. The operator should be grounded using
wrist strap. Semiconductor devices must not be touched with bare hands. Similar precautions need
to be taken for PW boards with semiconductor devices on it.
2
HANDLING OF UNUSED INPUT PINS FOR CMOS
Note:
No connection for CMOS device inputs can be cause of malfunction. If no connection is provided
to the input pins, it is possible that an internal input level may be generated due to noise, etc., hence
causing malfunction. CMOS devices behave differently than Bipolar or NMOS devices. Input levels
of CMOS devices must be fixed high or low by using a pull-up or pull-down circuitry. Each unused
pin should be connected to V
DD
or GND with a resistor, if it is considered to have a possibility of
being an output pin. All handling related to the unused pins must be judged device by device and
related specifications governing the devices.
3
STATUS BEFORE INITIALIZATION OF MOS DEVICES
Note:
Power-on does not necessarily define initial status of MOS device. Production process of MOS
does not define the initial operation status of the device. Immediately after the power source is
turned ON, the devices with reset function have not yet been initialized. Hence, power-on does
not guarantee out-pin levels, I/O settings or contents of registers. Device is not initialized until the
reset signal is received. Reset operation must be executed immediately after power-on for devices
having reset function.



PD4564323 for Rev.
E
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M7 98. 8