Revision 3.0

Subject to Change Without Notice

NL84620

4Kx64

(256K)

SyncCAM-1

Synchronous Content Addressable Memory (SyncCAM

)

Description

The NL84620 is a 256K bit Synchronous Content Addressable Memory (SyncCAM

). The device performs high-speed parallel

search operations on memory tables while simultaneously capturing and manipulating data from a data stream. Its primary
application is as an address filter or an address translator for Fast Ethernet, Gigabit Ethernet, and ATM switches.

Features

Match Flag times: 18/21/28 ns

CAM Index output (flow through mode): 21/25/33 ns

CAM Index output (pipelined mode): 10/12/16 ns

Sustained searches of up to 40 Million/Second

Separate 64-bit Comparand I/O bus, 64-bit Results bus
and 14-bit Instruction bus

Two validity bits (Skip and Empty) for each location
define the location as Valid, Skip, Empty or RAM

Four 64-bit wide Mask Registers for easy masking of
compare or write operations

14-bit instruction bus enables single cycle execution
of all instructions

Depth-expansion with no glue logic required

3.3V TTL compatible CMOS, 292-pin PBGA Package

Cont

r
o

l L

ogic

Address
Counter

Instruction Bus

Clock

Cascade In (Up & Down)

Reset

Chip Enable

Match Flag In (Up & Down)

System Match Flag

4K x 64

CAM Array

Global Mask Registers 0, 1, 2 & 3

Data Translation Register

Status Register 0 (SR0)

Status Register 1 (SR1)

Memory Configuration Register

RBUS

Comparand Bus

CBUS

Word Enables

Multiple Match Flag

Full Flag Input

Match Flag Out (Up & Down)

lidity

i
ts

Comparand Register

Results Bus

Multiple Match Flag Input

Cascade Out (Up & Down)

Full Flag

Instruction Error

Figure 1 NL84620 Block Diagram

Revision 3.0

Subject to Change Without Notice

NL84620

CBUS50

CBUS51

CBUS54

CBUS56

CBUS59

CBUS61

CBUS62

(NC)

RBUS62

RBUS61

RBUS59

RBUS56

RBUS54

RBUS51

RBUS50

CBUS49

CBUS48

CBUS53

CBUS55

CBUS57

CBUS60

CBUS63

(NC)

RBUS60

RBUS57

RBUS55

RBUS53

RBUS48

RBUS49

CBUS47

CBUS46

CBUS52

GND

CBUS58

VDD

(NC)

VDD

(NC)

VDD

RBUS63

RBUS58

GND

RBUS52

RBUS46

RBUS47

CBUS43

CBUS44

GND

VDD

GND

VDD

GND

VDD

GND

RBUS44

RBUS43

CBUS42

CBUS41

CBUS45

GND

RBUS45

RBUS41

RBUS42

CBUS37

CBUS38

CBUS40

VDD

RBUS40

RBUS38

RBUS37

CBUS35

CBUS36

VDD

RBUS36

RBUS35

CBUS32

CBUS34

CBUS39

GND

RBUS39

RBUS34

RBUS32

CBUS30

CBUS31

CBUS33

GND

RBUS33

RBUS31

RBUS30

CBUS27

CBUS28

CBUS29

VDD

GND

VDD

RBUS29

RBUS28

RBUS27

CBUS25

CBUS26

VDD

GND

VDD

RBUS26

RBUS25

CBUS24

CBUS22

CBUS23

GND

RBUS23

RBUS22

RBUS24

CBUS21

CBUS20

CBUS19

GND

RBUS19

RBUS20

RBUS21

CBUS18

CBUS17

CBUS16

VDD

RBUS16

RBUS17

RBUS18

CBUS15

CBUS14

VDD

RBUS14

RBUS15

CBUS12

CBUS11

CBUS13

GND

RBUS13

RBUS11

RBUS12

CBUS10

CBUS08

CBUS09

GND

VDD

GND

VDD

GND

VDD

GND

RBUS09

RBUS08

RBUS10

CBUS06

CBUS07

GND

/RST

IBUS01

IBUS05

VDD

IBUS10

IBUS13

/WEN3

VDD

/MFUI

CSCDI

/MFUO

VDD

(NC)

/IERR

GND

RBUS06

RBUS07

CBUS04

CBUS05

CBUS03

IBUS00

IBUS03

IBUS06

IBUS08

IBUS11

CLK

/WEN2

/WEN0

/MMFI

/MFDI

CSCUO

/MFDO

/SMF

/FF

RBUS01

RBUS03

RBUS05

CBUS02

CBUS01

CBUS00

IBUS02

IBUS04

IBUS07

IBUS09

IBUS12

/CE

GND

/WEN1

/FFI

CSCUI

(NC)

CSCDO

(NC)

/MMF

RBUS00

RBUS02

RBUS04

Figure 2 NL84620 Ball Assignment (292 PBGA, Top view)

Revision 3.0

Subject to Change Without Notice

NL84620

1.0 Functional Description

The NL84620 is a Synchronous Content Addressable
Memory (SyncCAM) designed for use as an address filter or
an address translator in 100/1000 Mb/s Ethernet and ATM
switches and routers. This device can also be used to
implement fast routing tables in Internet Protocol (IP)
switches. The NL84620 has a total associative memory
capacity of 256K bits organized as 4K x 64 bits.

A bi-directional 64-bit Comparand Bus (CBUS) enables all
internal registers and memory to be accessed. An output
only, 64-bit Results Bus (RBUS) provides status information
after a compare operation. A 14-bit Instruction Bus (IBUS)
allows instructions to be presented to the device once every
cycle. All operations on the device are timed synchronously
with the rising edge of a free running clock. This
architecture permits back-to-back compare cycles to be
executed without any bus latencies.

The Comparand Register (CR) is a 64-bit register that
enables one to write the comparand data (key) and compare
it with the contents of memory. This is the only register that
enables a user to store and compare data with memory.

The NL84620 has four Global Mask Registers (GMR3-
GMR0) that can each be selected on an operation-by-
operation basis for write or compare operations. For a write
operation, when the bits in these registers are programmed
with `1's, the corresponding bits in memory will be masked,
i.e. will not be written into. For compare operations, the
corresponding bits in the associative data word will be
forced to a match.

The 16-bit Device Configuration Register (DCR) enables the
user to configure the device operation. The user can
configure the RBUS to be in pipeline or flow through mode,
RBUS output to be in Status Register 0 (SR0) or Status
Register 1 (SR1) format, address counter to be incremented
automatically during write and so on. See Table 3d for a
complete list.

The Memory Configuration Register (MCR) is a 64-bit wide
register used as a mask during Compare instruction cycles.
It provides compare masking capability in addition to the
global masks. This memory configuration register is always
used during comparison as opposed to the global mask
registers, which may or may not be selected during
comparison. After reset, all bits are `0' indicating no
masking of any bits during comparison.

The Data Translation Register (DTR) is a 64-bit register that
allows manipulation of data stored in it.

Status Registers SR0 and SR1 hold status information after
compare, read, write or copy operations.

A 12-bit Address Counter (ACR) supplies the address to the
memory array. This counter may be loaded with any valid
start address and can be configured to increment once every

cycle for read or write operations. This allows data to be
loaded into or read out of the memory continuously.

Four Word Enable (/WEN3-/WEN0) inputs allow access to
the internal registers and memory on 16-bit boundaries.
These inputs also allow

for bus matching on the comparand

bus with no glue logic.

The NL84620 can be clocked up to frequencies of 40MHz
with a free running clock. A Chip Enable (/CE) input allows
the device to be selected or deselected similar to any
memory device. The device has flag inputs and outputs that
enable depth cascading with no glue logic. The Instruction
Error pin (/IERR) asserts an active low when erroneous
Opcodes are presented to the device.

2.0 Pin Description

2.1 Clock (CLK):
This is a free running clock that is used to time all
transactions on the CAM. The rising edge of the clock is the
timing reference.

2.2 Chip Enable (/CE):
This is a synchronous input that selects the device for all
operations, when asserted Low. When asserted High, the
device is deselected and is in idle mode. In idle mode, the
CBUS and the RBUS are high-z. For single device
operation, when the device is deselected (/CE asserted High)
the Match, Multiple Match and System Match Flags are
High and Full Flag is Low. For depth cascaded devices, the
deselected devices will pass the flag input states through to
the flag outputs. When /CE is taken from a "1" to a "0" (idle
to active), a NOP is necessary for the device (and the devices
in the cascade chain, if applicable) to be activated. See
Table 1.

2.3 Reset (/RST):
This is an asynchronous input and provides the hardware
reset for the device. During initialization, this pin must be
asserted low for a minimum of three (3) cycles. This will set
all CAM words to empty, initialize the control logic, and
clear all registers. The reset operation must be followed by at
least one NOP instruction. Table 2 and Tables 3a-g illustrate
the state of the part after reset.

2.4 Full Flag Input (/FFI):
This input is provided for depth cascading multiple CAMs.
When asserted low, this pin will allow data to be written into
the CAM at the next free address (NFA) using the "Write to
memory at NFA" instruction provided the device is not full.
However, write to memory at address specified by the
address counter is not affected by full flag input or output.
For single device operation, the /FFI pin is tied to ground.
For depth cascaded devices, the highest priority device has
its /FFI input tied to ground, all other devices in the cascade
having the /FFI tied to the Full Flag output (/FF) of the next
higher priority device. Refer to the depth cascading section
for more details.

Revision 3.0

Subject to Change Without Notice

NL84620

2.5 Match Flag Up Input (/MFUI):
This input is provided for depth cascading multiple CAMs.
For single device operation, this pin is tied to VDD. For
depth cascaded devices, the lowest priority device has its
/MFUI pin connected to VDD. All other devices in the
cascade have their /MFUI pin tied to the Match Flag Up
Output (/MFUO) of the next Lower priority device. Refer to
the depth cascading section for more details.

2.6 Match Flag Down Input (/MFDI):
This input is provided for depth cascading multiple CAMs.
For single device operation, this pin is tied to VDD. For
depth cascaded devices, the highest Priority device has its
/MFDI pin connected to VDD. All other devices in the
cascade have their /MFDI pin tied to the Match Flag Down
Output (/MFDO) of the next higher priority device. Refer to
the depth cascading section for more details.

2.7 Multiple Match Flag Input (/MMFI):
This input is provided for depth cascading multiple CAMs.
For single device operation, this pin is tied to VDD. For
depth cascaded devices the highest priority device has its
/MMFI tied to VDD. All other devices in the cascade have
their /MMFI pin tied to the Multiple Match Flag (/MMF) of
the next higher Priority device. Refer to the depth cascading
section for more details.

2.8 Cascade Down Input (CSCDI):
This input is provided for depth cascading multiple CAMs.
For single device operation, this pin is tied to ground. For
depth cascaded devices the highest priority device has its
CSCDI connected to ground. All other devices in the
cascade have their CSCDI pin tied to the CSCDO of the next
higher priority device. Refer to the depth cascading section
for more details.

2.9 Cascade Up Input (CSCUI):
This input is provided for depth cascading multiple CAMs.
For single device operation, this pin is tied to ground. For
depth cascaded devices the lowest Priority device has its
CSCUI connected to ground. All other devices in the
cascade have their CSCUI pin tied to the CSCUO of the next
lower priority device. Refer to the depth expansion section
for more details.

2.10 Word Enable (/WEN_0,1,2,3):
This is a synchronous input and enables access to the CAM
array and all the registers with 16-bit granularity. For 64-bit
entities in the CAM, /WEN_3 enables access to bits 63-48,
/WEN_2 to bits 47-32, /WEN_1 to bits 31-16 and /WEN_0
to bits 15-0. These control pins are effective only for read
and write to memory and the registers; for all other
operations they are a "don't care".

2.11 Instruction Bus (IBUS

.IBUS

This is a synchronous 14-bit bus that provides the operation
code (Opcode) to the CAM.

2.12 Comparand Bus (CBUS

.CBUS

This is a 64-bit synchronous I/O bus that conveys data to and
from the memory and the registers.

2.13 Instruction Error (/IERR):
This is a synchronous output and will be asserted low
whenever an erroneous Opcode is detected. An erroneous
Opcode is one that does not conform to the listed Opcodes
for the SyncCAM. In a depth cascade all devices will
provide the Instruction Error output. The user is advised
against issuing erroneous Opcodes, as the results will be
non-deterministic.

2.14 Cascade Down Output (CSCDO):
This output is provided for depth cascading multiple CAMs.
For single device operation this pin must be left
unconnected. For depth cascaded devices, the highest
priority device has its CSCDO connected to the CSCDI of
the next lower priority device. Refer to the depth expansion
section for more details.

2.15 Cascade Up Output (CSCUO):
This output is provided for depth cascading multiple CAMs.
For single device operation this pin must be left
unconnected. For depth cascaded devices, the lowest
priority device has its CSCUO connected to the CSCUI of
the next higher priority device. Refer to the depth expansion
section for more details.

2.16 Full Flag (/FF):
This is a synchronous output and is updated after Write to
Memory, Copy to Memory, set VBITs or Set Full Flag
operations. After reset, this pin is high. When the device is
full, /FF is asserted low. For depth cascaded devices, /FF is
connected to /FFI of the next lower priority device. For
depth cascaded devices, when single device mode is
selected, deselected devices pass /FFI through to /FF.

2.17 Match Flag Up Output (/MFUO)
This synchronous output is provided for depth cascading
CAMs. This output is updated for all compare operations.
After reset, /MFUO is high. For depth cascaded devices, the
/MFUO of a device is connected to the /MFUI of the next
higher priority device. For depth cascaded devices, when
single device mode is selected, deselected devices pass
/MFUI through to /MFUO.

2.18 Match Flag Down Output (/MFDO)
This synchronous output is provided for depth cascading
CAMs. This output is updated for all compare operations.
After reset, /MFDO is high. For depth cascaded devices, the
/MFDO of a device is connected to the /MFDI of the next
lower priority device. For depth cascaded devices, when
single device mode is selected, deselected devices pass
/MFDI through to /MFDO.

2.19 System Match Flag (/SMF)
This synchronous output provides the System Match Flag
(either for single device or cascaded devices). This output is
updated for all compare operations. After reset /SMF is
high. Functionally this output is identical to /MFDO. When
cascading, the /SMF is provided by the lowest priority
CAM. The /SMF from all other CAMs in the cascade may
be left unconnected.

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