ADC14155
14-Bit, 155 MSPS, 1.1 GHz Bandwidth A/D Converter
General Description
The ADC14155 is a high-performance CMOS analog-to-
digital converter capable of converting analog input signals
into 14-bit digital words at rates up to 155 Mega Samples Per
Second (MSPS). This converter uses a differential, pipelined
architecture with digital error correction and an on-chip
sample-and-hold circuit to minimize power consumption and
the external component count, while providing excellent dy-
namic performance. A unique sample-and-hold stage yields
a full-power bandwidth of 1.1 GHz. The ADC14155 operates
from dual +3.3V and +1.8V power supplies and consumes
974 mW of power at 155 MSPS.
The separate +1.8V supply for the digital output interface
allows lower power operation with reduced noise. A power-
down feature reduces the power consumption to 5 mW with
the clock input disabled, while still allowing fast wake-up time
to full operation.
The differential inputs provide a full scale differential input
swing equal to 2 times the reference voltage. A stable 1.0V
internal voltage reference is provided, or the ADC14155 can
be operated with an external reference.
For optimum performance, it is recommended to operate the
ADC14155 with a differential clock input, which doubles the
clock amplitude compared with single-ended clock opera-
tion. Clock mode (differential versus single-ended) and out-
put data format (offset binary versus 2's complement) are
pin-selectable. A duty cycle stabilizer maintains performance
over a wide range of clock duty cycles.
The ADC14155 is available in a 48-lead LLP package and
operates over the industrial temperature range of -40C to
+85C.
Features
n
1.1 GHz Full Power Bandwidth
n
Internal sample-and-hold circuit
n
Low power consumption
n
Internal precision 1.0V reference
n
Single-ended or Differential clock modes
n
Data Ready output clock
n
Clock Duty Cycle Stabilizer
n
Dual +3.3V and +1.8V supply operation (+/- 10%)
n
Power-down mode
n
Offset binary or 2's complement output data format
n
48-pin LLP package, (7x7x0.8mm, 0.5mm pin-pitch)
Key Specifications
n
Resolution
14 Bits
n
Conversion Rate
155 MSPS
n
SNR (f
IN
= 70 MHz)
71.3 dBFS (typ)
n
SFDR (f
IN
= 70 MHz)
85.3 dBFS (typ)
n
ENOB (f
IN
= 70 MHz)
11.5 bits (typ)
n
Full Power Bandwidth
1.1 GHz (typ)
n
Power Consumption
974 mW (typ)
Applications
n
High IF Sampling Receivers
n
Wireless Base Station Receivers
n
Power Amplifier Linearization
n
Multi-carrier, Multi-mode Receivers
n
Test and Measurement Equipment
n
Communications Instrumentation
n
Radar Systems
PRELIMINARY
July 2006
ADC14155
14-Bit,
155
MSPS,
1.1
GHz
Bandwidth
A/D
Converter
2006 National Semiconductor Corporation
DS201790
www.national.com
Connection Diagram
20179001
ADC14155
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2
Ordering Information
Industrial (-40C
T
A
+85C)
Package
ADC14155CISQ
48 Pin LLP
ADC14155EB
Evaluation Board
Block Diagram
20179002
ADC14155
www.national.com
3
Pin Descriptions and Equivalent Circuits
Pin No.
Symbol
Equivalent Circuit
Description
ANALOG I/O
3
V
IN
-
Differential analog input pins. The differential full-scale input
signal level is two times the reference voltage with each input
pin signal centered on a common mode voltage, V
CM
.
4
V
IN
+
43
V
RP
These pins should each be bypassed to AGND with a low ESL
(equivalent series inductance) 0.1 F capacitor placed very
close to the pin to minimize stray inductance. A 0.1 F
capacitor should be placed between V
RP
and V
RN
as close to
the pins as possible, and a 10 F capacitor should be placed
in parallel.
V
RP
and V
RN
should not be loaded. V
RM
may be loaded to
1mA for use as a temperature stable 1.5V reference.
It is recommended to use V
RM
to provide the common mode
voltage, V
CM
, for the differential analog inputs, V
IN
+ and V
IN
-.
45
V
RM
44
V
RN
46
V
REF
This pin can be used as either the +1.0V internal reference
voltage output (internal reference operation) or as the external
reference voltage input (external reference operation).
To use the internal reference, V
REF
should be decoupled to
AGND with a 0.1 F, low equivalent series inductance (ESL)
capacitor. In this mode, V
REF
defaults as the output for the
internal 1.0V reference.
To use an external reference, overdrive this pin with a low
noise external reference voltage. The output impedance of the
internal reference at this pin is 9k
. Therefore, to overdrive this
pin, the impedance of the external reference source should be
<<
9k
.
This pin should not be used to source or sink current.
The full scale differential input voltage range is 2 * V
REF
.
DIGITAL I/O
11
CLK+
The clock input pins can be configured to accept either a
single-ended or a differential clock input signal.
When the single-ended clock mode is selected through
CLK_SEL/DF (pin 8), connect the clock input signal to the
CLK+ pin and connect the CLK- pin to AGND.
When the differential clock mode is selected through
CLK_SEL/DF (pin 8), connect the positive and negative clock
inputs to the CLK+ and CLK- pins, respectively.
The analog input is sampled on the falling edge of the clock
input.
12
CLK-
ADC14155
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4
Pin Descriptions and Equivalent Circuits
(Continued)
Pin No.
Symbol
Equivalent Circuit
Description
8
CLK_SEL/DF
This is a four-state pin controlling the input clock mode and
output data format.
CLK_SEL/DF = V
A
, CLK+ and CLK- are configured as a
differential clock input. The output data format is 2's
complement.
CLK_SEL/DF = (2/3)*V
A
, CLK+ and CLK- are configured as a
differential clock input. The output data format is offset binary.
CLK_SEL/DF = (1/3)*V
A
, CLK+ is configured as a single-ended
clock input and CLK- should be tied to AGND. The output data
format is 2's complement.
CLK_SEL/DF = AGND, CLK+ is configured as a single-ended
clock input and CLK- should be tied to AGND. The output data
format is offset binary.
7
PD
This is a two-state input controlling Power Down.
PD = V
A
, Power Down is enabled. In the Power Down state
only the reference voltage circuitry remains active and power
dissipation is reduced.
PD = AGND, Normal operation.
17-24,
27-32
D0D13
Digital data output pins that make up the 14-bit conversion
result. D0 (pin 17) is the LSB, while D13 (pin 32) is the MSB of
the output word. Output levels are CMOS compatible.
33
OVR
Over-Range Indicator. This output is set HIGH when a sample
amplitude exceeds the 14-bit conversion range (0 to 16383).
34
DRDY
Data Ready Strobe. This pin is used to clock the output data. It
has the same frequency as the sampling clock. One word of
data is output in each cycle of this signal. The rising edge of
this signal should be used to capture the output data.
ANALOG POWER
1, 6, 9, 37,
40, 41, 48
V
A
Positive analog supply pins. These pins should be connected
to a quiet +3.3V source and be bypassed to AGND with 100
pF and 0.1 F capacitors located close to the power pins.
2, 5, 10, 38,
39, 42, 47
AGND
The ground return for the analog supply.
DIGITAL POWER
13
V
D
Positive digital supply pin. This pin should be connected to a
quiet +3.3V source and be bypassed to DGND with a 100 pF
and 0.1 F capacitor located close to the power pin.
14
DGND
The ground return for the digital supply.
15, 25, 36
V
DR
Positive driver supply pin for the ADC14155's output drivers.
This pin should be connected to a quiet voltage source of
+1.8V and be bypassed to DRGND with 100 pF and 0.1 F
capacitors located close to the power pins.
16, 26, 35
DRGND
The ground return for the digital output driver supply. These
pins should be connected to the system digital ground, but not
be connected in close proximity to the ADC's DGND or AGND
pins. See Section 6.0 (Layout and Grounding) for more details.
ADC14155
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