LP5550
PowerWise
TM
Technology Compliant Energy
Management Unit
General Description
The LP5550 is a PWI 1.0 compliant Energy Management
System for reducing power consumption of stand-alone mo-
bile phone processors such as base-band or applications
processors.
The LP5550 contains an advanced, digitally controlled
switching regulator for supplying variable voltage to proces-
sor core and memory. The device also incorporates 3 pro-
grammable LDO-regulators for powering I/O, PLLs and
maintaining memory retention in shutdown-mode.
The device is controlled via the PWI open-standard inter-
face. The LP5550 operates cooperatively with PowerWise
technology compatible processors to optimize supply volt-
ages adaptively over process and temperature variations or
dynamically
using
frequency/voltage
pre-characterized
look-up tables.
Features
n
Supports high-efficiency PowerWise Technology
Adaptive Voltage Scaling
n
PWI open standard interface for system power
management
n
Digitally controlled intelligent voltage scaling
n
1 MHz PWM switching frequency
n
Auto or PWI controlled PFM mode transition
n
Internal soft start/startup sequencing.
n
3 programmable LDOs for I/O, PLL, and memory
retention supply generation.
n
Power OK output.
Applications
n
GSM/GPRS/EDGE & UMTS cellular handsets
n
Hand-held radios
n
PDAs
n
Battery powered devices
n
Portable instruments
System Diagram
20154563
FIGURE 1. System Diagram
January 2006
LP5550
PowerW
ise
TM
T
echnology
Compliant
Energy
Management
Unit
2006 National Semiconductor Corporation
DS201545
www.national.com
Typical Application
Pin Descriptions
Pin #
Name
I/O
Type
Description
1
SCLK
I
D
PowerWise Interface (PWI) clock input
2
SPWI
I/O
D
PowerWise Interface (PWI) bi-directional data
3
RESETN
I
D
Reset, active low
4
VO2
O
A
LDO2 output, for supplying the I/O voltage on the SoC
5
VBAT1
P
P
Battery supply voltage
6
VO1
O
A
LDO1 output, for supplying a fixed voltage to a PLL etc. on the SoC
7
DGND
G
G
Digital ground
8
PWROK
O
D
Power OK, active high output signal
9
VBATSW
P
P
Battery supply voltage for switching regulator
10
SW
O
A
Switcher pin connected to coil
11
SWGND
G
G
Switcher ground
12
VBAT2
P
P
Battery supply voltage
13
VO3
O
A
LDO3 output, on-chip memory supply voltage
14
VFB
I
A
Switcher output voltage for supplying SoC core logic
15
AGND
G
G
Analog Ground
16
ENABLE
I
D
Enable, active high
A: Analog Pin
D: Digital Pin
I: Input Pin
O: Output Pin
I/O: Input/Output Pin
P: Power Pin
G: Ground Pin
20154530
FIGURE 4. Typical Application Circuit
LP5550
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Ordering Information
Voltage Option
Order Number
Package Marking
Supplied As
LP5550SQ
LP5550SQ
1000 units, Tape-and-Reel
LP5550SQX
LP5550SQ
4500 units, Tape-and-Reel
*Released. Samples available.
LP5550
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Absolute Maximum Ratings
(Notes 1, 2)
If Military/Aerospace specified devices are required,
please contact the National Semiconductor Sales Office/
Distributors for availability and specifications.
VBAT1, VBAT2, VBATSW
-0.3 to +6.0V
VO1, VO2, VO3 to GND
-0.3 to +VBAT1+0.3V
ENABLE, RESETN, VFB,
SW,
SPWI, SCLK, PWROK
-0.3 to VBAT2+0.3V
DGND, AGND, SWGND to
GND SLUG
0.3V
Junction Temperature
(TJ-MAX)
150C
Storage Temperature Range
-65C to 150C
Maximum Continuous
Power Dissipation
(PD-MAX) (Note 4)
1.0 W
Maximum Lead
Temperature (Soldering)
Note 4
ESD Rating (Note 3)
Human Body Model:
All pins
2.0kV
Operating Ratings
(Notes 1, 2)
VBAT1, VBAT2, VBATSW
3.0V to 5.5V
Junction Temperature (T
J
)
Range
-40C to +125C
Ambient Temperature (T
A
)
Range(Note 6)
-40C to +85C
Thermal Properties
(Note 7)
Junction-to-Ambient
Thermal Resistance (
JA
)
39.8C/W
General Electrical Characteristics
Unless otherwise noted, V
BAT1,2,SW
, RESETN, ENABLE = 3.6V.
Typical values and limits appearing in normal type apply for TJ = 25C. Limits appearing in boldface type apply over the entire
junction temperature range for operation, -40 to +125C. (Notes 2, 8, 9)
Symbol
Parameter
Conditions
Min
Typ
Max
Units
I
Q
Shutdown Supply current
V
BAT1,2,SW
= 2.0V, all circuits off.
1
6
A
Sleep State Supply Current
V
BAT1,2,SW
= 3.6V, LDO3 (V
O3
) on,
PWI on. All other circuits off.
70
85
A
Acitve State Supply Current
(No load, PFM mode)
V
BAT1,2,SW
= 3.6V, LDOs 1 and 2 on,
Switcher on, PWI on.
140
165
A
T
SD
Thermal Shutdown Threshold
160
C
Thermal Shutdown Hysteresis
10
LDO1 (PLL/Fixed Voltage) Characteristics
Unless otherwise noted, V
BAT1,2,SW
, RESETN, EN-
ABLE = 3.6V. Typical values and limits appearing in normal type apply for TJ = 25C. Limits appearing in boldface type apply
over the entire junction temperature range for operation, -40 to +125C. (Notes 2, 8, 9)
Symbol
Parameter
Conditions
Min
Typ
Max
Units
V
OUT
Accuracy
Output Voltage Accuracy
1mA
I
OUT
100mA,V
OUT
= 1.2V,
3.0V
V
BAT1,2,SW
5.5V
-3%
1.2
3%
V
V
OUT
Range
Programmable Output Voltage
Range
0A
I
OUT
100mA, Programming
Resolution=100mV
0.7
1.2
2.2
V
I
OUT
Recommended Output Current 3.0V
VBAT1,2,SW 5.5V
100
mA
Short Circuit Current Limit
V
OUT
= 0V
350
I
Q
Quiescent Current
I
OUT
= 0mA(Note 11)
35
45
A
V
OUT
Line Regulation
3.0V
V
BAT1,2,SW
5.5V, I
OUT
=
50mA
-0.125
0.125
%/V
Load Regulation
V
IN
= 3.6V, 1mA
I
OUT
100mA
-0.0085
0.0085 %/mA
Line Transient Regulation
3.6V
V
IN
3.9V, TRISE,FALL = 10
s
27
mV
Load Transient Regulation
V
IN
= 3.6V, 10mA
I
OUT
90 mA,
TRISE,FALL = 100 ns
86
mV
eN
Output Noise Voltage
10Hz
f 100kHz,C
OUT
= 2.2F
0.103
mVRMS
LP5550
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