NJG1707PG1
- 1 -
10
11
12
13
21
28
29
30
31
32
1
2
3
4
5
6
7
8
14
15
16
17
18
19
20
22
23
24
25
26
27
VDD
EXT2
GND
EXT1
GND
TX
GND
TER1
GND(LN A)
LNAIN
LNAOUT
EXTCAP
GND
G
N
D
C
T
L
1
C
T
L
2
C
T
L
3
V
S
S
G
N
D
A
N
T
2
R
X
A
N
T
1
T
E
R
2
G
N
D
G
N
D
G
N
D
A NT-SW
DECO RDER
ANT-SW CONTROL VO LTAGE
SW 5
SW 1
SW 3 SW 7
SW 4-2
SW 4-1
SW 6
SW 8
SW 9
SW 2
GND
GND(LN A)
9
GND
G
N
D
G
N
D
G
N
D
800MHz TDMA FRONT-END GaAs MMIC
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GENERAL DESCRIPTION
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PACKAGE OUTLINE
NJG1707PG1 is a front-end IC for a digital cellular phone of
800MHz band. A 2x6 antenna switches and a low noise
amplifier are included.
The parallel control signals of three bits logic connect T/R
circuits to internal two antennas or external two antennas. The
termination ports with external matching circuits make low
interference between diversity antennas.
The ultra small & thin FFP32-G1 package is adopted.
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FEATURES
Ultra small & thin package
FFP32-G1 (Mount Size: 4.5x4.5x0.85mm)
Antenna Switch
l
Low voltage operation
-2.5V (Tx only) and +3.5V
l
Low current consumption
10uA typ. (Tx Mode, P
in
=30dBm), 2uA typ. (Rx Mode, P
in
=10dBm)
l
Low insertion loss
0.5dB typ. @(Tx-ANT1, Tx-EXT1) f
in
=960MHz, P
in
=30dBm
l
Low Adjacent Channel
-63dBc typ. @ V
DD
=+3.5V, V
SS
=-2.5V, f
in
=960MHz, P
in
=30dBm
Leakage Power
Low Noise Amplifier
l
Low voltage operation
+2.7V typ.
l
Low current consumption
+2.7mA typ.
l
Small signal gain
17.5dB typ. @f=820MHz
l
Low noise figure
1.4dB typ. @ f=820MHz
l
High input IP3
IIP3=-4.5dBm typ. OIP3=+13dBm typ. @f=820MHz+820.1MHz
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PIN CONFIGURATION
FFP32 Type
(Top View)
NJG1707PG1
NJG1707PG1
- 2-
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ABSOLUTE MAXIMUM RATINGS
(T
a
=25C)
PARAMETER
SYMBOL
CONDTIONS
RATINGS
UNITS
Supply Voltage 1
V
DD1
V
DD
Terminal
6.0
V
Supply Voltage 2
V
DD2
LNAOUT Terminal
5.0
V
Supply Voltage 3
V
SS
V
SS
Terminal
-4.0~+0.3
V
Control Voltage
V
CTL
CTL1, CTL2, CTL3 Terminals
6.0
V
TX, ANT1, EXT1 Terminals
37
dBm
RX, ANT2, EXT2 Terminals
28
dBm
Input Power
P
in
LNAIN Terminal
10
dBm
Power Dissipation
P
D
600
mW
Operating
Temperature
T
opr
-40~+85
C
Storage
Temperature
T
stg
-55~+125
C
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ELECTRICAL CHARACTERISTICS 1 [ANTENNA SWITCH DC CHARACTERISTICS]
General Conditions:
PARAMETER
SYMBOL
CONDITIONS
MIN
TYP
MAX
UNITS
Positive Supply Voltage
V
DD
V
DD
Terminal
2.7
3.5
5.0
V
Negative Supply Voltage
V
SS
V
SS
Terminal
-3.5
-2.5
-2.0
V
Current Consumption 1
I
DD1
V
DD
Terminal
Rx Mode, No RF Signal
-
2.0
5.0
A
Current Consumption 2
I
SS1
V
SS
Terminal
Rx Mode, No RF Signal
-0.1
-
0
uA
Current Consumption 3
I
DD2
V
DD
Terminal, f
in
=0.1~2GHz
Tx Mode, P
in
=30dBm
-
10
30
uA
Current Consumption 4
I
SS2
V
SS
Terminal, f
in
=0.1~2GHz
Tx Mode, P
in
=30dBm
-30
-10
-
uA
Control Voltage (H)
V
CTL(H)
CTL1, CTL2, CTL3 Terminals
2.0
3.0
V
DD
V
Control Voltage (L)
V
CTL(L)
CTL1, CTL2, CTL3 Terminals
0
0
0.6
V
Control Current
I
CTL
CTL1, CTL2, CTL3=V
DD
or CTL1, CTL2, CTL3=0V
-1.3
-
1.3
uA
Control terminal Input
Impedance
R
in
CTL1, CTL2, CTL3 Terminals
4
-
-
M
T
a
=25C, V
DD
=3.5V, V
SS
=-2.5V
TX, RX, ANT1, ANT2, EXT1, EXT2: terminated (50
)
TER1, TER2 : grounded by 10pF capacitor
* The voltage of this terminal should be supplied before or same time with other DC supplying
terminals. (CTL1~3, V
SS
).
NJG1707PG1
- 3 -
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ELECTRICAL CHARACTRISTICS 2 [Tx Mode]
General Conditions:
PARAMETER
SYMBOL
CONDITION
MIN
TYP
MAX UNITS
Tx-ANT1 Insertion Loss
LOSS1
P
in
=30dBm
-
0.50
0.65
dB
Tx-EXT1 Insertion Loss
LOSS2
P
in
=30dBm
-
0.50
0.65
dB
Tx-Rx Isolation
ISL1
P
in
=30dBm
Tx-ANT1, Tx-EXT1 passing
24
27
-
dB
Tx-ANT1 Isolation
ISL2
P
in
=30dBm
Tx-EXT1 passing
22
25
-
dB
Tx-ANT2 Isolation
ISL3
P
in
=30dBm
Tx-ANT1, Tx-EXT1 passing
33
38
-
dB
Tx-EXT1 Isolation
ISL4
P
in
=30dBm
Tx-ANT1 passing
21
24
-
dB
Tx-EXT2 Isolation
ISL5
P
in
=30dBm
Tx-ANT1,Tx-EXT1 passing
32
37
-
dB
Input Power at
0.5dB Compression 1
P
-0.5dB
(1)
Tx-ANT1,Tx-EXT1 passing
33
35
-
dBm
Adjacent Channel
Leakage Power 1
ACP1
PDC Standard, 50kHz offset
P
in
=30dBm
Input Signal ACP=-64dBc @ 30dBm
-
-63
-60
dBc
Adjacent Channel
Leakage Power 2
ACP2
PDC Standard, 100kHz offset
P
in
=30dBm
Input Signal ACP=-76dBc @ 30dBm
-
-74
-70
dBc
2nd Harmonics 1
2f
0
(1)
P
in
=30dBm
Input Signal 2nd Harmonics=-70dBc
-
-65
-63
dBc
3rd Harmonics 1
3f
0
(1)
P
in
=30dBm
Input Signal 3rd Harmonics=-100dBc
-
-64
-62
dBc
VSWR 1
VSWR1
Tx-ANT1, Tx-EXT1 passing
-
1.2
1.5
Switching Time 1
T
D
1
CTL1~3
-
120
500
nsec
T
a
=25C,V
DD
=3.5V,V
SS
=-2.5V, f
in
=885~940MHz
Tested on PCB circuit as shown below.
Insertion loss of each connectors, striplines, and capacitors are excluded.
TX, RX, ANT1, ANT2, EXT1, EXT2: terminated (50
)
TER1, TER2: grounded by 10pF capacitor.
NJG1707PG1
- 4-
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ELECTRICAL CHARACTRISTICS 3 [Rx Mode]
General Conditions:
PARAMETER
SYMBOL
CONDITION
MIN
TYP
MAX
UNITS
Rx-ANT1 Insertion Loss
LOSS3
P
in
=10dBm
-
0.65
0.80
dB
Rx-ANT2 Insertion Loss
LOSS4
P
in
=10dBm
-
0.60
0.75
dB
Rx-EXT1 Insertion Loss
LOSS5
P
in
=10dBm
-
0.70
0.85
dB
Rx-EXT2 Insertion Loss
LOSS6
P
in
=10dBm
-
0.65
0.80
dB
Rx-ANT1 Isolation
ISL6
P
in
=10dBm
Rx-ANT2, Rx-EXT1, Rx-EXT2 passing
22
26
-
dB
Rx-ANT2 Isolation
ISL7
P
in
=10dBm
Rx-ANT1, Rx-EXT1, Rx-EXT2 passing
24
30
-
dB
Rx-EXT1 Isolation
ISL8
P
in
=10dBm
Rx-ANT1, Rx-ANT2, Rx-EXT2 passing
22
26
-
dB
Rx-EXT2 Isolation
ISL9
P
in
=10dBm
Rx-ANT1, Rx-ANT2, Rx-EXT1 passing
22
26
-
dB
Input Power at 1dB
Compression 1
P
-1dB
(1)
Rx-ANT1, Rx-ANT2, Rx-EXT1, Rx-
EXT2 passing
21
26
-
dBm
VSWR 2
VSWR2
RX-ANT1, RX-ANT2, RX-EXT1, RX-
EXT2 passing
-
1.2
1.6
Switching Time 2
T
D
2
CTL1~3
-
120
500
nsec
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ELECTRICAL CHARACTRISTICS 4 [LNA]
General Conditions:
PARAMETER
SYMBOL
CONDITION
MIN
TYP
MAX
UNITS
Operation Frequency
f
RF
810
-
885
MHz
Drain Voltage
V
DD
3
2.5
2.7
4.5
V
Current Consumption
I
DD
3
No RF input
-
2.7
3.6
mA
Small Signal Gain
Gain
16.0
17.5
18.5
dB
Gain Flatness
G
flat
fRF=810~885MHz
-
0.5
1.0
dB
Noise Figure
NF
-
1.4
1.6
dB
Pout at 1dB Gain
Compression Point
P
-1dB
(2)
-3.0
+1.0
-
dBm
Input 3
rd
order
Intercept Point
IIP3
-8.0
-4.5
-
dBm
LNAIN Port VSWR
VSWR
i
-
1.5
2.5
LNAOUT Port VSWR
VSWR
o
-
1.5
2.5
T
a
=25C, V
DD
=3.5V, V
SS
=0V, f
in
=810~885MHz
Tested on PCB circuit as shown below.
Insertion loss of each connectors, striplines, and capacitors are excluded.
TX, RX, ANT1, ANT2, EXT1, EXT2: terminated (50
)
TER1, TER2: grounded by 10pF capacitor.
T
a
=25C, V
DD
=3.5V, V
SS
=0V, f
in
=820MHz
Tested on PCB circuit as shown below.
NJG1707PG1
- 5 -
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TERMINAL INFORMATION
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TRUTH TABLE
"H"=V
CTL (H)
, "L"=V
CTL (L)
, "X"=H or L
CONTROL INPUT
CONTROL OUTPUT
Tx/Rx
Diversity
IN/OUT
ROUTE
CTL1
CTL2
CTL3
SW1 SW2 SW3 SW4 SW5 SW6 SW7 SW8 SW9
Tx-ANT1
H
X
H
OFF
OFF
OFF
ON
ON
OFF
OFF
OFF
ON
Tx-EXT1
H
X
L
OFF
OFF
ON
OFF
ON
ON
ON
OFF
OFF
Rx-ANT1
L
L
H
OFF
OFF
ON
OFF
ON
OFF
ON
ON
ON
Rx-ANT2
L
H
H
ON
OFF
OFF
OFF
OFF
ON
ON
ON
ON
Rx-EXT1
L
L
L
OFF
OFF
OFF
ON
ON
ON
OFF
ON
OFF
Rx-EXT2
L
H
L
OFF
ON
OFF
OFF
ON
ON
ON
ON
ON
PIN NO.
SYMBOL
DESCRIPTIONS
4
CTL1
5
CTL2
6
CTL3
Control signal input terminal of high impedance C-MOS logic. Logic level: High; more
than +2V, Low; 0~+0.6V. Please connect to GND or V
DD
with 100k
if potential is
open or uncertain.
7
V
SS
Negative supply terminal. Negative voltage of -3.5~-2.0V must be supplied on Tx
mode. This terminal is isolated on Rx mode, so open or 2.5~0V condition can be
used. Please connect bypass capacitor with GND to keep RF performance.
9
V
DD
Positive supply terminal. The voltage of this terminal should be supplied before or
same time with other DC supplying terminals (CTL1~3, V
SS
). The bias voltage should
be +2.7~+5.0V. Please connect bypass capacitor with GND to keep RF performance.
11
EXT2
RF port for Rx signal. A DC cut capacitor (56pF~100pF) is required to block V
DD
voltage.
13
EXT1
RF port for Tx/Rx signal. A DC cut capacitor (56pF~100pF) is required to block V
DD
voltage.
15
TX
Tx power input terminal. A DC cut capacitor is required to block V
DD
voltage, and also
an external matching circuit is required to improve VSWR(See Application circuit).
17
TER2
A termination terminal for ANT1 in case ANT2 is in use. The influence of ANT1
against ANT2 is reduced. A DC cut capacitor (10pF) is required to block V
DD
voltage.
19
ANT1
RF port for Tx/Rx signal. A DC cut capacitor (56pF~100pF) is required to block V
DD
voltage.
21
RX
Rx output terminal. A DC cut capacitor is required to block V
DD
voltage, and also an
external matching circuit is required to improve VSWR(See Application circuit).
23
ANT2
RF port for Rx signal. A DC cut capacitor (56pF~100pF) is required to block V
DD
voltage.
25
TER1
A termination terminal for ANT2 in case ANT1 is in use. The influence of ANT2
against ANT1 is reduced. A DC cut capacitor (10pF) is required to block V
DD
voltage.
26,27
GND(LNA)
Ground terminal of LNA. Please place ground plane close to this pin for good RF
performance.
28
LNAIN
LNA input terminal. An external matching circuit is required.
30
LNAOUT
LNA output terminal. An external matching circuit with LNA biasing element L3, L4 as
in application circuit is required.
31
EXTCAP
Bypass capacitor terminal of LNA. Please place C9 as in application circuit close to
this terminal.
1,2,3,8,10,
12,14,16,1
8,20,22,24,
29,32
GND
Ground terminal. Please connect to ground plane as close as possible for good RF
performance.
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