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NJU6538

Ver.2003-05-09

1/8, 1/9, 1/10 Duty

BITMAP LCD DRIVER with KEY SCAN

GENERAL DESCRIPTION

The NJU6538 is a 10-common x 65-segment bitmap LCD

driver to display graphics or characters.
It contains 650 bits display data RAM, microprocessor
interface circuit, common and segment drivers, key scan
circuit, and general output ports.

An image data from MPU through the serial interface is

stored into the 650 bits internal displayed on the LCD panel
through the commons and segments drivers.

The NJU6538 displays 10 x 65 dots graphics or

11-character 1-line by 5 x 7 dots character + 3 x 65 dots icons.
It contains key scan circuit transmitting the 25-keys maximum
(5 x 5 = 25) to MPU.

Also it provides 4 general purpose output ports with PWM

output function maximum to drive LEDs or others directly.

Furthermore, the NJU6538 can select a LCD driving voltage

out of 16 steps voltage by the instruction adjust the display
contrast of LCD panel.

FEATURES

Direct Correspondence between Display Data RAM and LCD Pixel

Display Data RAM

: 650-bits

LCD Drivers

: 65-seg, 10-com

Serial interface (SIO, SCL, CS)

Programmable Duty Ratio

1/8 Duty

7-common x 65-segment + 1-icon common

1/9 Duty

7-common x 65-segment + 2-icon common

1/10Duty

7-common x 65-segment + 3-icon common

Bias Ratio

1/4 bias

25-key scan Function (5 x 5 matrix)

Needless for anti-reverse current diodes in key scan

general Output Ports with 128-steps PWM output (possible LED driving) maximum 4-ports

Useful Instruction Set

Display ON/OFF, Page Address Set, Column Address Set, Display Data write, ADC Select, Inverse
Display ON/OFF, whole display ON/OFF, Reset, EVR Register Set, Duty Select, Power Save mode set,
General Output Port PWM phase / frequency set, General Output Port PWM data set, General Output
Port / Key scan output select

Bleeder Resistance On-chip

Software Contrast Control (16 steps)

Operating Voltage

Logic Operating Voltage 2.7 to 5.5V
LCD Driving Voltage

5.0

10.0V

Package Outline

QFP100-G1

QFP100-C2

C-MOS Technology

(Substrate: P)

PRELIMINARY

PACKAGE OUTLINE

NJU6538FC2

NJU6538FG1

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NJU6538

Ver.2003-05-09

PIN CONFIGRATION

SEG

SCL SIO SEG

SEG

/Po

VLCD

OSC

RESb

COM

SEG

NJU6538FC2

SEG

COM

SEG

NJU6538FG1

/Po

VLCD

OSC

RESb

SCL

SIO

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NJU6538

Ver.2003-05-09

BLOCK DIAGRAM

E.V.R.

VLCD2

VSS

Common Driver

Segment Driver

COM

SEG

6
3

SEG

6
4

SEG

6
5

Display Data RAM

Instruction Data Buffer

Instruction Decoder

Key Data Buffer

Key Scan

Control

Serial I/F

SIO

Oscillator

RESET

OSC

SEG

VLCD1

o3/

General Output

Driver

Power ON

Reset

RESb

Res

e
t

Timing

Generator

Column Address Decoder

age A

ddress

Dec

oder

Input

Buffer

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NJU6538

Ver.2003-05-09

TERMINAL DESCRIPTION

No.

FG1 FC2

Symbol I/O

Description

1 to 65

3 to 67

SEG

to SEG

Segment output terminal.

66 to 72 68 to 74

COM

to COM

Common output terminal.

73 to 75 75 to 77 COM

to COM

Icon common output terminal.

76 to 78 78 to 80

Po0 to Po2

General output port
128-step PWM waveform output by MPU control.

79 81 Po3/S

General output port / Key scanning input terminal
Select General output port or Key scanning input terminal by the
instruction.
A function must be selected either Po3 or S

General output port
128-step PWM waveform output by MPU control.

Key scanning input terminals

(No need for anti-reverse current diode in key scan)

80 to 83 82 to 85

to S

Key scanning input terminals.
(No need for anti-reverse current diode in key scan)

84 to 88 86 to 90

to K

Key scanning input terminals.
(with internal pull-down resistor)

89 91

Power supply terminal.(

2.7V to 5.5V)

VLCD1

LCD driving voltage input terminal.

91
92
93
94

93
94
94
96

VLCD2

LCD driving voltage stabilization capacitor terminals.
Connect the capacitor between each terminal and Vss.

95 97

Ground terminal.

96 98

OSC

I/O

Osclator terminal.
Conect the external resistor.

97 99

RESb

Reset terminal. (with internal pull-up resistor)
In case of only Power-on Reset should be open.

100

Chip enable terminal

SCL

Serial clock input terminal

100

SIO

I/O

Serial Data input or output terminal

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NJU6538

Ver.2003-05-09

FUNCTIONAL DESCRIPTION

(1) Description for each blocks

(1-1) Serial I/F

The serial I/F controls serial data from external data.

(1-2) Instruction data buffer

The instruction data buffer stores instruction code from external.

(1-3) Instruction decoder

The instruction decoder decodes instruction code and controls each blocks.

(1-4) Display data RAM

The Display data RAM stores data for display from MPU.

(1-5) Segment driver

The Segment driver generates driving waveform to segment terminal on display data.

(1-6) General output driver

The General output driver generates output signal level to general output terminal on output data.

(1-7) Common driver

The Common driver generates driving waveform to common terminal.

(1-8) Electrical Variable Resistance (E.V.R.)

The Electrical Variable Resistance adjusts LCD driving voltage from V0 to V2.

(1-9) Key scan controller

The Key scan controller controls to input from external Key data.

(1-10) Key data buffer

The data buffer for key stores Key data until next key data is stored.

(1-11) CR Oscillator

The Oscillator is external connect resistor, which generates the master clock.

(1-12) Reset circuit

The Reset circuit is type of detectable voltage. It resets internal circuit when the power turns on or

drop the voltage.

Fig.1 Display data RAM (DDRAM) Map

Page address

Data

Display Pattern

Common

Drivers

COM1

COM2

COM3

COM4

COM5

COM6

D0="0"

PAGE 0

COM7

COM8

COM9

D0="1"

PAGE 1

COM10

D0="0" 00 01 02 03 04 05 06

3F 40

Column

Address

ADC

D0="1" 40

3F 3E

3D 3C

3B 3A

Segment Drivers 1

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64 65

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NJU6538

Ver.2003-05-09

(2) Instruction

3-wired Serial I/F is clock synchronized of the SCL clock. and D

to D

signal select data or instruction by

A0 signal.

The data input as MSB(D7) first serially.

Table 1. Instruction Code (*: Don't Care)

Code

Instruction

A0 D

Description

(a)

Display

ON/OFF

1 0 1 0 1

1 1 0/1

LCD display ON / OFF
D

=0 : OFF, D

=1 : ON

(b)

Page

address

set

1 0 1 1 0

0 0 0/1

Set the page of DDRAM to the page
address registor.
D

=0 : PAGE 0, D

=1 : PAGE 1

Culumn address set
Higher order 3-bits

0 0 0 1 *

Higher order

Column add.

Set the Higher order 3 bits column
address to rhe registor.

(c)

Culumn address set
Lower order 4-bits

0 0 0 0

Lower order

Column add.

Set the Lower order 4 bits column
address to rhe registor.

(d)

Display data write

Write data

Write the data into the Display data

RAM(DDRAM)

(e)

ADC

select

1 0 1 0 0

0 0 0/1

Set the DDRAM to SEG driver
D

=0 : Nomal, D

=1 : Inverse

(f)

Inverse display On / Off

0/1

Inverse LCD display ON / OFF
D

=0 : Nomal, D

=1 : Inverse

(g)

Whole display ON
/ Normal display

1 0 1 0 0

1 0 0/1

Whole Display tern ON
D

=0: Normal, D

=1: Whole Display

(h)

Reset 0

Initialize the internal circuit

(i)

E.V.R. Register Set

E.V.R. data

Set the Contrast control E.V.R.
(16 steps)

(j)

Duty select

Duty

Duty set (1/8,1/9,1/10)
(D

)=( 0,0,0) : 1/8Duty

)=( 0,0,1) : 1/9 Duty

)=( 0,1,0) : 1/10 Duty

(k)

Power save mode set

Power

save

Set the Power save mode
(D

)=(0,0) : Nomal

)=(0,1) : Power save 1

)=(1,0) : Power save 2

)=(1,1) : Power save 3

(l)

General output port
PWM phase / freqency set

0 1 0 1 0

Phase

Freq.

Set the PWM phase / freqency
D

: PWM Phase set

: PWM Freqenccy set

General output port serect

Port

Select the General output port for
PWM level set

General output port PWM set
High order 3-bits
/ PWM enable set

1 0 0 0

PWM

High order
PWM data

PWMEN=0:"L" output
PWMEN=1:PWM output
Set the Higher order 3 bits PWM
data to rhe registor.

(m)

General output port PWM set
Lower order 4-bits

0 1 1 1

Lower order

PWM data

Set the Lower order 4 bits PWM
data to rhe registor.

(n)

General output port /
Key scan output select

1 0 0 1 0

0 0 0/1

Select General output port or Key
scan output select by Po3/S

terminal
D

=0 : General output port

=1 : Key scan output

(o)

Maker test

Test data

Do not use this instruction.

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NJU6538

Ver.2003-05-09

(2-1) Instruction discription

(a) Display ON / OFF

This instruction selects display turn-on or turn-off regardless of the contents of the DDRAM.

A0 D

0 1 0 1 0 1 1 1 D

D 0: Display OFF

1: Display ON

(b) Page address set

In order to access to the DDRAM for writing or reading display data, both "page address set" and

"column address set" instructions are required before accessing.

The page address "0" should be used for icon display because the only D

to D

is valid.

The page address "1" should be used for icon display because the only D

to D

is valid.

A0 D

0 1 0 1 1 0 0 0 A

Page

0 0
1 1

As above-mentioned, in order to access to the DDRAM for writing or reading display data, it is

necessary to execute both "page address set" and "column address set" before accessing. The
8-bit column address data will be valid when both upper 3-bit and lower 4-bit data are set into the
column address register.

Once the column address is set, it will automatically increment (+1) whenever the DDRAM will be

accessed, so that the DDRAM will be able to be continuously accessed without "column address
set" instruction.

The column address will stop increment and the page address will not be changed when the last

address (40)H is addressed.

A0 D

0 0 0 0 1 * A

Upper

4-bit

0 0 0 0 0 A

Lower

4-bit

Column address (HEX)

0
0

:
:

0
0

:
:

0
0

:
:

0
0

:
:

0
0

:
:

0
0

:
:

0
1

:
:

00
01

:
:

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NJU6538

Ver.2003-05-09

(d) Display data write

This instruction writes display data into the selected column address on the DDRAM.
The column address automatically increments (+1) whenever the display data is written by this

instruction, so that this instruction can be continuously issued without "column address set"
instruction.

A0 D

1 *

Write

data

*:Don

t Care

(e) ADC

select

This instruction selects segment driver direction.
The correspondence between the column address and segment driver direction is shown in Fig.1.
Segment Driver Output order is inverse, when this instruction executes, therefore, the placement

NJU6538 against the LCD panel becomes easy.

A0 D

0 1 0 1 0 0 0 0 D

D 0: Clokwise Output(Normal)

1: Counterclockwise Output(Inverse) S

(f)

Inverse display ON / OFF

This instruction inverses the status of turn-on or turn-off of entire LCD pixels. It doesn't change

the contents of the DDRAM.

A0 D

0 1 0 1 0 0 1 1 D

D 0: Normal

RAM data "1" correspond to "On"

1: Inverse

RAM data "0" correspond to "On"

(g) Whole display ON

This instruction turns on entire LCD pixels regardless the contents of the DDRAM. It doesn't

change the contents of DDRAM. This instruction executed prior to the "Normal or Inverse display
On/Off Set" Instruction.

A0 D

0 1 0 1 0 0 1 0 D

D 0: Normal Display

(Whole display OFF)

1: Whole Display turns On

(Whole display ON)

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NJU6538

Ver.2003-05-09

(h) Reset

This instruction reset the LSI to the following status, however it doesn't change the contents of

the DDRAM. Please be careful that it can't be substituted for the reset operation by using of the
RESb terminal.

Reset status by "reset" instruction:

1. Page address : (0) page
2. Column address : (00)

3. EVR register : (D

, D

= "1, 1, 1, 1")

4. Duty select :1/10 Duty
5. General output port(Po0 to Po3) PWM phase / frequency (D

= "0,0")

6. General output port(Po0 to Po3) PWMEN=0,

PWM value (PWM

, PWM

= " 0,0,0,0,0,0,0")

7. Set the General output port (Po3) by Po3/S0 terminal

The DDRAM is not affected by this initialization.

A0 D

0 1 1 1 0 0 0 1 0

(i) EVR register set

E.V.R. resister set instruction adjusts the contrast of the LCD, and selects.
One LCD driving voltage VLCD out of 16 voltage-stages by setting E.V.R. register.
Set the binary code "0000" when contrast adjustment is unused.

A0 D

0 0 0 1 0

E.V.R.

data

LCD2

terminal level (Typical)

0 0 0 0

LCD1

0 0 0 1

0.984V

LCD1

0 0 1 0

0.968V

LCD1

0 0 1 1

0.952V

LCD1

0 1 0 0

0.938V

LCD1

0 1 0 1

0.923V

LCD1

0 1 1 0

0.909V

LCD1

0 1 1 1

0.896V

LCD1

1 0 0 0

0.882V

LCD1

1 0 0 1

0.870V

LCD1

1 0 1 0

0.857V

LCD1

1 0 1 1

0.845V

LCD1

1 1 0 0

0.833V

LCD1

1 1 0 1

0.822V

LCD1

1 1 1 0

0.811V

LCD1

1 1 1 1

0.800V

LCD1

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NJU6538

Ver.2003-05-09

(j) Duty

select

Duty select instruction is which sets LCD driving duty ratio 1/8 or 1/9 or 1/10 duty.

A0 D

0 0 0 1 1 0

Duty

Duty ratio

Scan Common

1/8 Duty

COM1 to COM8 (5x7 character + 1-icon )

1/9 Duty

COM1 to COM9 (5x7 character + 2-icon )

1/10 Duty

COM1 to COM10 (5x7 character + 3-icon )

(k) Power save mode set

Power save mode reduces the operating current of application using Display Off and selects a

terminal condition of Key scan signal output. The terminal, which is set to "L", does not output Key
scan signal as shown in following table.

A0 D

0 0 1 0 0 0 0

Power save

Key scanning output terminals

states *1

Function

Internal

OSC.

LCD output

0 0

Normal

H H H H H

Power save 1

Stop

Display Off

Power save 2

Stop

Display Off

Power save 3

Stop

Display Off

*1 No scanning states.

(l)

General output port PWM phase / freqency set

General output port PWM phase / frequency set instruction setting PWM phase and PWM

frequency.

A0 D

0 0 1 0 1 0 0 Phase

Frequency

General Output Port PWM phase set

32-steps shift phase PWM output timinng by Po0 to Po1, Po1 to Po2, Po2 to Po3.

same phase PWM output timinng by Po0 to Po3.

General Output Port PWM frequency set

fsys / 128 frequency. (Default)

fsys / 256 frequency.

(fsys : system clock = fosc / 2)

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NJU6538

Ver.2003-05-09

(m) General output port set.

This instruction sets the PWM value outputted from Po0 ~ Po3 terminals. The "General output

port select" instruction selects the general output port to output with PWM. The "General output port
PWM set" instruction sets the PWM value.

The "General output port select instruction" and the "General output port PWM set instruction" is

not necessary to continuously perform. Because these instructions are independently.

1. General output port select.

This instruction selects the general output port to output with PWM.

A0 D

0 0 1 1 0 0 0 Port

Port

0 0

Po0

0 1

Po1

1 0

Po2

1 1

Po3

2. General output port PWM set

This instruction sets the PWM value outputted from Po0 ~ Po3 terminals.
The PWM output setting is available for 128-step at each port output terminals.

A0 D

0 1 0 0 0

PWMEN PWM

PWM

0 0 1 1 1

PWM

A) PWMEN

0:Selected general output port is "L" output.

1:Selected general output port outputs PWM depending on PWM data.

B) PWM

to PWM

PWM value:This register sets the duty value of PWM outputted from the selected general output port.

The PWM value set requires twice, which are upper 3-bit and lower 4-bit.
The PWM duty is (Register + 1 ) / 128.

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NJU6538

Ver.2003-05-09

(*:Don't Care)

PWM

DUT

PWM

DUT

0 * *

0/128

1 0 0 0 0 0 0 65/128

0 0 0 0 0 0 0 1/128

1 0 0 0 0 0 1 66/128

0 0 0 0 0 0 1 2/128

1 0 0 0 0 1 0 67/128

0 0 0 0 0 1 0 3/128

1 0 0 0 0 1 1 68/128

0 0 0 0 0 1 1 4/128

1 0 0 0 1 0 0 69/128

0 0 0 0 1 0 0 5/128

1 0 0 0 1 0 1 70/128

0 0 0 0 1 0 1 6/128

1 0 0 0 1 1 0 71/128

0 0 0 0 1 1 0 7/128

1 0 0 0 1 1 1 72/128

0 0 0 0 1 1 1 8/128

1 0 0 1 0 0 0 73/128

0 0 0 1 0 0 0 9/128

1 0 0 1 0 0 1 74/128

0 0 0 1 0 0 1 10/128

1 0 0 1 0 1 0 75/128

0 0 0 1 0 1 0 11/128

1 0 0 1 0 1 1 76/128

0 0 0 1 0 1 1 12/128

1 0 0 1 1 0 0 77/128

0 0 0 1 1 0 0 13/128

1 0 0 1 1 0 1 78/128

0 0 0 1 1 0 1 14/128

1 0 0 1 1 1 0 79/128

0 0 0 1 1 1 0 15/128

1 0 0 1 1 1 1 80/128

0 0 0 1 1 1 1 16/128

1 0 1 0 0 0 0 81/128

0 0 1 0 0 0 0 17/128

1 0 1 0 0 0 1 82/128

0 0 1 0 0 0 1 18/128

1 0 1 0 0 1 0 83/128

0 0 1 0 0 1 0 19/128

1 0 1 0 0 1 1 84/128

0 0 1 0 0 1 1 20/128

1 0 1 0 1 0 0 85/128

0 0 1 0 1 0 0 21/128

1 0 1 0 1 0 1 86/128

0 0 1 0 1 0 1 22/128

1 0 1 0 1 1 0 87/128

0 0 1 0 1 1 0 23/128

1 0 1 0 1 1 1 88/128

0 0 1 0 1 1 1 24/128

1 0 1 1 0 0 0 89/128

0 0 1 1 0 0 0 25/128

1 0 1 1 0 0 1 90/128

0 0 1 1 0 0 1 26/128

1 0 1 1 0 1 0 91/128

0 0 1 1 0 1 0 27/128

1 0 1 1 0 1 1 92/128

0 0 1 1 0 1 1 28/128

1 0 1 1 1 0 0 93/128

0 0 1 1 1 0 0 29/128

1 0 1 1 1 0 1 94/128

0 0 1 1 1 0 1 30/128

1 0 1 1 1 1 0 95/128

0 0 1 1 1 1 0 31/128

1 0 1 1 1 1 1 96/128

0 0 1 1 1 1 1 32/128

1 1 0 0 0 0 0 97/128

0 1 0 0 0 0 0 33/128

1 1 0 0 0 0 1 98/128

0 1 0 0 0 0 1 34/128

1 1 0 0 0 1 0 99/128

0 1 0 0 0 1 0 35/128

1 1 0 0 0 1 1 100/128

0 1 0 0 0 1 1 36/128

1 1 0 0 1 0 0 101/128

0 1 0 0 1 0 0 37/128

1 1 0 0 1 0 1 102/128

0 1 0 0 1 0 1 38/128

1 1 0 0 1 1 0 103/128

0 1 0 0 1 1 0 39/128

1 1 0 0 1 1 1 104/128

0 1 0 0 1 1 1 40/128

1 1 0 1 0 0 0 105/128

0 1 0 1 0 0 0 41/128

1 1 0 1 0 0 1 106/128

0 1 0 1 0 0 1 42/128

1 1 0 1 0 1 0 107/128

0 1 0 1 0 1 0 43/128

1 1 0 1 0 1 1 108/128

0 1 0 1 0 1 1 44/128

1 1 0 1 1 0 0 109/128

0 1 0 1 1 0 0 45/128

1 1 0 1 1 0 1 110/128

0 1 0 1 1 0 1 46/128

1 1 0 1 1 1 0 111/128

0 1 0 1 1 1 0 47/128

1 1 0 1 1 1 1 112/128

0 1 0 1 1 1 1 48/128

1 1 1 0 0 0 0 113/128

0 1 1 0 0 0 0 49/128

1 1 1 0 0 0 1 114/128

0 1 1 0 0 0 1 50/128

1 1 1 0 0 1 0 115/128

0 1 1 0 0 1 0 51/128

1 1 1 0 0 1 1 116/128

0 1 1 0 0 1 1 52/128

1 1 1 0 1 0 0 117/128

0 1 1 0 1 0 0 53/128

1 1 1 0 1 0 1 118/128

0 1 1 0 1 0 1 54/128

1 1 1 0 1 1 0 119/128

0 1 1 0 1 1 0 55/128

1 1 1 0 1 1 1 120/128

0 1 1 0 1 1 1 56/128

1 1 1 1 0 0 0 121/128

0 1 1 1 0 0 0 57/128

1 1 1 1 0 0 1 122/128

0 1 1 1 0 0 1 58/128

1 1 1 1 0 1 0 123/128

0 1 1 1 0 1 0 59/128

1 1 1 1 0 1 1 124/128

0 1 1 1 0 1 1 60/128

1 1 1 1 1 0 0 125/128

0 1 1 1 1 0 0 61/128

1 1 1 1 1 0 1 126/128

0 1 1 1 1 0 1 62/128

1 1 1 1 1 1 0 127/128

0 1 1 1 1 1 0 63/128

1 1 1 1 1 1 1 128/128

0 1 1 1 1 1 1 64/128

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NJU6538

Ver.2003-05-09

Example ) Set output PWM waveform of Po0 to Po3 terminal, shown below:

�

PWM phase set D

=0,

�

PWMEN=1,

�

(PWM

PWM

)=(1,0,0,0,0,0,0)

PWM frequency (f

PWM

)

Po0 1 65 66 128

Po1 1 65 66 128

Po2 1 65 66 128

Po3 1 65 66

32-steps 32-steps 32-steps

(n) General output port / Key scan output select

This instruction assigns function of general purpose output port or key scan output to Po3/S0

terminals.

A0 D

0 1 0 0 1 0 0 0 D

D 0: General output port
1:

Keyscan

output

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NJU6538

Ver.2003-05-09

(3) Input Data Format and Timing

Data format is shown below.
When the CE terminal goes to "L", I/F is data output.
When the CE terminal goes to "H" (rising edge) at SCL terminal "H", I/F is data input.

NOTE1) Data fetched at SCL rising edge.

NOTE2) A contents change of the instruction and data which were written is fetched by the 9th rising edge of

SCL.

NOTE3) When the instruction and data which were written are less than 9-bit, they are ignored and is not fetched.
NOTE4) When the instruction and data which were written are over 9-bit, the last 9-bit is valid.

(4) Power save mode set

Power save mode is set by "Power save mode set" instruction. The segment and common output "L" is

outputted, the OSC terminal halts an oscillation (it oscillates at the time of key-on), and consumption current
is decreased.

Power save mode is canceled, when normally set by "Power save mode set" instruction.

(5) Key scan circuit

Key scan circuit connects the 5 x 5 key-matrix maximum and reads the data of 25 keys maximum. It

chooses the number of keys in key-matrix by "General output port / key scan output select" instruction.

It outputs a identified key data to MPU after comparison with two data read from the key-matrix in twice for

reliable key operation. If those data are not identified, key data is not outputted. It outputs "L" signal through
"SO" terminal as the request after 332T[s] (T=1/fsys=2/fosc,fsys : Internal system clock frequency) when
any key is operated. Furthermore, the key scan circuit structures for reducing the external components like as
Diodes to prevent circuit short problem.

(5-1) The relation between output data and key matrix

The relation between output data and key matrix shows bellow table and sets "1" signal for operated

key.

In case of 20 keys application, unassigned area for keys from KD1 to KD5 in bellow table take "0"

signal.

In mode of Power save 1, area for keys from KD1 to KD20 in bellow table take "0" signal. In mode of

Power save 2, area from KD1 to KD15 take "0" signal also. The terminals, which are not connected any
keys, should be open.

KD1 KD2 KD3 KD4 KD5

KD6 KD7 KD8 KD9 KD10

KD11 KD12 KD13 KD14 KD15

KD16 KD17 KD18 KD19 KD20

KD21 KD22 KD23 KD24 KD25

* D7 D6 D5 D4 D3 D2 D1 D0 A0 *

SIO

SCL

Output Input Output

SIO state

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NJU6538

Ver.2003-05-09

(5-2) Data output timing

The data output format shows bellow. The data output mode is set by "L" status of SCL terminal at the

rising signal of CE terminal.

(5-3) Power save flag (PSF)

The status of Power save flag is outputted after KD25 in Key data reading. This flag sets "1" signal in

mode of Power save in Key data reading and sets "0" in mode of Normal.

(5-4) Timing of Key scan

Key scan cycle is 160T[S] (T=1/fsys=2/fosc,fsys : Internal system clock frequency). The data of key

scan is a result of comparison with a couple of Key scan for correct judge whether Key On or Off. When
the result of comparison is correct (accord), the NJU6538 recognizes Key On and outputs "L" level from
SIO terminal after 322T[S] from start of Key scan for a request to read key data out to external MPU.
When the SIO terminals outputs "L" signal, the key scan does not operate until end of key data reading
by MPU, and scanned key data is kept. When the result of comparison is incorrect (not accord), Key
scan operates again if any key is On. Therefore, Key scan may operate incorrectly in case of shorter
period of Key on than 322T[S]

*1 Instruction set the General output ports or output the Key scan signals (refer (1)Instruction (n)General output port

/ Key scan select)

Key scan cycle and the timing of Key data read out request are constant in any Power save mode.

Output Output Output

* KD1 KD2 KD24 KD25 PSF

Key data

SCL

SIO

T=1/fsys =2/fosc

(

fsys : Internal system clock frequency

)

SIO

322T [s]

160T[s]

Key ON

SIO state

- 16 -

NJU6538

Ver.2003-05-09

(5-5) Normal mode

Key scan operates with follows in normal mode.

1, Key scan signal output terminals S0 � S4 output "H" signals when key scan does not operate, and output key scan

signals after start of key scan operation. The conditions of key scan signal input terminals K0 � K4 are "L" state with
internal pull-down resistances, though "H" signal comes in to K0 � K4 corresponding to the turned on keys.

2, The function of key scan starts twice operations when any key is turned on. It stops when a couple of data by

continuously twice key scan operations are accorded and fixed as a correct key status. It operates more 2 times when
the key status is not fixed and any keys are still turning on. It repeats again and again until key status is fixed. The
correct key status data is stored and newly key scan operation does not start until external MPU reads data out after
key status is fixed.

3, When the key status is fixed, SO terminal outputs "L" signal as Key data read out request to MPU. MPU should read

key data out at detection of this "L" signal.

4, The Key data read out request signal is released and SO terminal outputs "H" signal after finish of MPU key data read

out for newly key scan operation.

SIO terminal requires pull up resistor because of Open drain type output. Multiple data of key are output in case of key

more input so that MPU should process the data by itself.

Key scan example (Normal mode)

Key data read

request

Key data read

request

Key data read

T = 1 / fosc

Key input 1

Key input 2

Data send

Key scan

322T[s]

SCL

Data send

Key data read

request

- 17 -

NJU6538

Ver.2003-05-09

(5-6) Power save mode

Key scan operates with follows in Power save mode.

1, Key scan signal output terminals S0 � S4 output "H", "L" signals by the Power save mode set when key scan does not

operate (refer the detail of instructions), and output key scan signals after start of key scan operation. The conditions of
key scan signal input terminals K0 � K4 are "L" state with internal pull-down resistances, though "H" signal comes in to
K0 � K4 corresponding to the turned on keys.

2, The oscillation circuit function of key scan starts twice operations when any keys on cross points with S0� S4 terminals

line and K0 � K4 turned on. It stops when a couple of data by continuously twice key scan operations are accorded and
fixed as a correct key status. It operates more 2 times when the key status is not fixed and any keys are still turning on.
It repeats again and again until key status is fixed. The correct key status data is stored and newly key scan operation
does not start until external MPU reads data out after key status is fixed.

3, When the key status is fixed, SIO terminal outputs "L" signal as Key data read out request to MPU. MPU should read

key data out at detection of this "L" signal.

4, The Key data read out request signal is released and SIO terminal outputs "H" signal after finish of MPU key data read

out for newly key scan operation. Although Power save mode is not released.

SIO terminal requires pull up resistor because of Open drain type output. Multiple data of key are output in case

of key more input so that MPU should process the data by itself.

Key scan example (Power save mode)
Ex.) D0= "0", D1= "1" (K4="H" power save)

*1 These diodes are required to recognize

key more input

of keys on the K4 line when only K4 terminal outputs "H"

signal in power save mode as shown above example. In case of no diodes, incorrect key data may read out
sometimes by

key more input

of keys on lines of K0 to K4.

T=1/fsys =2/fosc

(

fsys : Internal system clock frequency

)

When some key on these lines are turned on, the
oscillation starts and Key scan starts the operation until all
of key are turned off.

"L"

"H"

Data send

Key input

(K4)

Key scan

322T[s]

SCL

Key data read

request

Key data read

request

Key data read

T = 1 / fosc

- 18 -

NJU6538

Ver.2003-05-09

(5-7) Key More Input

Key scan signal output terminal S0 to S4 output "H" level in state of Key More Input. Although Key state

is detected without diodes to prevent unexpected key scan signal flow, non-pressed key data may
change pressed key data in triple or more key Input as shown in Fig. 1 and incorrect key data may be
output to external MPU. For prevention of miss-recognition by incorrect key data, diodes should be
inserted in front of K0 � K4 terminals as shown in Fig. 3 or control program of MPU should ignore the
combination of key data miss-recognition. For example, 4 keys and more ON data should be ignored.

Fig. 1

Miss-recognized example by

key more input

In modes of power save 1 (S0=0, S1=1 / Keys on only S5 line are valid) or power save 2 (S0=0, S1=1

/ Keys on only S4 and S5 lines are valid), pay attention about the followings. When Key More Input is
operated across the valid line and invalid, non-pressed key is miss-recognized as pressed key. However,
Key data on the invalid line is not read out and 4 keys and more operation in the mean time are not
ignored by MPU control program as shown in Fig. 2. In this case, diodes operate to prevent
miss-recognition as shown in Fig. 3.

Fig. 2 Miss-recognition in

power save 1

Fig. 3 Connect miss-recognition prevent diodes

Pressed key

Miss-recognized key

In case of 3 keys operation in left
picture, if S3 terminal outputs "H"
signal, this signal goes around on
the dotted line and non-pressed key
is miss-recognized as pressed key.

In case of power save 1, MPU control program can not
decide ether correct key data or incorrect as shown
above because key data on only S4 line is read out to
MPU (all of key data on S3 line become to "0".

Pressed key

Miss-recognized key

Miss-recognition
prevent diodes

No active key

Active key

- 19 -

NJU6538

Ver.2003-05-09

(5-8) Key data reading out operation by external MPU

(a) Display data writing

Display data and an instruction change operate at the rising edge of 9-bit on SCL signal.

(b) Key data reading out operation

The minimum period from Key in to SIO terminal = "L" is 322T(t1) by key scan operation. When

key scan operation performs again for key data fix preventing from noise or bouncing of key, the
period from Key in to SIO terminal = "L" is 676T(t1). When the SIO terminal outputs "L", the key
scan operation is stopped after execution of key data reading out operation. Therefore, fixed key
data is kept until end of key data reading out operation. When key data reading out operation is
performed during SO terminal = "H", both of key data from KD1 to KD25 and power save flag (PSF)
are not outputted correctly.

Key data reading out operation example

The flowchart below shows an example of timer interrupt application. When SIO terminal

condition is "L" after check of SIO terminal condition at every timer interrupt operation, it is decided
as Key In and key data reading out operation is performed. When SIO terminal condition is "H, it is
decided as Key Off. For the correct decision of Key Off, the timer interrupt cycle (1/t3) should be
expanded over the time added with [period of key scan (676T in case of measure against key
bouncing of key) and [period of key data reading out operation (t2)]. In this time, the period of timer
interrupt cycle (t3) must be set with enough margins including the range of fosc.

Sequence of key data reading out operation

Timer

SO="L"?

Key OFF

Key ON

Key data

read out

End of Timer

Yes

- 20 -

NJU6538

Ver.2003-05-09

Timing chart of key data reading out operation

(6) Reset circuit initializes

Reset circuit initializes the NJU6538 at Power ON and OFF. It generates reset signal to initialize the

system at low VDD less than power down detection voltage (2.0V typical).

(6-1) Initial status in reset

1, Stop the oscillation circuit
2, Display Off (Available Serial data transmission)
3, Disable Key scan function
4, Filled "L"" data in all of key data buffer

(6-2) The status of output port terminals in Reset

*1 This terminal operates as segment driver and outputs "L".
*2 This terminal consisted of Open-drain output type circuit requires external pull-up resister connect ting to

external power source for MPU. I f key data read is executed in power on reset, the read data is fixed as "H".

The reset circuit initializes the LSI to the following status by using of the input 10

�

s(min.) or over "L"

level signal into the RESb terminal. The LSI will return to normal operation after about 1.0

�

s(max.)

from the rising edge of the rest signal. The "Reset" instruction can't be substituted for the reset
operation by using of the RESb terminal. It executes above-mentioned only 7 to 13 items.

Output terminals

Reset status

SEG

to SEG

COM

to COM

Po0 to Po2

Po3/S

L *1

to S

SIO

H *2

t1: Key scan time
t2: Key data read time
t3: Interrupt cycle

*: t3 > t1 + t2

Key input

Decision

Interrupt

SCL

Key ON

t1 t2

Key ON

Key OFF

- 21 -

NJU6538

Ver.2003-05-09

(6-3) Reset status using the RESb terminal (default)

1. Serial interface register clear
2. Display off
3. ADC select

: D

="0" (Normal mode)

4. Normal Display (Non-inverse display)
5. Whole display off

: D

="0" (Normal mode)

6. Power save mode : D

, D

="0, 0" (Normal mode)

7. Page address

: 0 page

8. Column address

: 00

9. EVR register

: D

, D

="1, 1, 1, 1"

10. Duty select

: 1/10 Duty

11. General output port PWM phase and frequency : D

, D

="0, 0"

12. General output port : PWMEN=0 ("L" output),

PWM value : D

, D

="0, 0, 0, 0, 0, 0, 0"

13. Po3/S0 terminal : D

=" 0" (Po3)

(6-4) Initialization by Hardware

The NJU6538 incorporates reset terminal to initialize the all system. When the "L" level signal input

over then 10us(min.) to the RESb terminal, reset sequence is executed. In this time, internal busy during
1us after RESb terminal goes to "H".

Reset circuit

(6-5) Power on reset operation

When the voltage rising time of power source is over than 1mS, the generated signal of VDET

initializes the system of NJU6538 as reset. When the voltage falling time of power source is over than
1ms, the system is also reset.

When these voltage rising or falling time of power source are not over than 1ms, the Initialization

operation as reset does not operate correctly.

VDET

>1 ms

2.7V

OFF

>1 ms

VDET

Power on Reset

Hardware Reset

System Reset

RESb

- 22 -

NJU6538

Ver.2003-05-09

(7) LCD panel drive

(7-1) LCD driving voltage generation circuit

LCD driving voltage generation circuit generates LCD driving bias voltages V

LCD2

, V0, V1 and V2. It

adjusts the voltage by 8 steps electrical volume from V

LCD1

and allots the voltage to V

LCD2

, V0, V1 and V2

by resistor-voltage-dividing as shown in below.

VLCD1, VLCD2, V0, V1 and V2 terminals requires external capacitors for bias voltage stabilization

for display quality. These values of capacitors should be fixed in accordance with evaluation in the
application.

Duty ratio

1/8,1/9,1/10

Power

Supply

Bias 1/4

LCD

LCD2

-V

Note 1 : Resistor is typical value.

LCD2

Internal NJU6538

10k

(Note 1)

E.V.R. (16-steps)

VLCD

10k

(Note 1)

10k

(Note 1)

10k

(Note 1)

LCD1

10k

(Note 1)

- 23 -

NJU6538

Ver.2003-05-09

ABSOLUTE MAXIMUM RATINGS

Ta=25

�

PARAMETER SYMBOL

CONDITIONS

RATINGS UNIT

VDD max

terminal -0.3

+7.0

Supply voltage

VLCD max V

LCD1

terminal -0.3

+11.0

IN1

OSC, K

to K

,CE, SCL, SIO terminal

-0.3 to VDD+0.3

Input terminal voltage

IN2

LCD2,

to V

terminal -0.3

VLCD+0.3

OUT1

SIO terminal

-0.3 to +6.0

Output terminal voltage

OUT2

OSC, SEG

to SEG

,COM

to COM

to S

, Po

to Po

terminal

-0.3 to VDD+0.3

Ta=25

�

C QFP100-C2

1000

Power dissipation

Pdmax

Ta=25

�

C QFP100-G1

700

Storage temperature

Tstg

-55 to +125

�

Operating temperature

Topr

-40 to +85

�

Note 1)

All voltage values are specified as V

=0V.

Note 2)

If the LSI are used on condition beyond the absolute maximum rating, the LSI may be destroyed.

Using LSI within electrical characteristics is strongly recommended for normal operation.
Use beyond the erectric characteristics conditions will cause malfunction and poor reliability.

Note 3)

Decoupling capacitor should be connected between VDD and VSS due to the stabilized operation
forthe voltage converter.

- 24 -

NJU6538

Ver.2003-05-09

DC Electrical Characteristics

VDD=2.7 to 5.5V, Ta= - 40 to 85

�

PARAMETER

SYMBO

CONDITION MIN

TYP

MAX

UNIT

NOT

Power supply (1)

VDD VDD

2.7

5.5

Power supply (2)

VLCD1 VLCD1

5.0

10.0

Output voltage

VLCD2 VLCD2

4.0

VLCD1

V0 V0

VSS

VLCD2x3/4 VLCD2

V1 V1

VSS VLCD2x2/4 VLCD2

Input voltage

V2 V2

VSS VLCD2x1/4 VLCD2

V 1

"H" level input voltage (1)

VIH(1) K

to K

0.6VDD

VDD

"H" level input voltage (2)

VIH(2) SCL, SIO, CE

0.8VDD

VDD

"L" level input voltage (1)

VIL(1)

to K

, SCL, SIO, CE

0.2VDD

Hysteresis voltage

SCL, SIO, CE

0.25VDD

"H" level input current

SCL, SIO, CE,

= VDD

5.0

�

"L" level input current

SCL, SIO, K

to K

, CE,

= 0V

-5.0

�

Pull-up resistance

RESb VDD=5.0V,

= 0V

50 150 250

Pull-down resistance

to K

, VDD=5.0V,

= VDD

50 150 250

Output off-leak current

IOFFH SIO, VO=5.5V

6.0

�

VDD=5.0V,

Io = -500uA

VDD-1.2 VDD-0.2

"H" level output
voltage (1)

VOH(1)

to S

VDD=3.0V,

Io = -250uA

VDD-1.1 VDD-0.1

VDD=5.0V,

Io = -10mA

VDD-1.0

"H" level output
voltage (2)

VOH(2)

to Po

VDD=3.0V,

Io = -5mA

VDD-0.6

VDD=5.0V,

Io = 25

�

0.2 1.5

"L" level output voltage (1)

VOL(1)

to S

VDD=3.0V,

Io = 5

�

0.05 0.6

VDD=5.0V,

Io = 10mA

1.0

"L" level output voltage (2)

VOL(2)

to Po

VDD=3.0V,

Io = 5mA

0.6

"L" level output voltage (3)

VOL(3) SIO

Io = 1mA

0.5

Driver
ON-resistance (COM)

COM

Ta=25

�

, VO=V

LCD2

,VSS,V0,V2

+Id=1

�

A (COM terminal)

Driver
ON-resistance (SEG)

SEG

Ta=25

�

, VO=V

LCD2

,VSS,V1

+Id=1

�

A (SEG terminal)

Oscillation Frequency

OSC

Ta=25

�

, VDD=5.0V

OSC

=150k

38 50 62

kHz

V0 5.8

6.0

6.2

V1 3.8

4.0

4.2

LCD Driving voltage

E.V.R. value "0,0,0,0"
V

LCD1

=8.0V

1.8 2.0 2.2

Bleeder resistance

VLCD2-VSS,

Ta=25

�

E.V.R. resistance

EVR

VLCD1-VLCD2,

Ta=25

�

Power down
detect voltage

VDET

0.8

1.4

2.0

Reset time

RESb

1.0

�

Reset "L" pulse width

Trw

RESb

10.0

�

IDD1

Power save mode

100

�

IDD2

VDD=5.5V,
Output open f

OSC

=50kHz,

500

�

ILCD1

Power save mode

�

Operating current

ILCD2

VLCD1=10.0V
Output open f

OSC

=50kHz,

1000

�

Note 1)

The relation : VLCD1

VLCD2

VSS must be maintained.

Note 2)

RCOM and RSEG are the resistance values between power supply terminals (VSS, VLCD2, or V0, V1,

V2) and each common terminal, and supply voltage (VSS, VLCD2, or V0, V1, V2) and each segment
terminal respectively, and measured when the current Id is flown on every common and segment
terminals at a same time.

- 25 -

NJU6538

Ver.2003-05-09

AC Characteristics

VDD=2.7 to 5.5V, Ta= - 40 to 85

�

PARAMETER

SYMBOL

CONDITION MIN

TYP

MAX

UNIT

NOTE

"L" level
clock pulse width

WCLL

SCL

160

"H" level
clock pulse width

WCLH

SCL

160

Data setup time

SCL,

SIO

160

Data hold time

SCL,

SIO

160

CE wait time

CE,

SCL

160

CE setup time

CE,

SCL

160

CE hold time

CE,

SCL

160

CE "L" level width

WCL

160

SIO output delay time

SIO,

Rpu=4.7k

, CL=10pF

1.5

�

SIO rise time

SIO,

Rpu=4.7k

, CL=10pF

1.5

�

SCL rise tine

SCL fall time

SO terminal is Open-Drain type output, so that the characteristics of SO terminal are changed by values of pull-up resistance
Rpu and CL.

(1) Write operation

(2) Key data read operation

SCL

SIO

WCLH

WCLL

SCL

SIO

WCLL

WCLH

WCL

INVALID

- 26 -

NJU6538

Ver.2003-05-09

Relation between oscillation frequency and LCD frame frequency

(1)1/8 duty

Ex.)fosc=50kHz
Frame frequency =1/(40T x duty)=1/(40 x (2/50kHz) x 8)=78.1(Hz)

(2)1/10 duty

fosc=50kHz
Frame frequency =1/(35T x duty)=1/(35 x (2/50kHz) x 10)=71.4(Hz)

COM1

SEGn

1 2 3 4

8 1 2 3

LCD2

1frame

1 line select time(40 T[s])

LCD2

6 7

1 2 3

1 2 3 4

8 1

2 3

6 7

OFF

COM1

SEGn

1 2 3 4

1 2 3

LCD2

1frame

1 line select time(35 T[s])

LCD2

5 6

6 7

1 2 3 4

1 2 3 4 8

5 6

6 7

9 10

OFF

T = 1/fsys = 2/fosc
(

fsys : Internal system clock frequency

)

T = 1/fsys = 2/fosc
(

fsys : Internal system clock frequency

)

- 27 -

NJU6538

Ver.2003-05-09

APPLICATION CIRCUIT

*1 The rising time of Power source voltage at Power on and the falling time at Power off must keep over than 1ms

because of Voltage detection type Reset circuit operation.

*2 SO terminal requires external pull-up resistor connecting to Power source of external MPU because of Open-drain

type output.

*3 This capacitor for bias voltage stabilization should be connected in accordance with display quality in application.
*4 P

/ S

terminal is general output ports and Key scan signal output duplicated-function terminals. A function must be

selected either Segment output or other.

COM

MPU

RESb
CE
SC
SIO

V

LCD1

LCD2

General output ports

NJU6538

5 x5 key matrix *4

LCD

----

COM

SEG

----

SEG

7com 65seg matrix
+195 icon LCD panel

OSC

[CAUTION]

The specifications on this databook are only

given for information , without any guarantee
as regards either mistakes or omissions. The
application circuits in this databook are
described only to show representative usages
of the product and not intended for the
guarantee or permission of any right including
the industrial rights.

Электронный компонент: NJU6538