NT3882

Dot Matrix LCD 40-Channel Driver

V2.0 November, 1999

Features

Provides a 40 channel LCD driver

Internal serial to parallel conversion circuits:

20-bit shift register X 2
40-bit latch X 1
40-bit 4 level driver X 1

Logic circuit supply voltage range: 4.5V - 5.5V

LCD driving voltage range (V

- V

): 3.5V to 11V

Applicable LCD duty cycle: 1/2 to 1/16

Interfaces with a NT3881C/D LCD controller

LCD bias voltage can be supplied externally

Available in 64-pin QFP and in CHIP FORM

General Description

The NT3882 is a dot matrix LCD 40 channel driver
fabricated by low power CMOS technology. This IC
consists of two 20-bit shift registers, a 40-bit latch, and a
40-bit 4 level LCD driver. The NT3882 converts serial
data which is received from the LCD controller

(NT3881C/D) to parallel data and then outputs LCD
driving waveforms to drive LCD. Expansion of character-
type liquid crystal display can be easily obtained
according to the number and structure of characters.

Pin Configuration

Pad Configuration

1 0

1 1

1 2

1 3

1 4

1 5

1 6

1 7

1 8

1 9

2 0

2 1

2 2

2 3

2 4

2 5

2 6

2 7

2 8

2 9

3 0

3 1

3 2

3 3

3 4

3 5

3 6

3 7

3 8

3 9

4 0

4 1

4 2

4 3

4 4

4 5

4 6

4 7

4 8

4 9

5 0

5 1

N C

S 2 9

S 2 8

S 2 7

S 2 6

S 2 5

S 2 4

S 2 3

S 2 2

S 2 1

S 2 0

S 1 9

S 1 8

S 1 7

S 1 6

S 1 5

S 1 4

S 1 3

S 1 2

1
0

1
1

N
C

N C

C L 1

C L 2

G N D

D L 1

D R 1

D L 2

D R 2

N C

V 3

N C

V 2

S
4
0

S
3
9

S
3
8

S
3
7

S
3
6

S
3
5

N
C

S
3
0

S
3
1

S
3
2

S
3
3

S
3
4

N
C

NT3882F

N C

5 2

5 3

5 4

5 5

5 6

5 7

5 8

5 9

6 0

6 1

6 2

6 3

6 4

1 0

1 1

1 2

1 3

1 4

1 5

1 6

1 7

1 8

6 3

6 2

6 1

6 0

5 9

5 7

5 6

5 5

5 4

5 3

5 2

1 9

2 0

2 1

2 2

2 3

2 4

2 7

2 8

2 9

3 0

3 1

5 1

4 8

4 6

4 2

4 0

3 9

3 8

3 7

3 6

3 5

3 4

3 2

S 2 8

S 2 7

S 2 6

S 2 5

S 2 4

S 2 3

S 2 2

S 2 1

S 2 0

S 1 9

S 1 8

S 1 7

S 1 6

S 1 5

S 1 4

S 1 3

S
1
2

S
1
0

1
1

S
8

S
5

S
4

S
3

S
4
0

S
3
9

S
3
8

S
3
7

S
3
6

S
3
5

S
3
0

S
3
1

S
3
2

S
3
3

S
3
4

S
2
9

NT3882H

2 5

S 1

C L 1

C L 2

G N D

D L 1

D R 1

D L 2

D R 2

V 3

V 2

NT3882

Pin and Pad Descriptions

Pin No.

Pad No.

Designation

I/O

External Connection

Description

2- 24,

27 - 32,
52 - 57,

59 - 63

27 - 32,

2 - 24,

52 - 57,

59 - 63

S29 - S7,

S6 - S1,

S40 - S35,

S30 - S34

LCD panel

Segment signal output pins

Power supply

Power for logic circuits

CL1

Controller

Clock to latch serial data

CL2

Controller

Clock to shift serial data

GND

Power Supply

DL1

Controlleror NT3882

Data input of 1 - 20 bits from controller

DR1

NT3882

Data output of 20 bit shift register

DL2

Controlleror NT3882

Data input of 21 - 40 bits from controller

DR2

NT3882

Data output of 40 bit shift register

Controller

Alternate signal for LCD drivers

46, 48, 51

, V

Power Supply

Power for LCD drivers

1, 26, 33, 41,

43 - 45, 47,

49, 50, 58,

No connection

Functional Description

NT3882 is a dot matrix LCD segment driver LSI. It
operates with the controller, such as NT3881C/D, and/or
another segment driver LSI NT3882. NT3882 receives
serial data from the controller or another NT3882,
converts it to parallel data and then supplies the LCD
driving waveforms to the LCD panel.

1. CL1

This signal is used for latching the shift register contents.
When CL1 is set at high, the shift register contents are
transferred to the 40-bit 4level LCD driver. When CL1 is
set at low, the last display output data (S1 to S40) is
held.

2. CL2

Clock pulse inputs for the two 20-bit shift registers. The
data is shifted to a 40-bit latch at the falling edge of CL2.
The clock singal CL2 must be active when operating to
refresh shift registers' contents.

3. DL1

The 1 - 20 bit data from LCD controller is fed into the
first 20-bit shift register through DL1.

4. DR1

The 20th bit data of first 20-bit shift register output from
DR1. The data shifted out from DR1 after 20 bit delay
are synchronized with the clock pulse (CL2). By
connecting DR1 to DL2, two 20-bit shift registers can be
cascaded to one 40-bit shift register.

5. DL2

The 21 - 40 bit data from the LCD controller is fed into
the second 20-bit shift register through DL2.

6. DR2

The 40th bit data of the second 20-bit shift register
output is from DR2. The data shifted out from DR2 after
a 20-bit delay is synchronized with the clock pulse (CL2).
By connecting DR2 to the next NT3882 DL1, the cascade
construction is obtained to drive a wider LCD panel.

7. S1 to S40

These 40 bits represent the 40 data bits in the 40-bit
latch. One of V

, V

and V

is selected as a LCD

driving voltage source according to the combination of
latched data level and the alternate signal (M).

NT3882

The truth table is listed as follows:

Latched Data

Output level of S1 to S40

1(High)

(Selected)

0(Low)

1(High)

(Nonselected)

0(Low)

Absolute Maximum Ratings*

Power Supply Voltage (V

-GND) . . . . . . . -0.3V to 7.0V

Power Supply Voltage (V

-V

) . . . . . . . . . . . . . . . . . .

. . . . . . . . . . . . . . . . . . . . . . . V

- 13.5V to V

+ 0.3V

Input Voltage . . . . . . . . . . . . . . . . . .-0.3V to V

+ 0.3V

Operating Temperature . . . . . . . . . . . . . -20

C to + 75

Storage Temperature . . . . . . . . . . . . . .-55

C to + 125

*Comments

Stresses above those listed under "Absolute Maximum
Ratings" may cause permanent damage to this device.
These are stress ratings only. Functional operation of
this device at these or any other conditions above those
indicated in the operational sections of this specification
is not implied or intended. Exposed to the absolute
maximum rating conditions for extended periods may
affect device reliability.

DC Electrical Characteristics (V

= 5.0V, GND = 0V, V

= 0V, T

= 25

Symbol

Parameter

Terminal

Min.

Typ.

Max.

Unit

Conditions

Input Voltage

CL1, CL2

0.7 X V

DL1, DL2

0.3 X V

Output Voltage

DR1, DR2

- 0.4

= -0.4mA

0.4

= 0.4mA

Vi-Sj Voltage

Note 1

1.1

= 0.1mA for one of Sj

Descending

105

= 0.05mA for each of Sj

Input Leakage
Current

CL1, CL2
DL1, DL2

-5

= 0 or VDD

Vi Leakage
Current

, V

-10

S1 to S40 open

Power Supply
Current

Note 2

200

CL1

= 1KH

CL2

= 400KHz

Note 1: V

- S

= V

, V

; j = 1 to 40) equivalent circuit.

1Kmax.

Power

Switch

Data

Swtich

Note 2: Input/output current is excluded. When the input is at the intermediate level with CMOS, some excessive current

will flow through the input circuit to the power supply. To avoid this, the input level must be fixed at a high or low
state.

NT3882

AC Characteristics

= 5.0V, GND = 0V, V

= 0V, T

= 25

Symbol

Parameter

Terminal

Min.

Typ.

Max.

Unit

CL2

Data Shift Frequency

CL2

400

KHz

CW H

Clock Width

High

CL1, CL2

800

CW L

Low

CL2

800

Data Hold Time

DL1, DL2

300

SUD

Data Set-up Time

DL1, DL2

300

SUC1

Clock Set-up Time (CL2

CL1)

CL1, CL2

500

SUC2

Clock Set-up Time (CL1

CL2)

CL1, CL2

500

Clock Rise/Fall Time

CL1, CL2

200

Data Delay Time

500

Timing Waveforms

CWH

CWL

SUD

SUC1

SUC2

CWH

CL2

DL1,DL2

DR1,DR2

CL1

Электронный компонент: NT3882F