NT6862-5xxxx
8-Bit Microcontroller for Monitor
1
V2.2
Features
n
Operating voltage range: 4.5V to 5.5V
n
CMOS technology for low power consumption
n
6502 8-bit CMOS CPU core
n
8 MHz operation frequency
n
32K/24K/16K bytes of ROM
n
512 bytes of RAM
n
One 8-bit base timer
n
13 channels of 8-bit PWM outputs with 5V open drain
n
4 channel A/D converters with 6-bit resolution
n
25 bi-directional I/O port pins (8 dedicated I/O pins)
n
Hsync/Vsync signals processor for separate &
composite signals which includes hardware sync
signals polarity detection and frequency counters with
2 sets of Hsync counting intervals
n
Hsync/Vsync polarity controlled output, 5 selectable
free run output signals and self-test patterns, auto-
mute function, half freq. I/O function
n
Add a jitter filter at the front end of Hsync input path,
reduce the jitter interference of Hysync input
n
Two built-in I
2
C bus interfaces support VESA
DDC1/2B+
n
Two layers of interrupt management
NMI interrupt sources
- INTE0 (External INT with selectable edge trigger)
- INTMUTE (Auto Mute Activated)
IRQ interrupt sources
- INTS0/1 (SCL Go-low INT)
- INTA0/1 (Slave Address Matched INT)
- INTTX0/1 (Shift Register INT)
- INTRX0/1 (Shift Register INT)
- INTNAK0/1 (No Acknowledge)
- INTSTOP0/1 (Stop Condition Occurred INT)
- INTE1 (External INT with Selectable Edge Trigger)
- INTV (VSYNC INT)
- INTMR (Base Timer INT)
- INTADC (AD Conversion Done INT)
n
Hardware Watch-dog timer function
n
40-pin P-DIP and 42-pin S-DIP packages
General Description
The NT6862 is a new generation monitor
C for auto-sync
and digital control applications. Particularly, this chip
supports various and efficient functions to allow users to
easily develop USB monitors. It contains the 6502 8-bit
CPU core, 512 bytes of RAM used as working RAM and
stack area, 32K bytes of OTP ROM, 13-channels of 8-bit
PWM D/A converters, 4-channel A/D converters for key
detection which save I/O pins, one 8-bit pre-loadable base
timer, internal Hsync and Vsync signals processor, a
Watch-dog timer which prevents the system from abnormal
operation, and two I
2
C bus interfaces. The user can store
EDID data in the 128 bytes of RAM for DDC1/2B, so that
user can reduce a dedicated EEPROM for EDID. A Half
frequency output function can save external one-shot
circuit. These designs are committed to reduce component
cost. The 42 pin S-DIP IC provides two additional I/O pins
port40 & port41, Part number NT6862U represents the S-
DIP IC. For future reference, port40 & port42 are only
available for the 42 pin S-DIP IC.
NT6862-5xxxx
2
Pin Configurations
40-Pin P-DIP
[PGM] DAC2
DAC1/ADC3
[OE] DAC0/ADC2
[DB7] P27
[VPP] RESET
V
DD
GND
OSCO
OSCI
[CE] P14/PATTERN
[A10] P12/HALFO
[A9] P11/ADC1
[A8] P10/ADC0
P20 [DB0]
P07/HSYNCO [A7]
P31/SCL0 [A13]
DAC4/SCL1 [MODE1]
DAC3 [MODE0]
HSYNCI
VSYNCI/INTV [A14]
NT6862
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
P15/INTE0
[A11] P13/HALFI
P16/INTE1
17
18
19
20
24
23
22
21
DAC5/SDA1 [MODE2]
DAC6 [RESET]
CREG
P21 [DB1]
P22 [DB2]
P06/VSYNCO [A6]
P05/DAC12 [A5]
P04/DAC11 [A4]
P03/DAC10 [A3]
P02/DAC9 [A2]
P01/DAC8 [A1]
P00/DAC7 [A0]
P30/SDA0 [A12]
[DB6] P26
[DB5] P25
[DB4] P24
[DB3] P23
* [ ]: OTP Mode
42-Pin S-DIP
[PGM] DAC2
DAC1/ADC3
[OE] DAC0/ADC2
[VPP] RESET
V
DD
P40
GND
OSCO
OSCI
P15/INTE0
[A11] P13/HALFI
[A9] P11/ADC1
[A8] P10/ADC0
P00/DAC7 [A0]
P16/INTE1
P01/DAC8 [A1]
P02/DAC9 [A2]
P03/DAC10 [A3]
P04/DAC11 [A4]
P06/VSYNCO [A6]
P07/HSYNCO [A7]
DAC6 [RESET]
P41
DAC5/SDA1 [MODE2]
DAC4/SCL1 [MODE1]
DAC3 [MODE0]
HSYNCI
VSYNCI/INTV [A14]
CREG
NT6862U
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
[CE] P14/PATTERN
[A10] P12/HALFO
[DB7] P27
[DB6] P26
[DB5] P25
[DB4] P24
[DB3] P23
17
18
19
20
21
P05/DAC12 [A5]
P31/SCL0 [A13]
P30/SDA0 [A12]
P20 [DB0]
P21 [DB1]
P22 [DB2]
26
25
24
23
22
* [ ]: OTP Mode
Block Diagram
Timing Generator
CPU core
6502
Interrupt
Controller
H/V Sync Signals
Processor
SRAM + STACK
512 Bytes
Watch Dog Timer
PWM DACs
I/O Ports
OSCI
OSCO
V
DD
GND
HSYNCI
INTE0/1
SCL0
SDA0
DAC0 - DAC7
P00 - P07
P10 - P16
P30 - P31
VSYNCO
A/D Converter
ADC0 - ADC3
8-Bit Base Timer
P40 - P41
IIC BUS
P20 - P27
HSYNCO
HALFI
HALFO
DAC8 - DAC12
VSYNCI/INTV
OTP Program ROM
32K Bytes
PATTERN
SCL1
SDA1
Voltage
Regulator
CREG
NT6862-5xxxx
3
Pin Description
Pin No.
40 Pin
42 Pin
Designation
Reset Init.
I/O
Description
1
1
DAC2
[ PGM ]
O
[ I ]
Open drain 5V, D/A converter output 2
[OTP ROM program control]
2
2
DAC1/ADC3
DAC1
O
Open drain 5V, D/A converter output 1, shared with A/D
converter channel 3 input
3
3
DAC0/ADC2
[ OE ]
DAC0
O
Open drain 5V, D/A converter output 0, shared with A/D
converter channel 2 input
[OTP ROM program output enable]
4
4
RESET
[ VPP ]
I
[ P ]
Schmitt Trigger input pin, low active reset with internal
pulled down 50K
register *
[OTP ROM program supply voltage]
5
5
V
DD
P
Power
6
7
GND
P
Ground
7
8
OSCO
O
Crystal OSC output
8
9
OSCI
I
Crystal OSC input
9
10
P15/INTE0
I/O
Bi-directional I/O pin with internally pulled up 22K
register, shared with input pin of external interrupt source0
(NMI), with Schmitt Trigger, selectable triggered, and
internally pulled up 22K
register
10
11
P14/PATTERN
[ A15/CE ]
I/O
[ I ]
Bi-directional I/O pin with internally pulled up 22K
register, shared with the output of self test pattern
[ OTP ROM program address buffer & chip enable ]
11
12
P13/HALFI
[ A11 ]
P13
I/O
[ I ]
Bi-directional I/O pin with internally pulled up 22K
register, shared with half Hsync input.
[ OTP ROM program address buffer ]
12
13
P12/HALFO
[ A10 ]
P12
I/O
[ I ]
Bi-directional I/O pin with internally pulled up 22K
register, shared with half Hsync output
[ OTP ROM program address buffer ]
13
14
P11/ADC1
[ A9 ]
P11
I/O
[ I ]
Bi-directional I/O pin with internally pulled up 22K
register,
shared with A/D converter channel 1 input
[ OTP ROM program address buffer ]
14
15
P10/ADC0
[ A8 ]
P10
I/O
[ I ]
Bi-directional I/O pin with internally pulled up 22K
register,
shared with A/D converter channel 0 input
[ OTP ROM program address buffer ]
15
16
P16/INTE1
P16
I/O
Bi-directional I/O pin with internally pulled up 22K
register,
shared with input pin of external interrupt source1, with
Schmitt Trigger, selectable triggered, and an internal pulled
up 22K
register
NT6862-5xxxx
4
Pin Description (continued)
Pin No.
40 Pin
42 Pin
Designation
Reset Init.
I/O
Description
16 - 23
17 - 24
P27 P20
[ DB7 ] [ DB0]
I/O
[ I/O ]
Bi-directional I/O pin, push-pull structure with high current
drive/sink capability
[ OTP ROM program data buffer ]
24
25
P30/SDA0
[ A12 ]
P30
I/O
[ I ]
Open drain 5V bi-directional I/O pin P30, shared with
SDA0 pin of I
2
C bus Schmitt Trigger buffer
[ OTP ROM program address buffer ]
25
26
P31/SCL0
[ A13 ]
P31
I/O
[ I ]
Open drain 5V bi-directional I/O pin P31, shared with
SCL0 pin of I
2
c bus Schmitt Trigger buffer
[ OTP ROM program address buffer ]
26
27
P00/DAC7
[ A0 ]
P00
I/O
[ I ]
Bi-directional I/O pin with internally pulled up 22K
register, shared with open drain 5V D/A converter output
8
[ OTP ROM program address buffer ]
27
28
P01/DAC8
[ A1 ]
P01
I/O
[ I ]
Bi-directional I/O pin with internally pulled up 22K
register, shared with open drain 5V D/A converter output
9
[ OTP ROM program address buffer ]
28
29
P02/DAC9
[ A2 ]
P02
I/O
[ I ]
Bi-directional I/O pin with internally pulled up 22K
register, shared with open drain 5V D/A converter output
10
[ OTP ROM program address buffer ]
29
30
P03/DAC10
[ A3 ]
P03
I/O
[ I ]
Bi-directional I/O pin with internally pulled up 22K
register, shared with open drain 5V D/A converter output
11
[ OTP ROM program address buffer ]
30
31
P04/DAC11
[ A4 ]
P04
I/O
[ I ]
Bi-directional I/O pin with internally pulled up 22K
register, shared with open drain 5V D/A converter output
12
[ OTP ROM program address buffer ]
31
32
P05/DAC12
[ A5 ]
P05
I/O
[ I ]
Bi-directional I/O pin with internally pulled up 22K
register, shared with open drain 5V D/A converter output
13
[ OTP ROM program address buffer ]
32
33
P06/VSYNCO
[ A6 ]
P06
I/O
[ I ]
Bi-directional I/O pin with internally pulled up 22K
register, shared with vsync out
[ OTP ROM program address buffer ]
33
34
P07/HSYNCO
[ A7 ]
P07
I/O
[ I ]
Bi-directional I/O pin with internally pulled up 22K
register, shared with hsync out
[ OTP ROM program address buffer ]
34
35
CREG
O
On chip voltage regulator output. [Connect external
regulating cap. (10F - 100F) here]
35
36
DAC6
[ RESET ]
O
[ I ]
Open drain 5V, D/A converter output 6
[ OTP ROM reset ]
NT6862-5xxxx
5
Pin Description (continued)
Pin No.
Designation
Reset Init.
I/O
Description
40 Pin
42 Pin
36
38
DAC5/SDA1
[ MODE2 ]
O
[ I ]
Open drain 5V, D/A converter output 5, shared with open
drain SDA1 line of I
2
C bus, Schmitt Trigger buffer
[ OTP ROM mode select ]
37
39
DAC4/SCL1
[ MODE1 ]
O
[ I ]
Open drain 5V, D/A converter output 4, shared with open
drain SCL1 line of I
2
C bus, Schmitt Trigger buffer
[ OTP ROM mode select ]
38
40
DAC3
[ MODE0 ]
O
[ I ]
Open drain 5V, D/A converter output 3
[ OTP ROM mode select ]
39
41
HSYNCI
I
Debouncing & Schmitt Trigger input pin for video
horizontal sync signal internally pulled high, shared with
composite sync input. A jitter filter is added at the front
end, it could effectually reduce the jitter interference of
external noisy Hsync input.
40
42
VSYNCI/INTV
[ A14 ]
VSYNCI
I
[ I ]
Debouncing & Schmitt Trigger input pin for video vertical
sync signal, internal pull high, shared with input pin of
external interrupt source intv with Schmitt Trigger,
selectable triggered, and internal pulled up 22K
register
[ OTP ROM program address buffer ]
-
6
P40
I/O
Bi-directional I/O pin with internal pulled up 22K
register, only 42 pin S-DIP available
-
37
P41
I/O
Bi-directional I/O pin with internal pulled up 22K
register, only 42 pin S-DIP available
* This RESET pin must be pulled high by an external pulled-up register (5K
suggestion), or it will remain in low voltage
and continually keep the system in a rest state..
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