NT6880

Keyboard Controller

V1.0

Features

Built-in 6502 8-bit CPU

2 MHz CPU operation frequency

5K bytes of ROM

160 bytes of SRAM

One 8-bit programmable base timer with

1 - 256

sec interval

29 programmable bi-directional I/O pins

3 LED direct sink pins

Mask optional for built-in RC oscillator with an

external resistor or external ceramic resonator applied

Mask optional for DATA/CLK driving capability

Watch-dog timer reset

Built-in power-on reset

Built-in low voltage reset

CMOS technology for low power consumption

Available in 40 pin DIP package and 40 pad Chip
Form

General Description

The NT6880 is a single chip micro-controller for
keyboard applications. It incorporates a 6502 8-bit CPU
core, 5K bytes of ROM and 160 bytes of RAM used as
working RAM and stack area. It also includes 29
programmable bi-directional I/O pins and one 8-bit pre-

loadable base timer. Additionally, it includes a built-in
low voltage reset, a 4MHz RC oscillator requiring an
externally applied resistor or a 4MHz ceramic resonator
and a watch-dog timer that prevents system standstill.

Pin Configuration

G N D

N C

D A T A

C L K

P 3 0

P 3 1

P 3 2

P 3 3

P 3 4

P 1 1

P 0 0

P 0 2

P 0 3

P 1 7

P 0 4

P 2 0

P 2 1

P 2 2

P 2 3

P 2 5

P 2 6

L E D 0

L E D 1

D D

L E D 2

R / O S C O

O S C I

P 1 2

P 2 7

NT6880

1 0

1 1

1 2

1 3

1 4

1 5

1 6

2 5

2 6

2 7

2 8

2 9

3 0

3 1

3 2

3 3

3 4

3 5

3 6

3 7

3 8

3 9

4 0

R E S E T

P 0 1

P 0 5

P 0 6

P 0 7

P 1 0

1 7

1 8

1 9

2 0

P 2 4

P 1 6

P 1 5

P 1 4

P 1 3

2 4

2 3

2 2

2 1

Pad Configuration

N T 6 8 8 0 H

G
N
D

N
C

D
A
T
A

C
L
K

P
3
0

O
S
C
O

D
D

L
E

P 3 1

P 3 2

P 3 3

P 3 4

R E S E T

P 0 0

P 0 1

P 0 2

P 0 3

P 0 4

P 0 5

P 2 0

P 2 1

P 2 2

P 2 3

P 2 4

P 2 5

P 2 6

P 2 7

L E D 0

L E D 1

P
1
7

P
1
6

P
1
5

P
1
4

P
1
3

P
1
2

P
1
1

P
1
0

P
0
7

P
0
6

S
C

NT6880

Block Diagram

W a t c h D o g

Timer

6 5 0 2

C P U

5K Bytes

R O M

160 Bytes

S R A M + S T A C K

Base Timer

Interrupt

Controller

Timing Generator

(RC OSC/Ceramic Resonator: 4MHz)

Power-On RESET/

Low Voltage RESET

I/O PORTs

G N D

D A T A

C L K

L E D 0

L E D 1

L E D 2

P00 - P07

P10 - P17

P30 - P34

P20 - P27

D D

R E S E T

Pin and Pad Descriptions

Pin No.

Pad No.

Designation

I/O

Description

GND

Ground pin

No connection, recommended to connect V

or floating

DATA

I/O

I/O, 10K

pull-up resistor for communication

CLK

I/O

I/O, 10K

pull-up resistor for communication

5 - 9,

11 - 34

5 - 9,

11 - 34

P30 - P34,

P00 - P27

I/O

Bi-directional I/O pins

RESET

RESET signal input pin with internal pull up resistor; Active low

35 - 37

LED0 -

LED2

LED direct sink pins

Power supply

R/OSCO

47K

resistor connected for RC OSC or 4MHz ceramic resonator

connected

OSCI

No connection for RC OSC connected for 4MHz ceramic resonator

* Under the constraint of the maximum frequency variation, (

F/F)

max

1%, code 3, 7 (ceramic resonator option) must

be selected and pin 39 and pin 40 must be connected to a ceramic resonator. If (

F/F)

max

10%, code 1, 5 (RC OSC

option) it is recommended that pin 39 be connected to a 47K

resistor with

1% accuracy to V

. Pin 40 is floating.

NT6880

Functional Description

1. 6502 CPU

The 6502 is an 8-bit CPU. Please refer to the 6502 data sheet for more details.

A C C U M U L A T O R A

I N D E X R E G I S T E R X

I N D E X R E G I S T E R Y

P R O G R A M C O U N T E R P C

1 5

S I G N

O V E R F O L W

B R E A K

D E C I M A L M O D E

I N T E R R U P T M A S K

Z E R O

C A R R Y

S T A T U S R E G I S T E R P

U N U S E D

S Y S T E M R E G I S T E R S

U N U S E D

U S E R R O M

S R A M

R S T - L

I R Q - H

I R Q - L

R S T - H

F F F F

F F F E

F F F D

F F F C

E C 0 0

0 0 C F

0 0 C 0

0 0 9 F

0 0 0 0

S T A C K P T R

N M I V E C T O R

I R Q V E C T O R

F F F B

F F F A

N M I - L

N M I - H

S T A C K P O I N T E R S P

Figure 1.1 6502 CPU Registers and Status Flags

Figure 1.2. NT6880 Memory Map

NT6880

2. System Reserved Registers

Addr.

Register

Bit7

Bit6

Bit5

Bit4

Bit3

Bit2

Bit1

Bit0

R/W

$00C0

BT7

BT6

BT5

BT4

BT3

BT2

BT1

BT0

$00C1

TCON

ENBT

$00C2

CLRIRQX

CLRIRQTMR

$00C3

PORT0

PD07

PD06

PD05

PD04

PD03

PD02

PD01

PD00

$00C4

PORT1

PD17

PD16

PD15

PD14

PD13

PD12

PD11

PD10

$00C5

PORT2

PD27

PD26

PD25

PD24

PD23

PD22

PD21

PD20

$00C6

PORT3

PD34

PD33

PD32

PD31

PD30

$00C7

CLK

$00C8

DATA

$00C9

LED

LED2

LED1

LED0

$00CA

CLRWDT

$00CB

$00CC

$00CD

$00CE

$00CF

- : no effect

X : access not allowed

3. ROM: 5K X 8 bits

The built-in ROM program code, executed by the 6502
CPU, has a capacity of 5K X 8 bits and is addressed from
EC00H to FFFFH.

4. SRAM: 160 X 8 bits

The built-in SRAM is used for general purpose data
memory and for the stack area. SRAM is addressed from
0000H to 009FH. User can allocate stack area in the
SRAM by setting stack pointer register (S). Because the
6502 default stack pointer is 01FFH, it must be mapped to
009FH. Mapping from 01XX to 00XX is done internally by
setting the S register to 9FH via software programming.
For example :

LDX #$9F
TXS

For compatibility to UM6868A with 128-byte SRAM, the
user's source code can not be changed.
For example :

LDX #$7F
TXS

5. Power-On Reset

Built-in power-on reset circuit can generate a 150ms pulse
to reset the entire chip. The beginning of the 150ms pulse
occurs at 60% of V

when powered on.

The start of 150ms pulse

p o w e r

6 0 %

Figure 5.1. Power-On Reset Timing

NT6880

6. Timing Generator

This block generates the system timing and control
signal supplied to the CPU and on-chip peripherals.
There are two types of system clock sources: built-in RC
oscillator or external ceramic resonator. Both are mask
optional and generate a 4MHz system clock. They also
generate 2MHz for the CPU, and 1 MHz for base timer.

The following table provides the relationship between
external resistor and RC OSC frequency. (for reference
only)

External Resistor

)

RC OSC Frequency (MHz)

4.7

4.44

3.68

7. Base Timer (BT)

The base timer is an 8-bit counter with a 1MHz clock source. The base timer can be enabled/disabled by CPU. After reset,
the base timer is disabled and cleared. The base timer can be preset by writing BT7 - BT0 to the BT register at any time.
When enabled, the base timer starts counting from the preset value. When the value reaches FFH, it generates a timer
interrupt if the timer interrupt is enabled. When it reaches the maximum value of FFH, the base timer will wrap around and
begin counting at 00H. The timer interval can be programmed from 1 - 256

sec. The base timer can be enabled by writing

a '0' to ' ENBT ' in the TCON (Timer Control) register. The ENBT is a level trigger.

Base timer structure:

8-Bit timer

BT7

BT6

BT5

BT4

BT2

BT1

BT0

BT pre-load data:

Addr.

Bit

R/W

$00C0

BT7

BT6

BT5

BT4

BT3

BT2

BT1

BT0

(W)

Timer Control Register:

$00C1

TCON

ENBT

(W)

8. Interrupt Controller

When a BASE TIMER overflow occurs, it will set the IRQTMR flag. The IRQTMR flag cannot be directly accessed by the
software. Once set by an interrupt source, it remains High unless cleared by writing '1' to the corresponding bit in
CLRIRQX ($00C2H). This register is cleared to '0' on initialization by a system reset.
When an interrupt occurs, the CPU will jump to $FFFEH & $FFFFH to execute an interrupt service routine. When the
BASE TIMER interrupt occurs and enters an interrupt service routine, the IRQTMR flag must be cleared by the software.

Interrupt Control Register:

Addr.

Bit

R/W

$00C2

CLRIRQX

CLRIRQTMR

(W)

TMRINT

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